Semiconductor device, method for manufacturing semiconductor device, and power conversion device provided with semiconductor device

Abstract

Provided is a semiconductor device including: a semiconductor substrate provided with a drift region; a buffer region disposed between the drift region and a lower surface and having a doping concentration profile with three or more concentration peaks; and a collector region disposed between the buffer region and the lower surface, the three or more concentration peaks in the buffer region including: a first concentration peak closest to the lower surface; a second concentration peak next closest to the lower surface after the first concentration peak and disposed so as to be 5 μm or more in depth from the lower surface, the doping concentration of the second concentration peak being lower than the doping concentration of the first concentration peak and the doping concentration of the second concentration peak being less than 1.0 x 10 15 / cm 3 ; and a high concentration peak disposed further from the lower surface than the second concentration peak, the doping concentration of the high concentration peak being higher than the doping concentration of the second concentration peak.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device having a semiconductor device. Background Technology

[0002] Previously, it was known that a structure "with a field cutoff layer (FS layer) provided in an IGBT (Insulated Gate Bipolar Transistor) device" was known (for example, see Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: WO2016 / 204126 Summary of the Invention

[0006] Technical issues

[0007] In semiconductor devices such as IGBTs, it is desirable to improve characteristics such as latch-up tolerance.

[0008] Technical solution

[0009] To address the aforementioned issues, in a first aspect of the present invention, a semiconductor device is provided, comprising a semiconductor substrate having an upper surface and a lower surface, and a drift region having a first conductivity type. The semiconductor device may include a buffer zone of the first conductivity type disposed between the drift region and the lower surface, having three or more concentration peaks in the doping concentration distribution along the depth direction of the semiconductor substrate. The semiconductor device may include a collector region of a second conductivity type disposed between the buffer zone and the lower surface. The three or more concentration peaks in the buffer zone may have a first concentration peak closest to the lower surface. The three or more concentration peaks in the buffer zone may have a second concentration peak that is close to the lower surface in a manner second only to the first concentration peak. The second concentration peak may be configured to be at least 5 μm away from the lower surface in the depth direction. The doping concentration of the second concentration peak may be lower than the doping concentration of the first concentration peak. The doping concentration of the second concentration peak may be less than 1.0 × 10⁻⁶. 15 / cm 3 Three or more concentration peaks in the buffer can have a high concentration peak configured to be further away from the lower surface than the second concentration peak. The doping concentration of the high concentration peak can be higher than that of the second concentration peak.

[0010] A high concentration peak can be the peak furthest from the lower surface among three or more concentration peaks in the buffer zone.

[0011] A high concentration peak can be the highest doping concentration peak among three or more concentration peaks in the buffer zone, excluding the first concentration peak.

[0012] In the buffer zone, the doping concentration of each of the three or more concentration peaks, excluding the first concentration peak, can be less than 1.0 × 10⁻⁶. 15 / cm 3 .

[0013] In the buffer zone, the doping concentration of each of the three or more concentration peaks, excluding the first concentration peak, can be 3.0 × 10⁻⁶. 14 / cm 3 Above and 5.0×10 14 / cm 3 the following.

[0014] The buffer zone can have valleys between the concentration peaks where the doping concentration reaches a minimum. The doping concentration in each valley can be 2.0 × 10⁻⁶. 14 / cm 3 Above and 5.0×10 14 / cm 3 the following.

[0015] The dosage of the dopant of the second conductivity type in the collector region can be 8 × 10⁻⁶. 12 / cm 2 the following.

[0016] The doping concentration of the first concentration peak can be more than 0.1 times and less than 10 times the doping concentration of the collector region.

[0017] The doping concentration of the second concentration peak can be less than 0.1 times that of the first concentration peak.

[0018] The doping concentration of the high concentration peak can be less than 0.1 times that of the first concentration peak.

[0019] The doping concentration of the second concentration peak can be more than 0.6 times and less than 0.8 times that of the high concentration peak.

[0020] The buffer may contain more than three concentration peaks, including a third concentration peak, which is positioned between the second concentration peak and the high concentration peak, and the doping concentration of the third concentration peak is lower than that of the second concentration peak.

[0021] The doping concentration of the third concentration peak can be more than 0.4 times and less than 0.6 times that of the high concentration peak.

[0022] The full width at half maximum (FWHM) of the second concentration peak can be larger than that of the high concentration peak.

[0023] The full width at half maximum (FWHM) of the second concentration peak can be larger than that of all other concentration peaks.

[0024] The full width at half maximum (FWHM) of a high concentration peak can be more than twice that of the full width at half maximum (FWHM) of the first concentration peak.

[0025] The full width at half maximum (FWHM) of the second concentration peak can be more than twice that of the full width at half maximum (FWHM) of the first concentration peak.

[0026] The buffer may contain more than three concentration peaks, including a third concentration peak positioned between the second and higher concentration peaks. The full width at half maximum (FWHM) of the third concentration peak may be more than twice the FWHM of the first concentration peak.

[0027] High concentration peaks may have flat portions, which include the depth location where the doping concentration reaches its maximum value, and the doping concentration distribution is flat in the depth direction.

[0028] The third concentration peak may have a flat portion, which includes the depth location where the doping concentration shows a maximum value, and the doping concentration distribution is flat in the depth direction.

[0029] In a second aspect of the present invention, a semiconductor device is provided, comprising a semiconductor substrate having an upper surface and a lower surface, and a drift region having a first conductivity type. The semiconductor device may include a buffer zone of the first conductivity type disposed between the drift region and the lower surface, having three or more concentration peaks in the doping concentration distribution along the depth direction of the semiconductor substrate. The semiconductor device may also include a collector region of the second conductivity type disposed between the buffer zone and the lower surface. The three or more concentration peaks in the buffer zone may include: a first concentration peak closest to the lower surface; and a high concentration peak disposed furthest from the lower surface, having a doping concentration lower than that of the first concentration peak, and having a full width at half maximum (FWHM) of at least twice that of the first concentration peak.

[0030] In a third aspect of the present invention, a semiconductor device is provided, comprising a semiconductor substrate having an upper surface and a lower surface, and a drift region having a first conductivity type. The semiconductor device may include a buffer zone of the first conductivity type disposed between the drift region and the lower surface, having three or more concentration peaks in the doping concentration distribution along the depth direction of the semiconductor substrate. The semiconductor device may include a collector region of a second conductivity type disposed between the buffer zone and the lower surface. The three or more concentration peaks in the buffer zone may have a first concentration peak configured to be closest to the lower surface. The doping concentration of the first concentration peak may be 0.1 times or more and 10 times or less than that of the collector region. The three or more concentration peaks in the buffer zone may have a second concentration peak configured to be close to the lower surface in a manner second only to the first concentration peak. The doping concentration of the second concentration peak may be 0.1 times or less than that of the first concentration peak.

[0031] In a fourth aspect of the present invention, a power conversion device is provided, having a carrier frequency of 10 kHz or higher and comprising a semiconductor device of either the first or second aspect.

[0032] In a fifth aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include an ion implantation step of implanting hydrogen ions from the lower surface of a semiconductor substrate having a drift region of a first conductivity type to three or more depth locations. In the ion implantation step, a first device may be used to implant hydrogen ions to a first depth location closest to the lower surface among the three or more depth locations, and a second device, different from the first device, may be used to implant hydrogen ions to the deepest depth location farthest from the lower surface among the three or more depth locations. The full width at half maximum (FWHM) of the hydrogen chemical concentration peak at the deepest depth location may be at least twice the FWHM of the hydrogen chemical concentration peak at the first depth location.

[0033] It should be noted that the above summary of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0034] Figure 1 This is a top view showing an example of a semiconductor device 100.

[0035] Figure 2 yes Figure 1 An enlarged view of region D in the image.

[0036] Figure 3 It is shown Figure 2 A diagram of an example of the ee section.

[0037] Figure 4 It is shown Figure 3 A diagram showing an example of the doping concentration distribution along the depth direction at the location of the FF line.

[0038] Figure 5 This is an enlarged view of the doping concentration distribution in buffer 20.

[0039] Figure 6 This is another example of the doping concentration distribution in buffer 20.

[0040] Figure 7 This is another example of the doping concentration distribution in buffer 20.

[0041] Figure 8 This is another example of the doping concentration distribution in buffer 20.

[0042] Figure 9 This is a graph showing the doping concentration distribution in buffer 20 of the comparative example.

[0043] Figure 10 This is a graph showing the doping concentration distribution in buffer 20 of the comparative example.

[0044] Figure 11This is a diagram illustrating an example of the time waveforms of the collector-emitter voltage Vce and the collector current when a semiconductor device is turned off.

[0045] Figure 12 This is a diagram illustrating an example of the latch-up tolerance of a semiconductor device in a comparative example and an embodiment.

[0046] Figure 13 This is another example of the doping concentration distribution in buffer 20.

[0047] Figure 14 This is an enlarged view of the high concentration peak 25-4.

[0048] Figure 15 This is a graph showing the relationship between the accelerating voltage of hydrogen ions and the avalanche breakdown voltage at which the first concentration peak 25-1 is formed.

[0049] Figure 16 This is another example of the doping concentration distribution in buffer 20.

[0050] Figure 17 This is a diagram showing a portion of the manufacturing process of the semiconductor device 100.

[0051] Figure 18 This is a diagram showing an example of the hydrogen chemical concentration distribution in buffer 20 after heat treatment step S1503.

[0052] Figure 19 This indicates that it was used in Figures 1-12 The diagram shows the power conversion device 1302 of the semiconductor device 100 as described in the illustration.

[0053] Symbol Explanation

[0054] 10: Semiconductor substrate; 11: Well region; 12: Emitter region; 14: Base region; 15: Contact region; 16: Accumulation region; 18: Drift region; 20: Buffer zone; 21: Upper surface; 22: Collector region; 23: Lower surface; 24: Collector electrode; 25: Concentration peak; 26: Valley; 27: Lower tail; 28: Upper tail; 29: Straight section; 30: Dummy trench; 31: Front end; 32: Dummy insulating film; 34: Dummy conductive section; 38: Interlayer insulating film; 39: Straight section; 40: Gate trench; 41: Front end. 42: Gate insulating film; 44: Gate conductive part; 52: Emitter electrode; 54: Contact hole; 60, 61: Mesa section; 70: Transistor part; 80: Diode part; 81: Extension region; 82: Cathode region; 90: Edge termination structure part; 100: Semiconductor device; 125: Hydrogen concentration peak; 130: Peripheral gate wiring; 131: Active side gate wiring; 141: Flat portion; 160: Active part; 162: Edge; 164: Gate pad; 1300: Power supply; 1302: Power conversion device; 1304: Load Detailed Implementation

[0055] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily necessary for the technical means of the invention.

[0056] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0057] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes are used only to determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When a direction is referred to as the Z-axis without specifying positive or negative, it refers to a direction parallel to the +Z-axis and -Z-axis.

[0058] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction including the X-axis and Y-axis and parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0059] Additionally, the region extending from the center of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate is sometimes referred to as the upper surface side. Similarly, the region extending from the center of the semiconductor substrate in the depth direction to the lower surface of the semiconductor substrate is sometimes referred to as the lower surface side. In this specification, the center position in the depth direction of the semiconductor substrate is sometimes referred to as Zc.

[0060] In the context of this specification, the terms "same" or "equal" may also include cases with errors due to manufacturing deviations, etc. Such errors are, for example, within 10%.

[0061] In this specification, the conductivity type of the doped region containing impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopant. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate, thereby creating a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0062] In this specification, doping concentration refers to the donor or acceptor concentration at thermal equilibrium. In this specification, net doping concentration refers to the actual concentration obtained by adding the donor concentration (which is the concentration of positive ions) and the acceptor concentration (which is the concentration of negative ions), taking into account charge polarity. As an example, if the donor concentration is set to N... D Set the acceptor concentration to N A Then the actual net doping concentration at any position becomes N. D -N A In this specification, the net doping concentration is sometimes described as the doping concentration only.

[0063] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of accepting electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as electron-supplying donors. In this specification, VOH defects are sometimes referred to as hydrogen donors.

[0064] In this specification, when referred to as P+ or N+ type, it indicates a higher doping concentration than P- or N- type; when referred to as P- or N- type, it indicates a lower doping concentration than P- or N- type. Similarly, when referred to as P++ or N++ type, it indicates a higher doping concentration than P+ or N+ type. Unless otherwise stated, the unit system in this specification is SI. Although cm is sometimes used to express length, calculations can be performed after conversion to meters (m).

[0065] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electroactivated state. Chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be determined by voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured by diffusion resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by CV or SR methods can be taken as the value under thermal equilibrium conditions. Furthermore, in the N-type region, the donor concentration is sufficiently greater than the acceptor concentration; therefore, the carrier concentration in this region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can be used as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0066] Furthermore, when the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of the donor, acceptor, or net dopant in that region. When the concentrations of donor, acceptor, or net dopant are approximately uniform, the average concentration of the donor, acceptor, or net dopant in that region can be taken as the concentration of the donor, acceptor, or net dopant. In this specification, concentration per unit volume is expressed in atomos / cm³. 3 or / cm 3 This unit is used to indicate the concentration of donors or acceptors, or the chemical concentration, within a semiconductor substrate. The expression "atoms" can also be omitted.

[0067] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of diffusion resistance, within the range of current flow, the carrier mobility of the semiconductor substrate is sometimes lower than that in the crystalline state. This decrease in carrier mobility is caused by the dispersion of carriers due to the disorder (disorder) of the crystal structure caused by lattice defects, etc.

[0068] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. As an example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which acts as a donor) or the acceptor concentration of boron (which acts as an acceptor) is approximately 99% of their chemical concentration. On the other hand, in silicon semiconductors, the donor concentration of hydrogen (which acts as a donor) is approximately 0.1% to 10% of the chemical concentration of hydrogen. The concentrations in this specification can be values ​​at room temperature. As an example, values ​​at room temperature can be values ​​at 300 K (Kelvin) (approximately 26.9°C).

[0069] Figure 1 This is a top view showing an example of a semiconductor device 100. Figure 1 The diagram shows the positions obtained by projecting each component onto the upper surface of the semiconductor substrate 10. Figure 1 The image shows only a portion of the components of the semiconductor device 100; some components are omitted.

[0070] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0071] The semiconductor substrate 10 has end edges 162 when viewed from above. In this specification, "viewed from above" means viewed from the top surface side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 162 that are opposite each other when viewed from above. Figure 1 In this configuration, the X and Y axes are parallel to one of the end edges 162. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0072] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region in which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active portion 160, but... Figure 1 Omitted in .

[0073] The active section 160 is provided with at least one of a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs). Figure 1 In one example, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined alignment direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. In other examples, the active section 160 may contain only one of the transistor section 70 and the diode section 80.

[0074] exist Figure 1 In this specification, the area where the transistor section 70 is arranged is marked with the symbol "I", and the area where the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in...). Figure 1 (The middle direction is the Y-axis direction). The transistor section 70 and the diode section 80 may each have a long side in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section described later.

[0075] The diode portion 80 has an N+ type cathode region in the area contacting the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, sometimes an extension region 81 extending the diode portion 80 along the Y-axis to the gate wiring described later is also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0076] The transistor section 70 has a P+ type collector region in the area that contacts the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has an N-type emitter region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0077] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 164. Semiconductor device 100 may also have anode pads, cathode pads, and current sensing pads, etc. Each pad is located near the edge 162. "Near the edge 162" refers to the area between edge 162 and the emitter electrode when viewed from above. When mounting semiconductor device 100, each pad can be connected to external circuitry via wiring such as wires.

[0078] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes gate wiring connecting the gate pad 164 to the gate trench portion. Figure 1 In the diagram, the gate wiring is marked with a slanted shaded line.

[0079] The gate wiring in this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above. In this example, the peripheral gate wiring 130 surrounds the active portion 160 when viewed from above. Alternatively, the area surrounded by the peripheral gate wiring 130 when viewed from above may also be considered as the active portion 160. Furthermore, the peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring including aluminum or the like.

[0080] An active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, the deviation of the wiring length measured from the gate pad 164 in each region of the semiconductor substrate 10 can be reduced.

[0081] The active-side gate wiring 131 is connected to the gate trench portion of the active portion 160. The active-side gate wiring 131 is disposed above the semiconductor substrate 10. The active-side gate wiring 131 can be a wiring formed from a semiconductor such as polysilicon doped with impurities.

[0082] The active-side gate wiring 131 can be connected to the outer peripheral gate wiring 130. In this example, the active-side gate wiring 131 is configured to extend from one side of the outer peripheral gate wiring 130 to the other side of the outer peripheral gate wiring 130 in a manner that crosses the active portion 160 approximately at the center in the Y-axis direction. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0083] Alternatively, the semiconductor device 100 may also include a PN junction diode (not shown) formed of polysilicon or the like, i.e., a temperature sensing unit, and / or a current sensing unit (not shown) that simulates the operation of the transistor unit provided in the active unit 160.

[0084] In this example, the semiconductor device 100, when viewed from above, has an edge termination structure 90 between the active portion 160 and the edge 162. The edge termination structure 90 is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a protective ring surrounding the active portion 160 in an annular shape, a field plate, and a surface electric field reducing element.

[0085] Figure 2 yes Figure 1 An enlarged view of region D is shown. Region D includes the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 disposed inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131 disposed above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are disposed separately from each other.

[0086] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but... Figure 2 (Omitted). In this example, the interlayer insulating film has contact holes 54 provided in a manner that penetrates the interlayer insulating film. Figure 2 In the diagram, each contact hole 54 is marked with a slanted shaded line.

[0087] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. Furthermore, the emitter electrode 52 is connected to a dummy conductive portion within the dummy trench portion 30 through a contact hole disposed in the interlayer insulating film. The emitter electrode 52 can be connected to the dummy conductive portion of the dummy trench portion 30 at its front end in the Y-axis direction.

[0088] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench portion 40 at its front end 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30.

[0089] The emitting electrode 52 is formed of a material containing metal. Figure 2 The diagram shows the area where the emitting electrode 52 is disposed. For example, at least a portion of the emitting electrode 52 is formed of aluminum or an aluminum-silicon alloy such as AlSi, AlSiCu, or other metal alloys. The emitting electrode 52 may have a barrier metal formed of titanium and / or titanium compounds in a lower layer beneath the region formed of aluminum or the like. Furthermore, a plug formed by embedding tungsten or the like in contact with the contact hole may be provided.

[0090] Well region 11 is configured to overlap with the active-side gate wiring 131. Well region 11 is also configured to extend with a predetermined width in the area where it does not overlap with the active-side gate wiring 131. In this example, well region 11 is configured as an end in the Y-axis direction away from the contact hole 54 towards the active-side gate wiring 131. Well region 11 is a region of the second conductivity type with a higher doping concentration than the base region 14. In this example, base region 14 is P-type, and well region 11 is P+ type.

[0091] The transistor section 70 and the diode section 80 each have a plurality of trench sections arranged in the arrangement direction. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately arranged along the arrangement direction. In this example, the diode section 80 has a plurality of dummy trench sections 30 arranged along the arrangement direction. In this example, the diode section 80 does not have gate trench sections 40.

[0092] In this example, the gate trench portion 40 may have two straight portions 39 (the portion of the trench is straight along the extension direction) extending in an extension direction perpendicular to the arrangement direction and a front end portion 41 connecting the two straight portions 39. Figure 2 The extension direction in the middle is the Y-axis direction.

[0093] At least a portion of the front end portion 41 is preferably curved when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction to each other through the front end portion 41, the electric field concentration at the ends of the straight portions 39 can be mitigated.

[0094] In the transistor section 70, dummy trench sections 30 are provided between each straight section 39 of the gate trench section 40. One dummy trench section 30 may be provided between each straight section 39, or multiple dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight shape extending in the extending direction, or it may have the same straight section 29 and front end portion 31 as the gate trench section 40. Figure 2 The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and no front end portion 31 and a dummy trench portion 30 with a front end portion 31.

[0095] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are located within the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This mitigates the electric field concentration at the bottom of each trench portion.

[0096] In the arrangement direction, mesa-shaped portions are provided between each trench portion. A mesa-shaped portion refers to the area within the semiconductor substrate 10 that is sandwiched between trench portions. As an example, the upper end of the mesa-shaped portion is the upper surface of the semiconductor substrate 10. The depth of the lower end of the mesa-shaped portion is the same as the depth of the lower end of the trench portion. In this example, the mesa-shaped portion is configured to extend along the trench in the extension direction (Y-axis direction) on the upper surface of the semiconductor substrate 10. In this example, a mesa-shaped portion 60 is provided in the transistor portion 70, and a mesa-shaped portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa-shaped portion, it refers to each of mesa-shaped portion 60 and mesa-shaped portion 61.

[0097] A base region 14 is provided on each mesa. The region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 within the mesa, configured to be closest to the active-side gate wiring 131, is designated as base region 14-e. Figure 2 The diagram shows a base region 14-e disposed at one end of each isthmus in the extending direction, but a base region 14-e is also disposed at the other end of each isthmus. In each isthmus, the area enclosed by the base region 14-e when viewed from above can be provided with at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 can be disposed in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0098] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is configured to contact the gate trench portion 40. The mesa portion 60 that contacts the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0099] The contact area 15 and the emission area 12 in the platform 60 are respectively configured as a groove portion from one side to the other side in the X-axis direction. As an example, the contact area 15 and the emission area 12 of the platform 60 are alternately arranged along the extension direction of the groove portion (Y-axis direction).

[0100] In another example, the contact area 15 and the emission area 12 of the platform surface 60 can be arranged in a stripe pattern along the extension direction (Y-axis direction) of the groove portion. For example, the emission area 12 is provided in the area that contacts the groove portion, and the contact area 15 is provided in the area sandwiched by the emission area 12.

[0101] The emitter region 12 is not provided on the mesa 61 of the diode section 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa 61. On the upper surface of the mesa 61, in the area enclosed by the base regions 14-e, a contact region 15 may be provided in a manner that contacts each of the base regions 14-e. On the upper surface of the mesa 61, in the area enclosed by the contact region 15, a base region 14 may be provided. The base region 14 may be disposed throughout the entire area enclosed by the contact region 15.

[0102] A contact hole 54 is provided above each mesa surface. The contact hole 54 is located in the area enclosed by the base region 14-e. In this example, the contact hole 54 is located above each of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not located in the region corresponding to the base region 14-e and the sink region 11. The contact hole 54 may be located at the center of the mesa surface 60 in the arrangement direction (X-axis direction).

[0103] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 can be provided on the lower surface of the semiconductor substrate 10 in the region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are disposed between the lower surface 23 of the semiconductor substrate 10 and the buffer zone 20. Figure 2 In the diagram, the boundary between the cathode region 82 and the collector region 22 is represented by a dashed line.

[0104] The cathode region 82 is configured to be located away from the well region 11 in the Y-axis direction. This ensures a sufficient distance between the cathode region 82 and the P-type region (well region 11) with a high doping concentration and extending to its deepest point, thereby improving breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is configured to be further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may also be configured between the well region 11 and the contact hole 54.

[0105] Figure 3 It is shown Figure 2 A diagram showing an example of the ee cross section. The ee cross section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0106] An interlayer insulating film 38 is disposed on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of an insulating film such as silicate glass containing impurities such as boron or phosphorus, a thermally oxidized film, or other insulating films. The interlayer insulating film 38 has a layer of... Figure 2 Contact hole 54 as described in the diagram.

[0107] The emitter electrode 52 is disposed above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is disposed on the lower surface 23 of the semiconductor substrate 10. Both the emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0108] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift regions 18 are respectively disposed in the transistor section 70 and the diode section 80.

[0109] On the mesa 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are sequentially disposed from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is disposed below the base region 14. An N+ type accumulation region 16 may be disposed on the mesa 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0110] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is configured to contact the gate trench 40. The emitter region 12 may contact the trenches on both sides of the mesa 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0111] The base region 14 is located below the emitter region 12. In this example, the base region 14 is configured to contact the emitter region 12. The base region 14 may contact the groove portions on both sides of the stage surface 60.

[0112] Accumulation region 16 is disposed below base region 14. Accumulation region 16 is an N+ type region with a higher doping concentration than drift region 18. Accumulation region 16 may have concentration peaks of donors such as phosphorus or hydrogen donors. By providing a high-concentration accumulation region 16 between drift region 18 and base region 14, the carrier injection enhancement effect (IE effect) can be improved, thereby reducing the turn-on voltage. Accumulation region 16 may be configured to cover the entire lower surface of base region 14 in each mesa 60.

[0113] A P-type base region 14 is provided on the mesa 61 of the diode section 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may also be provided below the base region 14 in the mesa 61.

[0114] In both the transistor section 70 and the diode section 80, an N+ type buffer 20 may be provided below the drift region 18. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 has a concentration peak 25 with a doping concentration higher than that of the drift region 18. The doping concentration of the concentration peak 25 refers to the doping concentration at the apex of the concentration peak 25. Alternatively, the doping concentration of the drift region 18 can be the average doping concentration in a region with a roughly flat doping concentration distribution.

[0115] In the buffer 20 of this example, the doping concentration distribution along the depth direction (Z-axis direction) of the semiconductor substrate 10 has three or more concentration peaks 25. The concentration peaks 25 of the buffer 20 can be formed by ion implantation of N-type dopants such as hydrogen (protons) or phosphorus. The concentration peaks 25 of the buffer 20 can be set at the same depth position as, for example, the concentration peaks of hydrogen (protons) or phosphorus. The buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0116] In the transistor section 70, a P+ type collector region 22 is provided below the buffer 20. The acceptor concentration in the collector region 22 is higher than that in the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain acceptors different from the base region 14. The acceptor in the collector region 22 is, for example, boron.

[0117] In the diode section 80, an N+ type cathode region 82 is provided below the buffer zone 20. The donor concentration in the cathode region 82 is higher than that in the drift region 18. The donors in the cathode region 82 are, for example, hydrogen or phosphorus. It should be noted that the elements that become donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0118] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In regions where at least one of the emitter region 12, contact region 15, and accumulation region 16 is provided, each trench portion also extends through these doped regions to reach the drift region 18. The trench portion extending through the doped region is not limited to the case where the trench portion is formed after the doped region is formed. The case where the doped region is formed between the trench portions after the trench portion is formed is also included in the case where the trench portion extends through the doped region.

[0119] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but no gate trench section 40 is provided. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0120] The gate trench portion 40 has a gate trench disposed on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is disposed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position further inward than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0121] The gate conductive portion 44 can be configured to be longer than the base region 14 in the depth direction. The gate trench portion 40 at this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, an electron-based inversion layer channel is formed on the surface layer of the interface in the base region 14 that contacts the gate trench portion 40.

[0122] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench disposed on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is disposed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench and is located further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length in the depth direction as the gate conductive portion 44.

[0123] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0124] Figure 4 It is shown Figure 3 A diagram showing an example of the doping concentration distribution along the depth direction at the location of the FF line. Figure 4 The vertical axis is the logarithmic axis. Figure 4 In this process, the central position in the depth direction of the semiconductor substrate 10 is set as Zc.

[0125] Emitter region 12 has a concentration peak of N-type dopant. N-type dopant is, for example, phosphorus, but is not limited thereto. Base region 14 has a concentration peak of P-type dopant. P-type dopant is, for example, boron, but is not limited thereto. Accumulation region 16 has a concentration peak of N-type dopant. N-type dopant is, for example, hydrogen or phosphorus, but is not limited thereto.

[0126] The drift region 18 can have a flat region with a substantially constant doping concentration. The flat region is a continuous portion in the depth direction of the area where the doping concentration lies between a predetermined maximum value (max) and a predetermined minimum value (min). The maximum value (max) can be the maximum doping concentration in this region. The minimum value (min) can be 50%, 70%, or 90% of the maximum value (max).

[0127] Alternatively, the value of the doping concentration distribution in the flat region, relative to the average concentration of the doping concentration distribution within a predetermined range in the depth direction, may be within ±50%, ±30%, or ±10% of the average concentration of the doping concentration distribution.

[0128] The doping concentration of drift region 18 can be the same as the body donor concentration. In this example, the semiconductor substrate 10 is uniformly distributed with N-type body donors. Body donors are donors formed by dopants that are substantially uniformly contained within the ingot during the manufacturing of the raw material for the semiconductor substrate 10. In this example, the body donor is an element other than hydrogen. The dopants for the body donors are, for example, group V or group VI elements, such as phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the body donor is phosphorus. The body donor is also contained in the P-type region. The semiconductor substrate 10 can be a wafer cut from a semiconductor ingot or a chip formed by monolithically stacking wafers. The semiconductor ingot can be manufactured using any of the following methods: the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the floating zone method (FZ method). In this example, the ingot is manufactured using the MCZ method.

[0129] As an example, the oxide concentration in the substrate manufactured by the MCZ method is 1×10⁻⁶. 17 ~7×10 17 atoms / cm 3 As an example, the chemical concentration of oxides in a substrate manufactured by the FZ method is 1 × 10⁻⁶. 15 ~5×10 16 atoms / cm 3 The bulk donor concentration can be the chemical concentration of bulk donors distributed throughout the semiconductor substrate 10, or a value between 90% and 100% of that chemical concentration. In semiconductor substrates doped with group V or VI dopants such as phosphorus, the bulk donor concentration can be 1 × 10⁻⁶. 11 / cm 3 Above and 3×10 14 / cm 3 The bulk donor concentration of the semiconductor substrate doped with group V or group VI dopants is preferably 1 × 10⁻⁶. 12 / cm 3 Above and 2×10 14 / cm 3 The following applies. Alternatively, the semiconductor substrate 10 can also be an undoped substrate that does not contain dopants such as phosphorus. In this case, the bulk donor concentration (N) of the undoped substrate is... B0 For example, 1×10 10 / cm 3 Above and 5×10 12 / cm 3 The following is the bulk donor concentration (N) of the undoped substrate. B0 The preferred value is 1×10 11 / cm 3 The above. Bulk donor concentration (N) of the undoped substrate. B0 The preferred value is 5×10 12 / cm 3 the following.

[0130] Drift region 18 may also have a doping concentration higher than the bulk donor concentration. If charged particles such as helium ions, hydrogen ions, or electrons are irradiated onto the semiconductor substrate 10, lattice defects dominated by vacancies, such as single-atom vacancies (V) and diatomic vacancies (VV), are formed in the passage regions through which the charged particles pass. Atoms adjacent to vacancies have dangling bonds. Lattice defects also include interstitial atoms and / or dislocations, and in a broader sense, may also include donors and acceptors. However, in this specification, lattice defects dominated by vacancies are sometimes referred to as vacancy-type lattice defects, or simply lattice defects. Furthermore, because a large number of lattice defects are formed by injecting charged particles into the semiconductor substrate 10, the crystallinity of the semiconductor substrate 10 is sometimes severely disordered. In this specification, this disorder of crystallinity is sometimes referred to as disorder.

[0131] Furthermore, oxygen is present throughout the semiconductor substrate 10. This oxygen is introduced intentionally or unintentionally during the manufacture of the semiconductor ingot. Additionally, hydrogen may be present in at least a portion of the charged particle passage region. This hydrogen may be intentionally implanted into the interior of the semiconductor substrate 10. For example, hydrogen ions may be implanted to form the concentration peak 25 of the buffer zone 20. By using heat treatment or the like to diffuse the hydrogen implanted into the buffer zone 20, hydrogen (H), vacancies (V), and oxygen (O) combine within the semiconductor substrate 10 to form VOH defects.

[0132] VOH defects function as donors of electrons. In this specification, VOH defects are sometimes simply referred to as hydrogen donors. By forming hydrogen donors in the semiconductor substrate 10, the donor concentration in the charged particle passage region can be higher than the bulk donor concentration. Typically, a semiconductor substrate 10 with a predetermined bulk donor concentration corresponding to the characteristics of the device to be formed on the semiconductor substrate 10, particularly the rated voltage or withstand voltage, must be prepared. In contrast, when hydrogen donors are formed, the donor concentration of the semiconductor substrate 10 can be adjusted by controlling the charge particle dosage. Therefore, a semiconductor device 100 can be manufactured using a semiconductor substrate with a bulk donor concentration that does not correspond to the characteristics of the device. Although the deviation in bulk donor concentration during the manufacture of the semiconductor substrate 10 is relatively large, the charge particle dosage can be controlled with relatively high precision. Therefore, the concentration of lattice defects generated by the implantation of charged particles can also be controlled with high precision, and the donor concentration in the passage region can be controlled with high precision.

[0133] In this example, the doping concentration distribution in buffer 20 has multiple concentration peaks 25 located at different positions along the depth direction. Concentration peak 25 represents the donor concentration. Concentration peak 25 can have hydrogen as an impurity and hydrogen donors as donors. By setting multiple concentration peaks 25, the depletion layer reaching the collector region 22 can be further suppressed.

[0134] exist Figure 4 In the example shown, the concentration peak 25-1 closest to the lower surface 23, the second concentration peak 25-2 closest to the lower surface 23, the third concentration peak 25-3 closest to the lower surface 23, and the concentration peak 25-4 furthest from the lower surface 23 are shown. In other examples, the number of concentration peaks 25 can be three or more.

[0135] Collector region 22 has a concentration peak of P-type dopant. The P-type dopant is, for example, boron, but is not limited to this. The value of the concentration peak of collector region 22 is set as C1. Concentration C1 can also be the doping concentration value at the location in contact with the lower surface 23.

[0136] Figure 5 This is an enlarged view of the doping concentration distribution in buffer 20. Buffer 20 has a first concentration peak 25-1, a second concentration peak 25-2, and a high concentration peak 25-4.

[0137] The first concentration peak 25-1 is the concentration peak 25 closest to the lower surface 23 in the depth direction. The first concentration peak 25-1 can be the peak with the largest doping concentration P1 among multiple concentration peaks 25. It should be noted that the doping concentration of each concentration peak 25 is the doping concentration at the vertex of the doping concentration distribution. The doping concentration P1 can be 1.0 × 10⁻⁶. 15 / cm 3 The above can also be 5.0 × 10 15 / cm 3 The above can also be 1.0×10 16 / cm 3 That's all. By making the doping concentration P1 high, it is possible to suppress the depletion layer extending from the lower end of the base region 14 to the collector region 22.

[0138] The doping concentration P1 of the first concentration peak 25-1 can be more than 0.1 times and less than 10 times the doping concentration C1 of the collector region 22. The doping concentration P1 can be more than 0.2 times the doping concentration C1, more than 0.5 times the doping concentration C1, or more than 1 times the doping concentration C1. The doping concentration P1 can be less than 5 times the doping concentration C1, less than 2 times the doping concentration C1, less than 1 times the doping concentration C1, or less than 0.5 times the doping concentration C1.

[0139] The effective dose of the dopant of the second conductivity type in collector region 22 can be 8 × 10⁻⁶. 12 / cm 2The effective dose refers to the integral value obtained by integrating the doping concentration over a predetermined depth range. The effective dose of collector region 22 is the integral value of the doping concentration from the pn junction between the region outside collector region 22 and collector region 22 to the exposed lower surface 23 of collector region 22. The effective dose can be the same as or smaller than the implantation dose of the dopant ion implantation. In this example, it is approximately the same. This effective dose can be calculated by integrating the doping concentration in collector region 22 over the range from the lower surface 23 to the pn junction with the buffer layer, or by multiplying the full width at half maximum (FWHM) by the doping concentration of the peak. This dose can be 6 × 10⁻⁶. 12 / cm 2 The following can be 5×10 12 / cm 2 The following can be 3×10 12 / cm 2 The following can be 2×10 12 / cm 2 The following can also be 1×10 12 / cm 2 Below. On the other hand, from the viewpoint of reducing the deviation of the conduction voltage, this dose can be 3×10. 11 / cm 2 The above can be 5×10 11 / cm 2 The above can be 8×10 11 / cm 2 The above can also be 1×10 12 / cm 2 The depth of the collector region 22 can be greater than 0.1 μm and less than 0.5 μm.

[0140] The depth position Z1 of the first concentration peak 25-1 can be configured at a position less than 4 μm from the lower surface 23, less than 3 μm from the lower surface 23, or less than 2 μm from the lower surface 23. When the thickness of the semiconductor substrate 10 in the depth direction is set to T (μm), the distance between the depth position Z1 and the lower surface 23 can be less than 0.04 × T, less than 0.03 × T, or less than 0.02 × T.

[0141] The second concentration peak 25-2 is a concentration peak 25 that is second only to the first concentration peak 25-1 in the depth direction and close to the lower surface 23. The depth position Z2 of the second concentration peak 25-2 is configured to be 5 μm or more from the lower surface 23 in the depth direction of the semiconductor substrate 10. The depth position Z2 can be configured to be 7 μm or more from the lower surface 23, or it can be configured to be 10 μm or more from the lower surface 23. In addition, when the thickness in the depth direction of the semiconductor substrate 10 is set to T (μm), the depth position Z2 can be configured to be 0.05 × T or more from the lower surface 23, or it can be configured to be 0.07 × T or more from the lower surface 23, or it can be configured to be 0.1 × T or more from the lower surface 23.

[0142] The doping concentration P2 of the second concentration peak 25-2 is lower than the doping concentration P1 of the first concentration peak 25-1. Specifically, the doping concentration P2 is less than 1.0 × 10⁻⁶. 15 / cm 3 The doping concentration P2 can be 7.0 × 10⁻⁶. 14 / cm 3 The following can also be 5.0×10 14 / cm 3 The doping concentration P2 can be less than 0.1 times the doping concentration P1 of the first concentration peak 25-1. Alternatively, the doping concentration P2 can be less than 0.07 times or less than 0.05 times the doping concentration P1 of the first concentration peak 25-1.

[0143] If the doping concentration P2 of the second concentration peak 25-2 is high, the slope dVce / dt of the collector-emitter voltage Vce time waveform will increase when the depletion layer reaches the second concentration peak 25-2 at the time the semiconductor device 100 is turned off. At the time the depletion layer reaches the second concentration peak 25-2, there is a situation where Vce is approximately equal to the supply voltage Vcc. If dVce / dt increases when Vce is sufficiently high, the latch-up tolerance at room temperature will decrease. Latch-up tolerance is the collector current that prevents latch-up in the semiconductor device 100 at the upper limit of its capacity. In this example, by making the doping concentration P2 less than 1.0 × 10⁻⁶... 15 / cm 3 This can suppress the increase of dVce / dt when the depletion layer reaches the second concentration peak 25-2, and improve latch-up tolerance.

[0144] The high-concentration peak 25-4 is configured to be further away from the lower surface 23 than the second concentration peak 25-2. That is, the high-concentration peak 25-4 is positioned closer to the upper surface 21 than the second concentration peak 25-2. The doping concentration P4 of the high-concentration peak 25-4 is higher than the doping concentration P2 of the second concentration peak 25-2. However, the doping concentration P4 of the high-concentration peak 25-4 is lower than the doping concentration P1 of the first concentration peak 25-1. By setting the high-concentration peak 25-4, even if the doping concentration P2 of the second concentration peak 25-2 is reduced, the integral value of the doping concentration in the buffer 20 can be easily maintained. Therefore, the function of suppressing the expansion of the depletion layer can be maintained in the buffer 20.

[0145] The doping concentration P4 can be less than 1.0 × 10⁴. 15 / cm 3 The doping concentration P4 can be 8.0 × 10⁴. 14 / cm 3 The following can also be 6.0×10 14 / cm 3 The doping concentration P4 can be less than 0.1 times the doping concentration P1 of the first concentration peak 25-1. Alternatively, the doping concentration P4 can be less than 0.08 times or less than 0.06 times the doping concentration P1 of the first concentration peak 25-1.

[0146] Furthermore, since the high concentration peak 25-4 is positioned further up the surface 21 than the second concentration peak 25-2, the expansion of the depletion layer can be further suppressed on the upper surface 21 side. Additionally, as described later, the concentration peak 25, which is closer to the base region 14 where the depletion layer expands, has a smaller impact on dVce / dt when the depletion layer reaches its peak. Therefore, by positioning the high concentration peak 25-4 further up the surface 21 than the second concentration peak 25-2, the increase in dVce / dt can also be suppressed.

[0147] The high-concentration peak 25-4 can be the concentration peak furthest from the lower surface 23 among the multiple concentration peaks 25 in the buffer zone 20. In this case, the high-concentration peak 25-4 can contact the drift region 18. The depth position Z4 of the high-concentration peak 25-4 can be configured to be 15 μm or more from the lower surface 23, or 20 μm or more from the lower surface 23, or 25 μm or more from the lower surface 23. When the thickness in the depth direction of the semiconductor substrate 10 is set to T (μm), the depth position Z4 can be configured to be 0.15 × T or more from the lower surface 23, or 0.2 × T or more from the lower surface 23, or 0.25 × T or more from the lower surface 23. It should be noted that the depth position Z4 can be configured on the side of the lower surface 23 of the semiconductor substrate 10. That is, the depth position Z4 can be configured between the lower surface 23 and the depth position Zc. The distance between depth position Z4 and lower surface 23 can be less than 40 μm or less than 30 μm. The distance between depth position Z4 and lower surface 23 can be less than 0.4 × T or less than 0.3 T.

[0148] More than one concentration peak 25 can be set between the second concentration peak 25-2 and the high concentration peak 25-4. Figure 5 In the example, a third concentration peak 25-3 is positioned between the second concentration peak 25-2 and the high concentration peak 25-4. The high concentration peak 25-4 can be the peak with the highest doping concentration among the multiple concentration peaks 25, excluding the first concentration peak 25-1. That is, the doping concentration P3 of the third concentration peak 25-3 is lower than the doping concentration P4 of the high concentration peak 25-4. The doping concentration P3 of the third concentration peak 25-3 can be lower than or higher than the doping concentration P2 of the second concentration peak 25-2.

[0149] The depth position Z3 of the third concentration peak 25-3 can be configured to be 10 μm or more from the lower surface 23, or it can be configured to be 15 μm or more from the lower surface 23. When the thickness of the semiconductor substrate 10 in the depth direction is set to T (μm), the depth position Z3 can be configured to be 0.1 × T or more from the lower surface 23, or it can be configured to be 0.15 × T or more from the lower surface 23. The distance between the depth position Z3 and the lower surface 23 can be 25 μm or less, or it can be 20 μm or less. The distance between the depth position Z3 and the lower surface 23 can be 0.25 × T or less, or it can be 0.2 × T or less.

[0150] The distance (|Z2-Z1|) between depth positions Z2 and Z1 of the second concentration peak 25-2 can be larger than the distance (|Z3-Z2|) between depth positions Z2 and Z3. That is, the second concentration peak 25-2 can be positioned closer to the third concentration peak 25-3 between the first concentration peak 25-1 and the third concentration peak 25-3. Furthermore, the distance between depth positions Z3 and Z4 of the third concentration peak 25-3 can be larger than the distance between depth positions Z3 and Z2. That is, the third concentration peak 25-3 can be positioned closer to the second concentration peak 25-2 between the second concentration peak 25-2 and the high concentration peak 25-4. Thus, the concentration peak 25 that makes it easier for dVce / dt to increase can be positioned further away from other concentration peaks 25.

[0151] The doping concentration of each concentration peak 25 in the buffer 20, except for the first concentration peak 25-1, can be less than 1.0 × 10⁻⁶. 15 / cm 3 Therefore, the increase in the slope of dVce / dt at concentration peak 25, excluding the first concentration peak 25-1, can be suppressed. The doping concentration of concentration peak 25, excluding the first concentration peak 25-1, can be 0.9 × 10⁻⁶. 15 / cm 3 The following can be 0.8 × 10 15 / cm 3 The following can be 0.7 × 10 15 / cm 3 The following can be 0.6 × 10 15 / cm 3 The following can also be 0.5×10 15 / cm 3 the following.

[0152] In addition, the doping concentration of concentration peak 25, other than the first concentration peak 25-1, can be 3.0 × 10⁻⁶. 14 / cm 3 The above describes how maintaining the depletion layer expansion suppression function in buffer 20 becomes easier by ensuring that the doping concentration of each concentration peak 25 is above a certain level. The doping concentration of concentration peaks 25 other than the first concentration peak 25-1 can be 4.0 × 10⁻⁶. 14 / cm 3 The above can also be 5.0 × 10 14 / cm 3 The above. As an example, the doping concentration of peak 25, excluding the first concentration peak 25-1, is 3.0 × 10⁻⁶. 14 / cm 3 Above and 5.0×10 14 / cm 3 the following.

[0153] The doping concentration P2 of the second concentration peak 25-2 can be 0.6 times or more but less than 0.8 times the doping concentration P4 of the high concentration peak 25-4. The doping concentration P3 of the third concentration peak 25-3 can be 0.4 times or more but less than 0.6 times the doping concentration P4 of the high concentration peak 25-4. By maintaining the doping concentration of the concentration peaks 25 other than the high concentration peak 25-4 at a certain level, it becomes easier to suppress the expansion of the depletion layer. In addition, by maintaining the doping concentration of the concentration peaks 25 other than the high concentration peak 25-4 at a certain level, it is possible to suppress the increase in the slope of dVce / dt.

[0154] It should be noted that the doping concentration distribution in buffer 20 has a lower tail 27 where the doping concentration decreases from each concentration peak 25 toward the lower surface 23, and an upper tail 28 where the doping concentration decreases from each concentration peak 25 toward the upper surface 21. Figure 5 In the figure, the second concentration peak 25-2 is marked with the symbols 27 for the lower tail and 28 for the upper tail, but other concentration peaks 25 also have the symbols 27 for the lower tail and 28 for the upper tail.

[0155] In this example, concentration peak 25 is formed by ion implantation of N-type dopants such as hydrogen from the lower surface 23. In this case, N-type dopants are more abundant in the region between the implantation site and the lower surface 23 compared to the region between the implantation site and the upper surface 21. Therefore, the lower tail 27 of the doping concentration distribution in this example decreases in doping concentration more gradually than the upper tail 28.

[0156] Figure 6 This is another example of the doping concentration distribution in buffer 20. In this example, the region where the doping concentration reaches a minimum between the concentration peaks 25 is called valley 26. The doping concentration distribution excluding valley 26 can be compared with... Figure 5 The examples are the same, but they can also be different. Between the first concentration peak 25-1 and the second concentration peak 25-2, at depth Z... V1 The location is configured with the first valley 26-1 of concentration V1, between the second concentration peak 25-2 and the third concentration peak 25-3, at depth Z. V2 The location is configured with the second valley 26-2 of concentration V2, between the third concentration peak 25-3 and the high concentration peak 25-4, at depth Z. V3 The location is configured with the third valley 26-3 of concentration V3. It should be noted that this can be achieved between the high concentration peak 25-4 and the drift region 18, at depth Z. V3 In the direction toward the upper surface 21, where the doping concentration is approximately equal to the bulk donor concentration N B The initial position Zd is configured with the fourth valley 26-4.

[0157] The doping concentrations V1, V2, and V3 of each valley 26 can be 1.0 × 10⁻⁶. 14 / cm 3 The above. By maintaining a relatively high doping concentration in valley 26, it becomes easier to maintain the total dose in buffer 20 and thus maintain the depletion layer expansion suppression function, even if the doping concentration P2 of the second concentration peak 25-2 is reduced. The magnitude and ratio of the doping concentrations of each concentration peak 25 in this example, as well as their depth positions, can be compared with... Figure 5 The examples are the same.

[0158] The effective dose N2 of the second concentration peak 25-2 is lower than the effective dose N1 of the first concentration peak 25-1. Specifically, the effective dose N2 is less than 2.0 × 10⁻⁶. 11 / cm 2 The effective dose N2 can be 1.5 × 10⁻⁶. 11 / cm 2 The following can also be 1.0×10 11 / cm 2 The effective dose N2 can be less than 0.1 times the effective dose N1 of the first concentration peak 25-1. The effective dose N2 can be less than 0.07 times or less than 0.05 times the effective dose N1 of the first concentration peak 25-1. The effective dose Nn of the nth concentration peak 25-n can be located at position Z of the valley 26-(n-1) between the (n-1)th peak adjacent to the lower surface 23. Vn-1 Position Z of the valley 26-n between the (n+1)th peak adjacent to the upper surface 21 side Vn The integral value is obtained by integrating the doping concentration between these points. However, the effective dose NL of the concentration peak 25-L on the uppermost surface 21 side can be located at position Z from the valley 26-(L-1). VL-1 The integral value is obtained by integrating the doping concentration between position Zd and position L. L represents the Lth peak. L can be greater than 1; in this example, L is 4.

[0159] Figure 7 This is a diagram illustrating another example of the doping concentration distribution in buffer 20. In this example of buffer 20, the doping concentrations V1, V2, and V3 of each valley 26 are higher than... Figure 6 The example is high. In this example, the doping concentrations V1, V2, and V3 in valley 26 are all 2.0 × 10⁻⁶. 14 / cm 3 Above and 5.0×10 14 / cm 3 Therefore, it becomes easier to suppress the expansion of the depletion layer.

[0160] In this example, the doping concentration of peak 25, excluding the first concentration peak 25-1, can be 3.0 × 10⁻⁶. 14 / cm 3 Above and 6.0×10 14 / cm 3 The doping concentration of peak 25 (excluding the first concentration peak 25-1) and all valleys 26 is 2.0 × 10⁻⁶. 14 / cm 3 Above and 6.0×10 14 / cm 3 The following is a summary of the following: Therefore, it is possible to reduce the doping concentration of concentration peaks 25 other than the first concentration peak 25-1, thereby suppressing the increase of dVce / dt, and to maintain the dose of buffer 20, thereby suppressing the expansion of the depletion layer. The magnitude and ratio of the doping concentrations of each concentration peak 25 in this example, as well as their depth positions, can be compared with... Figure 5 The examples are the same.

[0161] In this example, a high doping concentration in the valley 26 is maintained by maximizing the full width at half maximum (FWHM) of each concentration peak 25. The shape of the concentration peaks 25 depends on the distribution of the N-type dopant obtained from ion implantation from the lower surface 23. For example, if an absorber is placed on the lower surface 23 and hydrogen ions are implanted with high acceleration energy, the range deviation of the hydrogen ions increases, and the FWHM of the chemical concentration distribution of the implanted hydrogen increases. By doing so, it is possible to obtain... Figure 7 The doping concentration distribution is as shown.

[0162] Figure 8 This is another example of the doping concentration distribution in buffer 20. In this example, the full width at half maximum (FWHM1) of the first concentration peak 25-1 is set as FWHM2, the full width at half maximum (FWHM2) of the second concentration peak 25-2 is set as FWHM3, the full width at half maximum (FWHM3) of the third concentration peak 25-3 is set as FWHM4, and the full width at half maximum (FWHM4) of the high concentration peak 25-4 is set as FWHM4.

[0163] Generally, the greater the distance between the concentration peak 25 and the lower surface 23, the greater the ion implantation range, and therefore the larger the full width at half maximum (FWHM). In this example, the FWHM2 of the second concentration peak 25-2 is larger than the FWHM4 of the high concentration peak 25-4. Therefore, even if the doping concentration P2 of the second concentration peak 25-2 is reduced, the integral value of the doping concentration near the second concentration peak 25-2 can still be large. Thus, the expansion of the depletion layer is easily suppressed. The FWHM2 can be more than twice, more than three times, or more than four times the FWHM4. As described above, by providing an absorber on the lower surface 23 and implanting hydrogen ions with high acceleration energy during the formation of the second concentration peak 25-2, the FWHM2 can be increased. In the formation of other concentration peaks 25, the absorber may not be provided on the lower surface 23.

[0164] The full width at half maximum (FWHM2) of the second concentration peak 25-2 can be larger than the FWHM of any other concentration peak 25. The FWHM2 of the second concentration peak 25-2 relative to the largest FWHM among the other concentration peaks 25 can be more than 2 times, more than 3 times, or more than 4 times. The doping concentration distribution other than the FWHM2 of the second concentration peak 25-2 is similar to... Figures 5 to 7 The same as any of the examples described herein.

[0165] Figure 9 This is a graph showing the doping concentration distribution in buffer 20 of the comparative example. In this example, the doping concentration P2 of the second concentration peak 25-2 is greater than 1.0 × 10⁻⁶. 15 / cm 3 In addition, the doping concentration P4 of the high concentration peak 25-4 is about 10% to 20% of the doping concentration P2 of the second concentration peak 25-2.

[0166] Figure 10 This is a graph showing the doping concentration distribution in buffer 20 of the comparative example. In this example, although the doping concentration P2 of the second concentration peak 25-2 is less than 1.0 × 10⁻⁶, the doping concentration P2 is still relatively high. 15 / cm 3 However, the doping concentration P4 of the high concentration peak 25-4 is less than the doping concentration P2 of the second concentration peak 25-2.

[0167] Figure 11 This is a diagram illustrating an example of the time waveforms of the collector-emitter voltage Vce and collector current when a semiconductor device is turned off. The semiconductor device in this example has… Figure 9 The doping concentration distribution of the comparative examples shown.

[0168] If the semiconductor device is turned off, the collector current decreases, and the collector-emitter voltage Vce increases. Additionally, the depletion layer extends from the base region 14 (see reference 14). Figure 3 The slope gradually expands from the lower end of the depletion layer 25. At the moment the depletion layer reaches each concentration peak 25, dVce / dt temporarily increases. The larger the value of Vce, the more significant the increase in the slope of dVce / dt. The closer the depletion layer is to the lower surface 23, the larger the value of Vce. Therefore, if the concentration peak 25 with a high doping concentration is located near the lower surface 23, dVce / dt increases significantly at the moment the depletion layer reaches that concentration peak 25.

[0169] exist Figure 11 In the comparative example, the doping concentration of the second concentration peak 25-2 is high. Therefore, at the moment t2 when the depletion layer reaches the second concentration peak 25-2, the slope of the collector-emitter voltage, dVce / dt, increases significantly. Consequently, the semiconductor device in the comparative example becomes prone to latch-up. Figure 11 In the diagram, an enlarged view of the time waveform of the collector-emitter voltage Vce near time t2 is shown within the dashed circle.

[0170] In contrast, Figures 5 to 8 In the semiconductor device 100 shown, the doping concentration of the second concentration peak 25-2 is reduced. Therefore, the semiconductor device 100 can suppress the increase in dVce / dt when the depletion layer reaches the second concentration peak 25-2. Furthermore, by setting a high concentration peak 25-4 with a relatively large doping concentration, the depletion layer expansion suppression function is maintained, and since the high concentration peak 25-4 is located away from the lower surface 23, the increase in dVce / dt when the depletion layer reaches the high concentration peak 25-4 can also be suppressed. Thus, the semiconductor device 100 can improve latch-up tolerance. It should be noted that... Figure 11 The voltage waveform in the embodiment is represented by the dashed waveform and the dashed waveform within the circle. The voltage waveform for the time not drawn with dashed lines in the embodiment is the same as the solid line in the comparative example.

[0171] Figure 12 This is a diagram illustrating an example of the latch-up tolerance of a semiconductor device in a comparative example and an embodiment. Figure 12 The latch-up withstand capability is the latch-up withstand capability at room temperature. The semiconductor device of Comparative Example 1 has... Figure 9 The doping concentration distribution shown indicates that the semiconductor device in Comparative Example 2 has... Figure 10 The doping concentration distribution shown indicates that the semiconductor device 100 of Example 1 has... Figure 5 The doping concentration distribution shown indicates that the semiconductor device 100 of Example 2 has... Figure 6 The doping concentration distribution is shown.

[0172] like Figure 9As shown, the high concentration peak 25-4 in Comparative Example 1 has a low doping concentration. Therefore, the depletion layer easily reaches the second concentration peak 25-2, which has a high doping concentration. In addition, since the second concentration peak 25-2 has a high doping concentration, dVce / dt easily increases, and the latch-up tolerance decreases.

[0173] like Figure 10 As shown, in Comparative Example 2, although the doping concentration of the second concentration peak 25-2 is low, the doping concentration of the high concentration peak 25-4 is even lower than that of the second concentration peak 25-2. Therefore, the depletion layer easily reaches the second concentration peak 25-2, and the latch-up tolerance is slightly reduced.

[0174] like Figure 5 and Figure 6 As shown, the doping concentration of the high-concentration peak 25-4 in Examples 1 and 2 is higher than that of the second-concentration peak 25-2. Therefore, it is possible to suppress the depletion layer from reaching the second-concentration peak 25-2. Furthermore, even when the depletion layer reaches the second-concentration peak 25-2, the increase in dVce / dt is suppressed due to the low doping concentration of the second-concentration peak 25-2. Therefore, the latch-up tolerance can be increased. It should be noted that in... Figure 7 as well as Figure 8 In the example shown, the latching tolerance can also be improved compared to Comparative Examples 1 and 2.

[0175] In order to reduce switching losses, semiconductor devices 100 used for high-frequency operation sometimes set the doping concentration of the collector region 22 to a low level. For example, the doping concentration of the collector region 22 of semiconductor device 100 is 7.0 × 10⁻⁶. 16 / cm 3 The doping concentration of collector region 22 can be 1.0 × 10⁻⁶. 16 / cm 3 The above can also be 6.0 × 10 16 / cm 3 above.

[0176] The latch-up tolerance of semiconductor device 100 is typically higher at room temperature than at high temperature. However, if the doping concentration of collector region 22 is reduced, the latch-up tolerance at room temperature becomes lower than that at high temperature. This phenomenon occurs because reducing the doping concentration of collector region 22 decreases the amount of carrier injection from collector region 22, resulting in a larger dVce / dt at room temperature compared to that at high temperature.

[0177] Increasing the doping concentration of collector region 22 can improve latch-up tolerance at room temperature. However, the increased carrier injection from collector region 22 leads to increased switching losses. Therefore, in high-frequency applications, it is particularly difficult to balance the suppression of switching losses with the improvement of latch-up tolerance at room temperature. The semiconductor device 100 in this example can improve latch-up tolerance at room temperature without increasing the doping concentration of collector region 22.

[0178] Figure 13 This is another example of the doping concentration distribution in buffer 20. In this example, the full width at half maximum (FWHM) of each concentration peak 25 in buffer 20 is... Figures 1 to 12 The examples described in the text differ. Other structures can be compared with... Figures 1 to 12 The buffer 20 described herein may be the same or different.

[0179] In this example, the full width at half maximum (FWHM4) of the high-concentration peak 25-4 is more than twice the FWHM1 of the first concentration peak 25-1. The FWHM4 can be more than four times or more than ten times the FWHM1. By increasing the FWHM4 of the high-concentration peak 25-4 near the upper surface 21 of the semiconductor substrate 10, the integral value of the doping concentration at the high-concentration peak 25-4 can be increased. Therefore, high latch-up tolerance at room temperature is achieved. Furthermore, even when the peak concentration of the high-concentration peak 25-4 is reduced, the integral value of the doping concentration at the high-concentration peak 25-4 is easily maintained. Therefore, reducing the peak concentration at the high-concentration peak 25-4 easily suppresses oscillations in the voltage or current waveform during a short circuit. It should be noted that a short circuit refers to a state where a voltage larger than that during normal operation is applied between the emitter electrode 52 and the collector electrode 24.

[0180] Furthermore, by reducing the full width at half maximum (FWHM1) of the first concentration peak 25-1, the formation of a high concentration of donors in the collector region 22 can be suppressed during the formation of the first concentration peak 25-1. Therefore, the influence of the doping concentration of the first concentration peak 25-1 on the doping concentration of the collector region 22 can be reduced, and the deviation of the Vce saturation voltage (Vce(sat)) of the IGBT in the ON state can be suppressed. Additionally, by reducing the FWHM1 of the first concentration peak 25-1, even if the first concentration peak 25-1 is formed near the lower surface 23, the influence on the doping concentration of the collector region 22 can be suppressed. Therefore, it is easier to form the first concentration peak 25-1 near the lower surface 23, and the generation of back-side avalanche breakdown is easily suppressed.

[0181] It should be noted that the portion where the doping concentration becomes a minimum in the doping concentration distribution is designated as a valley. When the doping concentration of a valley adjacent to concentration peak 25 is more than half the maximum doping concentration of that concentration peak 25, this valley can be designated as the end of the full width at half maximum (FWHM). For example, when the doping concentrations of both valleys surrounding concentration peak 25 are more than half the maximum doping concentration of that concentration peak 25, the interval between these two valleys can be designated as the FWHM of that concentration peak 25. Furthermore, when the doping concentration of drift region 18 is more than half the doping concentration P4 of high concentration peak 25-4, the boundary position between drift region 18 and high concentration peak 25-4 can be designated as the upper end of the FWHM4. The boundary position between drift region 18 and high concentration peak 25-4 is the position where the doping concentration of high concentration peak 25-4 and the doping concentration of drift region 18 initially become the same in the direction from depth position Z4 toward the upper surface 21 of semiconductor substrate 10.

[0182] Furthermore, the full width at half maximum (FWHM2) of the second concentration peak 25-2 can be more than twice, more than four times, or more than ten times that of the first concentration peak 25-1. By increasing the FWHM2 of the second concentration peak 25-2, the latch-up tolerance at room temperature can be further improved.

[0183] Furthermore, the full width at half maximum (FWHM3) of the third concentration peak 25-3 can be more than twice, more than four times, or more than ten times that of the first concentration peak 25-1. Increasing the FWHM3 of the third concentration peak 25-3 further improves the latch-up withstand capability at room temperature. Additionally, it makes it easier to suppress oscillations in the voltage or current waveform during short circuits.

[0184] All concentration peaks 25 in buffer zone 20, except for the first concentration peak 25-1, can have a full width at half maximum (FWHM1) of more than twice, more than four times, or more than ten times FWHM1. Furthermore, the greater the distance from the lower surface 23, the larger the FWHM of the concentration peaks 25 in buffer zone 20 can be.

[0185] The full width at half maximum (FWHM) of each concentration peak 25 can be controlled, for example, by using different types of devices to implant hydrogen ions at different depths. For example, when using a cyclotron-type implantation device, the FWHM of concentration peak 25 is relatively large. Furthermore, when using this implantation device, if the accelerating voltage increases, the FWHM also increases. The first concentration peak 25-1 can be implanted using a non-cyclotron-type implantation device. At least one of the concentration peaks 25 other than the first concentration peak 25-1 can be implanted using a cyclotron-type implantation device.

[0186] The doping concentration of the second concentration peak 25-1, where the slope towards the lower surface 23 is extended to the lower surface 23, is preferably below the doping concentration of the drift region 18. Furthermore, it is preferable that the full width at half maximum (FWHM2) of the second concentration peak 25-2 and the full width at half maximum (FWHM3) of the third concentration peak 25-3 are separated in the depth direction. Additionally, it is preferable that the full width at half maximum (FWHM3) of the third concentration peak 25-3 and the full width at half maximum (FWHM4) of the high concentration peak 25-4 are separated in the depth direction.

[0187] As an example, the full width at half maximum (FWHM) of the second concentration peak 25-2 and the third concentration peak 25-3 is 3 μm or more and 4 μm or less. The FWHM of the high concentration peak 25-4 is 4 μm or more and 6 μm or less. Furthermore, the acceleration energy of hydrogen ions for the formation of the second concentration peak 25-2 and the third concentration peak 25-3 can be 2.2 MeV or more and 2.7 MeV or less. The acceleration energy of hydrogen ions for the formation of the high concentration peak 25-4 can be 2.7 MeV or more and 3.6 MeV or less.

[0188] exist Figure 13 In the example, the doping concentration P4 of the high concentration peak 25-4 is less than the doping concentration P2 of the second concentration peak 25-2. As an example, the doping concentration P4 can be less than 70% of the doping concentration P2, less than 50% of the doping concentration P2, or less than 30% of the doping concentration P2.

[0189] Furthermore, the doping concentration P3 of the third concentration peak 25-3 can be lower than the doping concentration P4. The relative relationship between doping concentration P4 and doping concentration P3 can be compared with... Figures 1-12 The example described is the same. The doping concentration P3 is less than the doping concentration P2 of the second concentration peak 25-2. As an example, the doping concentration P3 can be less than 70% of the doping concentration P2, less than 50% of the doping concentration P2, or less than 30% of the doping concentration P2.

[0190] Furthermore, the doping concentration P2 of the second concentration peak 25-2 can be less than 20% of the doping concentration P1 of the first concentration peak 25-1, or less than 10% of the doping concentration P1 of the first concentration peak 25-1. The doping concentration P2 can be more than 1% of the doping concentration P1, or more than 5% of the doping concentration P1. The dose at each concentration peak 25 can be related to... Figures 1 to 12 The example described is the same. Furthermore, the depth position Z2 of the second concentration peak 25-2 can be located further down the lower surface 23 than the center of the second concentration peak 25-2, or it can be located further up the upper surface 21 than the center of the second concentration peak 25-2. It should be noted that the center of a peak refers to the center of its full width at half maximum (FWHM). The depth position of a peak refers to the position of its apex (maximum). In this example, the depth position Z2 of the second concentration peak 25-2 is located further down the lower surface 23 than the center of the second concentration peak 25-2. Similarly, the depth positions Z3 of the third concentration peak 25-3 and Z4 of the fourth concentration peak 25-4 can also be located further down the lower surface 23 than the center of their respective peaks, or they can be located further up the upper surface 21 than the center of their respective peaks, just like the depth position Z2 of the second concentration peaks.

[0191] Figure 14 This is an enlarged view of the high-concentration peak 25-4. In this example, the high-concentration peak 25-4 has a flat portion 141 where the doping concentration distribution is flat along the depth direction. The flat portion 141 is configured to cover a predetermined depth range, including the depth position where the doping concentration shows a maximum value (Z4 in this example). The length of the flat portion 141 along the depth direction can be 1 μm or more, 2 μm or more, 3 μm or more, or 5 μm or more. Furthermore, the flat portion refers to a continuous region where the doping concentration is below the maximum value (P4 in this example) and above the lower limit concentration PL. The lower limit concentration PL can be 95% of the maximum doping concentration (P4 in this example), 90% of the maximum doping concentration (P4 in this example), 85% of the maximum doping concentration (P4 in this example), 80% of the maximum doping concentration (P4 in this example), or 70% of the maximum doping concentration (P4 in this example). This allows for a larger full width at half maximum (FWHM) of the high-concentration peak 25-4.

[0192] exist Figure 14 The example shown is that the high concentration peak 25-4 has a flat portion 141. At least one of the second concentration peak 25-2 and the third concentration peak 25-3 may also have a flat portion 141. Alternatively, all concentration peaks 25 except the first concentration peak 25-1 may have a flat portion 141.

[0193] Figure 15 This is a graph showing the relationship between the accelerating voltage of hydrogen ions and the avalanche breakdown voltage at which the first concentration peak 25-1 is formed. The higher the accelerating voltage of hydrogen ions, the greater the distance between the first concentration peak 25-1 and the lower surface 23. The avalanche breakdown voltage is the emitter-collector voltage that causes avalanche breakdown in the region near the buffer zone 20 of the semiconductor substrate 10. Furthermore, in Figure 15 The figure shows that the dose of acceptor ions when forming the current collector region 22 is 1.0 × 10⁻⁶. 13 ions / cm 2 The situation and 1.5×10 13 ions / cm 2 The results of the measurement.

[0194] like Figure 15 As shown, the closer the first concentration peak 25-1 is to the lower surface 23, the greater the avalanche breakdown voltage. Therefore, it is preferable to set the full width at half maximum (FWHM1) of the first concentration peak 25-1 to a small value. Thus, even if the first concentration peak 25-1 is positioned near the lower surface 23, its impact on the collector region 22 can be reduced.

[0195] Figure 16 This is another example of the doping concentration distribution in buffer 20. In this example, the full width at half maximum (FWHM) of each concentration peak 25 in buffer 20 is compared with... Figure 13 and Figure 14 The same as any example described. Furthermore, the doping concentrations P1 to P4 of each concentration peak 25 are... Figures 1 to 12 This is the same as any example described herein. According to this example, as in... Figures 1 to 15 As explained, this can improve latching resistance. According to this example, as in... Figures 13 to 15 As explained, it can increase avalanche breakdown voltage and suppress oscillations in voltage and current waveforms during short circuits.

[0196] Figure 17 This diagram illustrates a portion of the manufacturing process of the semiconductor device 100. The manufacturing method in this example includes a top surface side structure formation step S1501, an ion implantation step S1502, and a heat treatment step S1503.

[0197] In the upper surface side structure formation step S1501, a structure is formed on the upper surface 21 side of the semiconductor substrate 10. The semiconductor substrate 10 may be an N-type substrate. In this case, the area remaining where no other areas are formed is called the drift region 18. The structure on the upper surface 21 side may refer to a structure located on the upper surface 21 side further than the center of the depth position of the semiconductor substrate 10. The structure on the upper surface 21 side may include, for example, an emitter region 12, a base region 14, an accumulation region 16, a trench, etc. The structure on the upper surface 21 side may include various insulating films such as an interlayer insulating film 38 disposed above the upper surface 21 of the semiconductor substrate 10 and various conductive components such as an emitter electrode 52.

[0198] In ion implantation step S1502, hydrogen ions are implanted from the lower surface 23 of the semiconductor substrate 10, where the drift region 18 is provided, to three or more depth locations (e.g., depth locations Z1, Z2, Z3, Z4). Here, a first device is used to implant hydrogen ions to the first depth location (e.g., Z1) closest to the lower surface 23 of the semiconductor substrate 10 among the three or more depth locations. The first device is, for example, a non-cyclotron type device. Additionally, a second device, different from the first device, is used to implant hydrogen ions to the deepest depth location (e.g., Z4) farthest from the lower surface 23 among the three or more depth locations. The second device is one that, when implanting hydrogen ions at the same depth location with the same dose, has a larger full width at half maximum (FWHM) of the hydrogen chemical concentration distribution than the first device. The second device is, for example, a cyclotron type device. In S1502, the second device can be used to perform ion implantation to all depth locations (e.g., Z2, Z3, Z4) except for the first depth location (Z1). Either hydrogen ion implantation based on the first device or hydrogen ion implantation based on the second device can be performed first.

[0199] In heat treatment step S1503, the semiconductor substrate 10 is heat-treated to convert the hydrogen ions implanted into the buffer 20 into hydrogen donors. As a result, the buffer 20 has the ability to... Figures 13 to 16 The doping concentration distribution is described in the text.

[0200] The thickness of the semiconductor substrate 10 can be adjusted by grinding the lower surface 23 of the semiconductor substrate 10 before the heat treatment step S1503. The collector region 22 and the cathode region 82 can be formed before or after the heat treatment step S1503. The collector electrode 24 can be formed after the heat treatment step S1503. Through such processes, a semiconductor device 100 can be manufactured.

[0201] Figure 18 This is a diagram illustrating an example of the hydrogen chemical concentration distribution in buffer 20 after heat treatment step S1503. The hydrogen chemical concentration distribution is compared to... Figures 13 to 16The doping concentration distribution of buffer 20 described herein is the same. In this example, buffer 20 has multiple hydrogen concentration peaks 125-k. Hydrogen concentration peak 125-k corresponds to concentration peak 25-k. The corresponding hydrogen concentration peaks 125-k and 25-k can be positioned at the same depth. Positioning two peaks at the same depth can mean that the apex of one peak is positioned within the full width at half maximum (FWHM) of the other peak.

[0202] The relative relationship between the concentration values ​​and full width at half maximum (FWHM4) of hydrogen concentration peaks 125 and 25 is the same as that between the corresponding concentration peaks 25 and 25. For example, the FWHM4h of the hydrogen concentration peak 125-4 at the deepest depth (Z4 in this example) can be more than twice the FWHM1h of the hydrogen concentration peak 125-1 at the first depth (Z1 in this example), more than four times the FWHM1h of the hydrogen concentration peak 125-1 at the first depth (Z1 in this example), and more than ten times the FWHM1h of the hydrogen concentration peak 125-1 at the first depth (Z1 in this example).

[0203] Figure 19 This indicates that it was used in Figures 1 to 18 The diagram illustrates the power conversion device 1302 of the semiconductor device 100. The power conversion device 1302 converts the voltage, current, frequency, waveform, and other characteristics of the power supplied from the power source 1300 to supply power to the load 1304. The semiconductor device 100 in this example can be used as a power conversion device 1302 for high-frequency operation. For example, the semiconductor device 100 can be used as a power conversion device 1302 with a switching frequency (carrier frequency) of 10 kHz or higher. As an example of the application of the power conversion device 1302, an inverter circuit for a welding machine can be cited. The switching frequency of the semiconductor device 100 in the power conversion device 1302 can be 20 kHz or higher, or 30 kHz or higher. Alternatively, the switching frequency of the semiconductor device 100 in the power conversion device 1302 can be 200 kHz or lower, or 100 kHz or lower. It should be noted that the application of the high-frequency operating power conversion device is not limited to inverter circuits for welding machines. For example, it could be an inverter circuit for an uninterruptible power supply, an inverter circuit and / or boost converter circuit for the powertrain of an EV (electric vehicle) and / or an EHV (electric hybrid vehicle), an inverter circuit for an air conditioner, etc.

[0204] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0205] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, description, and drawings can be implemented in any order, as long as there is no explicit use of terms such as "before" or "before," and the output of previous processes is not used for subsequent processes. Even if terms such as "firstly" or "nextly" are used to describe the flow of actions in the claims, description, and drawings for convenience, it does not mean that the actions must be performed in that order.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate has an upper surface and a lower surface, and a drift region of a first conductivity type is provided thereon; A buffer of the first conductivity type is disposed between the drift region and the lower surface, and the doping concentration distribution of the buffer in the depth direction of the semiconductor substrate has more than three concentration peaks. as well as A collector region of the second conductivity type is disposed between the buffer zone and the lower surface. The three or more concentration peaks in the buffer include: The first concentration peak is closest to the lower surface; A second concentration peak, approaching the lower surface in a manner second only to the first concentration peak, is configured to be at least 5 μm away from the lower surface in the depth direction. The doping concentration of the second concentration peak is lower than that of the first concentration peak, and the doping concentration of the second concentration peak is less than 1.0 × 10⁻⁶. 15 / cm 3 ;as well as The high-concentration peak is configured to be further away from the lower surface than the second concentration peak, and the doping concentration of the high-concentration peak is higher than that of the second concentration peak. The buffer zone has valleys between the concentration peaks where the doping concentration reaches a minimum. The doping concentration of each valley is 2.0 × 10⁻⁶. 14 / cm 3 Above and 5.0×10 14 / cm 3 the following.

2. The semiconductor device according to claim 1, characterized in that, The dosage of the dopant of the second conductivity type in the collector region is 8 × 10⁻⁶. 12 / cm 2 the following.

3. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first concentration peak is more than 0.1 times and less than 10 times the doping concentration of the collector region.

4. The semiconductor device according to claim 1, characterized in that, The full width at half maximum (FWHM) of the second concentration peak is larger than that of at least one of the other concentration peaks.

5. The semiconductor device according to claim 4, characterized in that, The full width at half maximum (FWHM) of the second concentration peak is larger than that of the high concentration peak.

6. The semiconductor device according to claim 4, characterized in that, The full width at half maximum (FWHM) of the second concentration peak is larger than that of all other concentration peaks.

7. The semiconductor device according to claim 1, characterized in that, The full width at half maximum (FWHM) of the high concentration peak is more than twice that of the full width at half maximum (FWHM) of the first concentration peak.

8. The semiconductor device according to claim 1, characterized in that, The full width at half maximum (FWHM) of the second concentration peak is more than twice that of the full width at half maximum (FWHM) of the first concentration peak.

9. The semiconductor device according to claim 1, characterized in that, The buffer contains three or more concentration peaks, including a third concentration peak, which is positioned between the second concentration peak and the high concentration peak. The full width at half maximum (FWHM) of the third concentration peak is more than twice that of the full width at half maximum (FWHM) of the first concentration peak.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The high concentration peak has a flat portion, which includes the depth location where the doping concentration shows a maximum value, and the doping concentration distribution is flat in the depth direction.

11. The semiconductor device according to claim 9, characterized in that, The third concentration peak has a flat portion, which includes the depth location where the doping concentration shows a maximum value, and the doping concentration distribution is flat in the depth direction.

12. A semiconductor device, characterized in that, have: A semiconductor substrate has an upper surface and a lower surface, and a drift region of a first conductivity type is provided thereon; A first conductivity type buffer is disposed between the drift region and the lower surface, and the doping concentration distribution of the buffer in the depth direction of the semiconductor substrate has more than four concentration peaks. as well as A collector region of the second conductivity type is disposed between the buffer zone and the lower surface. The four or more concentration peaks in the buffer include: The first concentration peak is closest to the lower surface; A second concentration peak is configured to approach the lower surface in a manner second only to the first concentration peak; and The third concentration peak is configured to be closer to the upper surface than the second concentration peak; and A high concentration peak is positioned between the third concentration peak and the upper surface. The full width at half maximum (FWHM) of the second concentration peak is larger than that of the third concentration peak and the high concentration peak.

13. The semiconductor device according to claim 12, characterized in that, The high-concentration peak is configured to be closest to the upper surface among the four or more concentration peaks.

14. The semiconductor device according to claim 12, characterized in that, The third concentration peak is configured to approach the lower surface in a manner second only to the second concentration peak.

15. The semiconductor device according to claim 12, characterized in that, The full width at half maximum (FWHM) of the second concentration peak is larger than that of all other concentration peaks.

16. A semiconductor device, characterized in that, have: A semiconductor substrate has an upper surface and a lower surface, and a drift region of a first conductivity type is provided thereon; A buffer of the first conductivity type is disposed between the drift region and the lower surface, and the doping concentration distribution of the buffer in the depth direction of the semiconductor substrate has more than three concentration peaks. as well as A collector region of the second conductivity type is disposed between the buffer zone and the lower surface. The three or more concentration peaks in the buffer include: A first concentration peak is configured to be closest to the lower surface, and the doping concentration of the first concentration peak is more than 0.1 times and less than 10 times that of the collector region; and The upper surface concentration peak is configured to be closer to the upper surface than the first concentration peak, and the doping concentration of the upper surface concentration peak is less than 0.1 times that of the first concentration peak.

17. The semiconductor device according to claim 16, characterized in that, The upper surface concentration peak is configured to approach the lower surface in a manner second only to the first concentration peak.

18. A power conversion device, characterized in that, A carrier frequency of 10 kHz or higher and comprising a semiconductor device according to any one of claims 1 to 17.

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