Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a dummy gate structure on the substrate; forming a sacrificial layer on the substrate between adjacent dummy gate structures, the top surface of the sacrificial layer being flush with the top surface of the dummy gate structure; forming a mask layer on the sacrificial layer in the first region, the mask layer having a first projection on the substrate, the sacrificial layer having a second projection on the substrate, the first projection being located in the second projection, and the area of ​​the first projection being smaller than the area of ​​the second projection; etching and removing the sacrificial layer and a portion of the thickness of the substrate exposed by the mask layer; removing the mask layer and the remaining sacrificial layer; etching the substrate between adjacent dummy gate structures to form a first trench in the first region; and forming an epitaxial layer in the first trench. The formation method provided by the embodiment of the present invention can form a full epitaxial layer, which is beneficial to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] When preparing semiconductor devices, it is often necessary to epitaxially grow two different semiconductor materials in different areas of a semiconductor substrate. For example, it is often necessary to epitaxially grow two different semiconductor materials in the source and drain of NMOS and PMOS. Before epitaxially growing the semiconductor material, it is necessary to form a trench in the substrate between adjacent gate structures, and the semiconductor material is epitaxially grown along the surface of the trench.

[0003] However, in long channel devices and short channel devices, due to the different distances between adjacent gate structures, the width and shape of the formed trenches are also different. The trench width in the long channel region is greater than that in the short channel region. When epitaxially growing semiconductor materials, it is easy to cause the semiconductor materials in the long channel region to grow insufficiently. When contact holes are subsequently formed on the source and drain, the contact holes are easy to penetrate the epitaxial layer in the long channel region, causing the metal layer in the contact hole to be directly connected to the substrate, forming a Schottky contact, which can easily cause the semiconductor device to fail.

[0004] Therefore, there is an urgent need to provide a method for forming a semiconductor structure, which can make the epitaxial layer in the long channel region grow fully and avoid the contact hole penetrating through the epitaxial layer and directly contacting the substrate, which is conducive to improving the performance of the semiconductor structure. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can make the epitaxial layer in the long channel region grow fully, thereby facilitating the improvement of the performance of the semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a dummy gate structure on the substrate; forming a sacrificial layer on the substrate between adjacent dummy gate structures, the top surface of the sacrificial layer being flush with the top surface of the dummy gate structure; forming a mask layer on the sacrificial layer in the first region, the mask layer having a first projection on the substrate, the sacrificial layer having a second projection on the substrate, the first projection being located in the second projection, and the area of ​​the first projection being smaller than the area of ​​the second projection; etching and removing the sacrificial layer and a portion of the thickness of the substrate exposed by the mask layer; removing the mask layer and the remaining sacrificial layer; etching the substrate between adjacent dummy gate structures to form a first trench in the first region; and forming an epitaxial layer in the first trench.

[0007] Optionally, after forming the epitaxial layer in the first trench, the method further includes: forming a contact hole exposing the top surface of the epitaxial layer; and forming a conductive layer in the contact hole.

[0008] Optionally, before forming a contact hole exposing the top surface of the epitaxial layer, the method further includes: forming a first dielectric layer on the substrate, wherein the first dielectric layer exposes the top of the pseudo gate structure; removing the pseudo gate structure to form a gate opening; forming a gate structure in the gate opening; and forming a second dielectric layer on the first dielectric layer and the gate structure, wherein the contact hole is located in the first dielectric layer and the second dielectric layer.

[0009] Optionally, the center point of the first projection coincides with the center point of the second projection.

[0010] Optionally, the step of forming the mask layer includes: forming an initial mask layer on the dummy gate structure and the sacrificial layer; and patterning the initial mask layer to remove a portion of the initial mask layer to form a mask layer.

[0011] Optionally, the sacrificial layer is a bottom anti-reflection layer or an organic dielectric layer.

[0012] Optionally, the material of the epitaxial layer includes silicon phosphide, silicon germanium or silicon arsenide.

[0013] Optionally, the process of forming the epitaxial layer includes an epitaxial growth process.

[0014] Optionally, the process of etching away the sacrificial layer exposed by the mask layer and a partial thickness of the substrate is a dry etching process.

[0015] Optionally, the process for removing the mask layer is a dry etching process, and the process for removing the remaining sacrificial layer is a wet etching process.

[0016] Optionally, the substrate further includes a second region.

[0017] Optionally, the method further includes: forming a second groove in the second area.

[0018] Optionally, the first region is used to form a long channel device, the second region is used to form a short channel device, and the width of the first trench is greater than the width of the second trench.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0020] A mask layer is formed on the sacrificial layer in the first area, and a first projection of the mask layer on the substrate is located in a second projection of the sacrificial layer on the substrate, and the area of ​​the first projection is smaller than the area of ​​the second projection, that is, the mask layer covers the surface of the middle area of ​​the sacrificial layer in the first area, and exposes the surface of the surrounding area of ​​the sacrificial layer in the first area; using the mask layer as a mask, after etching the exposed sacrificial layer and a partial thickness of the substrate for the first time, the substrate in the first area forms a shape in which the middle height is higher than the surrounding height, and the mask layer and the sacrificial layer are removed. When the substrate is etched for the second time, since the middle part of the substrate in the first area is relatively high, the first groove formed after etching is in a hump shape with a raised middle part, thereby increasing the specific surface area of ​​the bottom of the first groove, and when the epitaxial layer is grown in the first groove, it is beneficial for the epitaxial layer to grow fuller. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 3 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0022] Figures 4 to 16 It is a schematic structural diagram corresponding to each step of a formation process of a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] As can be seen from the background technology, currently the epitaxial layer growth in the long channel region is not full enough, resulting in poor performance of the semiconductor structure.

[0024] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 3 A structural schematic diagram of a semiconductor structure forming process in one embodiment is shown.

[0025] refer to Figure 1 , providing a substrate 10, wherein the substrate 10 includes a long channel region A and a short channel region B, wherein dummy gate structures 11 are respectively formed in the long channel region A and the short channel region B; etching the substrate 10 between adjacent dummy gate structures 11, forming a first trench 12 in the long channel region A, and forming a second trench 13 in the short channel region B.

[0026] refer to Figure 2 , an epitaxial layer 14 is formed in the first trench 12 and the second trench 13 .

[0027] refer to Figure 3 , forming a first dielectric layer 15 on the substrate 10; removing the dummy gate structure 11; forming a metal gate structure 16 at the location of the dummy gate structure 11; forming a second dielectric layer 17 on the first dielectric layer 15 and the metal gate structure 16; forming a contact hole 18 in the first dielectric layer 15 and the second dielectric layer 17, wherein the contact hole 18 exposes the surface of the epitaxial layer 14; and forming a conductive layer 19 in the contact hole 18.

[0028] The inventors have found that when the semiconductor structure is formed by the above method, due to the large spacing between adjacent pseudo-gate structures 11 in the long channel region A, when the first trench 12 is etched to form the first trench 12, the bottom of the first trench 12 formed is a plane with a small specific surface area. When the epitaxial layer is grown simultaneously in the first trench 12 and the second trench 13, due to the wide width and small specific surface area of ​​the first trench 12, the epitaxial layer 14 in the first trench 12 is not fully grown and has a thin thickness. When the second dielectric layer 17 and the first dielectric layer 15 in the long channel region A are etched to form the contact hole 18, the contact hole 18 easily penetrates the epitaxial layer 14 in the first trench 12 and directly contacts the substrate 10 below to form a Schottky contact, thereby increasing the capacitance of the semiconductor device and reducing the on-state current, which may cause the semiconductor device to fail.

[0029] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first groove is formed by etching a substrate twice. Before the first etching, a mask layer is formed on a sacrificial layer in a first region, a first projection of the mask layer on the substrate is located in a second projection of the sacrificial layer on the substrate, and an area of ​​the first projection is smaller than an area of ​​the second projection, that is, the mask layer covers a middle region of the sacrificial layer in the first region. During the first etching, the mask layer is used as a mask to etch the exposed sacrificial layer and a partial thickness of the substrate, so that the substrate forms a shape with a high middle and low surroundings. After removing the mask layer and the remaining sacrificial layer, the substrate is etched for a second time to form the first groove. Since the height of the substrate in the middle is relatively high, the bottom shape of the formed first groove is a hump-shaped shape with a protrusion in the middle, thereby increasing the specific surface area of ​​the bottom of the first groove. When an epitaxial layer is formed in the first groove, the epitaxial layer grows along the surface of the first groove. The increase in the specific surface area is conducive to making the grown epitaxial layer fuller, increasing the size of the epitaxial layer in the first groove, and solving the problem that the contact hole penetrates the epitaxial layer when a contact hole is subsequently formed on the epitaxial layer in the first region, thereby facilitating improving the performance of the semiconductor structure.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Figures 4 to 16 It is a schematic structural diagram corresponding to each step of a formation process of a semiconductor structure in one embodiment of the present invention.

[0032] refer to Figure 4 , providing a substrate, wherein the substrate includes a first region Ⅰ.

[0033] In this embodiment, the base includes a substrate (not shown) and a plurality of fins 100 arranged discretely on the substrate.

[0034] In other embodiments, no fins may be formed on the substrate.

[0035] In this embodiment, the material of the substrate is silicon.

[0036] In other embodiments, the material of the substrate may also be semiconductor materials such as germanium, silicon germanium, gallium arsenide, silicon on insulator (SOI), and germanium on insulator (GOI).

[0037] In this embodiment, the material of the fin 100 is silicon; in other embodiments, the material of the fin 100 may also be a semiconductor material such as silicon germanium.

[0038] In this embodiment, the method for forming the fin 100 includes: forming a fin material film (not shown) on the substrate; forming a patterned layer (not shown) on the fin material film; and etching the fin material film using the patterned layer as a mask until the substrate surface is exposed to form the fin 100.

[0039] In this embodiment, the substrate further includes a second region II.

[0040] It should be noted that the first region I is a long channel device region, and the second region II is a short channel device region. Specifically, the first region I can be used to form a long channel device, and the second region II can be used to form a short channel device.

[0041] The long channel device may include one or more of the following: a long channel NMOS (Long Channel N-Metal-Oxide-Semiconductor, LC-NMOS) device or a long channel PMOS (Long Channel P-Metal-Oxide-Semiconductor, LC-PMOS) device. In this embodiment, the first region I is used to form a long channel NMOS device.

[0042] The short channel device may include one or more of the following: static random access memory (SRAM), N-core components or P-core components. In this embodiment, the second region II is used to form an N-core component.

[0043] Continue to refer Figure 4 , a dummy gate structure 110 is formed on the substrate.

[0044] In this embodiment, specifically, a dummy gate structure 110 is formed on the substrate in the first region I and the second region II, and the dummy gate structure 110 spans across the fin 100 .

[0045] The width of the dummy gate structure 110 of the long channel device is greater than the width of the dummy gate structure 110 of the short channel device. The width of the dummy gate structure 110 is parallel to the extension direction of the fin 100 .

[0046] The spacing L1 between adjacent dummy gate structures 110 in the long channel device is greater than the spacing L2 between adjacent dummy gate structures 110 in the short channel device. The spacing between adjacent dummy gate structures 110 is the distance between adjacent dummy gate structures 110 in the extension direction parallel to the fin 100 .

[0047] In this embodiment, the dummy gate structure 110 includes: a dummy gate dielectric layer (not shown) located on the fin 100 , a dummy gate layer 111 located on the dummy gate dielectric layer, and a protection layer 112 located on the dummy gate layer 111 .

[0048] In this embodiment, sidewall spacers 113 are further formed on the sidewalls of the dummy gate layer 111 and the protection layer 112 .

[0049] In this embodiment, the material of the dummy gate dielectric layer is silicon oxide.

[0050] In this embodiment, the material of the dummy gate layer 111 is polysilicon.

[0051] In this embodiment, the material of the protective layer 112 is silicon nitride; in other embodiments, the material of the protective layer 112 can also be one or more combinations of materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbon boron nitride (SiCBN).

[0052] In this embodiment, the material of the side wall 113 is silicon nitride; in other embodiments, the material of the side wall 113 can also be one or more combinations of materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0053] The sidewall spacer 113 is used to define the positions of the source and drain to be formed subsequently, and the sidewall spacer 113 is used to protect the sidewall of the dummy gate layer 111 to avoid affecting the performance of the semiconductor structure.

[0054] refer to Figure 5 A sacrificial layer 200 is formed on the substrate between adjacent dummy gate structures 110 , and a top surface of the sacrificial layer 200 is flush with a top surface of the dummy gate structure 110 .

[0055] In this embodiment, specifically, the sacrificial layer 200 is formed on the substrate and the fin 100 between the adjacent dummy gate structures 110 in the first region I and the second region II.

[0056] In this embodiment, the sacrificial layer 200 is a bottom anti-reflection layer.

[0057] In other embodiments, the sacrificial layer 200 may also be an organic dielectric layer.

[0058] In this embodiment, the sacrificial layer 200 is formed by a spin coating process. The sacrificial layer 200 formed by the spin coating process has a smooth surface, which is conducive to the subsequent etching process to remove the sacrificial layer.

[0059] After forming the sacrificial layer 200 , a mask layer is formed on the sacrificial layer 200 in the first region I.

[0060] In this embodiment, the steps of forming the mask layer specifically include:

[0061] refer to Figure 6 , forming an initial mask layer 300 on the dummy gate structure 110 and the sacrificial layer 200 .

[0062] In this embodiment, the initial mask layer 300 is a photoresist layer.

[0063] In this embodiment, the process of forming the initial mask layer 300 is a chemical vapor deposition process; in other embodiments, the initial mask layer 300 may also be formed by an atomic layer deposition process.

[0064] The thickness of the initial mask layer 300 is in the range of If the thickness of the initial mask layer 300 is less than In the subsequent process of patterning the initial mask layer, the initial mask layer will be consumed, resulting in insufficient height of the mask layer formed subsequently; if the thickness of the initial mask layer 300 is greater than This will cause the thickness of the mask layer formed subsequently to be thicker. When the sacrificial layer and the substrate are etched using the mask layer as a mask, the depth-to-width ratio is relatively large, which is not conducive to the etching process.

[0065] refer to Figure 7 , patterning the initial mask layer 300 to remove portions of the initial mask layer 300 and the mask layer 310 .

[0066] In this embodiment, specifically, the initial mask layer 300 in the second region II and a portion of the initial mask layer 300 in the first region I are removed to form a mask layer 310 .

[0067] The mask layer 310 has a first projection on the substrate, and the sacrificial layer 200 has a second projection on the substrate. The first projection is located in the second projection, and an area of ​​the first projection is smaller than an area of ​​the second projection.

[0068] In this embodiment, since the first projection is located in the second projection and the area of ​​the first projection is smaller than the area of ​​the second projection, it means that the mask layer 310 does not completely cover the sacrificial layer 200 in the first area I, and the mask layer 310 covers the middle area of ​​the sacrificial layer 200 in the first area I, exposing the peripheral area of ​​the sacrificial layer 200.

[0069] refer to Figure 7 , along the extension direction of the fin 100 , the mask layer 310 exposes the surfaces of both sides of the sacrificial layer 200 in the first region I.

[0070] In this embodiment, the center point of the first projection coincides with the center point of the second projection.

[0071] This indicates that along the extension direction of the fin 100, the areas on both sides of the sacrificial layer 200 not covered by the mask layer 310 are equal, which is beneficial for uniform etching of the substrate on both sides of the mask layer 310 during the subsequent first etching of the substrate, so that when the substrate is etched for the second time to form a first groove, the shape of the first groove is more regular and symmetrical, which is beneficial for improving the growth quality of the epitaxial layer.

[0072] refer to Figure 8 After forming the mask layer 310, the mask layer 310 is used as a mask to etch the sacrificial layer 200 and a partial thickness of the substrate exposed by the mask layer 310.

[0073] In this embodiment, specifically, the sacrificial layer 200 in the second region II, the sacrificial layer 200 in the first region I not covered by the mask layer 310 , and the partial thickness of the fin 100 not covered by the mask layer 310 are removed by etching.

[0074] In this embodiment, the process of etching the sacrificial layer 200 and a partial thickness of the substrate exposed by the mask layer 310 is dry etching.

[0075] In this embodiment, the process parameters of the dry etching process include: the etching atmosphere includes CF4 and O2, wherein the gas flow rate of CF4 is 50-100 ml / min.

[0076] In this embodiment, the etching process consumes part of the mask layer 310 , so that the height of the mask layer 310 becomes shorter.

[0077] In this embodiment, a portion of the substrate not covered by the mask layer 310 is etched, so that the substrate of the first region I has a shape that is high in the middle and low on both sides, which is beneficial for the subsequent etching of the substrate of the first region I to form a first groove, so that the first groove has a hump shape with a protrusion in the middle.

[0078] refer to Fig. 9 , remove the mask layer 310 and the remaining sacrificial layer 200.

[0079] In this embodiment, after the mask layer 310 is removed by a dry etching process, the remaining sacrificial layer 200 is removed by a wet etching process.

[0080] In this embodiment, the process parameters of the dry etching include: the etching atmosphere includes N2F2, and the gas flow rate of N2F2 is 9-11 ml / min.

[0081] In this embodiment, the process parameters of the wet etching include: the wet etching solution includes hydrogen peroxide and ammonia.

[0082] In this embodiment, the process has an etching selectivity ratio for the mask layer 310 , the sacrificial layer 200 and the substrate, and the mask layer 310 and the sacrificial layer 200 can be removed without causing damage to the substrate.

[0083] refer to Fig.10 , etching the substrate between adjacent dummy gate structures 110 to form a first trench 410 in the first region I and a second trench 420 in the second region II.

[0084] In this embodiment, specifically, the fin 100 between the adjacent dummy gate structures 110 in the first region I and the second region II is etched to form a first trench 410 in the first region I and a second trench 420 in the second region II.

[0085] In the present embodiment, before forming the first groove 410 in the first region I, a portion of the substrate not covered by the mask layer 310 is etched first, so that the height in the middle of the substrate is higher than the surrounding height. When the substrate is etched for the second time to form the first groove 410, the height in the middle of the substrate is higher, so the formed first groove 410 is in the shape of a hump with a protrusion in the middle. The shape close to an arc surface can increase the specific surface area of ​​the bottom of the first groove 410. When the epitaxial layer is subsequently formed in the first groove 410, the area to which the epitaxial layer can be attached is increased, which is beneficial to the growth of the epitaxial layer, thereby forming a full epitaxial layer.

[0086] refer to Fig.11 , an epitaxial layer 430 is formed in the first trench 410 .

[0087] In this embodiment, the method further includes: forming an epitaxial layer 430 in the second trench 420 .

[0088] In this embodiment, the epitaxial layer 430 is used to form a source region and a drain region.

[0089] In this embodiment, the material of the epitaxial layer 430 is silicon phosphide (SiP); in other embodiments, the material of the epitaxial layer 430 may also be silicon germanium or silicon arsenide.

[0090] In this embodiment, the epitaxial layer 430 is formed by an epitaxial growth process. The epitaxial layer 430 needs to grow along the surface of the first trench 410 and the second trench 420. The increase in the specific surface area of ​​the first trench 410 is conducive to the growth of the epitaxial layer 430, so that a full epitaxial layer 430 can be formed in the first trench 410.

[0091] refer to Fig.12 , forming a first dielectric layer 510 on the substrate, wherein the first dielectric layer 510 exposes a top surface of the dummy gate structure 110 .

[0092] In this embodiment, the material of the first dielectric layer 510 is silicon oxide; in other embodiments, the material of the first dielectric layer 510 may also be a low-k dielectric material or an ultra-low-k dielectric material.

[0093] refer to Fig.13 , the dummy gate structure 110 is removed to form a gate opening 120 .

[0094] In this embodiment, the protection layer 112 , the dummy gate layer 111 and the dummy gate dielectric layer are removed, and the gate opening 120 is formed in the first dielectric layer 510 .

[0095] The process of removing the dummy gate structure 110 includes a dry etching process or a wet etching process.

[0096] refer to Fig.14 , a gate structure 130 is formed in the gate opening 120 .

[0097] In this embodiment, the gate structure 130 is a metal gate structure, and the gate electrode material of the gate structure 130 includes copper, aluminum or tungsten.

[0098] Continue to refer Fig.14 , a second dielectric layer 520 is formed on the first dielectric layer 510 and the gate structure 130 .

[0099] In this embodiment, the material of the second dielectric layer 520 is silicon oxide; in other embodiments, the material of the second dielectric layer 520 may also be a low-k dielectric material or an ultra-low-k dielectric material.

[0100] refer to Fig.15 , a contact hole 530 is formed in the first dielectric layer 510 and the second dielectric layer 520 , and the contact hole 530 exposes the top surface of the epitaxial layer 430 .

[0101] The contact hole 530 provides a process basis for subsequently forming a conductive plug electrically connected to the epitaxial layer 430 .

[0102] In this embodiment, the contact hole 530 is formed in both the first region I and the second region II.

[0103] In this embodiment, the step of forming the contact hole 530 includes: forming a patterned photoresist layer (not shown) on the second dielectric layer 520, the patterned photoresist layer defining the position and size of the contact hole to be formed; using the patterned photoresist layer as a mask, etching the second dielectric layer 520 and the first dielectric layer 510 until the top surface of the epitaxial layer of the first region I and the second region II is exposed to form the contact hole 530; and removing the patterned photoresist layer.

[0104] In this embodiment, since the epitaxial layer 430 in the first trench 410 grows relatively fully, the contact hole 530 in the first region I will not penetrate the epitaxial layer 430 to contact the fin 100 below.

[0105] refer to Fig.16 , a conductive layer 531 is formed in the contact hole 530 .

[0106] In this embodiment, the step of forming the conductive layer 531 includes: filling the contact holes 530 in the first area and the second area with a conductive material layer (not shown), wherein the conductive material layer also covers the top of the second dielectric layer 520; and performing chemical mechanical polishing on the conductive material layer until the top surface of the second dielectric layer 520 is exposed to form the conductive layer 531.

[0107] In this embodiment, the material of the conductive material layer is metal tungsten; in other embodiments, the material of the conductive material layer may also be aluminum, copper, platinum, cobalt, etc.

[0108] In this embodiment, the method for filling the conductive material layer is atomic layer deposition; in other embodiments, the conductive material layer may be filled by chemical vapor deposition, physical vapor deposition or electrochemical plating.

[0109] In the present embodiment, since the epitaxial layer 430 of the first region I is not penetrated when the contact hole 530 is formed, the conductive layer 531 formed in the contact hole 530 in the first region I will not contact the bottom substrate, thereby avoiding the formation of Schottky contact between the metal and the semiconductor material, solving the problem of increased capacitance of the semiconductor device and small on-state current during operation, which is beneficial to improving the performance of the semiconductor device.

[0110] In this embodiment, before forming the conductive layer 531 in the contact hole 530 , the method further includes: forming a barrier layer (not shown) on the bottom and sidewall surface of the contact hole 530 .

[0111] In this embodiment, the blocking layer is used to block the conductive metal of the conductive layer 531 formed in the contact hole 530 from diffusing into the first dielectric layer 520 and the second dielectric layer 530 .

[0112] In this embodiment, the material of the barrier layer 500 is titanium nitride; in other embodiments, the material of the barrier layer 500 may also be tantalum nitride.

[0113] In this embodiment, the method for forming the barrier layer 500 includes chemical vapor deposition; in other embodiments, the barrier layer may also be formed by physical vapor deposition or atomic layer deposition.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the first region being used to form a long channel device, and the second region being used to form a short channel device; forming a dummy gate structure on the substrate; forming a sacrificial layer on the substrate between adjacent dummy gate structures, wherein a top surface of the sacrificial layer is flush with a top surface of the dummy gate structure; forming a mask layer on the sacrificial layer in the first region, the mask layer covering a middle region of the sacrificial layer in the first region, the mask layer having a first projection on the substrate, the sacrificial layer having a second projection on the substrate, the first projection being located in the second projection, and an area of ​​the first projection being smaller than an area of ​​the second projection; Etching and removing the sacrificial layer and a part of the thickness of the substrate exposed by the mask layer, so that the substrate forms a shape with a high middle and low surroundings; removing the mask layer and the remaining sacrificial layer; Etching the substrate between adjacent dummy gate structures to form a first trench in the first region and a second trench in the second region, wherein a width of the first trench is greater than a width of the second trench; An epitaxial layer is formed in the first trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: After forming an epitaxial layer in the first trench, the method further comprises: forming a contact hole exposing a top surface of the epitaxial layer; A conductive layer is formed in the contact hole.

3. The method for forming a semiconductor structure according to claim 2, wherein: Before forming a contact hole exposing the top surface of the epitaxial layer, the method further comprises: forming a first dielectric layer on the substrate, wherein the first dielectric layer exposes the top of the dummy gate structure; removing the dummy gate structure to form a gate opening; forming a gate structure in the gate opening; A second dielectric layer is formed on the first dielectric layer and the gate structure, and the contact hole is located in the first dielectric layer and the second dielectric layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The center point of the first projection coincides with the center point of the second projection.

5. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the mask layer comprises: forming an initial mask layer on the dummy gate structure and the sacrificial layer; The initial mask layer is patterned to remove a portion of the initial mask layer to form a mask layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The sacrificial layer is a bottom anti-reflection layer or an organic dielectric layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the epitaxial layer includes silicon phosphide, silicon germanium or silicon arsenide.

8. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the epitaxial layer includes an epitaxial growth process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching away the sacrificial layer exposed by the mask layer and a partial thickness of the substrate is a dry etching process.

10. The method for forming a semiconductor structure according to claim 1, wherein: The process for removing the mask layer is a dry etching process, and the process for removing the remaining sacrificial layer is a wet etching process.

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