Semiconductor package

Abstract

Embodiments of the present disclosure relate to a semiconductor package. The semiconductor package includes a conductive structure, a first electronic element, and a second electronic element, wherein the first electronic element and the second electronic element are disposed side by side on the conductive structure, the first electronic element includes a first die and a first material and a second material on the first die, and an interface between the first material and the second material does not contact the first die on a side of the first electronic element facing the second electronic element. The purpose of the present application is to provide a semiconductor package to at least improve the yield of the semiconductor package.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor packages. Background Technology

[0002] In a fan-out chip-on-a-substrate (FOCOS) structure, a mismatch in the coefficient of thermal expansion (CTE) between the non-conductive film (NCF) and the epoxy molding compound (EMC) inside the high-bandwidth memory (HBM) leads to high temperatures during subsequent thermal cycling. This causes delamination between the NCF and EMC, resulting in cracks that extend outwards and may eventually reach the redistribution layer (RDL), causing trace breakage in the redistribution layer.

[0003] Figure 1A The diagram shows a cross-sectional view of a chip structure 1 on a fan-out substrate. The contact surface between the non-conductive film (NCF) 10 and the logic chip 30 spans most of the logic chip 30 and is close to the corners of the logic chip 30. Therefore, when a delamination or damage occurs between the non-conductive film (NCF) 10 and the epoxy molding compound (EMC) 20, the crack 50 can easily extend directly along the corners of the logic chip 30 and the interface between the non-conductive film (NCF) 10 and the epoxy molding compound (EMC) 20. The crack may even extend downward along the sidewall of the electronic component to the redistribution layer (RDL) 40, causing it to crack. This results in electrical connection failures between the chip and the high-bandwidth memory in existing heterogeneous integration products.

[0004] Figure 1B for Figure 1A The electron microscope image of region b shows that when the package is in operation, the internal temperature rises from room temperature to high temperature. After the non-conductive film (NCF) 10 expands at high temperature, it delaminates with the epoxy molding compound (EMC) 20, resulting in crack 50. As can be seen from region a, crack 50 extends from the corner of the logic chip 30 to the redistribution layer (RDL) 40.

[0005] Figure 1C for Figure 1A A top view, in which, Figure 1A It is along Figure 1C The cross-sectional view taken along line A-A' shows that a crack 50 is formed in the region between the high-bandwidth memory (HBM) 60 and the chip 80. Summary of the Invention

[0006] In view of the problems existing in related technologies, the purpose of this invention is to provide a semiconductor package to at least improve the yield of semiconductor packages.

[0007] To achieve the above objectives, the present invention provides a semiconductor package. The semiconductor package includes: a conductive structure; a first electronic component and a second electronic component disposed side-by-side on the conductive structure; the first electronic component includes a first die and a first material and a second material located on the first die; on the side of the first electronic component facing the second electronic component, the interface between the first material and the second material does not contact the first die.

[0008] In some embodiments, on the side of the first electronic component facing the second electronic component, the first material has a first cross-section, and the second material has a second cross-section, with the first and second cross-sections flush.

[0009] In some embodiments, the first electronic component further includes a barrier layer covering the first and second cut surfaces.

[0010] In some embodiments, the first and second cut surfaces are recessed relative to the sidewall of the first die.

[0011] In some embodiments, the first die has an active circuit.

[0012] In some embodiments, the first die is a logic first die.

[0013] In some embodiments, the first material is a non-conductive film (NCF).

[0014] In some embodiments, the second material is epoxy molding compound (EMC).

[0015] In some embodiments, the first electronic component further includes: a second die located above the first die, and a first material located between the first die and the second die.

[0016] In some embodiments, the first material also encapsulates the sidewalls of the second die.

[0017] In some embodiments, the lateral dimension of the first die is greater than the lateral dimension of the second die.

[0018] In some embodiments, the second die is a high-bandwidth memory (HBM) die.

[0019] In some embodiments, the lateral dimension of the first electronic component is smaller than the lateral dimension of the second electronic component.

[0020] In some embodiments, the semiconductor package further includes an underfill material located between the first electronic component, the second electronic component, and the conductive structure, wherein the first electronic component and the second electronic component are separated by the underfill material.

[0021] In some embodiments, the semiconductor package further includes: a molding compound that encapsulates a first electronic component, a second electronic component, and an underfill material.

[0022] In some embodiments, molding compound encapsulates the oppositely disposed sides of the first electronic component.

[0023] In some embodiments, the sidewalls of the molding compound are flush with the sidewalls of the conductive structure.

[0024] In some embodiments, the sides of the first material and the second material facing the second electronic component are recessed relative to the first die.

[0025] In some embodiments, the conductive structure is a redistribution layer (RDL). Attached Figure Description

[0026] Figures 1A to 1C This is a schematic diagram of a chip structure on a fan-out substrate in the prior art.

[0027] Figures 2A to 6 The following diagrams illustrate the formation process and finished product of semiconductor packages and electronic components therein, according to different embodiments of this application. Detailed Implementation

[0028] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0029] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0030] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0031] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0032] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0033] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0034] Figure 2A and Figure 2B The formation process of a first electronic component according to some embodiments of this application is illustrated. Reference Figure 2AThe second die 290 is placed above the first die 220. In some embodiments, the first die 220 has active circuitry. The first die 220 may be a logic die. The second die 290 may be a high-bandwidth memory (HBM) die. The lateral dimension of the first die 220 may be larger than the lateral dimension of the second die 290. A first material 240 and a second material 260 are formed on the first die 220, wherein the first material 240 and the second material 260 are formed around the sidewall of the second die 290 to encapsulate the sidewall of the second die 290. The first material 240 is located between the first die 220 and the second die 290, and between adjacent second dies 290. In some embodiments, the first material 240 may be a non-conductive film (NCF). The second material 260 may be an epoxy molding compound (EMC).

[0035] refer to Figure 2B A barrier layer 280 is formed, covering the upper surface of the second die 290, the outer sidewall of the second material 260, and the sidewall of the first die 220, thereby forming the first electronic component 200. In some embodiments, the barrier layer 280 has high adhesion, thereby preventing cracks caused by high-temperature expansion of the first material 240 from extending from the corners of the first die 220. In some embodiments, the material of the barrier layer 280 may be a molding compound (CPD) or a metallic material. In some embodiments, a chemical vapor deposition (CVD) process is performed to form the barrier layer 280.

[0036] Figure 2C and Figure 2D The process of forming a first electronic component according to other embodiments of this application is illustrated. During the formation... Figure 2A After the structure shown, refer to Figure 2C The first material 240 and the second material 260 on the left side of the second die 290 are cut using a wafer dicing process or a laser dicing process. The remaining portion after cutting results in the first material 240 having a first cut surface 242 and the second material 260 having a second cut surface 262. The first cut surface 242 and the second cut surface 262 are recessed relative to the sidewall of the first die 220. On the left side of the second die 290, the interface 250 between the first material 240 and the second material 260 does not contact the first die 220. The dicing step reduces the amount of the first material 240, thereby reducing its expansion at high temperatures. The interface 250 not contacting the first die 220 reduces the probability of any existing cracks extending outward along the surface of the first die 220.

[0037] refer to Figure 2D ,and Figure 2BSimilarly, a barrier layer 280 is formed, covering the upper surface of the second die 290, the outer walls of the first material 240 and the second material 260, the first cross-section 242, the second cross-section 262, and portions of the sidewalls on the left and right sides of the first die 220, thereby forming the first electronic component 200. In other embodiments, the barrier layer 280 covers the upper surface of the second die 290, the outer walls of the first material 240 and the second material 260, and all the sidewalls on the left and right sides of the first die 220, with the lower surface of the barrier layer 280 flush with the lower surface of the first die 220.

[0038] Figure 2E yes Figure 2C The top view shows that portions of the first material 240 and the second material 260 on the left side of the second core 290 are removed, thereby exposing the first core 220 below.

[0039] Figure 2F for Figure 2E Other embodiments are top views. In these embodiments, a laser drilling process can be used to remove portions of the first material 240 and the second material 260, exposing the upper surface of the first die 220 after drilling.

[0040] Figure 3 This is a cross-sectional schematic diagram of the semiconductor package 300 of this application. In some embodiments, a second material 260 is also formed to the bottom of the first die 220. A first electronic component 200 and a second electronic component 400 are electrically connected side-by-side on the conductive structure 100, wherein a conductive via 120 in the conductive structure 100 passes through the second material 260 and is electrically connected to the first electronic component 200. In some embodiments, the conductive structure 100 is a redistribution layer (RDL). An underfill material 500 is formed between the first electronic component 200, the second electronic component 400 and the conductive structure 100, thus separating the first electronic component 200 and the second electronic component 400 by the underfill material 500. In some embodiments, the underfill material 500 is an underfill material. The underfill material 500 may be selected from polyimide (PI), epoxy resin, polybenzoxazole (PBO), etc. Further, a molding compound 600 is formed to encapsulate the first electronic component 200, the second electronic component 400 and the underfill material 500. In some embodiments, the lateral dimension of the first electronic component 200 is smaller than the lateral dimension of the second electronic component 400.

[0041] Figure 4 Semiconductor packages according to other embodiments of this application are shown. Figure 3 The embodiment shown differs in that the sides of the first material 240 and the second material 260 facing the second electronic component 400 are recessed relative to the first die 220.

[0042] Figure 5 Semiconductor packages according to other embodiments of this application are shown. Figure 4 The difference between the embodiments shown is that, Figure 5 The embodiment shown cuts off all of the first material 240 and the second material 260 on the left side of the second die 290, so that the barrier layer 280 contacts the second die 290.

[0043] Figure 6 Semiconductor packages according to other embodiments of this application are shown. Figure 4 The embodiment shown differs in that, prior to forming the molding compound 600, the bottom filler material 500 in the region of the first electronic component 200 recessed relative to the second electronic component 400 is subjected to a wafer dicing or laser dicing process, stopping when the cutting reaches the upper surface of the barrier layer 280. The molding compound 600 is then filled after dicing, wherein the molding compound 600 contacts the sidewall of the first electronic component 200 facing the second electronic component 400.

[0044] In embodiments of the present invention, the first material 240 of the first electronic component 200 facing the second electronic component 400 is recessed, so that its contact surface with the first die 220 is far from the corners of the first die 220. This prevents damage to the contact interface between the first material 240 and the second material 260 from directly extending to the corners of the first die 220. Furthermore, in embodiments of the present invention, a barrier layer 280 formed by a sputtering process is located outside the contact surface between the first die 220 and the first material 240, and also outside the contact interface between the first material 240 and the second material 260. This barrier layer 280 blocks the extension path of cracks caused by damage / delamination of the contact interface between the first material 240 and the second material 260, thus suppressing the propagation of any possible cracks. The embodiments of the present invention do not require changes to the existing bottom filler material 500, the structure of the polyimide (PI) based conductive structure 100, or the structure of the second die 290, and can solve the technical problem of electrical connection failure between the existing first electronic component 200 and second electronic component 400, thereby improving the yield of semiconductor packages. In addition, the technical solution of the embodiments of the present invention is simple in design and has no complicated process.

[0045] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor package, characterized in that, include: Conductive structure; A first electronic component and a second electronic component are arranged side-by-side on the conductive structure. The first electronic component includes a first die and a first material and a second material located on the first die. On the side of the first electronic component facing the second electronic component, the interface between the first material and the second material does not contact the first die. On the side of the first electronic component facing the second electronic component, the first material has a first cross-section, and the second material has a second cross-section. The first cross-section and the second cross-section are flush and recessed relative to the sidewall of the first die. A barrier layer covers the first and second cut surfaces, wherein the barrier layer extends on the top surface of the first die.

2. The semiconductor package according to claim 1, characterized in that, The first material is a non-conductive film (NCF).

3. The semiconductor package according to claim 1, characterized in that, The second material is epoxy molding compound (EMC).

4. The semiconductor package according to claim 1, characterized in that, The lateral dimension of the first electronic component is smaller than that of the second electronic component.

5. The semiconductor package according to claim 4, characterized in that, Also includes: A bottom filler material is located between the first electronic component, the second electronic component, and the conductive structure, with the first electronic component and the second electronic component separated by the bottom filler material.

6. The semiconductor package according to claim 1, characterized in that, The conductive structure is a redistribution layer (RDL).

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