A MEMS integrated device and a method for manufacturing the same

Abstract

This invention provides a MEMS integrated device and its fabrication method. The device includes a first rewiring layer, a MEMS layer, and an application-specific integrated circuit (ASIC) layer. Wafer-level low-temperature silicon-silicon bonding connects the MEMS layer and the ASIC layer. The MEMS layer has a first via and a second via filled with copper. The first via penetrates the MEMS layer, and the second via penetrates a cover plate layer to connect to a movable MEMS structure layer. The first rewiring layer includes internal wiring connecting the first via, the second via, and an external electrode. The internal electrode is electrically connected to the first via. This invention achieves wafer-level integration and packaging of the MEMS device and the ASIC through wafer-level low-temperature silicon-silicon bonding. The copper-filled vias on the MEMS layer enable vertical interconnection between multi-layer chips, avoiding the need for additional vias on the ASIC for internal and external communication. The copper filling is compatible with advanced integrated circuit manufacturing processes, enabling direct integration of the MEMS device with ASIC wafers below 90 nanometers, improving compatibility, reducing packaging costs, and increasing packaging efficiency.

Description

Technical Field

[0001] This invention relates to the field of MEMS technology, and in particular to a MEMS integrated device and its fabrication method. Background Technology

[0002] MEMS (Micro-Electro-Mechanical-System) devices require integrated circuits to function effectively. Integrated circuits are used to enable communication between MEMS devices and the outside world; they are also used to process signals from MEMS devices, such as analog-to-digital conversion, amplification, and filtering.

[0003] Currently, most MEMS devices and integrated circuits are integrated and packaged together using stacked integration or side-by-side methods, with electrical connections between chips achieved through wire bonding. The aim is to achieve shorter signal path lengths, smaller parasitic capacitances, lower interconnect resistances, and smaller package sizes. The Fraunhofer Institute in Germany has proposed a concept for 3D MEMS integration based on through-silicon via (TSV) adapters. A TSV adapter refers to a silicon wafer containing TSV interconnects, with redistribution layers fabricated on its upper and lower surfaces. MEMS chips and integrated circuit chips are assembled on the TSV adapter using microbumps. To match the mechanical strength of the MEMS chip and the TSV adapter, the thickness of the TSV adapter typically needs to be greater than or equal to 200 micrometers. Simultaneously, due to the mismatch in thermal expansion coefficients between the copper TSV interconnects and the surrounding silicon substrate, the interconnect diameter of the copper TSVs is typically controlled to be less than or equal to 20 micrometers, and the aspect ratio of the TSV interconnects is greater than or equal to 10:1, making the manufacturing process quite challenging.

[0004] The stacked integration methods between MEMS devices and integrated circuits include chip-to-chip integration, chip-to-wafer integration, and wafer-to-wafer integration. Wafer-to-wafer integration involves processing MEMS wafers and integrated circuit wafers separately, and then packaging them by bonding. This method allows for packaging and testing on a whole wafer, and then cutting it into individual chips. The packaged chip size is the same as the chip size, which is highly efficient and small in size.

[0005] However, wafer-level integration requires the use of application-specific integrated circuits (ASICs) tailored to the MEMS device structure. Currently, the most advanced integration manufacturing processes of the world's leading integrated circuit manufacturers use copper interconnect technology, while traditional MEMS device interconnects generally use gold or aluminum wiring, which cannot achieve direct integration with advanced integrated circuit manufacturing processes. Summary of the Invention

[0006] This invention provides a MEMS integrated device to solve the problem that MEMS devices and application-specific integrated circuits cannot be directly integrated.

[0007] In a first aspect, embodiments of the present invention provide a MEMS integrated device, including a first redistribution layer, a MEMS layer, and an application-specific integrated circuit (ASIC) layer; the MEMS layer includes a cover plate layer and a MEMS movable structure layer; the cavity structure of the MEMS layer includes a MEMS movable structure; the MEMS layer and the ASIC layer are connected using wafer-level low-temperature silicon-silicon bonding technology; the MEMS layer has an inner wall deposited dielectric layer, a first via and a second via filled with copper, the first via penetrating the MEMS layer and connecting to the ASIC layer, and the second via penetrating the cover plate layer and connecting to the MEMS movable structure layer; the first redistribution layer is located on the side of the MEMS layer opposite to the ASIC layer; the first redistribution layer includes internal wiring connecting the first via, the second via, and an external electrode; the ASIC layer has an internal electrode connecting to an internal circuit on the side facing the MEMS layer, and the internal electrode is electrically connected to the via.

[0008] In one possible implementation, the first via is disposed outside the cavity region of the MEMS layer.

[0009] In one possible implementation, the side of the application-specific integrated circuit layer facing the MEMS layer further includes a second wiring layer; the second wiring layer includes internal wiring connecting the internal electrodes and the internal circuits.

[0010] In one possible implementation, the metal material of the internal circuit is copper.

[0011] In one possible implementation, the cavity structure contains a getter.

[0012] Secondly, embodiments of the present invention provide a method for fabricating a MEMS integrated device, comprising:

[0013] A MEMS layer is fabricated on a first wafer; the MEMS layer includes a cover plate layer and a MEMS movable structure layer; the cavity structure of the MEMS layer includes a MEMS movable structure.

[0014] An application-specific integrated circuit (ASIC) layer is fabricated on the second wafer.

[0015] Internal electrodes that connect to the internal circuits are fabricated on the surface of the application-specific integrated circuit layer.

[0016] Wafer-level low-temperature silicon-silicon bonding is performed on one side of the internal electrode fabricated between the MEMS layer and the application-specific integrated circuit layer.

[0017] A first via and a second via are etched on the MEMS layer. The first via penetrates the MEMS layer and its outlet on the side facing the application-specific integrated circuit layer is connected to the internal electrode. The second via penetrates the cover plate layer and is connected to the movable MEMS structure layer.

[0018] A dielectric layer is deposited on the inner wall of the through-hole; copper is electroplated inside the through-hole.

[0019] A first redistribution layer is fabricated on the side opposite to the MEMS layer and the application-specific integrated circuit layer; the first redistribution layer includes internal wiring connecting a first via, a second via, and an external electrode.

[0020] In one possible implementation, the first via is disposed outside the cavity region of the MEMS layer.

[0021] In one possible implementation, fabricating the application-specific integrated circuit layer on the second wafer includes:

[0022] A second redistribution layer is prepared on the upper surface of the application-specific integrated circuit layer. The second redistribution layer includes internal wiring connecting the internal electrodes and the internal circuit.

[0023] In one possible implementation, the metal material of the internal circuit is copper.

[0024] In one possible implementation, the cavity structure contains a getter.

[0025] This invention provides a MEMS integrated device, including a first rewiring layer, a MEMS layer, and an application-specific integrated circuit (ASIC) layer. The MEMS layer includes a cover plate layer and a MEMS movable structure layer. The cavity structure of the MEMS layer includes a MEMS movable structure. The MEMS layer and the ASIC layer are connected using wafer-level low-temperature silicon-silicon bonding technology. The MEMS layer has an inner wall deposited dielectric layer, a first via and a second via filled with copper. The first via penetrates the MEMS layer and connects to the ASIC layer, and the second via penetrates the cover plate layer and connects to the MEMS movable structure layer. The first rewiring layer is located on the side of the MEMS layer opposite to the ASIC layer. The first rewiring layer includes internal wiring connecting the first via, the second via, and an external electrode. The ASIC layer has an internal electrode on the side facing the MEMS layer that connects to internal circuits, and the internal electrode is electrically connected to the via. Wafer-level integration and packaging of MEMS devices and application-specific integrated circuits (ASICs) are achieved through wafer-level low-temperature silicon-silicon bonding. Copper-filled vias are set on the MEMS layer to achieve vertical interconnection between multi-layer chips, avoiding the need to add vias for internal and external communication on the ASIC. The copper filling is compatible with advanced integrated circuit manufacturing processes, enabling direct integration of MEMS devices and ASIC wafers below 90 nanometers, improving compatibility, reducing packaging costs, and increasing packaging efficiency. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of the MEMS integrated device provided in the embodiment of the present invention;

[0028] Figure 2 This is a top view of the MEMS layer structure provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of a MEMS integrated device structure with a rewiring layer provided in an embodiment of the present invention;

[0030] Figure 4 This is a flowchart of the fabrication method of MEMS integrated devices provided in the embodiments of the present invention;

[0031] Figure 5 This is a schematic diagram of the device structure corresponding to the preparation method S1 provided in the embodiments of the present invention;

[0032] Figure 6These are schematic diagrams of the device structures corresponding to the preparation methods S2 and S3 provided in the embodiments of the present invention;

[0033] Figure 7 These are schematic diagrams of the device structures corresponding to preparation methods S4 to S7 provided in the embodiments of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0035] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0036] The implementation of the present invention will be described in detail below with reference to the accompanying drawings:

[0037] Figure 1 This is a schematic diagram of the structure of a MEMS integrated device provided in an embodiment of the present invention. (Refer to...) Figure 1 The MEMS integrated device includes: a first redistribution layer 3, a MEMS layer 1, and an application-specific integrated circuit layer 2; the MEMS layer includes a cover plate layer 15 and a MEMS movable structure layer 16; the cavity structure 14 of the MEMS layer 1 includes a MEMS movable structure 141; the MEMS layer 1 and the application-specific integrated circuit layer 2 can be wafers fabricated on a silicon substrate.

[0038] MEMS layer 1 and ASIC layer 2 are connected using wafer-level low-temperature silicon-silicon bonding technology; that is, the separately fabricated MEMS wafer and ASIC wafer are connected into a whole through wafer-level low-temperature silicon-silicon bonding process; the side of the MEMS wafer that contacts the ASIC wafer is the bonding surface. The lower surface of cover plate layer 15 is connected to the upper surface of MEMS movable structure layer 16 through wafer-level low-temperature silicon-silicon bonding.

[0039] MEMS layer 1 has an inner wall with a dielectric layer deposited on it, and a first through-hole 11 and a second through-hole 12 filled with copper. The first through-hole 11 passes through MEMS layer 1 and connects to application-specific integrated circuit layer 2. The second through-hole 12 passes through cover plate layer 15 and connects to MEMS movable structure layer 16.

[0040] The first wiring layer 3 is located on the side opposite to the MEMS layer 1 and the application-specific integrated circuit layer 2. The first wiring layer 3 includes internal wiring connecting the first via 11, the second via 12 and the external electrode 31. The external electrode 31 is used for internal and external electrical connection of the MEMS integrated device. For example, the external electrode 31 may be a metal bump.

[0041] An internal electrode 21 is provided on the side of the application-specific integrated circuit layer 2 facing the MEMS layer 1, which is connected to the internal circuit. The internal electrode 21 is electrically connected to the first through hole 11. The external electrode 31, the first through hole 11, the second through hole 12 and the internal electrode 21 realize the internal circuit of the MEMS integrated device to be electrically connected to the external environment, so as to realize internal and external communication.

[0042] Application-specific integrated circuits (ASICs) have high integration density, and their structure is sensitive to crosstalk signals, making device isolation difficult. Adding vias to layer 2 of ASICs reduces device integration density and increases crosstalk.

[0043] By setting vias on MEMS layer 1 and filling the vias with copper, the first via 11 is connected to the internal electrode 21, and the second via 12 is connected to the MEMS movable structure layer 16. The first via 11 and the second via 12 are connected to the external electrode 31 through the redistribution layer, communication between the internal and external components of the integrated device is realized on MEMS layer 1, avoiding the need to add vias for internal and external communication on the application-specific integrated circuit.

[0044] Figure 2 This is a top view schematic diagram of the MEMS layer provided in an embodiment of the present invention. (Refer to...) Figure 2 :

[0045] In an optional embodiment, the first via 11 is disposed outside the cavity region 13 of the MEMS layer 1.

[0046] MEMS layer 1 includes a cavity structure 14, which is a sealed cavity. A movable MEMS structure 141 is disposed inside the cavity. The vertical region of the cavity structure 14 is the cavity region 13. The region outside the cavity region 13 of MEMS layer 1 is a non-critical region, which only serves as a structural support. Adding a first through-hole 11 to the non-critical region has little impact on the device performance and size of MEMS layer 1.

[0047] For example, the MEMS layer 1 includes multiple cavities, and the first via 11 is disposed outside the multiple cavity regions 13 of the MEMS layer 1.

[0048] For example, the MEMS layer 1 includes a plurality of first through holes 11 disposed outside the cavity region 13.

[0049] The internal electrode 21 can be positioned outside the cavity region 13; a first through-hole 11 is provided at the corresponding position of the internal electrode 21; the first through-hole 11 enables communication between the internal circuit and the outside of the MEMS integrated device. The position of the first through-hole 11 corresponds to the position of the internal electrode 21, and the first through-hole 11 is positioned outside the cavity region 13, which enables the MEMS layer 1 and the dedicated integrated circuit layer 2 to be compatible with each other, directly integrated, and improves packaging efficiency.

[0050] In an optional embodiment, the lower surface of the cover plate layer 15 is provided with a first groove 152; the MEMS movable structure layer 16 is provided with a MEMS movable structure 141 at a position corresponding to the first groove 152; the application-specific integrated circuit is provided with a second groove 222 at a position corresponding to the first groove 152; the first groove 152 and the second groove 222 together constitute a cavity structure 14 containing the MEMS movable structure 141.

[0051] Figure 3 This is a schematic diagram of a MEMS integrated device structure with a rewiring layer provided in an embodiment of the present invention; see reference. Figure 3 :

[0052] In an optional embodiment, the side of the application-specific integrated circuit layer 2 facing the MEMS layer 1 further includes a second redistribution layer 22; the second redistribution layer 22 includes internal wiring 221 connecting the internal electrodes 21 and the internal circuits.

[0053] For example, the second wiring layer 22 includes a multilayer dielectric layer 224 and internal wiring 221; the internal wiring 221 includes vertical wiring and horizontal wiring; the two ends of the internal wiring 221 are at different positions in the vertical direction.

[0054] The second wiring layer 22 is used to reposition the internal electrodes 21 of the application-specific integrated circuit (ASIC) layer 2. For example, the second wiring layer 22 is used to position the internal electrodes 21 of the ASIC outside the cavity region 13. When the internal circuit leads of the ASIC layer 2 are not completely distributed outside the cavity region 13 of the MEMS layer 1, the second wiring layer 22 is used to redistribute the positions of the internal electrodes 21, positioning them outside the cavity region 13 of the MEMS layer 1. The second wiring layer 22 allows the same ASIC to be compatible with the structures of multiple types of MEMS layers 1, improving compatibility.

[0055] In an optional embodiment, the metal material of the internal circuitry is copper. The metal material filling the vias is the same as that of the internal circuitry, and the processes are compatible, allowing for direct integration.

[0056] Advanced integrated circuit manufacturing processes below 90 nanometers generally use copper interconnect technology; while traditional MEMS device interconnects generally use gold or aluminum interconnects, which are different metal materials and have poor compatibility; the metal material of the first via 11 is copper, which can achieve mutual compatibility between MEMS layer 1 and advanced integrated circuit manufacturing processes and can be directly integrated.

[0057] The inner walls of the first via 11 and the second via 12 include a dielectric layer; the dielectric layer is used for electrical isolation between the metal material in the via and the substrate.

[0058] In an optional embodiment, a getter 223 is provided within the cavity structure 14.

[0059] Figure 4 This is a flowchart illustrating a method for fabricating a MEMS integrated device according to an embodiment of the present invention. (Refer to...) Figure 4 The preparation method includes:

[0060] In step S1, a MEMS layer 1 is fabricated on a first wafer; the MEMS layer 1 includes a cover plate layer 15 and a MEMS movable structure layer 16; the cavity structure 14 of the MEMS layer 1 includes a MEMS movable structure 141.

[0061] Figure 5 This is a schematic diagram of the device structure corresponding to the fabrication method S1 provided in this embodiment of the invention; refer to Figure 5 :

[0062] In an optional embodiment, fabricating MEMS layer 1 on the first wafer includes:

[0063] Reference Figure 5 In step a), an oxide layer 151 is prepared on the surface of a silicon wafer to obtain a cover layer 15; exemplaryly, the silicon wafer may be a double-sided polished silicon wafer. Exemplarily, the method for preparing the oxide layer 151 may include a thermal oxidation process, a plasma-enhanced chemical vapor deposition (PECVD) process, or a low-pressure chemical vapor deposition (LPCVD) process.

[0064] The etching area is defined on the surface of oxide layer 151 using photolithography.

[0065] The oxide layer 151 of the cover plate layer 15 is etched to form a first groove 152; exemplaryly, the etching method includes dry etching or wet etching. (Refer to...) Figure 5 Figure b is a schematic diagram of the structure of the cover plate layer 11 after etching.

[0066] Clean the first wafer and cover plate 15 to remove contaminants; for example, the first wafer may be a double-sided polished silicon wafer.

[0067] The bonded surfaces were activated using a plasma activation process.

[0068] The first wafer and the cover plate 15 are aligned so that the edges of the first wafer and the cover plate 15 are aligned.

[0069] Wafer-level low-temperature silicon-silicon bonding is performed on one side of the first groove 152 formed on the first wafer and the cover layer 15; exemplary, the bonding temperature of the wafer-level low-temperature silicon-silicon bonding is below 200 degrees Celsius. (Refer to...) Figure 5 c is a schematic diagram of the structure after bonding.

[0070] A MEMS movable structure 141 is fabricated on the surface of a first wafer to form a MEMS movable structure layer 16. This includes: defining an etching region on the side of the MEMS movable structure layer 16 opposite to the cover layer 15 using a double-sided photolithography process, the etching region corresponding to the position of the first groove 152; etching through the MEMS movable structure layer 16 to form the MEMS movable structure 141, the position of the MEMS movable structure 141 corresponding to the position of the first groove 152; for example, the etching process can be deep reactive ion etching. (Refer to...) Figure 5 In the middle d, it is a schematic diagram of the structure after etching the MEMS movable structure 141.

[0071] Figure 6 These are schematic diagrams of the device structures corresponding to preparation methods S2 and S3 provided in this embodiment of the invention; refer to Figure 6 :

[0072] In step S2, an application-specific integrated circuit layer 2 is fabricated on the second wafer.

[0073] In an optional embodiment, fabricating the application-specific integrated circuit layer 2 on the second wafer includes:

[0074] A second redistribution layer 22 is fabricated on the upper surface of the application-specific integrated circuit layer 2. The second redistribution layer 22 includes internal wiring 221 connecting the internal electrodes 21 and the internal circuitry. (Refer to...) Figure 6 A is a schematic diagram of the structure after the fabrication of the second redistribution layer 22.

[0075] For example, the second wiring layer 22 includes a multilayer dielectric layer 224 and internal wiring 221; the internal wiring 221 includes vertical wiring and horizontal wiring; the two ends of the internal wiring 221 are at different positions in the vertical direction.

[0076] The second wiring layer 22 is used to reposition the internal electrodes 21 of the application-specific integrated circuit (ASIC) layer 2. For example, the second wiring layer 22 is used to position the internal electrodes 21 of the ASIC outside the cavity region 13. When the internal circuit leads of the ASIC layer 2 are not completely distributed outside the cavity region 13 of the MEMS layer 1, the second wiring layer 22 is used to redistribute the positions of the internal electrodes 21, positioning them outside the cavity region 13 of the MEMS layer 1. The second wiring layer 22 allows the same ASIC to be compatible with the structures of multiple types of MEMS layers 1, improving compatibility.

[0077] In an optional embodiment, fabricating the application-specific integrated circuit layer 2 on the second wafer includes:

[0078] A second redistribution layer 22 is prepared on the upper surface of the application-specific integrated circuit layer 2; the second redistribution layer 22 includes a multilayer dielectric layer 224 and internal wiring 221; the multilayer dielectric layer 224 is etched to form a second groove 222; the position of the second groove 222 corresponds to the position of the first groove 152 mentioned above.

[0079] In an optional embodiment, after etching the multilayer dielectric layer 224 to form the second groove 222, the method further includes: preparing a getter 223 within the second groove 222 according to device application requirements. (See also...) Figure 6 C in the diagram is a schematic diagram of the structure after the getter is prepared.

[0080] In step S3, internal electrodes 21 that connect to the internal circuit are prepared on the surface of the application-specific integrated circuit layer 2.

[0081] Figure 7 These are schematic diagrams of the device structures corresponding to preparation methods S4 to S7 provided in this embodiment of the invention. (Refer to...) Figure 7 :

[0082] In step S4, wafer-level low-temperature silicon-silicon bonding is performed on one side of the internal electrode 21 fabricated between the MEMS layer 1 and the application-specific integrated circuit layer 2.

[0083] The side of the application-specific integrated circuit layer 2 where the internal electrode 21 is fabricated is the side where the second redistribution layer 22 is fabricated.

[0084] In an optional embodiment, it includes:

[0085] Clean MEMS layer 1 and application-specific integrated circuit layer 2 to remove contaminants.

[0086] The bonding surface is activated using a plasma activation process. The side of MEMS layer 1 that contacts application-specific integrated circuit layer 2 is the bonding surface.

[0087] Align the MEMS layer 1 and the application-specific integrated circuit layer 2.

[0088] The MEMS layer 1 and the application-specific integrated circuit (ASIC) layer 2 are bonded using wafer-level low-temperature silicon-silicon bonding. That is, the separately fabricated MEMS layer 1 and ASIC layer 2 are connected into a single unit using a wafer-level low-temperature silicon-silicon bonding process. (Refer to...) Figure 7 The figure in the middle is a schematic diagram of the structure after bonding.

[0089] For example, wafer-level low-temperature silicon-silicon bonding uses a bonding temperature below 200 degrees Celsius. Low-temperature bonding is compatible with circuit operating temperatures and reduces structural stress.

[0090] For example, wafer-level low-temperature silicon-silicon bonding is performed in a vacuum.

[0091] In an optional embodiment, after bonding, the first groove 152 and the second groove 222 form a sealed cavity; the cavity is provided with the aforementioned MEMS movable structure 141.

[0092] Correspondingly, the getter 223 prepared in the second groove 222 can absorb the residual gas in the cavity after vacuum bonding, thus meeting the device's requirements for the vacuum degree of packaging.

[0093] In an optional embodiment, after wafer-level low-temperature silicon-silicon bonding is performed on one side of the internal electrode 21 fabricated between the MEMS layer 1 and the application-specific integrated circuit layer 2, the method further includes: thinning a cover plate layer 15. Thinning the cover plate layer 15 can reduce the overall thickness of the device, enhance heat dissipation, and reduce the thickness of subsequent vias; it also reduces the difficulty of via fabrication and filling.

[0094] In step S5, a first via 11 and a second via 12 are etched on the MEMS layer 1. The first via 11 penetrates the MEMS layer 1, and its outlet on the side facing the application-specific integrated circuit layer 2 is connected to the internal electrode 21. The second via 12 penetrates the cover plate layer 15 and connects to the MEMS movable structure layer 16. (Refer to...) Figure 7 f is a schematic diagram of the structure after the through-hole is prepared.

[0095] For example, the etching process can be a deep reactive ion etching process.

[0096] In an optional embodiment, the second through hole 12 penetrates the cover plate layer 15 and the oxide layer 151, and the second through hole 12 is connected to the MEMS movable structure layer 16.

[0097] In an optional embodiment, the first via 11 is disposed outside the cavity region 13 of the MEMS layer 1.

[0098] MEMS layer 1 may include a cavity structure 14, which is a sealed cavity, and a movable MEMS structure 141 is disposed inside the cavity. The vertical region of the cavity structure 14 is the cavity region 13. The region outside the cavity region 13 of MEMS layer 1 is a non-critical region, which only serves as a structural support. Adding vias in the non-critical region has little impact on the device performance and size of MEMS layer 1.

[0099] For example, the MEMS layer 1 includes multiple cavities, and the first via 11 is disposed outside the multiple cavity regions 13 of the MEMS layer 1.

[0100] For example, the MEMS layer 1 includes a plurality of first through holes 11 disposed outside the cavity region 13.

[0101] The internal electrode 21 can be positioned outside the cavity region 13; a first through-hole 11 is provided at the corresponding position of the internal electrode 21; the first through-hole 11 enables communication between the internal circuit and the outside of the MEMS integrated device. The position of the first through-hole 11 corresponds to the position of the internal electrode 21, and the first through-hole 11 is positioned outside the cavity region 13, which enables the MEMS layer 1 and the dedicated integrated circuit layer 2 to be compatible with each other, directly integrated, and improves packaging efficiency.

[0102] In step S6, a dielectric layer is deposited on the inner wall of the through hole; and copper is electroplated into the through hole.

[0103] The vias include a first via 11 and a second via 12. The dielectric layer on the inner wall of the via is used to electrically isolate the metal material filling the via from the substrate.

[0104] In an optional embodiment, the metal material of the internal circuitry is copper.

[0105] Advanced integrated circuit manufacturing processes below 90 nanometers generally use copper interconnect technology; while traditional MEMS device interconnects generally use gold or aluminum interconnects, which are different metal materials and have poor compatibility; the through-hole metal material is copper, which can achieve mutual compatibility between MEMS layer 1 and advanced integrated circuit manufacturing processes, and can be directly integrated.

[0106] In step S7, a first redistribution layer 3 is prepared on the side opposite to the MEMS layer 1 and the application-specific integrated circuit layer 2; the first redistribution layer 3 includes internal wiring connecting the first via 11, the second via 12 and the external electrode 31.

[0107] For example, the external electrode 31 can be positioned at a location corresponding to the first through hole 11.

[0108] For example, the position of the external electrode 31 can be reset by rewiring.

[0109] The first via 11 and the second via 12 are connected through the first redistribution layer 3. That is, through the external electrode 31, the internal wiring of the first redistribution layer 3, the first via 11 and the second via 12, the electrical connection between the application-specific integrated circuit (ASIC) and the MEMS structure is realized, and the electrical connection between the ASIC, the MEMS structure and the outside of the integrated device is also realized.

[0110] For example, the external electrode 31 can be a metal bump. Using metal bumps for signal extraction can increase package interconnect density and reduce interconnect resistance and process parasitic parameters. (Refer to...) Figure 7 The figure in the middle is a schematic diagram of the structure after the external electrode is fabricated.

[0111] This invention provides a fabrication method that achieves interconnection between MEMS structures and application-specific integrated circuits (ASICs) through the fabrication of a first via 11, a second via 12, copper filling technology, and redistribution technology. The process is simple and relatively easy. Because the vias utilize copper filling, they are compatible with advanced integrated circuit chips. Placing the via openings on the cover plate layer 15 (which only provides packaging and support) and the MEMS movable structure layer 16 improves the compatibility of the via opening positions with ASIC chips. The integration of MEMS devices and ASICs, along with wafer-level vacuum packaging, is achieved through two wafer-level low-temperature silicon-silicon bonding techniques. This ensures compatibility with circuit operating temperatures, reduces structural stress, effectively reduces process parasitic parameters and chip area, and improves packaging efficiency. By sealing getters inside different cavities, the vacuum requirements of different devices can be met. Thinning technology reduces the thickness of the silicon cover plate layer, lowering the fabrication difficulty of vias while maintaining the same interconnect size density. Using metal bump flip-chip technology for signal extraction, after dicing, results in complete functional units, increasing interconnect density, reducing interconnect resistance and process parasitic parameters, and lowering packaging costs.

[0112] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A MEMS integrated device, characterized by, It includes a first wiring layer, a MEMS layer, and an application-specific integrated circuit layer using copper interconnect technology below 90 nanometers; The MEMS layer includes a cover plate layer and a MEMS movable structure layer; the cavity structure of the MEMS layer includes a MEMS movable structure. The MEMS layer and the dedicated integrated circuit layer are connected using wafer-level low-temperature silicon-silicon bonding technology. The MEMS layer has an inner wall deposited dielectric layer, a first through-hole and a second through-hole filled with copper. The first through-hole penetrates the MEMS layer and connects to the application-specific integrated circuit layer, and the second through-hole penetrates the cover plate layer and connects to the MEMS movable structure layer. The first wiring layer is located on the side opposite to the MEMS layer and the application-specific integrated circuit layer; the first wiring layer includes internal wiring connecting the first via, the second via and the external electrode; The dedicated integrated circuit layer has an internal electrode on the side facing the MEMS layer, which is connected to the internal circuit. The internal electrode is electrically connected to the first through hole. The first through-hole is located outside the cavity region of the MEMS layer in a non-critical area that only serves as structural support. The side of the application-specific integrated circuit (ASIC) layer facing the MEMS layer also includes a second rewiring layer; the second rewiring layer includes internal wiring connecting the internal electrodes and the internal circuits; the second rewiring layer is used to reset the position of the internal electrodes of the ASIC layer; the second rewiring layer includes multiple dielectric layers and the internal wiring; the internal wiring includes vertical wiring and horizontal wiring; the two ends of the internal wiring are at different positions in the vertical direction; the second rewiring layer is used to place the internal electrodes of the ASIC layer outside the cavity region; wherein, through the external electrodes, the internal wiring of the first rewiring layer, the first via, and the second via, electrical connection between the ASIC and the MEMS structure is realized, and electrical connection between the ASIC, the MEMS structure, and the outside of the integrated device is also realized.

2. The MEMS integrated device of claim 1, wherein, The internal circuit is made of copper.

3. The MEMS integrated device of claim 2, wherein, The cavity structure contains a getter.

4. A method of fabricating a MEMS integrated device, the method comprising: include: A MEMS layer is fabricated on a first wafer; the MEMS layer includes a cover plate layer and a MEMS movable structure layer. The cavity structure of the MEMS layer includes a movable MEMS structure; A dedicated integrated circuit layer is fabricated on the second wafer using copper interconnect technology below 90nm. Internal electrodes for connecting internal circuits are fabricated on the surface of the application-specific integrated circuit layer; Wafer-level low-temperature silicon-silicon bonding is performed on one side of the internal electrode fabricated between the MEMS layer and the application-specific integrated circuit layer; A first via and a second via are etched on the MEMS layer. The first via penetrates the MEMS layer and its outlet on the side facing the application-specific integrated circuit layer is connected to the internal electrode. The second via penetrates the cover plate layer and connects to the movable MEMS structure layer. The first via is located outside the cavity region of the MEMS layer and serves only as a non-critical area for structural support. A dielectric layer is deposited on the inner wall of the through-hole; copper is electroplated inside the through-hole. A first redistribution layer is fabricated on the side opposite to the MEMS layer and the application-specific integrated circuit layer; the first redistribution layer includes internal wiring connecting a first via, a second via, and an external electrode; The fabrication of an application-specific integrated circuit (ASIC) layer on the second wafer includes: fabricating a second redistribution layer on the upper surface of the ASIC layer; the second redistribution layer includes internal wiring connecting the internal electrodes and the internal circuits; the second redistribution layer is used to reset the positions of the internal electrodes of the ASIC layer; the second redistribution layer includes multiple dielectric layers and the internal wiring; the internal wiring includes vertical wiring and horizontal wiring; the two ends of the internal wiring are at different positions in the vertical direction; the second redistribution layer is used to place the internal electrodes of the ASIC layer outside the cavity region; wherein, through the external electrodes, the internal wiring of the first redistribution layer, the first via, and the second via, electrical connection between the ASIC and the MEMS structure is achieved, and electrical connection between the ASIC, the MEMS structure, and the outside of the integrated device is also achieved.

5. The MEMS integrated device fabrication method of claim 4, wherein, The internal circuit is made of copper.

6. The MEMS integrated device fabrication method of claim 5, wherein, The cavity structure contains a getter.

Images