Wire bonding structure of semiconductor package

Abstract

This invention relates to a wire bonding structure for a semiconductor package and a method for forming the same. The wire bonding structure includes: a redistribution layer; bonding pads located on the redistribution layer; and electronic components located on the redistribution layer and electrically connected to the bonding pads via leads, wherein the leads and bonding pads are interconnected via bump metal; wherein the redistribution layer includes dummy pads, which are at least partially located below the bump metal and within the vertical projection area of ​​the bump metal.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a wire bonding structure for a semiconductor package. Background Technology

[0002] like Figure 1 As shown, in current fan-out substrates, a fan-out layer 10 is disposed above the substrate 30. The fan-out layer 10 includes a dielectric layer of material such as PI (polyimide) and a redistribution line (RDL) located within the dielectric layer. A chip 20 is attached to the fan-out layer 10. Typically, wirebonding 15 is used to connect to pads on the fan-out layer 10 to connect the attached chip 20 to the RDL of the fan-out layer 10. However, current techniques for bonding to the RDL via wirebonding may encounter the following problems:

[0003] (1) After stacking the fan-out layer, the non-flat topography of the RDL surface will cause an imbalance in the wire bonding force.

[0004] (2) Organic PI material has low rigidity, and the force applied during wire bonding is easily absorbed by PI.

[0005] Both of the above factors can lead to poor bonding between the lead solder joint and the pad. Summary of the Invention

[0006] To address the aforementioned problems in related technologies, this invention proposes a lead bonding structure for a semiconductor package and a method for forming the same.

[0007] According to one aspect of the present invention, a lead bonding structure for a semiconductor package is provided, comprising: a redistribution layer; bonding pads located on the redistribution layer; and electronic components located on the redistribution layer and electrically connected to the bonding pads via leads, wherein the leads and the bonding pads are interconnected via bump metal; wherein the redistribution layer includes dummy pads, which are at least partially located below the bump metal and within the vertical projection area of ​​the bump metal.

[0008] In some embodiments, the area defined by the outer wall of the dummy pad is larger than the area defined by the outer wall of the bonding pad.

[0009] In some embodiments, the outer wall of the dummy pad is located outside the vertical projection area of ​​the bonding pad.

[0010] In some embodiments, the lead bonding structure further includes a connecting post located on a dummy pad and connecting the dummy pad to the bonding pad.

[0011] In some embodiments, the connecting posts include a plurality of connecting posts disposed at the same level, the plurality of connecting posts being arranged around a through hole beneath the bump metal.

[0012] In some embodiments, the dummy pad includes a first dummy pad and a second dummy pad located below the first dummy pad and spaced apart from the first dummy pad.

[0013] In some embodiments, the lead bonding structure further includes a plurality of connecting posts, including a connecting post connecting between the first dummy pad and the bonding pad and a connecting post connecting between the first dummy pad and the second dummy pad.

[0014] In some embodiments, a plurality of through-holes are provided below the bonding pads, and the plurality of through-holes are located within the area defined by the dummy pads.

[0015] In some embodiments, a plurality of through holes are stacked below the bonding pad, and the dummy pad is connected to the plurality of through holes.

[0016] In some embodiments, the outer wall of the dummy pad is perpendicularly aligned with the outer wall of the bonding pad.

[0017] According to another aspect of the present invention, a method for forming a semiconductor package is provided, comprising: providing a carrier and forming a redistribution layer on the carrier, wherein the redistribution layer includes dummy pads; forming bonding pads above the dummy pads; disposing electronic components above the redistribution layer and electrically connecting the bonding pads and the electronic components via leads, wherein a bump metal is formed between the bonding pads and the leads.

[0018] In some embodiments, the outer wall of the dummy pad is formed outside the area defined by the outer wall of the bonding pad, and the inner wall of the dummy pad is formed within the vertical projection area of ​​the bonding pad.

[0019] In some embodiments, forming a redistribution layer includes forming a connection post on a dummy pad, wherein the connection post is formed to be connected to the dummy pad.

[0020] In some embodiments, forming the connecting posts includes forming a plurality of connecting posts connected to the bonding pads on a layer at the same level below the bonding pads, and the plurality of connecting posts surrounding a through-hole below the bonding pads.

[0021] In some embodiments, the dummy pad is formed to include a first dummy pad and a second dummy pad located below the first dummy pad and spaced apart from the first dummy pad.

[0022] In some embodiments, the method further includes forming a connecting post located between the first dummy pad and the bonding pad.

[0023] In some embodiments, the method further includes forming a connecting post located between the first dummy pad and the second dummy pad.

[0024] In some embodiments, the method further includes forming a plurality of vias in a redistribution layer, wherein bonding pads are formed above the plurality of vias, and dummy pads surround the plurality of vias and are spaced apart from the plurality of vias.

[0025] In some embodiments, the method further includes forming a plurality of vias stacked in the redistribution layer, wherein bonding pads are formed above the plurality of vias and dummy pads are connected to the plurality of vias.

[0026] In some embodiments, the outer wall of the dummy pad is perpendicularly aligned with the outer wall of the bonding pad. Attached Figure Description

[0027] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0028] Figure 1 This is a schematic diagram of an existing fan-out type substrate.

[0029] Figure 2A This is a schematic diagram of a semiconductor package according to an embodiment of the present invention.

[0030] Figure 2B According to one embodiment Figure 2A A partially enlarged schematic diagram of the lead wire bonding structure in region A1.

[0031] Figure 2C yes Figure 2B A top-down view.

[0032] Figure 3 According to another embodiment Figure 2A A magnified view of a portion of region A1 in the diagram.

[0033] Figure 4A and Figure 4B According to another embodiment Figure 2A A magnified view of a portion of region A1 in the diagram.

[0034] Figure 4C and Figure 4D These are different embodiments. Figure 4A or Figure 4B A top-down view.

[0035] Figure 5 This is a flowchart of a method for forming a semiconductor package according to an embodiment of the present invention.

[0036] Figures 6A to 6D This is a schematic diagram of multiple stages of a method for forming a semiconductor package according to an embodiment of the present invention. Specific Implementation

[0037] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] An embodiment of the present invention provides a wire bonding structure for a semiconductor package. Figure 2A This is a schematic diagram of a semiconductor package according to an embodiment of the present invention. Figure 2A As shown, the RDL layer 220 can be formed on a carrier or substrate 210. The RDL layer 220 may include stacked multilayer dielectric materials 222 and corresponding multilayer RDLs 221 located within the dielectric materials 222. In some embodiments, the dielectric material 222 may be polyimide (PI) or other suitable dielectric materials. The surface of the RDL layer 220 has bonding pads 226. Electronic components 230 are also disposed on the surface of the RDL layer 220. In some embodiments, the electronic components 230 can be connected to the RDL layer 220 via an adhesive layer 235. The electronic components 230 are electrically connected to the bonding pads 226 on the RDL layer 220 via leads 250. The leads 250 and the bonding pads 226 are interconnected via bump metal 258.

[0039] Figure 2B According to one embodiment Figure 2A A partially enlarged schematic diagram of the lead-connection structure in region A1. Figure 2A and Figure 2B As shown, according to an embodiment of the present invention, the RDL layer 220 further includes dummy pads 280 located at least partially beneath the bump metal 258. The dummy pads 280 are not electrically connected to any RDL in the RDL layer 220. The dummy pads 280 are located at least partially beneath the bump metal 258. Figure 2A Within the vertical projection area of ​​the dummy pad 280. That is, the dummy pad 280 is at least partially located below the bump metal 258.

[0040] Because the dielectric material (e.g., PI) of the RDL layer 220 is relatively soft and has low support strength, in the above-described lead bonding structure of the present invention, by setting a dummy pad 280 in the vertical projection area below the bump metal 258, the dummy pad 280 can provide support for the bonding pad 226 of the lead 250, thereby making the foundation for the lead bonding process more stable during the lead bonding process, supporting the lead bonding process, and avoiding the bonding force of the lead being absorbed by the dielectric material (e.g., PI) of the RDL layer 220, resulting in poor bonding problems.

[0041] like Figure 2B As shown, the outer wall of the dummy pad 280 is located outside the vertical projection area of ​​the bonding pad 226. That is, the area defined by the outer wall of the dummy pad 280 is larger than the area defined by the outer wall of the bonding pad 226. Since the lead may be placed in a position below the bonding pad 226 where there is no support, delamination or cracking may occur between the bonding pad 226 and the dielectric material (e.g., PI) due to the bonding force, resulting in poor lead bonding stability. This invention provides a dummy pad 280 located below the bonding pad 226, and the area defined by the dummy pad 280 is larger than the bonding pad 226, which can provide sufficient support for lead bonding, avoid delamination or cracking, and improve lead bonding stability.

[0042] The dummy pad 280 can be multi-layered. For example... Figure 2B In the illustrated embodiment, the dummy pad 280 may include a first dummy pad 2801 and a second dummy pad 2802 located below and spaced apart from the first dummy pad 2801. The dummy pad 280 may also include a third dummy pad 2803 located below and spaced apart from the second dummy pad 2802. The RDL layer 220 may include a first RDL L2211, a second RDL L2212, and a third RDL L2213 stacked sequentially from bottom to top. The first dummy pad 2801 may be at the same layer level as the third RDL L2213 below the bonding pad 226. The second dummy pad 2802 may be at the same layer level as the second RDL L2212. The third dummy pad 2803 may be at the same layer level as the first RDL L2211.

[0043] In other embodiments, only a single-layer pseudo pad 2801 may be provided, and the single-layer pseudo pad 2801 may be located at the same level as the third layer RDL L2213, or it may be located at other levels.

[0044] In other embodiments, other layers of pseudo pads may also be provided.

[0045] Below the bonding pad 226, there are also a plurality of stacked vias 2291, 2292, and 2293. The vias 2291, 2292, and 2293 are located within the areas defined by corresponding dummy pads 2801, 2802, and 2803. Specifically, via 2291 interconnects the first RDL L2211 and the second RDL L2212; via 2291 is connected to pad P1 in the first RDL L2211 and pad P2 in the second RDL L2212. Via 2292 interconnects the second RDL L2212 and the third RDL L2213; specifically, via 2292 is connected to pad P2 in the second RDL L2212 and pad P3 in the third RDL L2213. Via 2293 interconnects the third layer RDL L2213 and the bonding pad 226. Specifically, via 3 is connected to pad P3 and bonding pad 226 in the third layer RDL L2213. Multilayer pseudo pads 2801, 2802, and 2803 can partially surround the pads P3, P2, and P1 of the corresponding RDL layers, so that pads P3, P2, and P1 can interconnect to other RDLs in the corresponding RDL layers.

[0046] Figure 2C yes Figure 2B A top-down view diagram. Combined with... Figure 2B and Figure 2C As shown, the size of the bonding pad 226 is A, the size of the pad P3 of the third RDL is B, and the size of the area defined by the dummy pad 280 is C. In some embodiments, the sizes of the pad P1 of the first RDL and the pad P2 of the second RDL can be equal, and both are equal to the size B of the pad P3 of the third RDL. In some embodiments, the size A of the bonding pad 226 can be in the range of 25 μm to 60 μm, and the size B of the pad P3 = C - 4 μm, and the size C of the area defined by the dummy pad 280 = A + 4 μm. In other embodiments, other suitable size configurations may also be used.

[0047] Figure 3 According to another embodiment Figure 2A A magnified view of a portion of region A1. Figure 3In one embodiment, a connecting post 2281 may also be provided on the first dummy pad 2801. The connecting post 2281 connects the first dummy pad 2801 to the bonding pad 226. There may be multiple connecting posts 2281, arranged around the through-hole 2293 below the bonding pad 226. Furthermore, a connecting post 2282 connects the first dummy pad 2801 and the second dummy pad 2802. The connecting post 2282 is at the same level as the through-hole 2292 and is arranged around the through-hole 2292. A connecting post 2293 connects the second dummy pad 2802 and the third dummy pad 2803. The connecting post 2293 is at the same level as the through-hole 2291 and is arranged around the through-hole 2291. Multiple connecting posts 2281, 2282, and 2283 may be arranged adjacent to the edge of the bonding pad 226. In some embodiments, one sidewall of the plurality of connecting posts 2281, 2282, 2283 may be perpendicularly aligned with the sidewall of the bonding pad 226, and the other sidewall of the plurality of connecting posts 2281, 2282, 2283 may be perpendicularly aligned with the inner wall of the corresponding dummy pads 2801, 2802, 2803. In other embodiments, the number and position of the connecting posts may be configured in other appropriate ways. For example, in other embodiments, only one or both of the connecting posts 2281, 2282, 2283 may be provided.

[0048] Figure 4A and Figure 4B According to another embodiment Figure 2A A magnified view of a portion of region A1 in the diagram. Figure 4C and Figure 4D These are different embodiments. Figure 4A or Figure 4B A top-down view.

[0049] exist Figure 4A and Figure 4B In the illustrated embodiment, dummy pads 280 are connected to a plurality of stacked vias 2291, 2292, and 2293. Specifically, dummy pads 2801, 2802, and 2803 are connected to the stacked vias 2291, 2292, and 2293 by connecting to corresponding pads P1, P2, and P3. In this embodiment, the outer wall of each dummy pad 280 may be perpendicularly aligned with the outer wall of the bonding pad 226. The outer wall of the dummy pad 280 may also extend beyond the outer wall of the bonding pad 226, i.e., the area defined by the dummy pad 280 is larger than the area of ​​the bonding pad 226. A plurality of connecting posts 2281, 2282, and 2283 are located within the area defined by the bonding pad 226. The sidewalls of the plurality of connecting posts 2281, 2282, and 2283 may be offset (spaced apart) perpendicularly from the sidewalls of the bonding pad 226.

[0050] exist Figure 4AIn the illustrated embodiment, a connecting post 2281 is provided connecting between the first dummy pad 2801 and the bonding pad 226, a connecting post 2282 connecting between the first dummy pad 2801 and the second dummy pad 2802, and a connecting post 2283 connecting between the second dummy pad 2802 and the third dummy pad 2803. Figure 4C and Figure 4D As shown, the number of connecting posts 2281, 2282, and 2283 at each level can be four (e.g., ...). Figure 4C ) or eight (such as Figure 4D In other embodiments, the number of connecting posts 2281, 2282, 2283 at each level can be any other number.

[0051] exist Figure 4B In the illustrated embodiment, a connecting post 2281 is provided only between the first dummy pad 2801 and the bonding pad 226. The second dummy pad 2802 and the third dummy pad 2803 can be vertically aligned with the first dummy pad. The second dummy pad 2802 and the third dummy pad 2803 can connect to pads P2 and P1 of corresponding levels to connect to the stacked vias 2291, 2292, and 2293. Figure 4C and Figure 4D As shown, the number of connecting posts 2281 between the first dummy pad 2801 and the bonding pad 226 can be four (e.g., Figure 4C ) or eight (such as Figure 4D In other embodiments, the number of connecting posts 2281 between the first dummy pad 2801 and the bonding pad 226 can be any other number.

[0052] According to embodiments of the present invention, a method for forming a semiconductor package having the wire bonding structure described above is also provided. Figure 5 A flowchart illustrating a method for forming a semiconductor package according to an embodiment of the present invention is shown.

[0053] In step S502, a carrier is provided, and an RDL layer is formed on the carrier, for example as... Figure 2A The RDL layer 220 in the text. The RDL layer includes pseudo pads, such as... Figure 2B , Figure 3 , Figure 4A and Figure 4B The pseudo pad 280 in the middle.

[0054] In step S504, a bonding pad is formed above the dummy pad, for example as... Figure 2A , Figure 2B , Figure 3 , Figure 4A and Figure 4B The bonding pad 226 in the middle.

[0055] In step S506, electronic components are placed above the RDL layer, such as... Figure 2A Electronic component 230. And via leads (e.g., as shown in the image). Figure 2A The lead 250 in the figure is used to electrically connect the bonding pad to the electronic component, wherein a bump metal 258 is formed between the bonding pad and the lead (e.g., Figure 2A (The bump metal 258 in the middle).

[0056] Figures 6A to 6D A schematic diagram of multiple stages of a method for forming a semiconductor package according to an embodiment of the present invention is shown.

[0057] like Figure 6A As shown, a carrier 210 is provided, and an RDL layer 220 is formed on the carrier 210. The RDL layer 220 may include, for example, Figure 2B , Figure 3 , Figure 4A and Figure 4B The pseudo pad 280 is shown.

[0058] like Figure 6B As shown, a bonding pad 226 is formed above the dummy pad 280.

[0059] In some embodiments, such as in forming as Figure 2B , Figure 3 , Figure 4A and Figure 4B In the embodiment of the illustrated structure, forming the RDL layer includes: forming a plurality of vias in the RDL layer, wherein bonding pads are formed above the plurality of vias, and dummy pads are arranged around and spaced from the plurality of vias. The bonding pads are formed above the plurality of vias, and the dummy pads are connected to the plurality of vias. The dummy pads may be formed to include: a first dummy pad and a second dummy pad located below and spaced from the first dummy pad. The dummy pads may also be formed to include a third dummy pad located below and spaced from the second dummy pad.

[0060] In some embodiments, such as in forming as Figure 3 , Figure 4A and Figure 4B In the embodiment of the illustrated structure, forming the RDL layer further includes: forming a connecting post on the dummy pad, wherein the connecting post is formed to connect to the dummy pad. A plurality of stacked vias are provided below the bonding pad. Forming the connecting post includes: forming a plurality of connecting posts connected to the bonding pad on a layer at the same level below the bonding pad, and the plurality of connecting posts surrounding the vias below the bonding pad. Forming the connecting post also includes: forming a connecting post located between the first dummy pad and the bonding pad.

[0061] In some embodiments, such as in forming as Figure 3 and Figure 4B In embodiments of the illustrated structure, forming the connecting post may further include: forming a connecting post located between the first dummy pad and the second dummy pad, and forming a connecting post located between the second dummy pad and the third dummy pad. In some embodiments, for example, when forming such a connecting post... Figure 4A and Figure 4B In the embodiment of the structure shown, the dummy pad is connected to a stacked via below the bonding pad. The outer wall of the dummy pad can be perpendicularly aligned with the outer wall of the bonding pad.

[0062] Then as Figure 6C As shown, electronic components 230 are disposed above RDL layer 220.

[0063] like Figure 6D As shown, the bonding pad 226 is electrically connected to the electronic component 230 via the lead 250. A bump metal 258 is formed between the bonding pad 226 and the lead 250.

[0064] In some embodiments, such as in forming as Figure 2B , Figure 3 , Figure 4A and Figure 4B In the embodiment of the structure shown, the outer wall of the dummy pad is formed outside the area defined by the outer wall of the bonding pad, and the inner wall of the dummy pad is formed within the vertical projection area of ​​the bonding pad.

[0065] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A wire bonding structure for a semiconductor package, characterized in that, include: Rewire layer; Bonding pads are located on the redistribution layer; An electronic component is located on the redistribution layer and electrically connected to the bonding pad via leads, wherein the leads and the bonding pad are interconnected by a bump metal located above the bonding pad; Multiple through-holes are stacked and located below the bonding pads; The redistribution layer includes a dummy pad, which is configured to surround the plurality of vias and define an annular region. The vertical projection of the outer wall of the bonding pad toward the dummy pad is located within the annular region, and the dummy pad is at least partially located below the bump metal and within the vertical projection area of ​​the bump metal.

2. The lead bonding structure of the semiconductor package according to claim 1, characterized in that, The area defined by the outer wall of the dummy pad is larger than the area defined by the outer wall of the bonding pad.

3. The lead bonding structure of the semiconductor package according to claim 1, characterized in that, The outer wall of the dummy pad is located outside the vertical projection area of ​​the bonding pad.

4. The lead bonding structure of the semiconductor package according to claim 1, characterized in that, Also includes: A connecting post is located on the dummy pad and connects the dummy pad to the bonding pad.

5. The lead bonding structure of the semiconductor package according to claim 4, characterized in that, The connecting posts include a plurality of connecting posts arranged at the same level, and the plurality of connecting posts are arranged around the plurality of through holes below the protrusion metal.

6. The lead bonding structure of the semiconductor package according to claim 1, characterized in that, The dummy pads include a first dummy pad and a second dummy pad located below the first dummy pad and spaced apart from it.

7. The lead bonding structure of the semiconductor package according to claim 6, characterized in that, Also includes: Multiple connecting posts, including a connecting post connecting between the first dummy pad and the bonding pad, and a connecting post connecting between the first dummy pad and the second dummy pad.

8. The lead bonding structure of the semiconductor package according to claim 1, characterized in that, The dummy pads are connected to the plurality of through holes.

9. The lead bonding structure of the semiconductor package according to claim 8, characterized in that, The outer wall of the dummy pad is perpendicularly aligned with the outer wall of the bonding pad.

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