Semiconductor package structure and method of manufacturing the same
By using inorganic materials to laminate organic substrates in the system-in-package structure, and combining dielectric and conductive layers to separate vias and suppression layers, the warping problem in the thermal process of organic materials is solved, resulting in higher product yield and packaging density.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ADVANCED SEMICON ENG INC
- Filing Date
- 2021-12-28
- Publication Date
- 2026-07-31
AI Technical Summary
In system-in-package (SIP) structures, the use of organic materials in the substrate for embedded components leads to severe warping during the thermal process, reducing product yield.
Inorganic materials are laminated into an organic substrate, and the expansion and contraction of the organic materials are suppressed after high-temperature sintering. Taking advantage of the difference in bonding force between inorganic and organic materials, dielectric and conductive layers are used to separate the vias and the suppression layer, forming a stable semiconductor packaging structure.
It effectively suppresses substrate warpage, improves product yield, and achieves higher packaging density through miniaturization and reduced signal transmission loss.
Smart Images
Figure CN114334901B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures and their manufacturing methods. Background Technology
[0002] In system-in-package (SISP) architectures, the technology of embedding active and passive components into the package substrate (SESUB) has advantages such as reducing the size of the package substrate product, and has become a research and development focus for manufacturers in this field in recent years.
[0003] In one case, the embedded component substrate has a substrate core layer for embedded components and circuit structures located on both sides of the substrate core layer. Usually, the dielectric material in the circuit structure is made of organic material. In terms of material properties, organic materials expand and contract severely during the thermal process, causing the overall substrate to warp and reducing the product yield. Summary of the Invention
[0004] This disclosure provides a semiconductor packaging structure and a method for manufacturing the same.
[0005] In a first aspect, this disclosure provides a semiconductor packaging structure, including: a substrate;
[0006] Electronic components are embedded in the substrate;
[0007] A first circuit structure is disposed on a first surface of the substrate, the first circuit structure is electrically connected to the electronic component, and the first circuit structure has a first suppression layer.
[0008] In some alternative embodiments, a second circuit structure is disposed on a second surface of the substrate opposite to the first surface, and the first circuit structure and the second circuit structure are symmetrically arranged and electrically connected through the electronic components.
[0009] In some alternative embodiments, the substrate has a first via, through which the first circuit structure and the second circuit structure are electrically connected.
[0010] In some alternative implementations, the first circuit structure and the second circuit structure are electrically connected via the electronic components.
[0011] In some alternative implementations, the first circuit structure has a second via, which is physically separated from the first suppression layer.
[0012] In some alternative embodiments, a first conductive layer is provided between the second via and the first suppression layer.
[0013] In some alternative embodiments, the first conductive layer is an electrode of a component, which is a capacitor or an inductor.
[0014] In some alternative embodiments, a first dielectric layer is provided between the second via and the first suppression layer.
[0015] In some alternative embodiments, the substrate has a second suppression layer.
[0016] In some alternative embodiments, the substrate has a first via that is physically separated from the second suppression layer.
[0017] In some alternative embodiments, a second conductive layer is provided between the second suppression layer and the first via.
[0018] In some alternative embodiments, a second dielectric layer is provided between the second suppression layer and the first via.
[0019] In some alternative embodiments, the substrate has a recess for accommodating the electronic component.
[0020] In some alternative implementations, it also includes:
[0021] A filler material is used to cover the electronic component and fill the gap between the recess and the electronic component.
[0022] In some alternative implementations, the first inhibition layer is an inorganic material.
[0023] In some alternative embodiments, the first dielectric layer is an organic material.
[0024] In some alternative implementations, the dielectric loss value of the first suppression layer is less than the dielectric loss value of the first dielectric layer.
[0025] In some alternative implementations, the dielectric constant of the first suppression layer is greater than the dielectric constant of the first dielectric layer.
[0026] In some alternative implementations, the coefficient of thermal expansion of the first suppression layer is less than that of the first dielectric layer.
[0027] In some alternative implementations, the first circuit structure and the second circuit structure have the same structure.
[0028] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging structure, including:
[0029] A substrate is provided in which electronic components are embedded;
[0030] A first circuit structure is formed on the first surface of the substrate, the first circuit structure having a first suppression layer.
[0031] In some alternative implementations, the first circuit structure is formed by the following method:
[0032] The first dielectric layer, the first suppression layer, and the first metal layer are laminated;
[0033] The first circuit structure is obtained by patterning.
[0034] In some alternative implementations, the first circuit structure is formed by the following method:
[0035] A first dielectric layer, a first suppression layer, a first conductive layer, and a first metal layer are laminated.
[0036] The first circuit structure is obtained by patterning.
[0037] In some alternative embodiments, the first conductive layer is formed around the first suppressing layer by a printing and sintering process.
[0038] In some alternative embodiments, the substrate has a second suppression layer and a first via, with a second conductive layer disposed between the second suppression layer and the first via.
[0039] In some alternative embodiments, the substrate has a second suppression layer and a first via, with a second dielectric layer disposed between the second suppression layer and the first via.
[0040] The semiconductor packaging structure and manufacturing method disclosed herein, by laminating inorganic materials into an organic substrate, can suppress the expansion and contraction of the organic materials surrounding the inorganic materials, since inorganic materials such as ceramic materials have smaller expansion and contraction amplitudes than organic materials after high-temperature sintering. Attached Figure Description
[0041] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0042] Figures 1 to 4 These are first to fourth structural schematic diagrams of semiconductor packaging structures according to embodiments of the present disclosure;
[0043] Figures 5 to 12 This is a schematic diagram of the first manufacturing process of the substrate in the semiconductor packaging structure according to an embodiment of the present disclosure;
[0044] Figures 13 to 19 This is a schematic diagram of the second manufacturing process of the substrate in the semiconductor packaging structure according to an embodiment of the present disclosure;
[0045] Figures 20 to 24 This is a schematic diagram of the third manufacturing process of the substrate in the semiconductor packaging structure according to an embodiment of the present disclosure;
[0046] Figures 25 to 27 This is a schematic diagram of the first manufacturing process of the first circuit structure in the semiconductor packaging structure according to an embodiment of the present disclosure;
[0047] Figures 28 to 30 This is a schematic diagram of the second manufacturing process of the first circuit structure in the semiconductor packaging structure according to an embodiment of the present disclosure.
[0048] Symbol explanation:
[0049] 1-Substrate, 11-First via, 111-First opening, 12-Second suppression layer, 13-Second dielectric layer, 14-Recess, 15-Substrate circuit layer, 16-Second conductive layer, 2-Electronic component, 3-First circuit structure, 31-Second via, 311-Second opening, 32-First conductive layer, 33-First suppression layer, 34-First dielectric layer, 35-First metal layer, 36-First circuit layer, 4-Second circuit structure, 5-Fill material, 6-Carrier board, 7-Temporary adhesive layer. Detailed Implementation
[0050] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0051] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.
[0052] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.
[0053] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.
[0054] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.
[0055] Figures 1 to 4 These are first to fourth structural schematic diagrams of a semiconductor packaging structure according to embodiments of the present disclosure. Figure 1 As shown, the semiconductor package structure includes a substrate 1, an electronic component 2, and a first circuit structure 3. The electronic component 2 is embedded in the substrate 1. The first circuit structure 3 is disposed on a first surface of the substrate 1. The first circuit structure 3 is electrically connected to the electronic component 2. The first circuit structure 3 has a first suppression layer 33.
[0056] In this embodiment, electronic component 2 can be an active component and / or a passive component. Active components can be, for example, chips with various functions (power management chips, logic function chips, memory chips, communication chips, microprocessor chips, graphics chips). Passive components can be, for example, capacitors, resistors, inductors, etc.
[0057] In this embodiment, the first suppression layer 33 can be made of an inorganic material. Inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, or tantalum oxide.
[0058] In one embodiment, the first circuit structure 3 may have a second via 31. The second via 31 may be made of a conductive material of metal or metal alloy, such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.
[0059] In one embodiment, substrate 1 may include a first dielectric layer 34. The first dielectric material may include an organic material, such as: polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc.
[0060] In one embodiment, the coefficient of thermal expansion of the first suppression layer 33 may be less than that of the first dielectric layer 34. When the first suppression layer 33 is laminated into the first dielectric layer 34, since the inorganic material of the first suppression layer 33 expands and contracts less after high-temperature sintering than the organic material of the first dielectric layer 34, the expansion and contraction of the first dielectric layer 34 surrounding the first suppression layer 33 can be suppressed, thereby reducing the degree of warpage.
[0061] In one embodiment, the dielectric constant of the first suppression layer 33 can be greater than that of the first dielectric layer 34. Due to the inclusion of the first suppression layer 33, the high dielectric constant Dk can effectively reduce the size of the impedance line to meet product miniaturization requirements.
[0062] In one embodiment, the dielectric loss value of the first suppression layer 33 can be less than that of the first dielectric layer 34. By incorporating the first suppression layer 33, the overall dielectric loss Df of the structure can be reduced, thereby reducing the loss of transmitted signals.
[0063] In one embodiment, if the inorganic material used in the first suppression layer 33 has good adhesion to the second via 31, the first suppression layer 33 can be exposed during the hole-opening process. In another embodiment, if the inorganic material used in the first suppression layer 33 has poor adhesion to the second via 31, the first suppression layer 33 can be kept from being exposed during the hole-opening process. That is, the second via 31 and the first suppression layer 33 can be physically separated to avoid contact between the first suppression layer 33 and the second via 31.
[0064] The physical separation between the second via 31 and the first suppression layer 33 can be achieved in the following two ways.
[0065] The first type, such as Figure 1 As shown, a first dielectric layer 34 may be provided between the second via 31 and the first suppression layer 33. Since the bonding force between organic materials and metals is greater than that between inorganic materials and metals, the first dielectric layer 34 can be used to separate the second via 31 and the first suppression layer 33, resulting in better bonding during the electroplating process of the second via 31.
[0066] The second type, such as Figure 2 As shown, a first conductive layer 32 can be provided between the second via 31 and the first suppression layer 33. Specifically, during the manufacturing process, the first conductive layer 32 can be pre-fabricated on the first suppression layer 33, thereby enabling the subsequent hole-opening process, such as laser drilling, to more accurately define the size of the second via 31. The first conductive layer 32 can be made of a conductive material of metal or metal alloy, such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or their alloys. Since the bonding force between metals is greater than that between inorganic materials and metals, the first conductive layer 32 can be used to separate the second via 31 and the first suppression layer 33, resulting in better bonding during the electroplating process of the second via 31.
[0067] In one embodiment, a capacitor or inductor may be composed of two electrodes and a dielectric material between them. Therefore, a first conductive layer 32 is disposed around the first suppression layer 33, and the first conductive layer 32 can serve as an electrode of the element (capacitor or inductor). The first suppression layer 33 and the first conductive layer 32 together can constitute a capacitor or inductor.
[0068] In one embodiment, the semiconductor package structure may further include a second circuit structure 4. The second circuit structure 4 may be disposed on a second surface of the substrate 1 opposite to the first surface, that is, the first circuit structure 3 and the second circuit structure 4 may be disposed on opposite sides of the substrate 1. The first circuit structure 3 and the second circuit structure 4 may be symmetrically arranged. The second circuit structure 4 may have the same structural features as the first circuit structure 3.
[0069] In one embodiment, the first line structure 3 can be electrically connected to the second line structure 4.
[0070] The electrical connection between the first circuit structure 3 and the second circuit structure 4 can be achieved in two ways. First, the substrate 1 can have a first via 11. The first circuit structure 3 and the second circuit structure 4 can be electrically connected through the first via 11. Second, the electronic component 2 can have a via inside. The first circuit structure 3 and the second circuit structure 4 can be electrically connected through the via inside the electronic component 2.
[0071] In one embodiment, the semiconductor package structure may further include a filler material 5. The substrate 1 may have a recess 14. The recess 14 may be used to accommodate an electronic component 2. The filler material 5 may cover the electronic component 2, filling the gap between the recess 14 and the electronic component 2. The filler material 5 may be, for example, a capillary underfill (CUF), a molded underfill (MUF), epoxy resin, resin, or other materials.
[0072] In one embodiment, such as Figure 3 and Figure 4 As shown, substrate 1 may have a second suppression layer 12. The second suppression layer 12 may be made of an inorganic material.
[0073] In one embodiment, if the inorganic material used in the second suppression layer 12 has good adhesion to the first via 11, the second suppression layer 12 can be exposed during the hole-opening process. In another embodiment, if the inorganic material used in the second suppression layer 12 has poor adhesion to the first via 11, the second suppression layer 12 can be kept from being exposed during the hole-opening process. That is, the first via 11 and the second suppression layer 12 can be physically separated to avoid contact between the second suppression layer 12 and the first via 11.
[0074] The first via 11 can be physically separated from the second suppression layer 12 in the following two ways.
[0075] The first type, such as Figure 3 As shown, a second dielectric layer 13 may be provided between the second suppression layer 12 and the first via 11. The second dielectric layer 13 may include an organic material. Since the bonding force between an organic material and a metal is greater than that between an inorganic material and a metal, the second dielectric layer 13 can be used to separate the first via 11 and the second suppression layer 12, resulting in better bonding during the electroplating process of the first via 11.
[0076] The second type, such as Figure 4 As shown, a second conductive layer 16 may be provided between the second suppression layer 12 and the first via 11. The second conductive layer 16 may be made of a conductive material such as metal or metal alloy. Specifically, during the manufacturing process, the second conductive layer 16 may be pre-fabricated on the second suppression layer 12, thereby enabling the use of laser or other hole-opening processes to more accurately define the size of the first via 11 during subsequent hole opening. The second conductive layer 16 may be made of a conductive material such as metal or metal alloy. Since the bonding force between metals is greater than that between inorganic materials and metals, the first conductive layer 32 can be used to separate the second via 31 and the first suppression layer 33, resulting in better bonding during the electroplating via process.
[0077] A substrate 1 is provided, and electronic components 2 are embedded in the substrate 1.
[0078] Please refer to Figures 5 to 30 , Figures 5 to 30 This is the manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure.
[0079] In one embodiment, such as Figures 5 to 12 The first manufacturing process of substrate 1 is shown. The dielectric material of substrate 1 can be an organic material.
[0080] like Figure 5 As shown, a substrate 1 is provided. A substrate circuit layer 15 is formed on the substrate 1.
[0081] like Figure 6 As shown, a first opening 111 is formed on the substrate 1.
[0082] Here, drilling processes such as laser drilling can be used to form the first opening 111.
[0083] like Figure 7 As shown, a first through-hole 11 is formed by filling it with conductive material.
[0084] like Figure 8 As shown, the recess 14 is formed in the substrate 1 .
[0085] Here, drilling techniques such as laser drilling can be used to form the recess 14.
[0086] like Figure 9 As shown, the substrate 1 is placed on the carrier plate 6 which has a temporary adhesive layer 7.
[0087] like Figure 10 As shown, electronic component 2 is placed in recess 14.
[0088] like Figure 11 As shown, the filler material 5 fills the gap between the electronic component 2 and the recess 14.
[0089] like Figure 12 As shown, remove the temporary adhesive layer 7 and the carrier plate 6.
[0090] In yet another embodiment, such as Figures 13 to 19 The second manufacturing process of substrate 1 is illustrated. Substrate 1 may have a second suppression layer 12. The second suppression layer 12 may be made of an inorganic material. If the bonding force between the inorganic material used in the second suppression layer 12 and the first via 11 is poor, the second suppression layer 12 may not be exposed when the via is opened. That is, the first via 11 and the second suppression layer 12 may be physically separated to avoid contact between the second suppression layer 12 and the first via 11.
[0091] like Figure 13As shown, a first opening 111 and a recess 14 are formed on the substrate 1.
[0092] like Figure 14 As shown, the substrate 1 is placed on the carrier plate 6 which has a temporary adhesive layer 7.
[0093] like Figure 15 As shown, electronic component 2 is placed in recess 14.
[0094] like Figure 16 As shown, a second dielectric layer 13 is formed in the first opening 111. A filler material 5 is formed in the recess 14.
[0095] Here, the second dielectric layer 13 can be made of an organic material. The formation of the second dielectric layer 13 and the filler 5 can be completed in the same step or in different steps.
[0096] like Figure 17 As shown, remove the temporary adhesive layer 7 and the carrier plate 6.
[0097] like Figure 18 As shown, a first opening 111 is formed in the second dielectric layer 13.
[0098] like Figure 19 As shown, a conductive material is filled to form a first via 11. A second dielectric layer 13 may be provided between the second suppression layer 12 and the first via 11. Since the bonding force between organic materials and metals is greater than that between inorganic materials and metals, the second dielectric layer 13 can be used to separate the first via 11 and the second suppression layer 12, resulting in better bonding during the electroplating process of the first via 11.
[0099] In yet another embodiment, such as Figures 20 to 24 The third manufacturing process of substrate 1 is shown. Substrate 1 may have a second suppression layer 12. The second suppression layer 12 may be made of an inorganic material. If the bonding force between the inorganic material used in the second suppression layer 12 and the first via 11 is poor, the second suppression layer 12 may not be exposed when the via is opened. That is, the first via 11 and the second suppression layer 12 may be physically separated to avoid contact between the second suppression layer 12 and the first via 11.
[0100] like Figure 20 As shown, a first opening 111 and a recess 14 are formed on the substrate 1. A second conductive layer 16 is formed on the second suppression layer 12.
[0101] Here, the second conductive layer 16 can be formed through a printing and sintering process. Therefore, during subsequent hole drilling, the second conductive layer 16 can assist laser drilling processes in more accurately defining the dimensions of the first via 11. The second conductive layer 16 can be made of a conductive material such as metal or a metal alloy.
[0102] like Figure 21 As shown, the substrate 1 is placed on the carrier plate 6 which has a temporary adhesive layer 7.
[0103] like Figure 22 As shown, electronic component 2 is placed in recess 14.
[0104] like Figure 23 As shown, a filler material 5 is formed in the recess 14. A conductive material is then filled in to form a first through-hole 11.
[0105] like Figure 24 As shown, remove the temporary adhesive layer 7 and the carrier plate 6.
[0106] The above illustrates three manufacturing processes for substrate 1. Based on substrate 1 obtained through any of the manufacturing processes, a first circuit structure 3 and a second circuit structure 4 are formed on a first surface and a second surface opposite to the first surface, respectively. The manufacturing process of the first circuit structure 3 is described below. The first circuit structure 3 is formed on the first surface of substrate 1, and the first circuit structure 3 may have a first suppression layer 33.
[0107] In one embodiment, such as Figures 25 to 27 The first manufacturing process of the first circuit structure 3 is shown. If the bonding force between the inorganic material used in the first suppression layer 33 and the second through hole 31 is poor, the first suppression layer 33 can be concealed when the hole is opened.
[0108] like Figure 25 As shown, a first dielectric layer 34, a first suppression layer 33, a first conductive layer 32, and a first metal layer 35 are laminated, with the first conductive layer 32 disposed around the first suppression layer 33.
[0109] Here, the first conductive layer 32 may be formed around the first suppression layer 33 by a printing and sintering process.
[0110] like Figure 26 As shown, the first metal layer 35 is patterned to form the second opening 311.
[0111] like Figure 27 As shown, a conductive material is filled to form a second via 31. The first circuit layer 36 is patterned by electroplating. The first circuit structure 3 is obtained.
[0112] Since the bonding force between metals is greater than that between inorganic materials and metals, the first conductive layer 32 can be used to separate the second via 31 from the first suppression layer 33, resulting in better bonding force during the electroplating process of the second via 31.
[0113] In yet another embodiment, such as Figures 28 to 30The second manufacturing process of the first circuit structure 3 is shown. If the bonding force between the inorganic material used in the first suppression layer 33 and the second through hole 31 is poor, the first suppression layer 33 can be concealed when the hole is opened.
[0114] like Figure 28 As shown, a first dielectric layer 34, a first suppression layer 33, and a first metal layer 35 are laminated.
[0115] like Figure 29 As shown, the first metal layer 35 is patterned to form the second opening 311.
[0116] like Figure 30 As shown, a conductive material is filled to form a second via 31. The first circuit layer 36 is patterned by electroplating. The first circuit structure 3 is obtained.
[0117] Since the bonding force between organic materials and metals is greater than that between inorganic materials and metals, the first dielectric layer 34 can be used to separate the second via 31 and the first suppression layer 33, resulting in better bonding force during the electroplating process of the second via 31.
[0118] Furthermore, the manufacturing method of the second circuit structure 4 can be obtained by the same method as the first circuit structure 3 described above, and will not be repeated here.
[0119] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.
Claims
1. A semiconductor package structure, comprising: substrate; Electronic components are embedded in the substrate; A first circuit structure is disposed on a first surface of the substrate, the first circuit structure is electrically connected to the electronic component, and the first circuit structure has a first suppression layer. The substrate has a recess, the electronic component is placed in the recess, and the first circuit structure covers the recess; The first circuit structure has a second via, which is electrically connected to the electronic component and is physically separated from the first suppression layer. A first conductive layer is provided between the second via and the first suppression layer, and the first conductive layer is an electrode of the element, the element being a capacitor or an inductor; or, a first dielectric layer is provided between the second via and the first suppression layer, the coefficient of thermal expansion of the first suppression layer being less than the coefficient of thermal expansion of the first dielectric layer, the dielectric constant of the first suppression layer being greater than the dielectric constant of the first dielectric layer, and the dielectric loss value of the first suppression layer being less than the dielectric loss value of the first dielectric layer.
2. The semiconductor packaging structure according to claim 1, further comprising: The second circuit structure is disposed on the second surface of the substrate opposite to the first surface. The first circuit structure and the second circuit structure are symmetrically arranged and electrically connected through the electronic components.
3. The semiconductor package structure of claim 2, wherein, The substrate has a first through hole, and the first circuit structure and the second circuit structure are electrically connected through the first through hole.
4. The semiconductor packaging structure according to claim 1, wherein, A first dielectric layer is provided between the second via and the first suppression layer.
5. The semiconductor package structure of claim 3, wherein, The substrate has a second suppression layer, and the first via is physically separated from the second suppression layer.
6. The semiconductor package structure of claim 5, wherein, A second conductive layer or a second dielectric layer is provided between the second suppression layer and the first via.
7. The semiconductor packaging structure according to claim 1, further comprising: A filler material is provided, wherein the substrate has a recess for accommodating the electronic component, the filler material covers the electronic component, and the filler material fills the gap between the recess and the electronic component.