Electrostatic protection structure and manufacturing method thereof

Abstract

The present disclosure provides an electrostatic protection structure and a manufacturing method thereof. The electrostatic protection structure comprises: a first diode structure, a first end of the first diode structure is connected to a ground end, and a second end is connected to a signal end; a second diode structure adjacent to the first diode structure, a first end of the second diode structure is connected to a power supply end, and a second end is connected to the signal end; and a breakdown voltage of the first diode structure and / or the second diode structure is less than a preset threshold. The above technical solution changes the avalanche breakdown occurring in the PN junction with a lower doping concentration and a higher applied voltage to the Zener breakdown occurring in the PN junction with a higher doping concentration by doping the first diode structure or the second diode structure, thereby improving the electrostatic discharge protection capability of the input and output ends of the integrated circuit.

Description

Technical Field

[0001] This application relates to the field of electrostatic discharge (ESD) protection technology for integrated circuits, and in particular to an ESD protection structure and a method for manufacturing the ESD protection structure. Background Technology

[0002] With the development of large-scale integrated circuits, their key process feature dimensions are constantly shrinking, making electrostatic discharge (ESD) damage to integrated circuits increasingly easier. ESD protection circuits are generally used to protect integrated circuits. The four modes of ESD protection for integrated circuits are: PS mode (positive charge flows in from the input terminal (I / O) and out from the ground terminal (VSS)); NS mode (negative charge flows in from the input terminal (I / O) and out from the ground terminal (VSS); PD mode (positive charge flows in from the IO terminal and out from the power supply terminal (VDD)); and ND mode (negative charge flows in from the IO terminal and out from VDD).

[0003] However, since integrated circuit inputs and outputs generally use the smallest process dimensions, the layout of the surrounding electrostatic discharge (ESD) protection circuits is limited. The metal interconnects in PS mode or ND mode are the longest, resulting in the largest parasitic resistance and making them the weakest points in terms of ESD protection.

[0004] Therefore, improving the electrostatic discharge protection capability of integrated circuit input and output terminals is a technical problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by this disclosure is to provide an electrostatic discharge protection structure and a method for manufacturing the electrostatic discharge protection structure, so as to improve the electrostatic discharge protection capability of the input and output terminals of integrated circuits.

[0006] To address the aforementioned issues, this disclosure provides an electrostatic discharge (ESD) protection structure, comprising: a first diode structure, wherein a first end of the first diode structure is connected to a ground terminal and a second end is connected to a signal terminal; a second diode structure, adjacent to the first diode structure, wherein a first end of the second diode structure is connected to a power supply terminal and a second end is connected to a signal terminal; and the breakdown voltage of the first diode structure and / or the second diode structure is less than a preset threshold.

[0007] In some embodiments, the first diode structure includes a P-type region, an N-type region, and a P-well. The P-type region serves as the first end of the first diode structure, the N-type region serves as the second end of the first diode structure, the P-well and the N-type region form a PN junction, and a shallow trench isolation structure exists between adjacent P-type regions.

[0008] In some embodiments, the first diode structure further includes a first doped region located within the P-well and below the N-type region.

[0009] In some embodiments, the dopant ion type of the first doped region is the same as that of the P-type region, including boron ions.

[0010] In some embodiments, the second diode structure includes a P-type region, an N-type region, and a first N-well, wherein the N-type region serves as the first end of the second diode structure, the P-type region serves as the second end of the second diode structure, the first N-well and the P-type region form a PN junction, and a shallow trench isolation structure exists between adjacent N-type regions.

[0011] In some embodiments, the second diode structure further includes a second doped region located within the first N-well and below the P-type region.

[0012] In some embodiments, the dopant ion type of the second doped region is the same as that of the N-type region, including phosphorus ions and arsenic ions.

[0013] In some embodiments, the electrostatic discharge protection structure further includes a substrate, the substrate comprising: a semiconductor substrate, a deep N-well layer located on the semiconductor substrate, and / or a second N-well located next to the first diode and in a direction away from the second diode.

[0014] This disclosure also provides a method for fabricating an electrostatic discharge (ESD) protection structure, comprising: providing a substrate; forming a first diode substructure and a second diode substructure on the substrate; performing ion implantation on the first diode substructure to form a first diode structure; and / or performing ion implantation on the second diode substructure to form a second diode structure; wherein the reverse breakdown voltage of the first diode structure and / or the second diode structure is less than the reverse breakdown voltage of the first diode substructure and / or the second diode substructure.

[0015] In some embodiments, the method of forming the substrate includes: providing a semiconductor substrate, forming a deep N-well layer on the semiconductor substrate and / or forming a second N-well adjacent to the first diode structure and in a direction away from the second diode structure.

[0016] In some embodiments, the first diode substructure includes a P-type region, an N-type region, and a P-well. The P-type region serves as the anode of the first diode substructure and is connected to the ground terminal. The N-type region serves as the cathode of the first diode substructure and is connected to the signal terminal. The P-well and the N-type region form a PN junction.

[0017] In some embodiments, the ion implantation of the first diode substructure includes forming a heavily doped region of a first doping type below the cathode of the first diode substructure to reduce the reverse breakdown voltage of the first diode structure.

[0018] In some embodiments, ions of the same type as the doping ions in the P-well are used to ion-dopat the heavily doped region of the first doping type, and the doping concentration is greater than that of the P-well.

[0019] In some embodiments, the second diode substructure includes a P-type region, an N-type region, and a first N-well. The N-type region serves as the cathode of the second diode substructure and is connected to the power supply terminal. The P-type region serves as the anode of the second diode substructure and is connected to the signal terminal. The first N-well and the P-type region form a PN junction.

[0020] In some embodiments, the ion implantation of the second diode substructure includes forming a heavily doped region of a second doping type below the anode of the second diode substructure to reduce the reverse breakdown voltage of the second diode structure.

[0021] In some embodiments, the ion implantation of the second diode substructure includes forming a heavily doped region of a second doping type below the anode of the second diode substructure to reduce the reverse breakdown voltage of the second diode structure.

[0022] In some embodiments, ions of the same type as the N-well doping ions are used to ion-dopat the heavily doped region of the second doping type, and the doping concentration is greater than that of the N-well.

[0023] In some embodiments, the first diode substructure includes a P-well and a plurality of P-type regions, with a shallow trench isolation structure formed between adjacent P-type regions.

[0024] In some embodiments, the second diode substructure includes: a first N-well and a plurality of N-type regions, with a shallow trench isolation structure formed between adjacent N-type regions.

[0025] The above technical solution, by doping the first diode substructure or the second diode substructure, changes the avalanche breakdown that occurs in a PN junction with a low doping concentration and a high applied voltage to a Zener breakdown that occurs in a PN junction with a high doping concentration, thereby reducing the breakdown voltage, improving the voltage clamping capability, and thus improving the electrostatic discharge protection capability of the integrated circuit.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an electrostatic protection structure according to an embodiment of the present disclosure.

[0028] Figure 2 This is a schematic diagram of the first diode structure in an electrostatic discharge protection circuit according to an embodiment of the present disclosure.

[0029] Figure 3 This is a schematic diagram of an electrostatic protection structure according to an embodiment of the present disclosure.

[0030] Figure 4 This is a schematic diagram of the second diode structure in an electrostatic discharge protection circuit according to an embodiment of the present disclosure.

[0031] Figure 5 This is a schematic diagram of a method for manufacturing an electrostatic protection structure according to an embodiment of this disclosure.

[0032] Figure 6 This is a schematic diagram of a first diode substructure and a second diode substructure in one embodiment of the present disclosure.

[0033] Figure 7 This is a schematic diagram of the first diode substructure and the second diode substructure in another embodiment of this disclosure.

[0034] Figure 8 This is a schematic diagram of the first diode structure and the second diode structure in another embodiment of this disclosure. Detailed Implementation

[0035] The specific embodiments of the electrostatic discharge (ESD) protection structure and its manufacturing method provided in this application will be described in detail below with reference to the accompanying drawings. The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the scope of this disclosure or its application or use. That is, those skilled in the art will understand that they merely illustrate exemplary methods that can be used, and not exhaustive methods. Furthermore, unless otherwise specifically stated, the relative arrangement of components and steps described in these embodiments does not limit the scope of this disclosure.

[0036] Figure 1 This is a schematic diagram of an electrostatic protection structure according to an embodiment of this disclosure. Please refer to the following: Figure 1 The electrostatic discharge (ESD) protection structure includes a first diode structure 1 and a second diode structure 2. The first end 11 of the first diode structure 1 is connected to a ground terminal, and the second end 12 is connected to a signal terminal 3. The second diode structure 2 is adjacent to the first diode structure 1, and its first end 21 is connected to a power supply terminal, and its second end 22 is connected to the signal terminal 3. The breakdown voltage of the first diode structure 1 is less than a preset threshold. In this specific embodiment, the preset threshold for the breakdown voltage is 4V.

[0037] In some embodiments, the first diode structure 1 includes a P-type region 4, an N-type region 5, and a P-well 61. The P-type region 4 serves as the first terminal 11 of the first diode structure 1, and the N-type region 5 serves as the second terminal 12 of the first diode structure 1. The P-well 61 and the N-type region 5 form a PN junction. The P-type region 4 serves as the lead-out structure of the P-well 61, connected to the ground terminal. The doping concentration of the P-type region 4 is greater than that of the P-well 61 to reduce contact resistance. A shallow trench isolation structure 7 is provided between adjacent P-type regions 4. The shallow trench isolation structure 7 is used to isolate adjacent P-type regions 4 or to isolate the N-type region 5 from the P-type region 4. The depth of the shallow trench isolation structure 7 is greater than the depth of the P-type region 4 and the N-type region 5 to achieve electrical isolation. The shallow trench isolation structure 7 includes an oxide layer, such as silicon oxide. In some embodiments, the shallow trench isolation structure 7 further includes a silicon nitride layer. Silicon oxide and silicon nitride layers are sequentially formed at the bottom and sidewalls of the shallow trench, and then an oxide layer is deposited within the trench to form the shallow trench isolation structure 7. The shallow trench isolation structure 7 is strip-shaped and arranged between the P-type region 4 and the N-type region 5 along the direction of extension of the sidewalls of the P-type region 4 and the N-type region 5.

[0038] In some embodiments, the first diode structure 1 further includes a first doped region 81, located within the P-well 61 and below the N-type region 5. The doped ion type of the P-type region 4 is boron ions, the doped ion type of the first doped region 81 is the same as that of the P-type region 4, and the ion doping concentration of the first doped region 81 is greater than that of the P-well 61.

[0039] In some embodiments, the electrostatic discharge protection structure further includes a substrate 9, the substrate 9 including a semiconductor substrate 91, a deep N-well layer 92 located on the semiconductor substrate, and / or a second N-well 93 located next to the first diode 1 and away from the direction of the second diode 2.

[0040] Figure 2 This is a schematic diagram of the first diode structure in an electrostatic discharge (ESD) protection circuit according to an embodiment of this disclosure. Please refer to the following: Figure 2The electrostatic discharge (ESD) protection circuit includes a pull-down circuit A, a pull-up circuit B, a load circuit C, a clamping power supply D, a first diode structure 1, and a second diode structure 2. The first terminal 11 of the first diode structure 1 is connected to the ground terminal VSS, and the second terminal 12 is connected to the signal terminal 3. The first terminal 21 of the second diode structure 2 is connected to the power supply terminal VDD, and the second terminal 22 is connected to the signal terminal 3. In PS mode, current flows in from the signal terminal 3. If the first diode experiences avalanche breakdown with a breakdown voltage above 10V, positive charges will reach the ground terminal via the second diode structure 2 and the clamping power supply D. Due to the long path and parasitic resistance, the voltage drop between the signal terminal 3 and the ground terminal VSS will be much greater than the source-drain breakdown voltage of the NMOS transistor N in the pull-down circuit A, causing damage to the NMOS transistor N in the pull-down circuit A. By doping the first diode structure 1, positive charges flow in from the signal terminal 3, breaking down the first diode with a breakdown voltage of approximately 4V. This clamps the voltage drop between the signal terminal 3 and the ground terminal VSS to approximately 4V, protecting the NMOS transistor N in the pull-down circuit A.

[0041] The above technical solution, by performing additional doping on the first diode structure 1 to form a first doped region 81 with a high doping concentration, makes the P-well 61, the first doped region 81 and the N-type region 5 form a PN junction with a high doping concentration. This changes the avalanche breakdown with a high breakdown voltage that occurs in the PN junction with a low doping concentration to the Zener breakdown with a low breakdown voltage that occurs in the PN junction with a high doping concentration, thereby reducing the reverse breakdown voltage of the first diode structure 1, enhancing the voltage clamping capability of the first diode structure, protecting the NMOS transistor N in the pull-down circuit A, and thus improving the electrostatic discharge protection capability of the integrated circuit input and output terminals.

[0042] Figure 3 This is a schematic diagram of an electrostatic protection structure according to an embodiment of this disclosure. Please refer to the following: Figure 3 The electrostatic discharge (ESD) protection structure includes a first diode structure 1 and a second diode structure 2. The first end 11 of the first diode structure 1 is connected to a ground terminal, and the second end 12 is connected to a signal terminal 3. The second diode structure 2 is adjacent to the first diode structure 1, and its first end 21 is connected to a power supply terminal, and its second end 22 is connected to the signal terminal 3. The breakdown voltage of the second diode structure 2 is less than a preset threshold. In this specific embodiment, the preset threshold for the breakdown voltage is 4V.

[0043] In some embodiments, the second diode structure 2 includes a P-type region 4, an N-type region 5, and a first N-well 62. The N-type region 5 serves as the first terminal 21 of the second diode structure 2, and the P-type region 4 serves as the second terminal 22 of the second diode structure. The first N-well 62 and the P-type region 4 form a PN junction. The N-type region 5 serves as the lead-out structure of the first N-well 62, connected to the power supply terminal. The doping concentration of the N-type region 5 is greater than that of the first N-well 62 to reduce contact resistance. A shallow trench isolation structure 7 is provided between adjacent N-type regions 5. The shallow trench isolation structure 7 is used to isolate adjacent P-type regions 4 or to isolate the N-type region 5 from the P-type region 4. The depth of the shallow trench isolation structure 7 is greater than the depth of the P-type region 4 and the N-type region 5 to achieve electrical isolation. The shallow trench isolation structure 7 includes an oxide layer, such as silicon oxide. In some embodiments, the shallow trench isolation structure 7 further includes a silicon nitride layer. Silicon oxide and silicon nitride layers are sequentially formed at the bottom and sidewalls of the shallow trench, and then an oxide layer is deposited within the trench to form the shallow trench isolation structure 7. The shallow trench isolation structure 7 is strip-shaped and arranged between the P-type region 4 and the N-type region 5 along the direction of extension of the sidewalls of the P-type region 4 and the N-type region 5.

[0044] In some embodiments, the second diode structure 2 further includes a second doped region 82, located within the first N-well 62 and below the P-type region 4. The doped ions of the N-type region 5 are phosphorus ions or arsenic ions, the doped ion type of the second doped region 82 is the same as that of the N-type region 5, and the ion doping concentration of the second doped region 82 is greater than that of the first N-well 62.

[0045] In some embodiments, the electrostatic discharge protection structure further includes a substrate 9, the substrate 9 including a semiconductor substrate 91, a deep N-well layer 92 located on the semiconductor substrate and / or a second N-well 93 located next to the first diode 1 and away from the direction of the second diode 2.

[0046] Figure 4 This is a schematic diagram of the second diode structure in an electrostatic discharge (ESD) protection circuit according to an embodiment of this disclosure. Please refer to the following: Figure 4The electrostatic discharge (ESD) protection circuit includes a pull-down circuit A, a pull-up circuit B, a load circuit C, a clamping power supply D, a first diode structure 1, and a second diode structure 2. The first terminal 11 of the first diode structure 1 is connected to the ground terminal VSS, and the second terminal 12 is connected to the signal terminal 3. The first terminal 21 of the second diode structure 2 is connected to the power supply terminal VDD, and the second terminal 22 is connected to the signal terminal 3. In ND mode, negative charge flows in from the signal terminal 3. If the second diode experiences avalanche breakdown with a breakdown voltage exceeding 10V, the current will reach the ground terminal via the clamping power supply D and the first diode structure 1. Due to the long path and parasitic resistance, the voltage drop between the signal terminal 3 and the power supply terminal VDD will be much greater than the source-drain breakdown voltage of the PMOS transistor P in the pull-up circuit B, causing damage to the PMOS transistor P in the pull-up circuit B. By doping the second diode structure 2, negative charge flows in from the signal terminal 3, breaking down the second diode with a breakdown voltage of approximately 4V. This clamps the voltage drop between the signal terminal 3 and the power supply terminal VDD to approximately 4V, protecting the PMOS transistor P in the pull-up circuit B.

[0047] The above technical solution, by performing additional doping on the second diode structure 2 to form a second doped region 82 with a high doping concentration, enables the N-well 62, the second doped region 82, and the P-type region 4 to form a PN junction with a high doping concentration. This changes the avalanche breakdown with a high breakdown voltage that occurs in the PN junction with a low doping concentration to the Zener breakdown with a low breakdown voltage that occurs in the PN junction with a high doping concentration, thereby reducing the reverse breakdown voltage of the second diode structure 2, enhancing the voltage clamping capability of the second diode structure, protecting the PMOS transistor P in the pull-up circuit B, and thus improving the electrostatic discharge protection capability of the integrated circuit input and output terminals.

[0048] In other embodiments, while the first doped region 81 in the first diode structure 1 is doped with boron ions, the second doped region 82 in the second diode structure 2 is doped with phosphorus ions or arsenic ions. This protects the NMOS transistor N in the pull-down circuit A in the event of PS mode failure and the PMOS transistor P in the pull-up circuit B in the event of ND mode failure, thereby improving the electrostatic discharge protection capability of the integrated circuit's input and output terminals.

[0049] Figure 5 This is a schematic diagram of a method for manufacturing an electrostatic protection structure according to an embodiment of this disclosure. Please refer to the following. Figure 5The method for fabricating the electrostatic discharge (ESD) protection structure includes: step S101, providing a substrate; step S102, forming a first diode substructure and a second diode substructure on the substrate; step S103, performing ion implantation on the first diode substructure to form a first diode structure; and step S104, performing ion implantation on the second diode substructure to form a second diode structure, wherein the reverse breakdown voltage of the first diode structure and / or the second diode structure is less than the reverse breakdown voltage of the first diode substructure and / or the second diode substructure. In other embodiments, only the first diode substructure or only the second diode substructure may be ion implanted.

[0050] Step S101, providing a substrate. The method of forming the substrate includes: providing a semiconductor substrate, forming a deep N-well layer on the semiconductor substrate, and / or a second N-well located adjacent to the first diode and away from the direction of the second diode.

[0051] Step S102: A first diode substructure and a second diode substructure are formed on the substrate. Figure 6 This is a schematic diagram of a first diode substructure and a second diode substructure according to an embodiment of this disclosure. Please refer to the following: Figure 6 The first diode substructure 101 includes a P-type region 4, an N-type region 5, and a P-well 61. The P-type region 4 serves as the anode of the first diode substructure, i.e., the first end 11 of the first diode structure, connected to the ground terminal; the N-type region 5 serves as the cathode of the first diode substructure, i.e., the second end 12 of the first diode structure, connected to the signal terminal 3; the P-well 61 and the N-type region 5 form a PN junction. The second diode substructure includes a P-type region 4, an N-type region 5, and a first N-well 62. The N-type region 5 serves as the cathode of the second diode substructure, i.e., the first end 21 of the second diode structure, connected to the power supply terminal; the P-type region 4 serves as the anode of the second diode substructure, i.e., the second end 22 of the second diode structure, connected to the signal terminal 3; the first N-well 62 and the N-type region 5 form a PN junction.

[0052] Step S103: Ion implantation is performed on the first diode substructure to form the first diode structure. Figure 1 This is a schematic diagram of an electrostatic protection structure according to an embodiment of this disclosure. Please refer to the following: Figure 1A heavily doped region 81 of a first doping type is formed below the cathode of the first diode substructure to form a first diode structure 1, thereby reducing the reverse breakdown voltage of the first diode structure 1. The first diode structure 1 includes a P-type region 4, an N-type region 5, and a P-well 61. The P-type region 4 serves as the first terminal 11 of the first diode structure 1, and the N-type region 5 serves as the second terminal 12 of the first diode structure 1. The P-well 61 and the N-type region 5 form a PN junction. The P-type region 4 serves as the lead-out structure of the P-well 61, connected to the ground terminal. The doping concentration of the P-type region 4 is greater than that of the P-well 61 to reduce contact resistance. Ion implantation of the first diode substructure includes forming a first doped region 81 of a first doping type below the cathode of the first diode substructure to reduce the reverse breakdown voltage of the first diode structure. The first doped region 81 is located within the P-well 61 and below the N-type region 5. The doped ion type of the P-type region 4 is boron ion, the doped ion type of the first doped region 81 is the same as that of the P-type region 4, and the ion doping concentration of the first doped region 81 is greater than that of the P-well 61.

[0053] Step S104: Ion implantation is performed on the second diode substructure to form the second diode structure. Figure 3 This is a schematic diagram of an electrostatic protection structure according to an embodiment of this disclosure. Please refer to the following: Figure 3 A heavily doped region 82 of a second doping type is formed below the anode of the second diode substructure to form the second diode structure 2, thereby reducing the reverse breakdown voltage of the second diode structure 2. In this specific embodiment, the preset threshold of the breakdown voltage is 4V. The second diode structure 2 includes a P-type region 4, an N-type region 5, and a first N-well 62. The N-type region serves as the first terminal 21 of the second diode structure 2, the P-type region 4 serves as the second terminal 22 of the second diode structure, the N-well 62 and the P-type region 4 form a PN junction, and the N-type region 5 serves as the lead-out structure of the first N-well 62, connecting to the power supply terminal. The doping concentration of the N-type region 5 is greater than that of the first N-well 62 to reduce the contact resistance. The ion implantation of the second diode substructure includes forming a second doped region 82 of a second doping type below the anode of the second diode substructure. The second doped region 82 is located within the N-well 62 and below the P-type region 4 to reduce the reverse breakdown voltage of the second diode structure 2. The doped ions in the N-type region 5 are phosphorus ions or arsenic ions, the doped ion type in the second doped region 82 is the same as that in the N-type region 5, and the ion doping concentration in the second doped region 82 is greater than that in the N-well 62.

[0054] The above technical solution involves doping the area below the cathode of the first diode substructure 101 with boron ions to form a heavily doped region 81 of the first doping type, thereby forming a PN junction with a high doping concentration between the P-well 61, the heavily doped region 81, and the N-type region 5. It also involves doping the area below the anode of the second diode substructure with phosphorus or arsenic ions to form a heavily doped region 82 of the second doping type, thereby forming a PN junction with a high doping concentration between the N-well 62, the heavily doped region 82, and the P-type region 4. This transforms the high-voltage avalanche breakdown that occurs in a PN junction with a low doping concentration into a low-voltage Zener breakdown that occurs in a PN junction with a high doping concentration, thereby reducing the reverse breakdown voltage of the first diode structure 1 or the second diode structure 2, improving voltage clamping capability, and thus enhancing the electrostatic discharge protection capability of the integrated circuit's input and output terminals.

[0055] Figure 7 This is a schematic diagram of a first diode substructure and a second diode substructure according to another embodiment of this disclosure. Please refer to the following. Figure 7 The first diode substructure 101 includes a P-well 61 and a plurality of P-type regions 4, with a shallow trench isolation structure 7 formed between adjacent P-type regions 4. A portion of the P-type regions 4 serves as the anode of the first diode substructure, connected to the ground terminal VSS. The second diode substructure 102 includes a first N-well 62 and a plurality of N-type regions, with a shallow trench isolation structure 7 formed between adjacent N-type regions. A portion of the N-type regions 5 serves as the anode of the second diode substructure, connected to the power supply terminal VDD. The shallow trench isolation structure 7 includes an oxide layer, such as silicon oxide. In some embodiments, the shallow trench isolation structure 7 further includes a silicon nitride layer. Silicon oxide and silicon nitride layers are sequentially formed at the bottom and sidewalls of the shallow trench, and then oxide is deposited within the trench to form the shallow trench isolation structure 7. The shallow trench isolation structure 7 is strip-shaped and arranged between the P-type regions 4 and the N-type regions 5 along the direction of extension of the sidewalls of the P-type regions 4 and the N-type regions 5.

[0056] Figure 8 This is a schematic diagram of the first diode structure and the second diode structure in another embodiment of this disclosure. Please refer to the following. Figure 8The ion implantation of the first diode substructure includes forming a third doped region 83 of a third doping type on a portion of the P-type region 4 of the first diode substructure. The third doped region 83 serves as the cathode of the first diode structure, i.e., the second terminal 12 of the first diode structure, connected to the signal terminal 3. A portion of the P-type region 4 that has not undergone the third type of doping serves as the first terminal 11 of the first diode structure, connected to the ground terminal. The P-well 61, the portion of the P-type region, and the third doped region 83 constitute a PN junction. The third doped region 83 can be formed simultaneously using the process of manufacturing source-drain contact plugs for NMOS transistors. When manufacturing NMOS transistors, to reduce the contact resistance of the source-drain contact plugs and increase conductivity, an additional N-type heavy doping is performed on the source-drain region. Therefore, the third doped region 83 can be formed simultaneously without additional process steps. The ion implantation of the second diode substructure includes forming a fourth doped region 84 of a fourth doping type on a portion of the N-type region 5 of the second diode substructure. This fourth doped region 84 serves as the cathode of the second diode structure, meaning the second terminal 22 of the second diode structure is connected to the signal terminal. The N-well 62, the portion of the N-type region, and the fourth doped region of the fourth doping type constitute a PN junction. The fourth doped region 84 can be formed simultaneously using the process of manufacturing source-drain contact plugs for PMOS transistors. When manufacturing PMOS transistors, to reduce the contact resistance of the source-drain contact plugs and increase conductivity, an additional P-type heavy doping is performed on the source-drain region. Therefore, the fourth doped region 84 can be formed simultaneously without additional process steps.

[0057] In some other embodiments, only the first diode substructure may be ion implanted to form the third doped region 83, or only the second diode substructure may be ion implanted to form the fourth doped region 84.

[0058] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention.

Claims

1. An electrostatic protection structure, characterized in that, include: The first diode structure has a first end connected to a ground terminal and a second end connected to a signal terminal. The second diode structure is adjacent to the first diode structure. The first end of the second diode structure is connected to the power supply terminal, and the second end is connected to the signal terminal. The breakdown voltage of the first diode structure and / or the second diode structure is less than a preset threshold. The first diode structure includes a P-type region, an N-type region, and a P-well, wherein the P-type region serves as the first end of the first diode structure, and the N-type region serves as the second end of the first diode structure. The first diode structure further includes: a first doped region located within the P-well and below the N-type region; The first doped region of the first doping type is doped with ions of the same type as the doping ions of the P-well, and the doping concentration is greater than that of the P-well.

2. The electrostatic protection structure according to claim 1, characterized in that, The P-well and the N-type region form a PN junction, and there is a shallow trench isolation structure between adjacent P-type regions.

3. The electrostatic protection structure according to claim 2, characterized in that, The dopant ion type in the first doped region is the same as that in the P-type region, including boron ions.

4. The electrostatic protection structure according to claim 1, characterized in that, The second diode structure includes a P-type region, an N-type region, and a first N-well. The N-type region serves as the first end of the second diode structure, and the P-type region serves as the second end of the second diode structure. The first N-well and the P-type region form a PN junction, and there is a shallow trench isolation structure between adjacent N-type regions.

5. The electrostatic protection structure according to claim 4, characterized in that, The second diode structure further includes a second doped region located within the first N-well and below the P-type region.

6. The electrostatic protection structure according to claim 5, characterized in that, The doping ion types in the second doped region are the same as those in the N-type region, including phosphorus ions and arsenic ions.

7. The electrostatic protection structure according to claim 1, characterized in that, Also includes: The substrate includes: a semiconductor substrate, a deep N-well layer on the semiconductor substrate, and / or a second N-well located next to the first diode and away from the direction of the second diode.

8. A method for manufacturing an electrostatic protection structure, characterized in that, include: Provide substrate; A first diode substructure and a second diode substructure are formed on the substrate; Ion implantation is performed on the first diode substructure to form the first diode structure; and / or Ion implantation is performed on the second diode substructure to form the second diode structure; The reverse breakdown voltage of the first diode structure and / or the second diode structure is less than the reverse breakdown voltage of the first diode substructure and / or the second diode substructure; The first diode substructure includes a P-type region, an N-type region, and a P-well, wherein the P-type region serves as the first end of the first diode substructure, and the N-type region serves as the second end of the first diode substructure. The first diode substructure further includes: a first doped region located within the P-well and below the N-type region; The first doped region of the first doping type is doped with ions of the same type as the doping ions of the P-well, and the doping concentration is greater than that of the P-well.

9. The method for manufacturing the electrostatic protection structure according to claim 8, characterized in that, The method of forming the substrate includes: providing a semiconductor substrate, forming a deep N-well layer on the semiconductor substrate, and / or forming a second N-well adjacent to the first diode structure and in a direction away from the second diode structure.

10. The method for manufacturing the electrostatic protection structure according to claim 9, characterized in that, The P-type region serves as the anode of the first diode substructure, connected to the ground terminal, and the N-type region serves as the cathode of the first diode substructure, connected to the signal terminal. The P-well and the N-type region form a PN junction.

11. The method for manufacturing the electrostatic protection structure according to claim 10, characterized in that, The ion implantation of the first diode substructure includes: forming a heavily doped region of the first doping type below the cathode of the first diode substructure to reduce the reverse breakdown voltage of the first diode structure.

12. The method for manufacturing the electrostatic protection structure according to claim 9, characterized in that, The second diode substructure includes a P-type region, an N-type region, and a first N-well. The N-type region serves as the cathode of the second diode substructure and is connected to the power supply terminal. The P-type region serves as the anode of the second diode substructure and is connected to the signal terminal. The first N-well and the P-type region form a PN junction.

13. The method for manufacturing the electrostatic protection structure according to claim 12, characterized in that, The ion implantation of the second diode substructure includes forming a heavily doped region of a second doping type below the anode of the second diode substructure to reduce the reverse breakdown voltage of the second diode structure.

14. The method for manufacturing the electrostatic protection structure according to claim 13, characterized in that, The heavily doped region of the second doping type is ion-doped using ions of the same type as the N-well doping ions, with a doping concentration greater than that of the N-well.

15. The method for manufacturing the electrostatic protection structure according to claim 9, characterized in that, The first diode substructure includes a P-well and a plurality of P-type regions, with a shallow trench isolation structure formed between adjacent P-type regions.

16. The method for manufacturing the electrostatic protection structure according to claim 9, characterized in that, The second diode substructure includes: a first N-well and a plurality of N-type regions, with a shallow trench isolation structure formed between adjacent N-type regions.

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