Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a device isolation layer on a substrate, a pattern group including a fin pattern extending in a first direction, and a gate structure extending in a second direction to intersect the fin pattern. A first pattern group of the pattern group can include the first fin pattern. At least a portion of the first fin pattern can be arranged in the second direction at a first pitch. The first pattern group can include a first flat portion extending from a first recessed portion. A central axis of the first recessed portion can be spaced apart from a central axis of one of the first fin pattern in the second direction by a first distance. The first flat portion can have a first width in the second direction, the first width being greater than the first pitch. The first distance can be about 0.8 times to about 1.2 times the first pitch.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0125674, filed on September 28, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The exemplary embodiments disclosed herein relate to a semiconductor device and a method of manufacturing the same. Background Technology

[0004] With the increasing demand for high performance, high speed, and / or multifunctionality in semiconductor devices, the integration density of semiconductor devices is increasing. As semiconductor devices trend towards higher integration, the scaling down of transistors within semiconductor devices has accelerated, and methods for forming transistors with reduced dimensions have been investigated. Furthermore, to overcome the limitations in operating characteristics caused by the size reduction of planar metal-oxide-semiconductor FETs (MOSFETs), efforts have been made to develop semiconductor devices including FinFETs with three-dimensional channels. Summary of the Invention

[0005] Example embodiments of this disclosure provide a semiconductor device including a fin pattern with uniform dimensions and / or a method of manufacturing thereof.

[0006] According to exemplary embodiments of the present invention, a semiconductor device may include: a substrate; a device isolation layer on the substrate; a plurality of pattern groups, each pattern group including a fin pattern extending from the substrate, the fin pattern protruding upward beyond the upper surface of the device isolation layer and extending in a first direction; and a gate structure on the substrate. The gate structure may intersect the fin pattern and may extend in a second direction intersecting the first direction. The plurality of pattern groups may include a first pattern group including a first fin pattern. At least one pair of first fin patterns may be arranged in the second direction at a first spacing, and the first spacing may be the minimum spacing of the first fin patterns in the second direction. The first pattern group may include a first recess and a first flat portion of the substrate. The central axis of the first recess may be spaced apart from the central axis of a corresponding first fin pattern in the second direction by a first distance. The first flat portion may extend from the first recess and may have a first width in the second direction. The first distance may be about 0.8 to about 1.2 times the first spacing. The first width may be greater than the first spacing.

[0007] According to exemplary embodiments of the present invention, a semiconductor device may include: a substrate; a device isolation layer on the substrate; a pattern set on the substrate including fin patterns extending along a first direction; and a gate structure on the substrate. The gate structure may intersect with the fin patterns and extend in a second direction perpendicular to the first direction. The fin patterns of the pattern set may include a first fin pattern and a second fin pattern arranged with a minimum spacing in the second direction. The pattern set may include a first recess and a second recess of the substrate, which may be recessed into the substrate. The first fin pattern and the second fin pattern may be located between the first recess and the second recess. The first recess and the second recess may be adjacent to the first fin pattern and the second fin pattern, respectively. The pattern set may also include a flat portion of the substrate. The flat portion may extend from at least one of the first recess and the second recess, and the flat portion may have a substantially flat surface. The width of the substantially flat surface of the flat portion in the second direction may be greater than the minimum spacing.

[0008] According to exemplary embodiments of the present invention, a semiconductor device may include a substrate and a device isolation layer. The substrate may include a first flat portion having a first width. The substrate may include a first recess and a second recess, each recessed into the substrate. One end of the first recess may be connected to one end of the first flat portion. One end of the second recess may be connected to the other end of the first flat portion. The substrate may include a first fin pattern, a second fin pattern, and a third fin pattern, each projecting vertically from the substrate. The first fin pattern may be connected to the other end of the first recess. The second fin pattern may be connected to the other end of the second recess. The third fin pattern may be arranged such that it is at least a distance from the center of one of the first and second fin patterns. The device isolation layer may cover the first flat portion, the first recess, and the second recess on the substrate. The first width may be greater than the horizontal distance between the central axis of the first recess and the central axis of the first fin pattern.

[0009] According to an example embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming a mask layer, a first sacrificial layer, and a second sacrificial layer on a substrate; forming a second sacrificial pattern by etching the second sacrificial layer; forming a first spacer on the sidewall of the second sacrificial pattern; selectively removing the second sacrificial pattern relative to the first spacer; etching the first sacrificial layer using the first spacer as an etching mask to form the first sacrificial pattern; forming the second spacer on the sidewall of the first sacrificial pattern; selectively removing the first sacrificial pattern relative to the second spacer; etching the mask layer using the second spacer as an etching mask to form a mask pattern; removing a portion of the mask pattern using a photolithography process; etching the substrate using the mask pattern as an etching mask to form a fin pattern and a protective fin pattern; removing the protective fin pattern to form a recess in the substrate using a photolithography process; forming a device isolation layer such that the upper portion of the fin pattern can protrude; removing the first spacer, the second spacer, and the mask pattern; and forming a gate structure and source / drain regions. Attached Figure Description

[0010] The above and other aspects, features, and effects of the inventive concept of this disclosure will be more clearly understood from the following specific embodiments, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0012] Figures 2A to 2C This is a cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0013] Figures 3A to 3C This is a cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0014] Figures 4A to 4C This is a cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0015] Figure 5 This is a cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0016] Figures 6A to 16 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure; and

[0017] Figures 17A to 20B This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0018] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the numerical values ​​intended to be associated include manufacturing or operational tolerances (e.g., ±10%) near said numerical values. Furthermore, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended not to require precision in the geometry, but rather a tolerance for that geometry within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially,” it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical values ​​or shapes.

[0019] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0020] Figure 1 This is a plan view of a semiconductor device according to an example embodiment. Figure 2A This shows a cross-sectional view of a semiconductor device taken along line I-I'. Figure 2B This shows a cross-sectional view of the semiconductor device taken along line II-II'. Figure 2C This shows a cross-sectional view of the semiconductor device taken along line III-III'.

[0021] refer to Figures 1 to 2C The semiconductor device 100 may include a substrate 101, fin patterns 105A, 105B and 105C, a device isolation layer 110, source / drain regions 130, a gate structure 160, an interlayer insulating layer 170 and a contact structure 180. The semiconductor device 100 may include a FinFET device, wherein the fin patterns 105A, 105B and 105C may be configured as transistors with fin structures.

[0022] Substrate 101 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon germanide (SiGe). Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0023] Substrate 101 may have a first region R1, a second region R2, and a third region R3. In semiconductor device 100, the first to third regions R1, R2, and R3 may be spaced apart from each other or adjacent to each other. Fin patterns 105A, 105B, and 105C extending in a first direction X may be formed in the first to third regions R1, R2, and R3 of substrate 101 using photoresist patterning. Protective fin patterns 105GA, 105GB, and 105GC (see [reference needed]) may be removed from the first to third regions R1, R2, and R3 of substrate 101. Figure 9AThe recesses RS1, RS2 and RS3 are formed using a process. The first flat portion FP1 and the second flat portion FP2, which extend from the second recess RS2 and the third recess RS3 respectively, can be formed in the second region R2 and the third region R3 of the substrate 101.

[0024] Fin patterns 105A, 105B, and 105C may extend from substrate 101 and may protrude further than the upper surface of device isolation layer 110. Fin patterns 105A, 105B, and 105C may be configured to extend on substrate 101 along a first direction X and may be spaced apart from each other in a second direction Y by a desired and / or alternative predetermined distance. Fin patterns 105A, 105B, and 105C may have substantially the same width.

[0025] Fin patterns 105A, 105B and 105C may include a first pattern group PG1, a second pattern group PG2 and a third pattern group PG3. The first pattern group PG1 includes one or more fin patterns 105A formed in the first region R1, the second pattern group PG2 includes one or more second fin patterns 105B formed in the second region R2, and the third pattern group PG3 includes one or more third fin patterns 105C formed in the third region R3.

[0026] Each of the first to third pattern groups PG1, PG2, and PG3 can be configured as a single pattern group formed on substrate 101, for example, by a multi-patterning process (e.g., self-aligned quadruple patterning (SAQP), self-aligned triple patterning (SATP), or self-aligned double patterning (SADP)). The number of fin patterns included in a single pattern group is not limited to the example shown in the figures. Patterns (including dummy patterns) formed in a single pattern group can be arranged by a multi-patterning process at a desired and / or alternative predetermined spacing P1 or a desired and / or alternative predetermined interval. The term "spacing" as used in the specification can refer to the distance between the central axis of the first pattern and the central axis of the second pattern adjacent to the first pattern. The central axis of the pattern can be a central axis truncated along a direction parallel to the direction in which the pattern extends. For example, the central axis of a pattern extending along a first direction can be defined between the side surfaces of the pattern that are opposite each other along a second direction.

[0027] Each of the first to third pattern groups PG1, PG2, and PG3 may respectively include a first recessed portion to a third recessed portion RS1, RS2, and RS3 formed on the substrate 101 by a multiple patterning process. The second pattern group PG2 may include a first flat portion FP1 formed on the substrate 101 by a multiple patterning process. The third pattern group PG3 may include a second flat portion FP2 formed on the substrate 101 by a multiple patterning process. The first to third recessed portions RS1, RS2, and RS3, the first flat portion FP1, and the second flat portion FP2 may be configured as patterns formed on the surface of the substrate 101, and may also be understood as components included in the substrate 101.

[0028] like Figure 1 As shown in the first region R1, the first fin patterns 105A and the first recess RS1 in the first pattern group PG1 can be arranged in the second direction Y at a spacing substantially the same as the minimum spacing P1. The first fin patterns 105A of the first pattern group PG1 can be arranged at a second spacing greater than the minimum spacing P1. The second spacing can be substantially equal to approximately twice the minimum spacing P1.

[0029] like Figure 1 As shown in the second region R2, the adjacent second fin patterns 105B in the second pattern group PG2 can be arranged with a minimum spacing P1 in the second direction Y, and the adjacent second fin patterns 105B and the second recess RS2 can be arranged with a spacing substantially the same as the minimum spacing P1 in the second direction Y. Figure 1 As shown in the third region R3, the adjacent third fin patterns 105C in the third pattern group PG3 can be arranged with a minimum spacing P1 in the second direction Y, and the adjacent third fin patterns 105C and the third recess RS3 can be arranged with a spacing that is substantially the same as the minimum spacing P1 in the second direction Y.

[0030] like Figure 1 As shown in the second region R2 and the third region R3, the first flat portion FP1 and the second flat portion FP2 can refer to the flat surface of the substrate 101 without a pattern, or they can correspond to the area (indicated by the dotted line) in the upper part of the substrate 101 where a mask pattern is formed in a multi-patterning process. In this case, the central axis of the mask pattern corresponding to the first flat portion FP1 and the second flat portion FP2 can be set from the center of the adjacent second recess RS2 or the third recess RS3 along the second direction Y at a spacing substantially the same as the minimum spacing P1.

[0031] Considering the possibility of process errors in the manufacturing of semiconductor devices, the phrase "substantially the same" as used in the specification may be used. For example, the concept of "first distance" and "second distance" being substantially the same may mean that one distance corresponds to about 0.8 to about 1.2 times the other distance, or about 0.7 to about 1.3 times the other distance.

[0032] The first recess RS1 may be configured to be adjacent to the first fin pattern 105A of the first pattern group PG1 and may extend in the first direction X. The first recess RS1 may be located at a height lower than the height of the upper end of the first fin pattern 105A. The first recess RS1 may be a pattern formed on the surface of the substrate 101 between the first fin patterns 105A, and in an example embodiment, the shape of the first recess RS1 may be based on the protective fin pattern 105GA (see...). Figure 9A The etching depth varies. For example, the first recess RS1 can have a shape like... Figure 2A The first region R1 in the figure shows a concave shape, but its example embodiments are not limited to this.

[0033] The center of the first recess RS1 can be spaced apart from the center of the adjacent first fin pattern 105A by a first distance d1 in the second direction Y. The first distance d1 can be substantially the same as the minimum spacing P1, or it can be about 0.8 to about 1.2 times the minimum spacing P1. The first distance d1 can be less than the second spacing of the first fin pattern 105A in the first region R1.

[0034] The second recess RS2 can be positioned adjacent to the second fin pattern 105B of the second pattern group PG2 and can extend in the first direction X. The second recess RS2 can be positioned at a height lower than the upper end of the second fin pattern 105B. Similar to the first recess RS1, the shape of the second recess RS2 can vary depending on the etching depth of the protective fin pattern.

[0035] like Figure 2A As shown in the second region R2, two pairs of second fin patterns 105B can be provided, and a pair of second recesses RS2 and a first flat portion FP1 can be provided between the two pairs of second fin patterns 105B. The center of each second recess in the pair of second recesses RS2 can be spaced apart from the center of the second fin pattern in the adjacent pair of second fin patterns 105B near the second recess by a second distance d2 in the second direction Y. The second distance d2 can be substantially the same as the minimum spacing P1, or it can be about 0.8 to about 1.2 times the minimum spacing P1.

[0036] A first flat portion FP1 may be disposed between a pair of second recesses RS2. The first flat portion FP1 may refer to a portion of the surface of the substrate 101, which may be substantially smooth and without irregularities. The first flat portion FP1 may have a first width W1 in the second direction Y. The first width W1 of the first flat portion FP1 may be equal to or greater than the minimum pitch P1. The first width W1 of the first flat portion FP1 may be less than approximately twice the minimum pitch P1, or may be equal to approximately twice the minimum pitch P1. For example, in an exemplary embodiment, the first width W1 of the first flat portion FP1 may be greater than approximately twice the minimum pitch P1 and less than approximately four times the minimum pitch P1.

[0037] The first flattened portion FP1 may be a region in which an upper mask pattern is removed during the manufacturing process of a semiconductor device, thereby preventing the formation of a fin pattern, and the first width W1 of the first flattened portion FP1 may vary depending on the amount of mask pattern removed from the upper portion. For example, when only one mask pattern 120DA is removed from the upper portion of the substrate 101 (see... Figure 7A When the first flat portion FP1 is used, the first width W1 can be substantially the same as twice the distance Fd between the opposing side surfaces of the second fin pattern 105B and the sum of the width Fw of the second fin pattern 105B. Alternatively, the first width W1 of the first flat portion FP1 can be substantially the same as the value obtained by subtracting the width Fw of one of the second fin patterns 105B from twice the minimum spacing P1.

[0038] One end of the first flat portion FP1 can be connected to one end of the second recessed portion RS2, and the other end of the first flat portion FP1 can be connected to one end of another second recessed portion RS2. The other end of the second recessed portion RS2 connected to one end of the first flat portion FP1 can be connected to the second fin pattern 105B, and the other end of the second recessed portion RS2 connected to the other end of the first flat portion FP1 can be connected to another second fin pattern 105B.

[0039] The third recess RS3 can be positioned adjacent to the third fin pattern 105C of the third pattern group PG3 and can extend in the first direction X. The third recess RS3 can be positioned at a height lower than the upper end of the third fin pattern 105C. Similar to the first recess RS1, the shape of the third recess RS3 can vary depending on the etching depth of the protective fin pattern.

[0040] like Figure 2AAs shown in the third region R3, a pair of third recesses RS3 and a pair of second flat portions FP2 can be configured as a pair of third fin patterns 105C interposed therebetween. The center of each of the pair of third recesses RS3 can be spaced apart by a third distance d3 in the second direction Y from the center of the adjacent pair of third fin patterns 105C near that third recess. The third distance d3 can be substantially the same as the minimum spacing P1, or can be about 0.8 to about 1.2 times the minimum spacing P1.

[0041] A pair of second flat portions FP2 may be disposed on both sides of a pair of third recesses RS3, wherein the pair of third recesses RS3 are located between the pair of second flat portions FP2. The pair of second flat portions FP2 may refer to a portion of the surface of the substrate 101, which may be substantially smooth and without bumps. Each of the pair of second flat portions FP2 may have a second width W2 in the second direction Y. The second width W2 of the second flat portion FP2 may be greater than approximately twice the minimum pitch P1, or may be equal to twice the minimum pitch P1. The second width W2 may be greater than the first width W1.

[0042] The second flattened portion FP2 can be a region where the upper mask pattern is removed during the manufacturing of a semiconductor device, thus preventing the formation of a fin pattern. Furthermore, the second width W2 of the second flattened portion FP2 can be varied according to the number of mask patterns removed from the upper portion. For example, when two mask patterns 120DB arranged adjacent to each other in the second direction Y are removed from the upper portion of the substrate 101 (see...), the fin pattern can be changed. Figure 7A When the second flat portion FP2 is used, the second width W2 can be substantially the same as the sum of three times the distance Fd between the opposite sides of the pair of third fin patterns 105C and twice the width Fw of one of the third fin patterns 105C. Alternatively, the second width W2 of the second flat portion FP2 can be substantially the same as the value obtained by subtracting the width Fw of one of the third fin patterns 105C from three times the minimum spacing P1.

[0043] However, in the example embodiment, the second flat portion FP2 may further extend to the outside of the third pattern group PG3 in the third region R3.

[0044] In the example embodiment, the second width W2 of the second flat portion FP2 can also vary depending on the arrangement of the third fin pattern 105C in the third pattern group PG3. For example, in the third region R3, when the third recess RS3 (the outermost pattern in the third pattern group), a pair of third fin patterns 105C, and the third recess RS3 (the innermost pattern in the third pattern group) are arranged in a right-to-left order, the second width W2 of the second flat portion FP2 adjacent to the third recess RS3 (the innermost pattern in the third pattern group) can be greater than approximately four times the minimum spacing P1, or it can be the same as four times the minimum spacing P1.

[0045] Device isolation layer 110 may define fin patterns 105A, 105B, and 105C in substrate 101. For example, device isolation layer 110 may be formed by a shallow trench isolation (STI) process. Device isolation layer 110 may cover a portion of the side surfaces of fin patterns 105A, 105B, and 105C and the upper surface of substrate 101. Device isolation layer 110 may cover first to third recesses RS1, RS2, and RS3, first flat portion FP1, and second flat portion FP2 formed on substrate 101. Device isolation layer 110 may be formed of an insulating material. Device isolation layer 110 may be formed of, for example, oxides, nitrides, or combinations thereof.

[0046] Source / drain regions 130 can be disposed on the fin patterns 105A, 105B, and 105C on both sides of the gate structure 160. For example... Figure 2B As shown, fin patterns 105A, 105B, and 105C may be partially recessed on both sides of the gate structure 160, and source / drain regions 130 may be disposed on the recessed fin patterns 105A, 105B, and 105C. The source / drain regions 130 may be configured as source or drain regions of transistors in the semiconductor device 100. The source / drain regions 130 may be connected to each other or merged on two or more fin patterns, and may form a single source / drain region 130, but exemplary embodiments are not limited thereto.

[0047] The source / drain region 130 may be a semiconductor layer comprising silicon (Si) and may be formed by an epitaxial layer. The source / drain region 130 may include n-type or p-type impurities. The source / drain region 130 may be a semiconductor layer comprising silicon germanide (SiGe). In an example embodiment, the source / drain region 130 may include multiple regions containing elements and / or dopants of different concentrations.

[0048] The gate structure 160 can be configured to intersect with fin patterns 105A, 105B, and 105C, and can extend in the upper portion of the fin patterns 105A, 105B, and 105C in the second direction Y. The channel region of the transistor can be formed in the fin patterns 105A, 105B, and 105C intersecting with the gate structure 160. The gate structure 160 may include a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the fin patterns 105A, 105B, and 105C, a spacer layer 164 on the side surface of the gate electrode 165, and a gate capping layer 166 on the upper surface of the gate electrode 165.

[0049] The gate dielectric layer 162 may be disposed between the fin patterns 105A, 105B, and 105C and the gate electrode 165, and may cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be disposed around all surfaces of the gate electrode 165 except for the uppermost surface. The gate dielectric layer 162 may extend to the region between the gate electrode 165 and the spacer layer 164, but its exemplary embodiments are not limited thereto. The gate dielectric layer 162 may include oxides, nitrides, or high-k materials. High-k materials may refer to dielectric materials with a dielectric constant higher than that of silicon oxide (SiO2). High-k materials may include, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSixO2). y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y ) and praseodymium oxide (Pr2O3).

[0050] Gate electrode 165 may be disposed on the upper portion of fin patterns 105A, 105B, and 105C. Gate electrode 165 may be spaced apart from fin patterns 105A, 105B, and 105C by gate dielectric layer 162. Gate electrode 165 may comprise a conductive material and may comprise, for example, a metal nitride (e.g., titanium nitride film (TiN), tantalum nitride film (TaN), or tungsten nitride film (WN)) and / or a metallic material (e.g., aluminum (Al), tungsten (W), or molybdenum (Mo)) or a semiconductor material (e.g., doped polycrystalline silicon). Gate electrode 165 may be formed of two or more layers. Gate electrodes 165 may be isolated from each other by gate isolation patterns 168 between adjacent transistors.

[0051] Spacer layer 164 may be disposed on both side surfaces of gate electrode 165. Spacer layer 164 may insulate source / drain region 130 and gate electrode 165. In an example embodiment, spacer layer 164 may have a multilayer structure. Spacer layer 164 may be formed of oxide, nitride, and oxynitride, and may be formed of a low-k film.

[0052] The gate capping layer 166 can be disposed on the upper part of the gate electrode 165, and its lower surface and side surface can be surrounded by the gate electrode 165 and the spacer layer 164.

[0053] Interlayer insulating layer 170 may be configured to cover device isolation layer 110, source / drain region 130, and gate capping layer 166. Interlayer insulating layer 170 may include at least one of, for example, oxides, nitrides, and oxynitrides, and may include a low-k material.

[0054] Contact structure 180 can penetrate interlayer insulation layer 170 and can connect to source / drain region 130, and can apply electrical signals to source / drain region 130. Contact structure 180 may have a sloped side surface, wherein, depending on the aspect ratio, the width of the lower portion of the sloped side surface is narrower than the width of the upper portion, but exemplary embodiments thereof are not limited thereto. Contact structure 180 may be configured to contact the upper surface of source / drain region 130 without being recessed into source / drain region 130.

[0055] Contact structure 180 may include a conductive layer, a metal-semiconductor compound layer between the conductive layer and the source / drain region 130, and a contact barrier metal layer surrounding the conductive layer. The conductive layer may include W, Co, Ti, alloys thereof, or combinations thereof. The metal-semiconductor compound layer may be a silicide layer and may include, for example, CoSi, NiSi, or TiSi. The contact barrier metal layer may include TiN, TaN, WN, or combinations thereof.

[0056] Figures 3A to 3C This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 3A It shows the relationship with Figure 2A An enlarged view of the region corresponding to the first region R1 shown in the diagram. Figure 3B It shows the relationship with Figure 2A An enlarged view of the region corresponding to the second region R2 shown in the diagram. Figure 3C It shows the relationship with Figure 2A The enlarged view of the region corresponding to the third region R3 shown in the figure.

[0057] Figure 3A An example shape of the pattern of the first pattern group PG1 in the first region R1 of the substrate 101 of the semiconductor device 100A is shown.

[0058] The first fin pattern 105A may have a shape that protrudes from the substrate 101 and whose width decreases upward in the second direction Y. The first fin pattern 105A may be spaced apart from each other by protective fin patterns removed from the area between the first fin patterns 105A at a spacing of approximately twice the minimum spacing P1.

[0059] The first recess RS1 may include protrusions PT1 and PT2 and a recess RC recessed between protrusions PT1 and PT2. Protrusions PT1 and PT2 may have a bimodal shape protruding upward toward the upper surface of the device isolation layer 110. The central axis of the recess RC may be spaced apart from the central axis of the adjacent first fin pattern 105A by a first distance d1 in the second direction Y. The relationship between the first distance d1 and the minimum spacing P1 may be the same as described in the foregoing example embodiments.

[0060] The lower end of the recess RC can be positioned at a height approximately 60 nm or more lower than the upper end of the first fin pattern 105A. This height can be determined based on the flat surface of the substrate 101. The upper ends of the protrusions PT1 and PT2 can be positioned at a height higher than the lower end of the recess RC. Protrusions PT1 and PT2 may include curved portions. Compared to an example using a deep trench isolation process to remove dummy fin patterns, the first protrusion PT1 and the second protrusion PT2 can have curved shapes with relatively smooth ends. Protrusions PT1 and PT2 can be removed by removing the protective fin pattern 105GA (see [reference needed]) formed during the fabrication of the semiconductor device. Figure 9A The first recess RS1 may be formed by means of a first protrusion PT1 and a second protrusion PT2. In an example embodiment, the first recess RS1 may include one of a first protrusion PT1 and a second protrusion PT2.

[0061] The lower end of the recess RC can be located at a height lower than the upper end of the first fin pattern 105A by a first depth h1. The lower end of the recess RC can be located at a height lower than the upper surface of the device isolation layer 110 by a second depth h2. In an example embodiment, the first depth h1 can be, for example, about 60 nm or more, about 60 nm or more and about 170 nm or less. The first depth h1 can be, for example, about 60 nm or more and about 150 nm or less. The second depth h2 can be, for example, about 10 nm or more, about 10 nm or more and about 120 nm or less. The second depth h2 can be, for example, about 10 nm or more and about 110 nm or less. When the first depth h1 and the second depth h2 are greater than or less than the above ranges, ghost fins may remain, which may degrade the electrical performance of the semiconductor device.

[0062] Figure 3B An example shape of the pattern of the second pattern group PG2 in the second region R2 of the substrate 101 of the semiconductor device 100A is shown.

[0063] A pair of second fin patterns 105B may have a shape that protrudes from the substrate 101 and whose width decreases upward in the second direction Y. A pair of adjacent second fin patterns 105B may be spaced apart from each other with a minimum spacing P1.

[0064] Each of the second recesses RS2 may include a first protrusion PT1, a second protrusion PT2, and a recess RC recessed between the first protrusion PT1 and the second protrusion PT2. The protrusions PT1 and PT2 may have a bimodal shape protruding upward toward the upper surface of the device isolation layer 110. The central axis of the recess RC may be spaced apart from the central axis of the adjacent second fin pattern 105B by a second distance d2 in the second direction Y. The relationship between the second distance d2 and the minimum spacing P1 may be the same as described above. The second recesses RS2 may have a shape similar to that of the first recesses RS1, and the description of the first recesses RS1 may also be applied to the second recesses RS2.

[0065] The first protrusion PT1 may be spaced apart by a first interval S1 in the second direction Y from the second fin pattern 105B adjacent to the first protrusion PT1. The second protrusion PT2 may be adjacent to the first flat portion FP1 and may be spaced apart by a second interval S2 in the second direction Y from the second fin pattern 105B adjacent to the first protrusion PT1. The first interval S1 may refer to the distance between the central axis of the second fin pattern 105B and the upper end of the first protrusion PT1, and the second interval S2 may refer to the distance between the central axis of the second fin pattern 105B and the upper end of the second protrusion PT2. The first interval S1 may be about 0.5 to about 0.8 times the minimum spacing P1, and the second interval S2 may be about 1.2 to about 1.5 times the minimum spacing P1.

[0066] The first flat portion FP1 can be configured to connect to a pair of second recesses RS2 between the pair of second recesses RS2. The first flat portion FP1 can refer to a substantially flat portion of the upper surface of the substrate 101. The relationship between the first width W1 of the first flat portion FP1 and the minimum spacing P1 can be the same as described above.

[0067] The second recess RS2, located on one side of the first flat portion FP1, can be spaced apart from the adjacent second fin pattern 105B by a second distance d2. Another second recess RS2, located on the other side of the first flat portion FP1, can be spaced apart from the other second fin pattern 105B by a third distance. The relationship between the second distance d2 and the minimum spacing P1 can also be applied to the description of the third distance in the second region R2.

[0068] Figure 3CAn example shape of the pattern of the third pattern group PG3 in the third region R3 of the substrate 101 of the semiconductor device 100A is shown.

[0069] A pair of third fin patterns 105C may have a shape that protrudes from the substrate 101 and whose width decreases upward in the second direction Y. A pair of adjacent third fin patterns 105C may be spaced apart from each other with a minimum spacing P1.

[0070] As mentioned above (reference) Figure 3A As described in the example embodiment, each of the third recesses RS3 may include a first protrusion PT1, a second protrusion PT2, and a recess RC recessed between the first protrusion PT1 and the second protrusion PT2. The protrusions PT1 and PT2 may have a bimodal shape protruding upward toward the upper surface of the device isolation layer 110. The central axis of the recess RC may be spaced a third distance d3 from the central axis of the adjacent third fin pattern 105C in the second direction Y. The relationship between the third distance d3 and the minimum spacing P1 may be the same as that described in the aforementioned example embodiment. The third recess RS3 may have a shape similar to that of the second recess RS2, and the description of the second recess RS2 may also be applied to the third recess RS3.

[0071] A pair of second flat portions FP2 may extend from each of a pair of third recesses RS3 and may be substantially flat. The description of the second width W2 of each of the pair of second flat portions FP2 may be the same as that in the foregoing example embodiment.

[0072] Figures 4A to 4C This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 4A It shows the relationship with Figure 2A An enlarged view of the region corresponding to the first region R1 shown in the diagram. Figure 4B It shows the relationship with Figure 2A An enlarged view of the region corresponding to the second region R2 shown in the diagram. Figure 4C It shows the relationship with Figure 2A The enlarged view of the region corresponding to the third region R3 shown in the figure.

[0073] Figure 4A An example shape of the pattern of the first pattern group PG1 in the first region R1 of the substrate 101 of the semiconductor device 100B is shown.

[0074] The lower end of the first recess RS1 can be positioned at a height lower than the lower end of the first fin pattern 105A. The first recess RS1 can be partially recessed from the surface of the substrate 101 and can have a downwardly recessed shape. The first recess RS1 can be configured as a groove that is downwardly recessed without sharp protrusions. The first recess RS1 can have a "U" shape or a shape similar to a "U". The central axis of the first recess RS1 can be spaced apart from the central axis of the first fin pattern 105A by a first distance d1 in the second direction Y. The relationship between the first distance d1 and the minimum spacing P1 can be compared with the aforementioned reference. Figure 3A The same as described in the example embodiments.

[0075] The lower end of the first recess RS1 can be located at a height that is a third depth h3 lower than the upper end of the first fin pattern 105A. The lower end of the first recess RS1 can be located at a height that is a fourth depth h4 lower than the upper surface of the device isolation layer 110. In an example embodiment, the third depth h3 can be greater than the first depth h1, and the fourth depth h4 can be greater than the second depth h2. In an example embodiment, for example, the third depth h3 can be about 60 nm or more, about 60 nm or more and about 170 nm or less. The third depth h3 can be, for example, about 60 nm or more and about 150 nm or less. The fourth depth h4 can be, for example, about 10 nm or more, about 10 nm or more and about 120 nm or less. The fourth depth h4 can be, for example, about 10 nm or more and about 110 nm or less. When the third depth h3 and the fourth depth h4 are greater than or less than the above ranges, dummy fins or false fins may remain, which may degrade the electrical performance of the semiconductor device.

[0076] Figure 4B An example shape of the pattern of the second pattern group PG2 in the second region R2 of the substrate 101 of the semiconductor device 100B is shown.

[0077] The lower end of the second recess RS2 can be positioned at a height lower than the surface of the first flat portion FP1. The second recess RS2 can be a groove that can be recessed downwards without sharp protrusions. The structure, except for the shape of the second recess RS2, can be similar to the aforementioned reference. Figure 3B The structures in the described example embodiments are the same.

[0078] Figure 4C An example shape of the pattern of the third pattern group PG3 in the third region R3 of the substrate 101 of the semiconductor device 100B is shown.

[0079] The lower end of the third recess RS3 can be positioned at a height lower than the surface height of the second flat portion FP2. The third recess RS3 can be configured as a groove that is recessed downwards without sharp protrusions. The structure, except for the shape of the third recess RS3, can be the same as described above. Figure 3C The structures in the described example embodiments are the same.

[0080] Figure 5 This is a cross-sectional view of a semiconductor device according to an example embodiment, showing the corresponding... Figure 2A The area.

[0081] refer to Figure 5 The semiconductor device 100C may include: fin patterns 105A, 105B, and 105C; a channel structure 140 including multiple channel layers 141, 142, and 143; and source / drain regions 130 (see...). Figure 2B The semiconductor device 100C may also include a device isolation layer 110, an interlayer insulating layer 170, and a contact structure 180. In the following description, only those related to… Figures 2A to 2C The semiconductor device 100 shown has a different structure.

[0082] In semiconductor device 100C, fin patterns 105A, 105B, and 105C may have fin structures, and gate electrode 165 may be disposed between fin patterns 105A, 105B, and 105C and channel structure 140, between multiple channel layers 141, 142, and 143 of channel structure 140, and in the upper part of channel structure 140. Therefore, semiconductor device 100C may include a multi-bridge channel FET (MBCFET) formed by channel structure 140, source / drain regions 130, and gate electrode 165. TM ).

[0083] The channel structure 140 may include first to third channel layers 141, 142, and 143 on fin patterns 105A, 105B, and 105C, with two or more channel layers spaced apart from each other in a third direction Z perpendicular to the upper surfaces of fin patterns 105A, 105B, and 105C. The first to third channel layers 141, 142, and 143 may be connected to source / drain regions 130 and may be spaced apart from the upper surfaces of fin patterns 105A, 105B, and 105C. The first to third channel layers 141, 142, and 143 may be surrounded by a gate dielectric layer 162 and a gate electrode 165. The first to third channel layers 141, 142, and 143 may be formed of a semiconductor material and may include at least one of silicon (Si), silicon germanide (SiGe), and germanium (Ge). For example, the first to third channel layers 141, 142, and 143 may be formed of the same material as the substrate 101. In the example embodiment, the number and shape of the channel layers 141, 142, and 143 included in a single channel structure 140 may vary.

[0084] Figures 6A to 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Figures 6A to 16 A method for removing unwanted dummy patterns in a self-aligned quadruple patterning (SAQP) process is shown. For example, a method for removing at least three dummy patterns arranged sequentially in the second direction Y from a pattern set in a second region R2 and a third region R3 is shown.

[0085] refer to Figure 6A A mask layer 120, a first sacrificial layer 122, and a second sacrificial layer can be formed on a substrate 101, and the second sacrificial layer can be etched to form a sacrificial pattern 124'.

[0086] Substrate 101 may be a semiconductor substrate, such as a silicon wafer. Substrate 101 may be a silicon-on-insulator (SOI) substrate.

[0087] The mask layer 120 may be formed of a silicon-containing material (e.g., silicon oxide (SiOx), silicon oxynitride (SiON), silicon nitride (SixNy)), a carbon-containing material (e.g., an amorphous carbon layer (ACL) or a spin-on hard mask (SOH)), or a metal. For example, the mask layer 120 may include multiple layers.

[0088] The first sacrificial layer 122 and the second sacrificial layer may include one of polycrystalline silicon, amorphous carbon layer (ACL), or spin-coated hard mask (SOH).

[0089] The mask layer 120, the first sacrificial layer 122, and the second sacrificial layer can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or spin coating processes, and a baking or curing process can be additionally performed depending on the material.

[0090] Photoresist (PR) can be formed on the second sacrificial layer, and a linear photoresist pattern can be formed using photolithography. The second sacrificial pattern 124' can be formed by anisotropically etching the second sacrificial layer using the photoresist pattern as an etching mask.

[0091] refer to Figure 6B A first spacer 128 can be formed on the sidewall of the second sacrificial pattern 124'.

[0092] A first spacer material layer can be formed to conformally cover the second sacrificial pattern 124', and an etch-back process can be performed to form the first spacer 128 on the sidewalls of the second sacrificial pattern 124'. Through the etch-back process, the sidewalls of the first spacer 128 can have a shape that curves toward the second sacrificial pattern 124'.

[0093] Consider the final fin patterns 105A, 105B, and 105C (see...) Figure 1 or Figure 2A The thickness of the first spacer material layer is determined by the spacing or pitch between the fin patterns. The spacing or pitch between the fin patterns to be formed can be narrower than the resolution limit of commercially available lithography equipment.

[0094] The first spacer material layer can be formed of a material that has etch selectivity relative to the material of the second sacrificial pattern 124'. For example, when the second sacrificial pattern 124' is formed of one of polycrystalline silicon, an amorphous carbon layer (ACL), or a spin-coated hard mask (SOH), the first spacer material layer can be formed of silicon oxide or silicon nitride. The first spacer material layer can be formed by atomic layer deposition (ALD).

[0095] refer to Figure 6C The first spacer can be formed independently on the first sacrificial layer 122 by selectively removing the second sacrificial pattern 124' relative to the first spacer 128.

[0096] refer to Figure 6D The first sacrificial pattern 122' can be formed by etching the first sacrificial layer 122 using the first spacer 128 as an etching mask. When forming the first sacrificial pattern 122', the mask layer 120 can be exposed.

[0097] refer to Figure 6E A second spacer 126 can be formed on the sidewall of the first sacrificial pattern 122'. The first spacer 128 can be removed.

[0098] A second spacer material layer can be formed to conformally cover the first sacrificial pattern 122', and an etch-back process can be performed to form the second spacer 126 on the sidewall of the first sacrificial pattern 122'.

[0099] The thickness of the second spacer material layer, i.e., the width of the second spacer 126, can be determined by considering the width Fw of the fin patterns 105A, 105B, and 105C to be ultimately formed. The width of the fin patterns 105A, 105B, and 105C to be ultimately formed can be narrower than the resolution limit of commercially available lithography equipment.

[0100] The second spacer material layer can be formed of a material that has etch selectivity relative to the material of the first sacrificial pattern 122'. For example, when the first sacrificial pattern 122' is formed of one of polycrystalline silicon, an amorphous carbon layer (ACL), or a spin-coated hard mask (SOH), the second spacer material layer can be formed of silicon oxide or silicon nitride. The second spacer material layer can be formed by atomic layer deposition (ALD).

[0101] refer to Figure 6F By selectively removing the first sacrificial pattern 122' relative to the second spacer 126, a second spacer 126 can be formed that is independently retained on the mask layer 120.

[0102] refer to Figure 6G A mask pattern can be formed by etching the mask layer 120 using the second spacer 126 as an etching mask.

[0103] The mask pattern can be formed in the position corresponding to the second spacer 126. The mask pattern can correspond to the fin pattern to be used and the dummy pattern not needed in a single pattern group.

[0104] In the first region R1, a pattern 105A for forming the first fin can be formed (in... Figure 9A The first mask pattern 120AA (in the middle) can be formed for forming the first protective fin pattern 105GA (in the middle) Figure 9A The first protective mask pattern in the middle is 120GA.

[0105] In the second region R2, a pattern 105B for forming the second fin can be formed (in... Figure 9A The second mask pattern 120AB (in the middle) can be formed for forming the second protective fin pattern 105GB (in Figure 9A The second protective mask pattern 120GB (in the middle) can be formed, and the first dummy mask pattern 120DA can be formed before the fin pattern is formed.

[0106] In the third region R3, a pattern 105C for forming the third fin can be formed. Figure 9AThe third mask pattern 120AC (in the middle) can be used to form the third protective fin pattern 105GC (in the middle). Figure 9A The third protective mask pattern 120GC (in the middle) can be formed, and a second dummy mask pattern 120DB can be formed before the fin pattern is formed.

[0107] refer to Figure 7A A first material layer 112 can be formed, and a first photoresist pattern P10 with a first opening OP1 can be formed on the first material layer 112.

[0108] refer to Figure 7B A portion of the first material layer 112 can be removed through the first opening OP1 of the first photoresist pattern P10, and the mask pattern 120' and the second spacer 126 can be partially removed in the second region R2 and the third region R3.

[0109] The first material layer 112 can be formed to cover the surface of the substrate 101 and fill the area between the mask patterns 120AA, 120GA, 120AB, 120GB, 120DA, 120AC, 120GB, and 120DB. The first material layer 112 can be formed to fill the area between the second spacers 126 and cover the upper surface of the second spacers 126. A first photoresist pattern P10 can be formed on the first material layer 112.

[0110] The mask patterns 120DA and 120DB removed from the second region R2 and the third region R3, as well as the second spacer 126, can be associated with the formation of... Figure 2A The patterns corresponding to the positions of the flat portions FP1 and FP2 are shown. The position of the first opening OP1 can correspond to the area in each of the pattern groups where no fin pattern is formed.

[0111] In this process, the first width W1 and the second width W2 of the flat portions FP1 and FP2 in the second region R2 and the third region R3 can be determined based on the number of mask patterns removed through the first opening OP1.

[0112] refer to Figure 8 The substrate 101 is anisotropically etched using mask patterns 120AA, 120GA, 120AB, 120GB, 120AC and 120GB as etching masks. The first fin pattern 105A and the first protective fin pattern 105GA can be formed on the first region R1 of the substrate 101, the second fin pattern 105B and the second protective fin pattern 105GB can be formed on the second region R2, and the third fin pattern 105C and the third protective fin pattern 105GC can be formed on the third region R3.

[0113] In the first to third fin patterns 105A, 105B and 105C, the gate electrode 165 (see [reference] in semiconductor device 100) can be formed. Figure 2B The channel region is surrounded by the first to third protective fin patterns 105GA, 105GB, and 105GC. These patterns can be dummy patterns, arranged adjacent to the first to third protective fin patterns 105A, 105B, and 105C, and include etching residues LP deposited on their sidewalls by etching load caused by the gap difference between the patterns. Since the first to third protective fin patterns 105GA, 105GB, and 105GC, whose width changes due to etching load, are removed in subsequent processes, the fin patterns 105A, 105B, and 105C that are ultimately retained can have a uniform size (or width).

[0114] In this process, a first initial flattening portion FP1a and a second initial flattening portion FP2a can be formed on the surface of the substrate 101 corresponding to the removed mask patterns 120DA and 120DB.

[0115] refer to Figure 9A A second material layer 114 can be formed, and a second photoresist pattern P20 with a second opening OP2 can be formed on the second material layer 114.

[0116] refer to Figure 9B A portion of the second material layer 114 can be removed through the second opening OP2 of the second photoresist pattern P20, and a portion of the first to third protective fin patterns 105GA, 105GB and 105GC can be removed.

[0117] The second material layer 114 can be partially removed from the top at the position corresponding to the second opening OP2. With the partial removal of the second material layer 114, portions of the first to third protective fin patterns 105GA, 105GB, and 105GC can be exposed. The second spacer 126 and mask patterns 120GA, 120GB, and 120GC corresponding to the second opening OP2 can be removed, and the exposed first to third protective fin patterns 105GA, 105GB, and 105GC can be removed from the top. Therefore, portions of the first to third recesses RS1, RS2, and RS3 can be formed in the first to third regions R1, R2, and R3.

[0118] refer to Figure 10A A third material layer 116 can be formed, and a third photoresist pattern P30 with a third opening OP3 can be formed on the third material layer 116.

[0119] refer to Figure 10BA portion of the third material layer 116 can be removed by the third photoresist pattern P30, and other first protective fin patterns can be removed to the third protective fin patterns 105GA, 105GB and 105GC.

[0120] The third material layer 116 can be partially removed from the top at the position corresponding to the third opening OP3. A portion of the third material layer 116 can be removed, thereby exposing a portion of the remaining first protective fin patterns to the third protective fin patterns 105GA, 105GB, and 105GC. The second spacer 126 and mask patterns 120GA, 120GB, and 120GC corresponding to the third opening OP3 can be removed, and the remaining exposed first protective fin patterns to the third protective fin patterns 105GA, 105GB, and 105GC can be removed from the top. Therefore, as... Figure 2A As shown, the first recessed portion to the third recessed portion RS1, RS3 and RS3 can be formed in the first region to the third region R1, R2 and R3, and the first flat portion FP1 and the second flat portion FP2 can be formed therein.

[0121] refer to Figure 11A and Figure 11B , instead of reference Figures 9A to 10B The described process can form a first material layer 112a, and a first photoresist pattern P10a with openings OP1a, OP2a and OP3a can be formed. The first material layer 112a can be partially removed, and the first to third protective fin patterns 105GA, 105GB and 105GC can be removed in the same manufacturing process.

[0122] Figure 12A and Figure 12B A more detailed explanation is provided by reference. Figures 9A to 10B The described process is a process for removing the protective fin pattern from the first region to the third region R1, R2 and R3. Figure 12A It shows Figure 11B An enlarged view of section “A” is shown, illustrating the process of removing the protective fin pattern between adjacent fin patterns 105 and protective fin pattern 105G.

[0123] refer to Figure 12A The protective fin pattern 105G can be removed from the upper part, thereby forming a double-peaked recess RS in the lower part. The recess RS may include upwardly protruding protrusions PT1 and PT2 and a recess RC between the protrusions.

[0124] When dummy fins are removed using a deep trench isolation process, the dummy fins can remain in the removed area with a sharp, protruding shape because the insulating layer, including a material such as silicon oxide, and the dummy fins, including a material such as silicon, are removed together. To limit and / or prevent the retention of fins with sharp protrusions by the deep trench isolation process, trenches with a desired and / or alternative predetermined depth or deeper can be formed. According to example embodiments, see reference... Figures 9A to 10B As such, since the recessed portion RS is formed by selectively removing only the protective fin pattern, the recessed portion RS can be retained as a bimodal pattern with a curved surface rather than an upward-pointing sharp pattern.

[0125] refer to Figure 12B The protective fin pattern 105G can be removed from the top, thereby forming a recess RS that is recessed downwards from the surface of the substrate 101. The recess RS can be a trench that can be recessed downwards without sharp protrusions. The depth of the recess RS can be relatively less than the depth of a recess formed by isolation through deep trenches. For example, the recess RS can be formed to a depth of about 10 nm or more and about 60 nm or less from the top end of the fin pattern 105. Since adjacent fin patterns 105 can be isolated without forming the recess RS deeply, the tilt of the fin pattern 105 can be reduced.

[0126] refer to Figure 13 The device isolation layer 110 can be formed such that the upper part of the fin patterns 105A, 105B and 105C can protrude.

[0127] The space between the first fin pattern and the third fin patterns 105A, 105B and 105C can be filled with the device isolation layer 110. The mask pattern 120' remaining on the first fin pattern to the third fin patterns 105A, 105B and 105C can be removed, and a portion of the device isolation layer 110 can be etched to a desired and / or alternative predetermined depth, such that the upper portion of the first fin pattern to the third fin patterns 105A, 105B and 105C can protrude.

[0128] refer to Figure 14 It can form a sacrificial grid structure 150 that intersects with fin patterns 105A, 105B and 105C.

[0129] The sacrificial gate structure 150 can be formed in, for example, by subsequent processes. Figure 2B and Figure 2CThe region shown contains a gate dielectric layer 162, a gate electrode 165, and a gate capping layer 166. Each sacrificial gate structure 150 may include a sacrificial gate insulating layer 152, a sacrificial gate electrode 155, and a sacrificial gate capping layer 156. The sacrificial gate insulating layer 152 and the sacrificial gate capping layer 156 may be insulating layers, while the sacrificial gate electrode 155 may be a conductive layer, but the exemplary embodiments are not limited thereto. Spacer layers 164 may be disposed on both sides of the sacrificial gate structure 150.

[0130] refer to Figure 15 Fin patterns 105A, 105B and 105C can be partially recessed into both sides of the sacrificial gate structure 150 and can form source / drain regions 130.

[0131] Source / drain regions 130 can be formed on fin patterns 105A, 105B, and 105C, which can be recessed after partially removing the fin patterns 105A, 105B, and 105C from both sides of the sacrificial gate structure 150. Source / drain regions 130 can be formed using, for example, a selective epitaxial growth (SEG) process. Source / drain regions 130 can include impurity-doped semiconductor materials, such as Si, SiGe, or SiC. Impurities can be in-situ doped during the formation of source / drain regions 130 or can be implanted separately after growth.

[0132] After the source / drain region 130 is formed, an interlayer insulating layer 170 can be formed. The interlayer insulating layer 170 can be formed by depositing an insulating material to cover the sacrificial gate structure 150 and the source / drain region 130, and exposing the upper surface of the sacrificial gate structure 150 by a planarization process.

[0133] refer to Figure 16 It can remove the sacrificial gate structure 150 and form the gate structure 160.

[0134] The sacrificial gate structure 150 can be selectively removed relative to the fin patterns 105A, 105B, and 105C. The sacrificial gate structure 150 can be removed using at least one of dry etching and wet etching processes. An opening can be formed in the region where the sacrificial gate structure 150 has been removed.

[0135] The gate dielectric layer 162, the gate electrode 165, and the gate capping layer 166 may be formed sequentially to fill the opening. The gate dielectric layer 162 may be formed substantially conformally along the sidewalls and lower surface of the opening. The gate electrode 165 may be formed of multiple layers of conductive material.

[0136] Subsequently, refer to Figures 2A to 2C It can form a barrier pattern 168 and a contact structure 180.

[0137] In the example embodiment, it has been described that the gate isolation pattern 168 can be formed after the gate electrode 165 is formed. However, in the process of forming the sacrificial gate structure 150, the gate isolation pattern 168 can be formed first, and the sacrificial gate structure 150 can be removed to form the gate structure 160. In this case, the gate dielectric layer 162 can be configured to extend along the sidewalls of the gate isolation pattern 168.

[0138] Figures 17A to 19 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Figures 17A to 19 A method for removing unwanted dummy patterns in a self-aligned double patterning (SADP) process is shown. For example, a method is provided for removing at least two dummy patterns arranged sequentially in the second direction Y from a pattern set in a second region R2 and a third region R3.

[0139] refer to Figure 17A A first sacrificial layer 222 and a second sacrificial layer can be formed on the substrate 101, and the second sacrificial layer can be etched to form a second sacrificial pattern 224'.

[0140] The first sacrificial layer 222 and the second sacrificial layer may be formed of silicon-containing materials (e.g., silicon oxide (SiOx), silicon oxynitride (SiON), silicon nitride (SixNy), or polycrystalline silicon), carbon-containing materials (e.g., amorphous carbon layer (ACL) or spin-coated hard mask (SOH)), or metal.

[0141] Photoresist can be formed on the second sacrificial layer, and a linear photoresist pattern can be formed using photolithography. The second sacrificial pattern 224' can be formed by anisotropically etching the second sacrificial layer using the photoresist pattern as an etching mask.

[0142] refer to Figure 17B A first spacer 228 can be formed on the sidewall of the second sacrificial pattern 224'. The formation of the first spacer 228 can be related to a reference. Figure 6B The formation of the first spacer 128 is the same. Through the etch-back process, the sidewalls of the first spacer 228 can have a shape that bends toward the second sacrificial pattern 224'.

[0143] refer to Figure 17C The first spacer can be formed independently on the first sacrificial layer 222 by selectively removing the second sacrificial pattern 224' relative to the first spacer 228.

[0144] refer to Figure 17D The first sacrificial pattern 222' can be formed by etching the first sacrificial layer 222 using the first spacer 228 as an etching mask.

[0145] refer to Figure 18AA first material layer 212 can be formed, and a first photoresist pattern P12 with a first opening OPa can be formed on the first material layer 212.

[0146] refer to Figure 18B A portion of the first material layer 212 can be removed through the first opening OPa of the first photoresist pattern P12, and the first sacrificial pattern 222' and the second sacrificial pattern 224' can be partially removed from the second region R2 and the third region R3.

[0147] In this process, the width of the flat portion in the second region R2 and the third region R3 can be determined based on the number of first sacrificial patterns 222' removed through the first opening OPa.

[0148] refer to Figure 19 By using the first sacrificial pattern 222' as an etching mask to anisotropically etch the substrate 101, the first fin pattern 205A and the first protective fin pattern 205GA can be formed on the first region R1 of the substrate 101, the second fin pattern 205B and the second protective fin pattern 205GB can be formed on the second region R2, and the third fin pattern 205C and the third protective fin pattern 205GC can be formed on the third region R3.

[0149] The first to third protective fin patterns 205GA, 205GB, and 205GC can be configured to be adjacent to the first to third protective fin patterns 205A, 205B, and 205C, respectively, and can be dummy patterns, with etching residues deposited on the sidewalls of the dummy patterns by the etching load caused by the gap difference between the patterns. Since the first to third protective fin patterns 205GA, 205GB, and 205GC, whose widths are altered by the etching load, are removed in subsequent processes, the fin patterns 205A, 205B, and 205C that are ultimately retained can have uniform dimensions (or widths).

[0150] refer to Figure 20A A second material layer 224 can be formed, and a second photoresist pattern P22 with a second opening OPb can be formed on the second material layer 224.

[0151] refer to Figure 20B A portion of the second material layer 224 can be removed through the second opening OPb of the second photoresist pattern P22, and the first to third protective fin patterns 205GA, 205GB and 205GC can be removed.

[0152] The first to third protective fin patterns 205GA, 205GB, and 205GC can be exposed from the second material layer 224 at positions corresponding to the second opening OPb, and these patterns can be removed to form first to third recesses RS1, RS2, and RS3 in the first to third regions R1, R2, and R3. The shapes of the first to third recesses RS1, RS2, and RS3 can be as follows: Figure 12A or Figure 12B The shape of the recessed portion RS shown.

[0153] For reference Figures 13 to 16 The device isolation layer 110, source / drain regions 130, and gate structure 160 can be formed. Subsequently, gate isolation pattern 168 and contact structure 180 can be formed.

[0154] The example embodiments can also be applied to a vertical FET in which the active region extends vertically to the upper surface of the substrate 101 and the gate structure surrounds the active region, or to a negative capacitance FET (NCFET) using a gate insulating film with ferroelectric properties.

[0155] According to the foregoing example embodiments, a semiconductor device comprising fin patterns of uniform size in a single pattern group and a method thereof can be provided. Therefore, a semiconductor device with improved reliability can be manufactured.

[0156] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; Device isolation layer, on the substrate; Multiple pattern groups, each pattern group including a fin pattern extending from the substrate, the fin pattern protruding upward beyond the upper surface of the device isolation layer, and the fin pattern extending in a first direction; as well as A gate structure is provided on the substrate, the gate structure intersecting the fin pattern, and the gate structure extending in a second direction intersecting the first direction. The plurality of pattern groups includes a first pattern group containing a first fin pattern. Wherein, at least one pair of the first fin patterns are arranged at a first spacing in the second direction, and the first spacing is the minimum spacing of the first fin patterns in the second direction. The first pattern group includes a first recessed portion and a first flat portion on the substrate. The central axis of the first recessed portion is spaced apart from the central axis of the corresponding first fin pattern in the first fin pattern by a first distance in the second direction. The first flat portion extends from the first recessed portion and has a first width in the second direction. Wherein, the first distance is 0.8 to 1.2 times the first spacing, and Wherein, the first width is greater than the first spacing.

2. The semiconductor device of claim 1, wherein, The first recess includes: a bimodal protrusion that protrudes upward toward the upper surface of the device isolation layer; and The recessed portion is located between the two peaks.

3. The semiconductor device according to claim 2, wherein, The bimodal protrusion includes a first protrusion and a second protrusion. The first protrusion is adjacent to the corresponding first fin pattern and has a first upper end. The second protrusion is adjacent to the first flat portion and has a second upper end. The first upper end is spaced apart from the central axis of the corresponding first fin pattern by a first interval in the second direction. The second upper end is spaced apart from the central axis of the corresponding first fin pattern by a second interval in the second direction. The first interval is 0.5 to 0.8 times the first spacing, and The second interval is 1.2 to 1.5 times the first interval.

4. The semiconductor device according to claim 2, wherein, The lower end of the recessed portion is positioned at a height in the substrate that is 60 nm or more lower than the height of the upper end of the corresponding first fin pattern.

5. The semiconductor device according to claim 2, wherein, The first recessed portion is connected to one end of the first flat portion. The first pattern group includes a second recessed portion of the substrate, which is recessed into the substrate and connected to the other end of the first flat portion. Wherein, the central axis of the second recess is spaced a third distance from the central axis of another first fin pattern in the first fin pattern of the first pattern group in the second direction, and The third distance is 0.8 to 1.2 times the first distance.

6. The semiconductor device of claim 5, wherein, The second recess includes: The bimodal protrusions upward toward the upper surface of the device's isolation layer; and The recessed portion is located between the bimodal protrusions of the second recessed portion.

7. The semiconductor device of claim 5, wherein, The first flat portion has a substantially flat surface.

8. The semiconductor device according to claim 1, wherein, The lower end of the first recess is positioned at a height in the substrate that is lower than the height of the surface of the first flat portion.

9. The semiconductor device according to claim 8, wherein, The first recessed portion has a groove shape in the substrate that is recessed downwards without any sharp protrusions.

10. The semiconductor device according to claim 1, in, The first recessed portion is connected to one end of the first flat portion. The first pattern group includes a second recessed portion of the substrate, which is recessed into the substrate and connected to the other end of the first flat portion. Wherein, the central axis of the second recess is spaced apart from the central axis of another first fin pattern in the first fin pattern of the first pattern group by a third distance in the second direction. Wherein, the third distance is 0.8 to 1.2 times the first distance, and Wherein, the lower ends of the first recess and the second recess are located at a height in the substrate that is lower than the height of the surface of the first flat portion.

11. The semiconductor device according to claim 1, further comprising: Multiple channel layers, located on each of the first fin patterns, are spaced apart from each other in the vertical direction. Each of the plurality of channel layers is surrounded by a gate dielectric layer and a gate electrode of the corresponding gate structure in the gate structure.

12. The semiconductor device according to claim 1, in, The plurality of pattern groups includes a second pattern group, the second pattern group including second fin patterns arranged in the second direction at a second spacing greater than the first spacing. The second fin pattern comprises two adjacent second fin patterns. The second pattern group includes a second recess in the substrate, the central axis of which is located between the two adjacent second fin patterns, and is spaced a second distance from the central axis of one of the two adjacent second fin patterns in the second direction. The second recess is recessed into the substrate. Wherein, the second distance is less than the second spacing.

13. A semiconductor device, comprising: Substrate; Device isolation layer, on the substrate; A pattern group comprising a fin pattern extending along a first direction on the substrate; as well as A gate structure, on the substrate, intersects the fin pattern and extends in a second direction perpendicular to the first direction. The fin pattern of the pattern group includes a first fin pattern and a second fin pattern arranged at a minimum spacing in the second direction. The pattern group includes a first recessed portion and a second recessed portion of the substrate, wherein the first recessed portion and the second recessed portion are recessed into the substrate. The first fin pattern and the second fin pattern are located between the first recess and the second recess. The first recessed portion and the second recessed portion are respectively adjacent to the first fin pattern and the second fin pattern. The pattern set further includes a flat portion of the substrate, the flat portion extending from at least one of the first recess and the second recess, and the flat portion having a substantially flat surface. Wherein, the substantially flat surface of the flat portion has a width in the second direction that is greater than the minimum spacing.

14. The semiconductor device according to claim 13, wherein, The width of the substantially flat surface of the flat portion is greater than twice the minimum spacing and less than four times the minimum spacing.

15. The semiconductor device according to claim 14, wherein, The lower end of at least one of the first recess and the second recess is located at a first depth from the upper surface of the device isolation layer.

16. The semiconductor device according to claim 15, wherein, The first depth ranges from 10 nm to 110 nm.

17. The semiconductor device according to claim 13, wherein, At least one of the first recess and the second recess includes: The bimodal protrusions upward toward the upper surface of the device's isolation layer; and The recessed portion is located between the two peaks.

18. A semiconductor device, comprising: Substrate, The substrate includes a first flat portion having a first width. The substrate includes a first recess and a second recess, each recessed into the substrate. One end of the first recessed portion is connected to one end of the first flat portion, and One end of the second recessed portion is connected to the other end of the first flat portion. The substrate includes a first fin pattern, a second fin pattern, and a third fin pattern, each projecting vertically from the substrate. The first fin pattern is connected to the other end of the first recess. The second fin pattern is connected to the other end of the second recess. The third fin pattern is arranged such that it is at the minimum distance from the center of one of the first fin pattern and the second fin pattern; as well as A device isolation layer covers the first flat portion, the first recessed portion, and the second recessed portion on the substrate. Wherein, the first width is greater than the horizontal distance between the central axis of the first recess and the central axis of the first fin pattern. Wherein, the central axis of the first recess is spaced apart from the central axis of the first fin pattern by a first distance, the first distance being 0.8 to 1.2 times the minimum spacing.

19. The semiconductor device according to claim 18, in, The first distance is equal to the minimum spacing, and Wherein, the central axis of the second recess is spaced apart from the central axis of the second fin pattern by a second distance, the second distance being equal to the minimum spacing.

20. The semiconductor device according to claim 19, in, The first flat portion has a substantially flat surface, and The first recess and a portion of the second recess include a bimodal protrusion protruding upward toward the upper surface of the device isolation layer and a recessed portion between the bimodal protrusions. The other part of the first recess and the other part of the second recess are trenches in the substrate, which are recessed further downward than the substantially flat surface of the first flat portion.

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