integrated circuit

Abstract

An integrated circuit is disclosed. The integrated circuit includes at least one decoupling unit, wherein the at least one decoupling unit includes at least one P-type decoupling MOSFET and at least one N-type decoupling MOSFET, and the number of the at least one P-type decoupling MOSFET is different from the number of the at least one N-type decoupling MOSFET.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2020-0127482, filed on September 29, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to an integrated circuit, and more specifically, to an integrated circuit comprising logic units and decoupling units, and a method for designing the integrated circuit. Background Technology

[0003] For an integrated circuit to operate, it may consume current supplied from a power source. When current consumption increases or decreases rapidly, the potential difference between the positive and negative power supply voltages (e.g., a reference potential) may fluctuate. Noise caused by these potential difference fluctuations can lead to system malfunctions. Therefore, decoupling units, including decoupling capacitors, are used in integrated circuits to stably maintain the potential difference between the reference potential and the power supply potential regardless of the integrated circuit's operation. Summary of the Invention

[0004] One or more example embodiments provide an integrated circuit including asymmetric decoupling units and a method for designing the integrated circuit.

[0005] According to one aspect of an example embodiment, an integrated circuit is provided, the integrated circuit including at least one decoupling unit, wherein the at least one decoupling unit includes: a plurality of P-type metal-oxide-semiconductor field-effect transistors (MOSFETs) arranged along a first direction; and a plurality of N-type MOSFETs spaced apart from the plurality of P-type MOSFETs and arranged along the first direction in a second direction perpendicular to the first direction, wherein the plurality of P-type MOSFETs includes at least one P-type decoupling MOSFET, the plurality of N-type MOSFETs includes at least one N-type decoupling MOSFET, and a first number of the at least one P-type decoupling MOSFET is different from a second number of the at least one N-type decoupling MOSFET.

[0006] According to one aspect of an example embodiment, an integrated circuit is provided, the integrated circuit including a first decoupling unit having a first height in a first direction, wherein the first decoupling unit includes: a plurality of first P-type metal-oxide-semiconductor field-effect transistors arranged along a second direction perpendicular to the first direction; and a plurality of first N-type MOSFETs spaced apart from the plurality of first P-type MOSFETs in the first direction and arranged along the second direction, wherein the plurality of first P-type MOSFETs includes at least one first P-type decoupling MOSFET and at least one first P-type dummy MOSFET, the plurality of first N-type MOSFETs includes at least one first N-type decoupling MOSFET and at least one first N-type dummy MOSFET, and a first number of the at least one first P-type decoupling MOSFET is different from a second number of the at least one first N-type decoupling MOSFET.

[0007] According to one aspect of an example embodiment, an integrated circuit is provided, the integrated circuit including at least one decoupling unit, wherein the at least one decoupling unit includes: a first conductivity type decoupling metal-oxide-semiconductor field-effect transistor; and a second conductivity type decoupling MOSFET, and a first capacitance associated with the first conductivity type decoupling MOSFET is greater than a second capacitance associated with the second conductivity type decoupling MOSFET. Attached Figure Description

[0008] The above and / or other aspects will be more clearly understood from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a layout diagram illustrating an integrated circuit according to an example embodiment;

[0010] Figure 2 This is a layout diagram illustrating an example of an asymmetric decoupling unit according to an exemplary embodiment;

[0011] Figures 3A to 3F This is a cross-sectional view of an example of the structure of a unit according to an exemplary embodiment;

[0012] Figures 4A to 4D This is a diagram used to describe an example of an asymmetric decoupling unit according to some other example embodiments;

[0013] Figure 5 This is a diagram used to describe an example of an asymmetric decoupling unit according to some other example embodiments;

[0014] Figure 6 This is a diagram used to describe an example of an asymmetric decoupling unit according to some other example embodiments;

[0015] Figure 7This is a diagram used to describe an example of an asymmetric decoupling unit according to some other example embodiments;

[0016] Figure 8 This is a layout diagram illustrating an integrated circuit according to an example embodiment; and

[0017] Figure 9 This is a flowchart of a method for manufacturing an integrated circuit (IC) according to an example embodiment. Detailed Implementation

[0018] Figure 1 This is a layout diagram of an integrated circuit according to an example embodiment.

[0019] According to an example embodiment, integrated circuit 1 may include a logic block having a normal cell region 2 and an empty region (also referred to as a "dummy gate region") 3. Integrated circuit 1 may also include a peripheral circuit region 4 surrounding the edge of the logic block.

[0020] Integrated circuit 1 may include multiple cells arranged on normal cell region 2. A cell is a unit of layout included in an integrated circuit, which can be designed to perform a predetermined function and may also be referred to as a standard cell. Integrated circuit 1 may include multiple cells with various functions, and the cells may be aligned and arranged according to multiple rows.

[0021] Complementary MOSFETs (CMOSFETs), including P-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and N-type MOSFETs, can be formed on normal cell region 2. The combination of CMOSFETs can constitute a logic circuit for performing a predetermined function.

[0022] Similar to the P-type and N-type MOSFETs in normal cell region 2, P-type and N-type MOSFETs can be formed in empty region 3. Asymmetric decoupling units, including P-type and N-type MOSFETs used as decoupling capacitors, can be disposed in at least a portion of empty region 3. The asymmetric decoupling units will be described in more detail below.

[0023] Figure 2 This is a layout diagram illustrating an example of an asymmetric decoupling unit ASDC1 according to an example embodiment. In detail, Figure 2 The upper part shows the circuit diagram of the asymmetric decoupling unit ASDC1, and Figure 2 The lower part shows the layout of the asymmetric decoupling unit ASDC1. In this disclosure, "nea" (n is a natural number) in the circuit diagram represents n connected (e.g., series connected and / or parallel connected) elements (e.g., transistors). When n = 1, "1ea" represents a single element (e.g., a transistor).

[0024] A plane including the X and Y axes can be referred to as a horizontal plane. A component positioned relative to other components in the positive (+) Z direction can be referred to as being above other components, and a component positioned relative to other components in the negative (-) Z direction can be referred to as being below other components. Furthermore, the area of ​​a component can refer to the dimension occupied by the component in a plane parallel to the horizontal plane, and the height of a component can refer to the length of the component in the Y-axis direction. In the accompanying drawings of this specification, for ease of explanation, only some layers may be shown, and vias may be shown even if they are below the pattern of a wiring layer, to indicate the connection between the pattern of the wiring layer and the pattern below it.

[0025] A pattern (which may be referred to herein as electric field lines) in which a positive supply voltage VDD and a negative supply voltage (or ground potential) VSS are applied at the boundaries of a row can extend along the X-axis, and the first active region RX1 of a P-type MOSFET is formed therein (refer to...). Figure 3E ) and the second active region RX2 in which an N-type MOSFET is formed (refer to Figure 3E It can extend along the X-axis. In some embodiments, the pattern providing the power supply voltage is included in one or more wiring layers.

[0026] like Figure 2 As shown, at least one active pattern can extend along the X-axis direction over the active region. The active pattern can intersect with a gate electrode extending along the Y-axis direction and form a transistor. When the fin active pattern extends along the X-axis direction, the transistor formed by the fin active pattern and the gate electrode can be called a FinFET. See below for reference. Figures 3A to 3E The exemplary embodiments described herein will focus primarily on cells including FinFETs; however, it will be understood that this description can also be applied to cells including transistors having structures different from FinFETs. For example, an active pattern may include multiple nanosheets spaced apart from each other in the Z-axis direction and extending along the X-axis direction, and a cell may include a multi-bridge channel FET (MBCFET) in which the nanosheets form the gate electrode. Furthermore, a cell may include a ForkFET in which nanosheets for P-type transistors and nanosheets for N-type transistors are separated from each other by dielectric walls, thus the N-type and P-type transistors have adjacent structures. Additionally, a cell may include a vertical FET (VFET) having a structure in which source / drain regions (S / D regions) are spaced apart from each other in the Z-axis direction, with a channel region located between the source / drain regions and a gate electrode surrounding the channel region. Furthermore, a cell may include field-effect transistors (FETs) (such as complementary FETs (CFETs), negative FETs (NCFETs), and carbon nanotube (CNT) FETs), and may also include bipolar junction transistors and other three-dimensional (3D) transistors.

[0027] The asymmetric decoupling unit ASDC1 can be a unit used to maintain a constant voltage difference between the positive supply voltage VDD and the negative supply voltage (or ground potential) VSS. According to an example embodiment, the asymmetric decoupling unit ASDC1 may not include input pins and output pins already formed in the first wiring layer M1.

[0028] In this embodiment, the asymmetric decoupling unit ASDC1 may include seven N-type MOSFETs and seven P-type MOSFETs. According to an example embodiment, the N-type MOSFETs may include one or more N-type decoupling MOSFETs NDCT1 and one or more N-type dummy MOSFETs NDMT1. According to an example embodiment, the P-type MOSFETs may include one or more P-type decoupling MOSFETs PDCT1 and one or more P-type dummy MOSFETs PDMT1.

[0029] The asymmetric decoupling unit ASDC1 can have an asymmetric circuit configuration. According to an example embodiment, the number of P-type decoupling MOSFETs PDCT1 can differ from the number of N-type decoupling MOSFETs NDCT1. The asymmetric decoupling unit ASDC1 can use P-type MOSFETs as the main decoupling capacitor. Here, the asymmetric decoupling unit ASDC1 using P-type MOSFETs as the main decoupling capacitor indicates that the number of P-type MOSFETs used as decoupling capacitors is greater than the number of N-type MOSFETs used as decoupling capacitors. According to some embodiments, the number of P-type decoupling MOSFETs PDCT1 can be greater than the number of N-type decoupling MOSFETs NDCT1. For example, as... Figure 2 As shown, the number of P-type decoupling MOSFETs PDCT1 can be 6, while the number of N-type decoupling MOSFETs NDCT1 can be 1.

[0030] According to an example embodiment, the number of P-type dummy MOSFETs PDMT1 may differ from the number of N-type dummy MOSFETs NDMT1. According to an example embodiment, the number of P-type dummy MOSFETs PDMT1 may be less than the number of N-type dummy MOSFETs NDMT1. For example, as... Figure 2 As shown, the number of P-type dummy MOSFETs PDMT1 can be 1, while the number of N-type dummy MOSFETs NDMT1 can be 6.

[0031] The asymmetric decoupling unit ASDC1 may include four active patterns extending along the X direction. According to an example embodiment, the asymmetric decoupling unit ASDC1 may have a width (length in the X direction) corresponding to eight gate pitches CPP. Here, the X, Y, and Z directions can be used interchangeably with the X-axis direction, Y-axis direction, and Z-axis direction, respectively.

[0032] As process technology advances, when the cell height (i.e., length in the Y direction) decreases, the space between the first and second active regions may be reduced, resulting in insufficient space in the decoupling cell to separate and rewire the gates in the first and second active regions. Therefore, only one of the P-type and N-type MOSFETs positioned at the same location in the X direction (or stacked on top of each other in the Y direction) can be used as a decoupling capacitor.

[0033] Here, the capacitance of the P-type decoupling MOSFET can be similar to that of the N-type decoupling MOSFET. On the other hand, the leakage current caused by gate tunneling of the P-type and N-type decoupling MOSFETs can vary depending on the characteristics of the integrated circuit (e.g., gate pitch CPP). For example, when the gate pitch CPP of the integrated circuit is within a first range (e.g., from about 1 nm to about 10 nm), the leakage current caused by a P-type MOSFET can be less than the leakage current caused by an N-type MOSFET. In another example, when the minimum pitch of the integrated circuit is in a second range different from the first range, the leakage current caused by an N-type MOSFET can be less than the leakage current caused by a P-type MOSFET.

[0034] According to an example embodiment, a decoupling unit can be constructed primarily using a MOSFET with excellent leakage current characteristics among P-type and N-type MOSFETs. Specifically, by using a conductive MOSFET with small leakage current characteristics according to the characteristics of the integrated circuit (e.g., minimum pitch) as the main decoupling capacitor, a decoupling unit with the same capacitance level and improved leakage current characteristics can be provided. On the other hand, in an asymmetric decoupling unit, using one of the P-type and N-type decoupling MOSFETs with excellent leakage current characteristics as the main decoupling capacitor is not limited to a larger number, as long as the first capacitance associated with said one is greater than the second capacitance associated with the other of the P-type and N-type decoupling MOSFETs. Different numbers of decoupling MOSFETs (see...) can be used... Figure 2 etc.), different areas of the active region (see Figure 7 (etc.) to achieve the above different capacitors.

[0035] Figures 3A to 3F This is a cross-sectional view of an example of the structure of a unit according to an exemplary embodiment. In detail, Figure 3A It is along Figure 2 The sectional view taken by line 2A-2A'. Figure 3B It is along Figure 2 The sectional view taken by line 2B-2B'. Figure 3C It is along Figure 2 The sectional view taken from line 2C-2C'. Figure 3D It is along Figure 2 A sectional view taken from the line 2D-2D'. Figure 3E It is along Figure 2 The sectional view taken by line 2E-2E', and Figure 3F It is along Figure 2 The sectional view taken from line 2F-2F'.

[0036] Despite Figures 3A to 3F Not shown, but a gate spacer may be formed on the side surface of the gate electrode, and a gate dielectric layer may be formed between the gate electrode and the gate spacer and on the bottom surface of the gate electrode. Furthermore, a barrier layer may be formed on the surface of the contact and / or on the via. Referring below... Figure 2 describe Figures 3A to 3E And will omit the references already taken Figures 3A to 3E The given description.

[0037] Reference Figure 3A The substrate 10 may include bulk silicon or silicon-on-insulator (SOI). As a non-limiting example, the substrate 10 may include SiGe, silicon-germanium-on-insulator (SGOI), InSb, PbTe compounds, InAs, phosphides, GaAs, or GaSb. A first fin F1 may extend along the X-axis on the substrate 10. First source / drain regions to eighth source / drain regions SD11, SD12, SD13, SD14, SD15, SD16, SD17, and SD18 may be formed in the first fin F1. First interlayer insulating layers to fourth interlayer insulating layers 31, 32, 33, and 34 may be formed on the first fin F1.

[0038] The first source / drain region SD11, the second source / drain region SD12, and the first gate electrode G1 can constitute a P-type dummy MOSFET PDMT1. The second source / drain region SD12, the third source / drain region SD13, and the second gate electrode G2 can constitute a P-type decoupling MOSFET PDCT1. The third source / drain region SD13, the fourth source / drain region SD14, and the third gate electrode G3 can constitute a P-type decoupling MOSFET PDCT1. The fourth source / drain region SD14, the fifth source / drain region SD15, and the fourth gate electrode G4 can constitute a P-type decoupling MOSFET PDCT1. The fifth source / drain region SD15, the sixth source / drain region SD16, and the fifth gate electrode G5 can constitute a P-type decoupling MOSFET PDCT1. The sixth source / drain region SD16, the seventh source / drain region SD17, and the sixth gate electrode G6 can constitute a P-type decoupling MOSFET PDCT1. The seventh source / drain region SD17, the eighth source / drain region SD18, and the seventh gate electrode G7 can constitute a P-type decoupling MOSFET PDCT1. Therefore, the asymmetric decoupling unit ASDC1 can include six P-type decoupling MOSFETs PDCT1 and one P-type dummy MOSFET PDMT1.

[0039] The first source / drain contact to the eighth source / drain contact CA11, CA12, CA13, CA14, CA15, CA16, CA17, and CA18 can penetrate the second interlayer insulation layer 32 and can be sequentially connected to the first source / drain region to the eighth source / drain region SD11, SD12, SD13, SD14, SD15, SD16, SD17, and SD18, respectively. At least one of the first source / drain contact to the eighth source / drain contact CA11, CA12, CA13, CA14, CA15, CA16, CA17, and CA18 may include a lower source / drain contact that penetrates the first interlayer insulation layer 31 and an upper source / drain contact that penetrates the second interlayer insulation layer 32.

[0040] The first source / drain contacts to the eighth source / drain contacts CA11, CA12, CA13, CA14, CA15, CA16, CA17, and CA18 can be connected to any one of the patterns in the first wiring layer M1 through vias penetrating the third interlayer insulating layer 33. According to some embodiments, the first source / drain contact CA11, the second source / drain contact CA12, the fourth source / drain contact CA14, the sixth source / drain contact CA16, and the eighth source / drain contact CA18 can be connected to the first pattern P11 to which a positive power supply voltage VDD is applied. Therefore, the positive power supply voltage VDD can be applied to the first source / drain region SD11, the second source / drain region SD12, the fourth source / drain region SD14, the sixth source / drain region SD16, and the eighth source / drain region SD18. The layer in which the first pattern P11 and the fourth interlayer insulating layer 34 are formed can be referred to as the first wiring layer M1. In the first wiring layer M1, second to fourth patterns P12, P13 and P14, which will be described later, can also be formed (see reference). Figure 3E ).

[0041] Reference Figure 3B The device isolation layer ISO can be formed on the substrate 10. The device isolation layer ISO can be referenced as follows: Figure 3E and Figure 3F The active region is described as being isolated. First interlayer insulating layers 31 to 34 can be formed on the device isolation layer ISO. A first gate contact CB1 can penetrate the second interlayer insulating layer 32 and connect to the first gate electrode G1. A first gate via VB1 can penetrate the third interlayer insulating layer 33 and connect to the first gate contact CB1 and the second pattern P12. The second pattern P12 corresponds to... Figure 2 Node A in the circuit diagram.

[0042] The third source / drain contact CA13, the fifth source / drain contact CA15, and the seventh source / drain contact CA17 can penetrate the second interlayer insulation layer 32. The third source / drain via VA13, the fifth source / drain via VA15, and the seventh source / drain via VA17 can penetrate the third interlayer insulation layer 33 and connect to the second pattern P12. The third source / drain via VA13, the fifth source / drain via VA15, and the seventh source / drain via VA17 can be sequentially connected to the third source / drain contact CA13, the fifth source / drain contact CA15, and the seventh source / drain contact CA17, respectively. Therefore, Figure 3A The third source / drain region SD13, the fifth source / drain region SD15, and the seventh source / drain region SD17 shown can be electrically short-circuited with the first gate electrode G1 at node A.

[0043] In some embodiments, as Figure 3B The difference shown can omit the first gate contact CB1, and the second pattern P12 can be electrically connected to the first gate electrode G1 through a gate via penetrating the second interlayer insulating layer 32 and the third interlayer insulating layer 33.

[0044] Reference Figure 3C The second to seventh gate contacts CB2, CB3, CB4, CB5, CB6, and CB7 can penetrate the second interlayer insulating layer 32 and are sequentially connected to the second to seventh gate electrodes G2, G3, G4, G5, G6, and G7, respectively. The second to seventh gate vias VB2, VB3, VB4, VB5, VB6, and VB7 can penetrate the third interlayer insulating layer 33 and are connected to the second to seventh gate electrodes G2, G3, G4, G5, G6, and G7, respectively. The second to seventh gate vias VB2, VB3, VB4, VB5, VB6, and VB7 can also be connected to the third pattern P13. The third pattern P13 corresponds to... Figure 2 Node B in the circuit diagram.

[0045] The first source / drain contact CA21 can penetrate the second interlayer insulating layer 32. The first source / drain via VA21 can penetrate the third interlayer insulating layer 33 and connect to the third pattern P13 and the first source / drain contact CA21. Therefore, the first source / drain region SD31 formed on the NMOS region (refer to...) Figure 3D It can be electrically short-circuited at node B with the second to seventh gate electrodes G2, G3, G4, G5, G6 and G7.

[0046] In some embodiments, as Figure 3C The difference shown can omit the second to seventh gate contacts CB2, CB3, CB4, CB5, CB6 and CB7, and the third pattern P13 can be connected to the second to seventh gate electrodes G2, G3, G4, G5, G6 and G7 via gate vias penetrating the second interlayer insulating layer 32 and the third interlayer insulating layer 33.

[0047] Reference Figure 3D The first source / drain region to the eighth source / drain region SD31, SD32, SD33, SD34, SD35, SD36, SD37 and SD38 can be formed in the third fin F3. The first interlayer insulating layer to the fourth interlayer insulating layer 31, 32, 33 and 34 can be formed on the third fin F3.

[0048] The first source / drain region SD31, the second source / drain region SD32, and the first gate electrode G1 can form an N-type decoupling MOSFET NDCT1. The second source / drain region SD32, the third source / drain region SD33, and the second gate electrode G2 can form an N-type dummy MOSFET NDMT1. The third source / drain region SD33, the fourth source / drain region SD34, and the third gate electrode G3 can form an N-type dummy MOSFET NDMT1. The fourth source / drain region SD34, the fifth source / drain region SD35, and the fourth gate electrode G4 can form an N-type dummy MOSFET NDMT1. The fifth source / drain region SD35, the sixth source / drain region SD36, and the fifth gate electrode G5 can form an N-type dummy MOSFET NDMT1. The sixth source / drain region SD36, the seventh source / drain region SD37, and the sixth gate electrode G6 can form an N-type dummy MOSFET NDMT1. The seventh source / drain region SD37, the eighth source / drain region SD38, and the seventh gate electrode G7 can constitute an N-type dummy MOSFET NDMT1. Therefore, the asymmetric decoupling unit ASDC1 can include one N-type decoupling MOSFET NDCT1 and six N-type dummy MOSFETs NDMT1.

[0049] The first source / drain contacts to the eighth source / drain contacts CA21, CA22, CA23, CA24, CA25, CA26, CA27, and CA28 can penetrate the second interlayer insulation layer 32 and can be sequentially connected to the first source / drain region to the eighth source / drain region SD31, SD32, SD33, SD34, SD35, SD36, SD37, and SD38, respectively. At least one of the first source / drain contacts to the eighth source / drain contacts CA21, CA22, CA23, CA24, CA25, CA26, CA27, and CA28 may include a lower source / drain contact that penetrates the first interlayer insulation layer 31 and an upper source / drain contact that penetrates the second interlayer insulation layer 32.

[0050] The first source / drain contacts through the eighth source / drain contacts CA21, CA22, CA23, CA24, CA25, CA26, CA27, and CA28 can be connected to any one of the patterns in the first wiring layer M1 via vias penetrating the third interlayer insulating layer 33. According to some embodiments, the second source / drain contacts CA22 through the eighth source / drain contacts CA28 can be connected to a fourth pattern P14 to which a negative power supply voltage (or ground potential) VSS is applied. Therefore, the negative power supply voltage (or ground potential) VSS can be applied to the second source / drain regions SD32 through the eighth source / drain regions SD38.

[0051] Reference Figure 3E The field insulating layer 20 may be formed on the substrate 10. As a non-limiting example, the field insulating layer 20 may include any one of SiO2, SiN, SiON, SiOCN, and combinations thereof. In some embodiments, the field insulating layer 20 may be as follows: Figure 3D The diagram shows some side surfaces surrounding the active pattern (i.e., fins). First to fourth interlayer insulating layers 31, 32, 33, and 34 may be formed on the field insulating layer 20. First to fourth fins F1, F2, F3, and F4 may extend along the X-axis on the field insulating layer 20.

[0052] Source / drain regions SD14, SD24, SD34, and SD44 can be arranged on the first to fourth fins F1, F2, F3, and F4, respectively. An isolation layer ISO extending along the X-direction can be disposed between the first fin F1 and the second fin F2 and between the third fin F3 and the fourth fin F4. The first active region RX1 and the second active region RX2 can be separated from each other by the device isolation layer ISO.

[0053] The fourth source / drain contact CA14 can penetrate the second interlayer insulation layer 32 and connect to the two source / drain regions SD14 and SD24, thus the two source / drain regions SD14 and SD24 can be electrically connected to each other. Furthermore, the fourth source / drain contact CA24 can penetrate the second interlayer insulation layer 32 and connect to the two source / drain regions SD34 and SD44, thus the two source / drain regions SD34 and SD44 can be electrically connected to each other.

[0054] The fourth source / drain via VA14 can penetrate the third interlayer insulation layer 33 and connect to the fourth source / drain contact CA14 and the first pattern P11. Therefore, a positive power supply voltage VDD can be applied to the source / drain regions SD14 and SD24. The fourth source / drain via VA24 can penetrate the third interlayer insulation layer 33 and connect to the fourth source / drain contact CA24 and the fourth pattern P14. Therefore, a negative power supply voltage (or ground potential) VSS can be applied to the source / drain regions SD34 and SD44. The first to fourth patterns P11, P12, P13 and P14 described above can be formed in the first wiring layer M1.

[0055] Reference Figure 3F, a field insulating layer 20 may be formed on a substrate 10, and first to fourth fins F1, F2, F3, and F4 penetrating the field insulating layer 20 may intersect a fifth gate electrode G5 extending in the Y-axis direction. For example, the fifth gate electrode G5 may include a metal such as Ti, Ta, W, Al, or Co or a combination thereof. In another example, the fifth gate electrode G5 may include a semiconductor material such as Si or SiGe. In another example, the fifth gate electrode G5 may include a multilayer structure in which two or more conductive materials are stacked. For example, according to some embodiments, the fifth gate electrode G5 may include a work function layer and a filling conductive film of a conformal deposition structure, the work function layer includes any one of TiN, TaN, TiC, TaC, and TiAlC, and the filling conductive film fills the inside of the work function layer of the conformal deposition structure and includes W or Al.

[0056] As described above, the fifth gate electrode G5 may be electrically connected to the third pattern P13 through a fifth gate contact CB5 and a fifth gate via VB5.

[0057] Figures 4A to 4D is a diagram for describing an example of an asymmetric decoupling unit according to some other example embodiments.

[0058] Figure 4A is a diagram for describing an example of an asymmetric decoupling unit ASDC1a according to some other embodiments. Specifically, Figure 4A the upper part of shows a circuit diagram corresponding to the asymmetric decoupling unit ASDC1a, and Figure 4A the lower part of shows a layout corresponding to the asymmetric decoupling unit ASDC1a.

[0059] For ease of explanation, descriptions identical to those given above with reference to Figures 2 to 3E will be omitted, and the following description will focus on the differences from Figures 2 to 3E those.

[0060] Referring to Figure 4A , the asymmetric decoupling unit ASDC1a may include seven N-type MOSFETs and seven P-type MOSFETs. Different from the asymmetric decoupling unit ASDC1 of [[ID=**28**]] Figure 2 , the asymmetric decoupling unit ASDC1a may include five P-type decoupling MOSFETs PDCT1, two P-type dummy MOSFETs PDMT1, two N-type decoupling MOSFETs NDCT1, and five N-type dummy MOSFETs NDMT1. According to an example embodiment, the asymmetric decoupling unit ASDC1a is mainly constructed of P-type MOSFETs having excellent current leakage characteristics. However, since the number of P-type decoupling MOSFETs PDCT1 and the number of N-type decoupling MOSFETs NDCT1 can be freely changed, the degree of design freedom can be increased.

[0061] Figure 4B is a diagram for describing an example of an asymmetric decoupling unit ASDC1b according to some other embodiments. Specifically, Figure 4B the upper part of shows a circuit diagram corresponding to the asymmetric decoupling unit ASDC1b, and Figure 4B the lower part of shows a layout corresponding to the asymmetric decoupling unit ASDC1b.

[0062] For ease of explanation, descriptions identical to those given above with reference to Figures 2 to 3E will be omitted, and the following description will focus on the differences from Figures 2 to 3E the differences.

[0063] Referring to Figure 4B , the asymmetric decoupling unit ASDC1b may include seven N-type MOSFETs and seven P-type MOSFETs. Different from the Figure 2 asymmetric decoupling unit ASDC1 of, the asymmetric decoupling unit ASDC1b may include four P-type decoupling MOSFETs PDCT1, three P-type dummy MOSFETs PDMT1, three N-type decoupling MOSFETs NDCT1, and four N-type dummy MOSFETs NDMT1.

[0064] Figure 4C is a diagram for describing an example of an asymmetric decoupling unit ASDC1c according to some other embodiments. Specifically, Figure 4C the left part of shows a circuit diagram corresponding to the asymmetric decoupling unit ASDC1c, and Figure 4C the right part of shows a layout corresponding to the asymmetric decoupling unit ASDC1c.

[0065] For ease of explanation, descriptions identical to those given above with reference to Figures 2 to 3E will be omitted, and the following description will focus on the differences from Figures 2 to 3E the differences.

[0066] Referring to Figure 4C , different from Figure 2 in, the asymmetric decoupling unit ASDC1c may have four gate pitches CPP. According to an example embodiment, the asymmetric decoupling unit ASDC1c may include three N-type MOSFETs and three P-type MOSFETs. Different from the Figure 2 asymmetric decoupling unit ASDC1 of, the asymmetric decoupling unit ASDC1c may include two P-type decoupling MOSFETs PDCT1, one P-type dummy MOSFET PDMT1, one N-type decoupling MOSFET NDCT1, and two N-type dummy MOSFETs NDMT1.

[0067] According to the example embodiment, based on the reference Figures 2 to 3F and Figure 4C Based on the given description, those skilled in the art can easily implement an asymmetric decoupling unit that can have 5 to 7 gate pitch CPPs or 9 or more gate pitch CPPs.

[0068] Figure 4D This is a diagram illustrating an example of an asymmetric decoupling unit ASDC1d according to some other embodiments. In detail, Figure 4D The upper part shows the circuit diagram corresponding to the asymmetric decoupling unit ASDC1d, and Figure 4D The lower part shows the layout corresponding to the asymmetric decoupling unit ASDC1d.

[0069] For ease of explanation, references to the above will be omitted. Figures 2 to 3E The descriptions given below are identical to those already provided, and will focus on the descriptions that are identical to those given below. Figures 2 to 3E The differences.

[0070] Reference Figure 4D The asymmetric decoupling unit ASDC1d can have eight gate pitch CPPs. According to an example embodiment, the asymmetric decoupling unit ASDC1d may include seven N-type MOSFETs and seven P-type MOSFETs. Figure 2 Unlike the asymmetric decoupling unit ASDC1, the asymmetric decoupling unit ASDC1d can include one P-type decoupling MOSFET PDCT1, six P-type dummy MOSFETs PDMT1, six N-type decoupling MOSFETs NDCT1 and one N-type dummy MOSFET NDMT1.

[0071] According to the example embodiment, the leakage characteristics of the N-type MOSFET in the asymmetric decoupling unit ASDC1d can be superior to those of the P-type MOSFET. Therefore, the asymmetric decoupling unit ASDC1d can use an N-type MOSFET as the main decoupling capacitor.

[0072] Figure 5 This is a diagram illustrating an example of the asymmetric decoupling unit ASDC2 according to an example embodiment. In detail, Figure 5 The upper part shows the circuit diagram corresponding to the asymmetric decoupling unit ASDC2, and Figure 5 The lower part shows the layout corresponding to the asymmetric decoupling unit ASDC2.

[0073] For ease of explanation, references to the above will be omitted. Figures 2 to 3E The descriptions given below are identical to those already provided, and will focus on the descriptions that are identical to those given below. Figures 2 to 3E The differences.

[0074] Reference Figure 5 The asymmetric decoupling unit ASDC2 may include seven P-type decoupling MOSFETs PDCT2 and seven N-type dummy MOSFETs NDMT2. According to an example embodiment, a positive supply voltage VDD may be applied to the source and drain of the P-type decoupling MOSFETs PDCT2, and a negative supply voltage (or ground potential) VSS may be applied to the gate of the P-type decoupling MOSFETs PDCT2. According to an example embodiment, the source and drain of the N-type dummy MOSFETs NDMT2 may be floating.

[0075] although Figure 5 The asymmetric decoupling unit ASDC2 shown includes eight gate pitch CPPs, but the embodiments are not limited thereto. For example, the asymmetric decoupling unit ASDC2 may include two to seven gate pitch CPPs or nine or more gate pitch CPPs.

[0076] According to the example embodiment, when Figure 2 When the asymmetric decoupling unit ASDC1 uses a P-type decoupling MOSFET PDCT1 as the main decoupling capacitor, at least one N-type MOSFET is required as the decoupling capacitor to provide a negative power supply voltage (or ground potential) VSS as bias.

[0077] On the other hand, because a negative supply voltage (or ground potential) VSS is applied to the gate electrode of the P-type decoupling MOSFET PDCT2, which serves as a decoupling capacitor, the asymmetric decoupling unit ASDC2 can omit any of the N-type MOSFETs as decoupling capacitors for biasing. Therefore, all P-type MOSFETs in the asymmetric decoupling unit ASDC2 can be used as decoupling capacitors, and all N-type MOSFETs in the asymmetric decoupling unit ASDC2 can be N-type dummy MOSFETs NDMT2. In other words, the asymmetric decoupling unit ASDC2 can exclude both P-type dummy MOSFETs and N-type decoupling MOSFETs.

[0078] Figure 6 This is a diagram illustrating an example of the asymmetric decoupling unit ASDC3 according to an example embodiment. In detail, Figure 6 The upper part shows the circuit diagram corresponding to the asymmetric decoupling unit ASDC3, and Figure 6 The lower part shows the layout corresponding to the asymmetric decoupling unit ASDC3.

[0079] For ease of explanation, references to the above will be omitted. Figure 5 The descriptions given below are identical to those already provided, and will focus on the descriptions that are identical to those given below. Figure 5 The differences.

[0080] Reference Figure 6, the asymmetric decoupling unit ASDC3 may include seven P-type dummy MOSFETs PDMT3 and seven N-type decoupling MOSFETs NDCT3. Different from Figure 5 's asymmetric decoupling unit ASDC2, the asymmetric decoupling unit ASDC3 may use an N-type MOSFET as the main decoupling capacitor. Thus, according to an exemplary embodiment, a negative power supply voltage (or ground potential) VSS may be applied to the source and drain of the N-type MOSFET, and a positive power supply voltage VDD may be applied to the gate of the N-type MOSFET. According to an exemplary embodiment, the source and drain of the P-type MOSFET may be floating. According to an exemplary embodiment, the asymmetric decoupling unit ASDC3 may not include a P-type decoupling MOSFET and may not include an N-type dummy MOSFET.

[0081] Figure 7 is a diagram for describing an example of an asymmetric decoupling unit ASDC4 according to an exemplary embodiment. Specifically, Figure 7 the upper part of Figure 7 shows a circuit diagram corresponding to the asymmetric decoupling unit ASDC4, and

[0082] the lower part of Figure 6 shows a layout corresponding to the asymmetric decoupling unit ASDC4. Figure 6 For ease of explanation, descriptions identical to those given above with reference to

[0083] will be omitted, and the following description will focus on the differences from Figure 7 . Referring to

[0084] Figure 7 Figure 7In the illustrated embodiment, the height of the first active region RX1' can be twice or greater than (e.g., three times) the height of the second active region RX2'. According to the example embodiment, the number of active patterns arranged on the first active region RX1' can be greater than the number of active patterns arranged on the second active region RX2'. For example, the number of active patterns arranged on the first active region RX1' can be three, and the number of active patterns arranged on the second active region RX2' can be one. However, the embodiment is not limited to this.

[0085] According to the example embodiment, by forming the first active region RX1' (the first active region RX1' is the region used to form a P-type MOSFET with excellent leakage current characteristics) to be larger than the second active region RX2' (the second active region RX2' is the region used to form an N-type MOSFET), an asymmetric decoupling unit ASDC4 with improved leakage current characteristics and an equivalent level of capacitance can be provided.

[0086] Figure 8 This is a diagram illustrating an example layout of integrated circuit 11 according to an example embodiment.

[0087] According to some embodiments, integrated circuit 11 may include a plurality of asymmetric decoupling units ASDC1, ASDC5 and ASDC6 with different heights. Figure 8 Only the first wiring layer M1, vias, gate electrodes, and active regions are shown.

[0088] The asymmetric decoupling unit ASDC1 can be referenced above. Figures 2 to 3E The asymmetric decoupling unit ASDC1 is described in a substantially identical manner. According to an example embodiment, the height of the asymmetric decoupling unit ASDC5 may be approximately twice the height of the asymmetric decoupling unit ASDC1. According to an example embodiment, the height of the asymmetric decoupling unit ASDC6 may be approximately three times the height of the asymmetric decoupling unit ASDC1.

[0089] According to an example embodiment, the asymmetric decoupling unit ASDC5 may include a first sub-unit ASDC5_1 that is substantially identical to the asymmetric decoupling unit ASDC1. The asymmetric decoupling unit ASDC5 may include a second sub-unit ASDC5_2 that is substantially identical in structure to the asymmetric decoupling unit ASDC5_1, wherein the asymmetric decoupling unit ASDC5_1 is reversed relative to an axis parallel to the X direction. Therefore, the circuit diagrams corresponding to the first sub-unit ASDC5_1 and the second sub-unit ASDC5_2 are... Figure 2 The circuit diagram shown in the upper part is the same. The first sub-unit ASDC5_1 and the second sub-unit ASDC5_2 can share the first wiring layer M1 to provide a negative power supply voltage (or ground potential) VSS.

[0090] Based on the description of the asymmetric decoupling unit ASDC5, those skilled in the art can easily implement an asymmetric decoupling unit having a height approximately twice that of the asymmetric decoupling unit ASDC1 and including a first unit and a second unit sharing a common positive power supply voltage VDD.

[0091] The asymmetric decoupling unit ASDC6 may include a first active region RX1” and a second active region RX2”. The second active region RX2” may be a single unit and may have a height substantially the same as the height of the second active region RX2” of the asymmetric decoupling unit ASDC1. The device isolation layer ISO” may be located between the first active region RX1” and the second active region RX2”. The height of the device isolation layer ISO” may be substantially the same as the height of the device isolation layer ISO of the asymmetric decoupling unit ASDC1.

[0092] The first active region RX1” can be set as a single unit, and the height of the first active region RX1” can be greater than the height of the second active region RX2”. For example, the height of the first active region RX1” can be at least twice the height of the second active region RX2”; however, the embodiments are not limited to this. For example, multiple first active regions RX1” can be set, and the device isolation layer can be located between the first active regions RX1”.

[0093] The height of the first active region RX1” in the asymmetric decoupling unit ASDC6 can be greater than the height of the first active region RX1 in the asymmetric decoupling unit ASDC1. The height of the first active region RX1” included in the asymmetric decoupling unit ASDC6 can be greater than... Figure 2 The height of the first active region RX1 of the asymmetric decoupling unit ASDC1 is three times that of the first active region RX1.

[0094] According to an example embodiment, among the patterns included in the first wiring layer M1, two patterns P61 and P63 for supplying the positive power supply voltage VDD and two patterns P62 and P64 for supplying the negative power supply voltage (or ground potential) VSS can be alternately arranged on the asymmetric decoupling unit ASDC6.

[0095] According to an example embodiment, the first to third patterns P61, P62, and P63 may extend along the X direction on the first active region RX1". According to an example embodiment, portions of the first to third patterns P61, P62, and P63 may overlap with the first active region RX1" in the Z direction. According to an example embodiment, unlike in the asymmetric decoupling unit ASDC1, in the asymmetric decoupling unit ASDC6, the device isolation layer ISO" may not be disposed between the first pattern P61 and the second pattern P62, or between the second pattern P62 and the third pattern P63. Therefore, because the face-to-face area between the active region and the gate electrode is increased, the capacitance relative to the area of ​​the asymmetric decoupling unit ASDC6 can be increased.

[0096] Figure 9 This is a flowchart of a method for manufacturing an integrated circuit (IC) according to an example embodiment. In detail, Figure 9 The flowchart illustrates an example of a method for manufacturing an IC that includes decoupling units. For example... Figure 9 As shown, the method of manufacturing an IC may include multiple operations S20, S40, S60 and S80.

[0097] The cell library (or standard cell library) D12 can include information about the cells, such as functional information, characteristic information, and layout information. For example... Figure 9 As shown, the cell library D12 may include first data D_ASDC1 to sixth data D_ASDC6, and the first data D_ASDC1 to sixth data D_ASDC6 are used to define the reference above. Figures 2 to 8 The data of the described asymmetric decoupling units ASDC1, ASDC1a, ASDC1b, ASDC1c, ASDC1d, ASDC2, ASDC3, ASDC4, ASDC5 and ASDC6.

[0098] In operation S20, a logic synthesis operation can be performed to generate a netlist D13 from RTL data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) can perform logic synthesis from RTL data D11, composed of VHSIC Hardware Description Language (VHDL) and Verilog, with reference to a cell library D12, thereby generating a netlist D13 including a bitstream or a netlist. The semiconductor design tool can select any one of the asymmetric decoupling cells ASDC1, ASDC1a, ASDC1b, ASDC1c, ASDC1d, ASDC2, ASDC3, ASDC4, ASDC5, and ASDC6 from the cell library D12 based on IC conditions.

[0099] In operation S40, a placement and routing (P&R) operation can be performed to generate layout data D14 from netlist D13. For example, for IC floor plan, a semiconductor design tool (e.g., a P&R tool) can determine the number of regions in which asymmetric decoupling units ASDC1, ASDC1a, ASDC1b, ASDC1c, ASDC1d, ASDC2, ASDC3, ASDC4, ASDC5, and ASDC6 are arranged, and the number of rows corresponding to the asymmetric decoupling units ASDC1, ASDC1a, ASDC1b, ASDC1c, ASDC1d, ASDC2, ASDC3, ASDC4, ASDC5, and ASDC6.

[0100] Next, the semiconductor design tool can reference the cell library D12 from the netlist D13 and arrange the asymmetric decoupling cells ASDC1, ASDC1a, ASDC1b, ASDC1c, ASDC1d, ASDC2, ASDC3, ASDC4, ASDC5, and ASDC6 in the region used for arranging the asymmetric decoupling cells ASDC1, ASDC1a, ASDC1b, ASDC1c, ASDC1d, ASDC2, ASDC3, ASDC4, ASDC5, and ASDC6. The semiconductor design tool can generate layout data D14 defining the asymmetric decoupling cells ASDC1, ASDC1a, ASDC1b, ASDC1c, ASDC1d, ASDC2, ASDC3, ASDC4, ASDC5, and ASDC6. The layout data D14 can have a format such as GDSII and can include geometric information about cells and interconnects. Operation S40 can be referred to as a method of designing an IC, or operations S20 and S40 can be collectively referred to as a method of designing an IC, and will be described below. Figure 7 Describe an example of operation S40.

[0101] In operation S60, operations for fabricating a mask can be performed. For example, optical proximity correction (OPC) can be applied to the layout data D14 to correct distortions caused by the properties of light in photolithography (e.g., refraction). The data applied by the OPC can be used to define patterns on the mask to form patterns to be disposed in multiple layers, and at least one mask (or photomask) for forming the patterns in each layer can be fabricated. In some embodiments, the layout of the IC can be modified in a limited manner in operation S60, and this limited modification of the IC in operation S60 is a post-processing step for optimizing the structure of the IC and can be referred to as design polishing.

[0102] In operation S80, operations for manufacturing an IC can be performed. For example, an IC can be manufactured by patterning multiple layers using at least one mask manufactured in operation S60. For example, a front-end process (FEOL) may include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, and forming source and drain electrodes, and individual devices such as transistors, capacitors, and resistors can be formed on a substrate through the FEOL. Furthermore, for example, a back-end process (BEOL) may include operations such as silylation of gate, source, and drain regions, addition of dielectrics, planarization, forming vias, adding metal layers, forming vias, and forming passivation layers, and individual devices such as transistors, capacitors, and resistors can be interconnected through the BEOL. In some embodiments, a middle process (MOL) may be performed between the FEOL and BEOL, and contacts may be formed on individual components. The IC can then be packaged in a semiconductor package and used as a component for various applications.

[0103] Although this disclosure has been specifically shown and described with reference to its embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. An integrated circuit, said integrated circuit comprising at least one decoupling unit, in, The at least one decoupling unit includes: a plurality of P-type metal-oxide-semiconductor field-effect transistors arranged along a first direction; and a plurality of N-type metal-oxide-semiconductor field-effect transistors arranged along the first direction and spaced apart from the plurality of P-type metal-oxide-semiconductor field-effect transistors in a second direction perpendicular to the first direction. The plurality of P-type metal-oxide-semiconductor field-effect transistors include at least one P-type decoupled metal-oxide-semiconductor field-effect transistor. The plurality of N-type metal-oxide-semiconductor field-effect transistors include at least one N-type decoupled metal-oxide-semiconductor field-effect transistor. The first number of the at least one P-type decoupled metal-oxide-semiconductor field-effect transistors differs from the second number of the at least one N-type decoupled metal-oxide-semiconductor field-effect transistors. The plurality of P-type metal-oxide-semiconductor field-effect transistors include at least one P-type dummy metal-oxide-semiconductor field-effect transistor. Among them, the plurality of N-type metal-oxide-semiconductor field-effect transistors include at least one N-type dummy metal-oxide-semiconductor field-effect transistor, and The third number of the at least one P-type dummy metal-oxide-semiconductor field-effect transistors is different from the fourth number of the at least one N-type dummy metal-oxide-semiconductor field-effect transistors.

2. The integrated circuit according to claim 1, wherein, The first number of the at least one P-type decoupled metal-oxide-semiconductor field-effect transistors is greater than the second number of the at least one N-type decoupled metal-oxide-semiconductor field-effect transistors.

3. The integrated circuit according to claim 1, wherein, The first gate electrode of the at least one P-type decoupled metal-oxide-semiconductor field-effect transistor is connected to the source region of the at least one N-type decoupled metal-oxide-semiconductor field-effect transistor, and The second gate electrode of the at least one N-type decoupled metal-oxide-semiconductor field-effect transistor is connected to the drain region of the at least one P-type decoupled metal-oxide-semiconductor field-effect transistor.

4. The integrated circuit according to claim 1, wherein, A first wiring configured to provide a positive power supply voltage is connected to the source region of the at least one P-type decoupled metal-oxide-semiconductor field-effect transistor, and The second wiring, configured to provide a negative power supply voltage, is connected to the drain region of the at least one N-type decoupled metal-oxide-semiconductor field-effect transistor.

5. The integrated circuit according to claim 1, wherein, The first number of the at least one P-type decoupled metal-oxide-semiconductor field-effect transistors is the same as the fourth number of the at least one N-type dummy metal-oxide-semiconductor field-effect transistors.

6. The integrated circuit according to claim 1, wherein, The first sum of the first number of at least one P-type decoupled metal-oxide-semiconductor field-effect transistors and the third number of at least one P-type dummy metal-oxide-semiconductor field-effect transistors is the same as the second sum of the second number of at least one N-type decoupled metal-oxide-semiconductor field-effect transistors and the fourth number of at least one N-type dummy metal-oxide-semiconductor field-effect transistors.

7. The integrated circuit according to claim 1, wherein, A first wiring configured to provide a positive power supply voltage is connected to the first source region and the first drain region of the at least one P-type dummy metal-oxide-semiconductor field-effect transistor, and a second wiring configured to provide a negative power supply voltage is connected to the second source region and the second drain region of the at least one N-type dummy metal-oxide-semiconductor field-effect transistor.

8. An integrated circuit, the integrated circuit including a first decoupling unit having a first height in a first direction, in, The first decoupling unit includes: a plurality of first P-type metal-oxide-semiconductor field-effect transistors arranged along a second direction perpendicular to the first direction; and a plurality of first N-type metal-oxide-semiconductor field-effect transistors arranged along the second direction and spaced apart from the plurality of first P-type metal-oxide-semiconductor field-effect transistors in the first direction. The plurality of first P-type metal-oxide-semiconductor field-effect transistors include at least one first P-type decoupled metal-oxide-semiconductor field-effect transistor and at least one first P-type dummy metal-oxide-semiconductor field-effect transistor. The plurality of first N-type metal-oxide-semiconductor field-effect transistors include at least one first N-type decoupled metal-oxide-semiconductor field-effect transistor and at least one first N-type dummy metal-oxide-semiconductor field-effect transistor. Wherein, the first number of the at least one first P-type decoupled metal-oxide-semiconductor field-effect transistors is different from the second number of the at least one first N-type decoupled metal-oxide-semiconductor field-effect transistors, and The third number of the at least one first P-type dummy metal-oxide-semiconductor field-effect transistors is different from the fourth number of the at least one first N-type dummy metal-oxide-semiconductor field-effect transistors.

9. The integrated circuit of claim 8, further comprising a second decoupling unit having a second height different from the first height of the first decoupling unit. in, The second decoupling unit includes a first sub-unit that is substantially the same as the first decoupling unit and a second sub-unit that is substantially the same as the first decoupling unit that is reversed about an axis parallel to the second direction.

10. The integrated circuit according to claim 9, wherein, The first subunit and the second subunit are configured to share a first wiring, which is configured to provide a positive power supply voltage.

11. The integrated circuit according to claim 9, wherein, The first subunit and the second subunit are configured to share a first wiring, which is configured to provide a negative power supply voltage.

12. The integrated circuit of claim 9, further comprising a third decoupling unit having a third height different from the first and second heights. in, The third decoupling unit includes a first active region in which a plurality of third P-type metal-oxide-semiconductor field-effect transistors are formed, and a second active region in which a plurality of third N-type metal-oxide-semiconductor field-effect transistors are formed. The fourth height of the first active region in the first direction is greater than the fifth height of the second active region in the first direction.

13. The integrated circuit according to claim 12, wherein, The fourth height of the first active region in the first direction is at least twice the fifth height of the second active region in the first direction.

14. The integrated circuit according to claim 12, wherein, The third decoupling unit includes only one first active region.

15. An integrated circuit, said integrated circuit comprising at least one decoupling unit, in, The at least one decoupling unit includes: a first conductivity type decoupling metal-oxide-semiconductor field-effect transistor; and a second conductivity type decoupling metal-oxide-semiconductor field-effect transistor, and The first capacitance associated with the first conductivity type decoupled metal-oxide-semiconductor field-effect transistor is greater than the second capacitance associated with the second conductivity type decoupled metal-oxide-semiconductor field-effect transistor, and The at least one decoupling unit further includes: a third number of second conductivity type dummy metal-oxide-semiconductor field-effect transistors; and a fourth number of first conductivity type dummy metal-oxide-semiconductor field-effect transistors. Wherein, the third quantity is different from the fourth quantity, and Among them, at least one of the fourth number of first conductivity type dummy metal-oxide-semiconductor field-effect transistors includes a source and a drain that are both connected to the supply voltage wiring layer of the integrated circuit.

16. The integrated circuit according to claim 15, in, The first type of conductivity decoupled metal-oxide-semiconductor field-effect transistors are multiple. Among them, there are multiple decoupled metal-oxide-semiconductor field-effect transistors of the second conductivity type, and The first number of decoupled metal-oxide-semiconductor field-effect transistors of the first conductivity type is greater than the second number of decoupled metal-oxide-semiconductor field-effect transistors of the second conductivity type.

17. The integrated circuit according to claim 15, wherein, The first leakage current of the first conductivity type decoupled metal-oxide-semiconductor field-effect transistor is less than the second leakage current of the second conductivity type decoupled metal-oxide-semiconductor field-effect transistor.

18. The integrated circuit according to claim 15, wherein, The first conductivity type decoupled metal-oxide-semiconductor field-effect transistor and the second conductivity type dummy metal-oxide-semiconductor field-effect transistor share a first gate electrode extending along a second direction perpendicular to the first direction, and The second conductivity type decoupled metal-oxide-semiconductor field-effect transistor and the first conductivity type dummy metal-oxide-semiconductor field-effect transistor share a second gate electrode extending along the second direction.

19. The integrated circuit according to claim 15, wherein, The at least one decoupling unit further includes: The first active region extends along the first direction; and The second active region extends along the first direction and is spaced apart from the first active region in a second direction perpendicular to the first direction. In this embodiment, a first conductivity type decoupled metal-oxide-semiconductor field-effect transistor is formed on the first active region. In this embodiment, a second conductivity type decoupled metal-oxide-semiconductor field-effect transistor is formed on the second active region, and Wherein, the first active region has a first length in the second direction that is greater than the second active region in the second direction.

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