Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The application relates to the technical field of semiconductors, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a semiconductor base, a bit line and a word line. The semiconductor base comprises a substrate and an isolation structure. The isolation structure is located above the substrate and is used for isolating a plurality of active regions. The bit line is located in the substrate and is connected with the active regions. The word line intersects with the active regions and surrounds the active regions. The unit configuration size on the semiconductor base is small, that is, the size of the semiconductor structure is further reduced, and the control ability of the buried bit line is stronger, so that the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] With the increasing integration density in semiconductor manufacturing processes, improving the integration density of memory has become a trend.

[0003] Dynamic random access memory (DRAM) is a type of semiconductor memory that comprises an array of memory cells and a peripheral area consisting of control circuitry. Each memory cell includes a transistor electrically connected to a capacitor, which controls the storage or release of charge in the capacitor to store data. The control circuitry, through word lines (WL) and bit lines (BL) that span the array and are electrically connected to each memory cell, can be located at each memory cell to control data access.

[0004] Existing DRAM technology mainly uses buried word line structures, which have large cell configuration sizes and limited control capabilities. Summary of the Invention

[0005] This invention provides a semiconductor structure and a method for fabricating the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] According to a first aspect of the present invention, a semiconductor structure is provided, comprising:

[0007] A semiconductor substrate, comprising a substrate and an isolation structure, wherein the isolation structure is located above the substrate and is used to isolate multiple active regions;

[0008] Bit lines are located within the substrate and are connected to the active region.

[0009] The character line intersects with the active area and surrounds the active area.

[0010] In one embodiment of the present invention, the substrate is an SOI substrate.

[0011] In one embodiment of the present invention, the substrate includes:

[0012] First semiconductor layer;

[0013] An oxide insulating layer is located on the first semiconductor layer, and the bit line is located within the oxide insulating layer.

[0014] The second semiconductor layer is located on the oxide insulating layer;

[0015] The active region includes a second semiconductor layer.

[0016] In one embodiment of the present invention, the bottom end of the bit line is in contact with the oxide insulating layer; and / or, the top end of the bit line is not higher than the lower surface of the second semiconductor layer.

[0017] In one embodiment of the present invention, the thickness of the oxide insulating layer in a first direction is greater than 100 nm, and the first direction is perpendicular to the first semiconductor layer.

[0018] In one embodiment of the present invention, the thickness of the bit line in the first direction is 40nm-70nm; and / or, the thickness of the bit line in the second direction is 30nm-70nm, the first direction being perpendicular to the second direction.

[0019] In one embodiment of the present invention, the active region includes:

[0020] The drain region is connected to the bit line and is formed by epitaxial growth.

[0021] The source region channel is located above the drain region.

[0022] The source region is located above the source channel.

[0023] In one embodiment of the present invention, the semiconductor structure further includes:

[0024] The gate oxide layer covers the top of the drain region, the sidewalls of the source channel, and the bottom and sidewalls of the source region.

[0025] The word lines intersect with the source channel, and a gate oxide layer is provided between the word lines and the source channel.

[0026] In one embodiment of the present invention, the isolation structure includes:

[0027] A first insulating dielectric layer is located on the substrate and covers the sidewalls of the drain region.

[0028] In one embodiment of the present invention, the isolation structure further includes:

[0029] The second insulating dielectric layer is located on the first insulating dielectric layer, and the source channel, source electrode region and word line are all located within the second insulating dielectric layer.

[0030] A gate oxide layer is disposed between the second insulating dielectric layer and the sidewall of the source region.

[0031] In one embodiment of the present invention, the thickness of the drain region in the second direction is 3nm-10nm greater than the thickness of the bit line in the second direction; and / or, the thickness of the drain region in the second direction is greater than the thickness of the source channel in the second direction, and the thickness of the source region in the second direction is greater than the thickness of the source channel in the second direction.

[0032] The second direction is parallel to the substrate.

[0033] In one embodiment of the present invention, a vertical storage transistor is formed in the overlapping region where the bit line and word line spaces intersect. The vertical storage transistor is located on the bit line and connected to the bit line. One overlapping region corresponds to one vertical storage transistor. The cell configuration size of the vertical storage transistor on the semiconductor substrate is greater than or equal to four times the square of the minimum feature size.

[0034] According to a second aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising:

[0035] Forming a substrate;

[0036] Bit lines are formed within the substrate;

[0037] Multiple active regions are formed on the potential line, and the potential line is connected to the active regions;

[0038] A word line is formed above the bit line, intersecting with the active area and surrounding the active area.

[0039] In one embodiment of the present invention, forming a substrate includes:

[0040] Provide a first semiconductor layer;

[0041] An oxide insulating layer is formed on the first semiconductor layer;

[0042] A second semiconductor layer is formed on the oxide insulating layer.

[0043] In one embodiment of the present invention, forming a bit line includes:

[0044] An opening is formed on the substrate, with the bottom surface of the opening located within the oxide insulating layer;

[0045] A bit line is formed within the opening;

[0046] The top of the bit line is not higher than the lower surface of the second semiconductor layer.

[0047] In one embodiment of the present invention, forming an active region includes:

[0048] A third semiconductor layer is formed on the second semiconductor layer, and the third semiconductor layer covers the upper surface of the bit line;

[0049] Partial etching of the second and third semiconductor layers, with the remaining second and third semiconductor layers serving as the drain region;

[0050] A fourth semiconductor layer is formed on the drain region;

[0051] Partial etching of the fourth semiconductor layer, with the remaining fourth semiconductor layer serving as the source channel and source region, and the drain region, source channel, and source region serving as the active region.

[0052] In one embodiment of the present invention, forming word lines includes:

[0053] A first insulating dielectric layer is formed on the oxide insulating layer, and the first insulating dielectric layer covers the sidewall of the drain region;

[0054] A gate oxide layer is formed on the first insulating dielectric layer, and the gate oxide layer covers the top of the drain region, the sidewall of the source channel, and the bottom and sidewall of the source region.

[0055] A conductive material layer is formed on the surface of the gate oxide layer;

[0056] The conductive material layer outside the area where the word line is located is etched, and the remaining conductive material layer serves as the word line.

[0057] A second insulating dielectric layer is formed on the first insulating dielectric layer so that the source channel, the source electrode region, and the word line are all located within the second insulating dielectric layer, and the first insulating dielectric layer and the second insulating dielectric layer serve as an isolation structure.

[0058] In one embodiment of the present invention, the third semiconductor layer is monocrystalline silicon. After monocrystalline silicon is generated based on the second semiconductor layer by epitaxial process, the monocrystalline silicon is in-situ doped or ion implanted to form a drain region; and / or, the fourth semiconductor layer is monocrystalline silicon. After monocrystalline silicon is generated based on the drain region by epitaxial process, the monocrystalline silicon is in-situ doped or ion implanted to form a source channel and a source region.

[0059] In the semiconductor structure of the present invention, the bit lines are located within the substrate and connected to the active region, while the word lines intersect with the active region and surround the active region. This allows for a smaller cell configuration size on the semiconductor substrate, i.e., a further reduction in the size of the semiconductor structure, and stronger control over the embedded bit lines, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0060] Various objects, features, and advantages of the invention will become more apparent from the following detailed description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings. The drawings are merely illustrative of the invention and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar parts. Wherein:

[0061] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0062] Figure 2 This is a schematic diagram illustrating a method for forming a substrate and a mask layer in a semiconductor structure according to an exemplary embodiment;

[0063] Figure 3 This is a top view of a semiconductor structure forming an opening according to an exemplary embodiment;

[0064] Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure at point AA;

[0065] Figure 5 This is a top view of a semiconductor structure forming bit lines according to an exemplary embodiment.

[0066] Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure at point BB;

[0067] Figure 7 This is a top view of a semiconductor structure forming a third semiconductor layer according to an exemplary embodiment.

[0068] Figure 8 yes Figure 7 Schematic diagram of the cross-sectional structure at point CC;

[0069] Figure 9 This is a top view of a semiconductor structure forming a drain region according to an exemplary embodiment;

[0070] Figure 10 yes Figure 9 Schematic diagram of the cross-sectional structure at point DD;

[0071] Figure 11 This is a top view of a semiconductor structure forming a first insulating dielectric layer according to an exemplary embodiment.

[0072] Figure 12 yes Figure 11 Schematic diagram of the cross-sectional structure at the middle EE;

[0073] Figure 13 This is a top view of a semiconductor structure forming a fourth semiconductor layer according to an exemplary embodiment.

[0074] Figure 14 yes Figure 13 Schematic diagram of the cross-sectional structure at the middle FF point;

[0075] Figure 15 This is a top view of a semiconductor structure forming a source channel and a source region according to an exemplary embodiment;

[0076] Figure 16 yes Figure 15 Schematic diagram of the cross-sectional structure at the middle GG point;

[0077] Figure 17 This is a top view of a semiconductor structure forming a second insulating dielectric layer according to an exemplary embodiment.

[0078] Figure 18 yes Figure 17 A schematic diagram of the cross-sectional structure at point HH;

[0079] Figure 19 This is a top view of a semiconductor structure forming a conductive material layer according to an exemplary embodiment.

[0080] Figure 20 yes Figure 19 Schematic diagram of the cross-sectional structure at point II;

[0081] Figure 21 This is a top view of a semiconductor structure forming word lines according to an exemplary embodiment;

[0082] Figure 22 yes Figure 21 Schematic diagram of the cross-sectional structure at the middle JJ;

[0083] Figure 23 This is a top view of a semiconductor structure forming a third insulating dielectric layer according to an exemplary embodiment.

[0084] Figure 24 yes Figure 23 A schematic diagram of the cross-sectional structure at point KK.

[0085] The annotations in the attached figures are explained as follows:

[0086] 10. Semiconductor substrate; 11. Active region; 111. Drain region; 112. Source channel; 113. Source region; 12. Substrate; 121. First semiconductor layer; 122. Insulating oxide layer; 123. Second semiconductor layer; 13. Isolation structure; 131. First insulating dielectric layer; 132. Gate oxide layer; 133. Second insulating dielectric layer; 20. Bit line; 21. Bit line isolation layer; 22. Barrier layer; 23. Conductive layer; 30. Word line;

[0087] 40. Opening; 41. Third semiconductor layer; 42. Fourth semiconductor layer; 44. Conductive material layer; 45. Oxide layer; 46. Nitride layer; 47. Photoresist. Detailed Implementation

[0088] Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different embodiments without departing from the scope of the present invention, and the description and drawings therein are for illustrative purposes only and not intended to limit the present invention.

[0089] In the following description of different exemplary embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention and illustrate, by way of example, various exemplary structures, systems, and steps that can implement multiple aspects of the invention. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the invention. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the invention, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the invention.

[0090] One embodiment of the present invention provides a method for fabricating a semiconductor structure; please refer to [the relevant documentation]. Figure 1 Methods for fabricating semiconductor structures include:

[0091] S101, forming substrate 12;

[0092] S103, bit line 20 is formed in substrate 12;

[0093] S105, multiple active regions 11 are formed on bit line 20, and bit line 20 is connected to active regions 11;

[0094] S107, a word line 30 is formed above the bit line 20, the word line 30 intersects with the active region 11, and the word line 30 surrounds the active region 11.

[0095] The semiconductor structure fabrication method of one embodiment of the present invention forms a buried bit line 20 in a substrate 12 and an active region 11 and a word line 30 above the bit line 20. The bit line 20 is connected to the active region 11 and the word line 30 intersects the active region 11. This eliminates the need for bit line contact holes connecting the bit line 20 and the active region 11, and the cell configuration size on the substrate 12 is smaller, that is, the size of the semiconductor structure can be further reduced. In addition, the control capability of the buried bit line 20 is stronger, thereby improving the performance of the semiconductor structure.

[0096] It should be noted that a vertical storage transistor is formed in the overlapping region where the bit line 20 and word line 30 intersect. The vertical storage transistor is located on the bit line 20 and connected to the bit line 20. One overlapping region corresponds to one vertical storage transistor. The vertical storage transistor includes an active region 11.

[0097] In related technologies, a memory transistor has a width of 3F perpendicular to the word line direction and a width of 2F perpendicular to the bit line direction. The area required for a memory transistor on the substrate is 6F² (3F*2F, i.e., a 3×2 buried word line structure). Here, F represents the minimum feature size, which is the minimum limit linewidth and minimum limit line spacing achievable based on the resolution of current lithography equipment. The minimum limit linewidth and minimum limit line spacing are equal. That is, based on the resolution of existing lithography equipment, the unit size of the fabricated memory transistor can only reach 6F², and cannot be further reduced.

[0098] "Cell configuration size" refers to the cell configuration size that needs to be configured on the substrate for a single memory cell. Specifically, it includes the actual size occupied by a memory cell on the substrate and the spacing required between that memory cell and adjacent memory cells. For example, if N memory transistors occupy a size of M on the substrate, then the cell configuration size of one memory transistor on the substrate is N / M. For vertical memory transistors with a vertical structure, the word line and the bit line space intersect and have overlapping regions, where one overlapping region corresponds to one vertical memory transistor.

[0099] The semiconductor structure fabricated in this embodiment, according to the relevant fabrication process, can form bit lines 20 and word lines 30 with a minimum feature size F, and the spacing between adjacent bit lines 20 and adjacent word lines 30 is also greater than or equal to the minimum feature size F. Therefore, the width of a vertical memory transistor in the direction perpendicular to the bit lines is 2F, and the width in the direction perpendicular to the word lines is also 2F. Consequently, the cell configuration size of the vertical memory transistor can reach 4F² (2F*2F, i.e., a 2×2 buried bit line structure). That is, the cell configuration size of the vertical memory transistor is greater than or equal to four times the square of the minimum feature size. Compared to a 3×2 buried word line structure, the cell configuration size is smaller, i.e., the stacking density is higher.

[0100] In one embodiment, substrate 12 is an SOI substrate.

[0101] In one embodiment, the method of fabricating a semiconductor structure further includes: forming an isolation structure 13, the isolation structure 13 covering the substrate 12, and both the word line 30 and the active region 11 being located within the isolation structure 13.

[0102] In one embodiment, forming a substrate 12 includes: providing a first semiconductor layer 121; forming an oxide insulating layer 122 on the first semiconductor layer 121; and forming a second semiconductor layer 123 on the oxide insulating layer 122.

[0103] Specifically, the first semiconductor layer 121 may be formed of a silicon-containing material. The first semiconductor layer 121 may be formed of any suitable material, such as at least one of silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.

[0104] The oxide insulating layer 122 may include materials such as silicon dioxide (SiO2) and silicon oxycarbonate (SiOC).

[0105] The second semiconductor layer 123 may be formed of a silicon-containing material. The second semiconductor layer 123 may be formed of any suitable material, including at least one of silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.

[0106] It should be noted that the first semiconductor layer 121, the oxide insulating layer 122, and the second semiconductor layer 123 form an insulating substrate silicon (SOI), and the bit line 20 is disposed within the insulating substrate silicon.

[0107] In one embodiment, the thickness of the oxide insulating layer 122 is greater than 100 nm, and the thickness of the second semiconductor layer 123 is 18 nm-22 nm.

[0108] In one embodiment, forming a bit line 20 includes: forming an opening 40 on a substrate 12, the bottom surface of which is located within an oxide insulating layer 122; forming a bit line 20 within the opening 40; wherein the top end of the bit line 20 is not higher than the lower surface of the second semiconductor layer 123, i.e., the bit line 20 is buried within the oxide insulating layer 122.

[0109] In one embodiment, combined Figure 2 A mask layer is deposited on the insulating substrate silicon formed by the first semiconductor layer 121, the oxide insulating layer 122, and the second semiconductor layer 123, and a mask pattern is formed on the mask layer. The mask pattern corresponds to the area where the bit line 20 is located (this reflects a three-dimensional space, that is, based on the plane where the bit line 20 is located, the corresponding space above and below is the area where the bit line 20 is located). The area where the mask pattern is located is etched to form an opening 40. For details, please refer to [reference needed]. Figure 3 and Figure 4 Finally, a position line 20 is formed within the opening of 40. See the attached diagram for details. Figure 5 and Figure 6 .

[0110] In one embodiment, the mask layer includes an oxide layer 45, a nitride layer 46, and a photoresist 47, combined with Figure 2 An oxide layer 45 is formed on the second semiconductor layer 123, a nitride layer 46 is formed on the oxide layer 45, a photoresist 47 is formed on the nitride layer 46, and an opening 40 is formed by photolithography and etching. The opening 40 does not penetrate the oxide insulating layer 122. The depth of the opening 40 in the oxide insulating layer 122 is 40nm-70nm, and the width is 30nm-70nm.

[0111] It should be noted that the oxide insulating layer 122, oxide layer 45, nitride layer 46, and photoresist 47 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0112] In one embodiment, the bit line 20 includes: a bit line isolation layer 21 located within an oxide insulating layer 122; a barrier layer 22 covering the inner surface of the bit line isolation layer 21; and a conductive layer 23 disposed within the barrier layer 22, with the barrier layer 22 covering the upper surface of the conductive layer 23; wherein the barrier layer 22 is connected to the active region 11.

[0113] Combination Figure 5 and Figure 6 A bit line isolation layer 21 is formed inside the opening 40, covering the inner surface of the opening 40. A barrier layer 22 is formed inside the opening 40, covering the inner surface of the bit line isolation layer 21. A conductive layer 23 is filled inside the opening 40. Finally, the upper surface of the conductive layer 23 is covered by the barrier layer 22. The barrier layer 22 may only cover the upper surface of the conductive layer 23, leaving the upper surface of the bit line isolation layer 21 exposed. Of course, the barrier layer 22 may completely cover the upper surfaces of the conductive layer 23 and the bit line isolation layer 21.

[0114] Specifically, the bit line isolation layer 21 may include materials such as silicon nitride (SiN) and silicon carbide nitride (SiCN). The barrier layer 22 may include at least one of tungsten silicide (WSi), titanium nitride (TIN), and titanium (TI), and the conductive layer 23 may include tungsten (W).

[0115] It should be noted that the bit line isolation layer 21, the barrier layer 22 and the conductive layer 23 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, remote plasma nitriding (RPN), thermal oxidation and other processes, and no limitation is made here.

[0116] In one embodiment, forming an active region 11 includes: forming a drain region 111 on a bit line 20; forming a source region channel 112 on the drain region 111; and forming a source region 113 on the source region channel 112. That is, the drain region 111, the source region channel 112, and the source region 113 are arranged sequentially in the vertical direction to form a three-dimensional active region 11.

[0117] In one embodiment, forming an active region 11 includes: forming a third semiconductor layer 41 on a second semiconductor layer 123, the third semiconductor layer 41 covering the upper surface of the bit line 20; partially etching the second semiconductor layer 123 and the third semiconductor layer 41, the remaining second semiconductor layer 123 and the third semiconductor layer 41 serving as a drain region 111; forming a fourth semiconductor layer 42 on the drain region 111; partially etching the fourth semiconductor layer 42, the remaining fourth semiconductor layer 42 serving as a source channel 112 and a source region 113, the drain region 111, the source channel 112 and the source region 113 serving as the active region 11.

[0118] Specifically, after forming bit line 20, the mask layer covering the second semiconductor layer 123 is removed, and a third semiconductor layer 41 is formed on the second semiconductor layer 123, such as... Figure 7 and Figure 8 As shown, the third semiconductor layer 41 covers the bit line 20, and the second semiconductor layer 123 and the third semiconductor layer 41 can be made of the same material.

[0119] A mask layer is used to cover the third semiconductor layer 41, and a mask pattern is formed on the mask layer. The mask pattern corresponds to the area where the drain region 111 is located. The second semiconductor layer 123 and the third semiconductor layer 41 outside the mask pattern are etched. The remaining second semiconductor layer 123 and the third semiconductor layer 41 serve as multiple spaced drain regions 111, such as... Figure 9 and Figure 10 As shown. In this embodiment, the width of the drain region 111 is greater than the width of the bit line 20. Furthermore, the width of the drain region 111 is 3nm-10nm greater than the width of the bit line 20.

[0120] In one embodiment, both the second semiconductor layer 123 and the third semiconductor layer 41 can be monocrystalline silicon. The third semiconductor layer 41 is formed on the second semiconductor layer 123 through an epitaxial growth (Epi) process. That is, after the second semiconductor layer 123 and the third semiconductor layer 41 form monocrystalline silicon, the monocrystalline silicon is in-situ doped or ion implanted to form the drain region 111. The second semiconductor layer 123 can be formed by an epitaxial process.

[0121] Accordingly, the fourth semiconductor layer 42 can be monocrystalline silicon. After monocrystalline silicon is generated based on the drain region 111 through epitaxial process, the monocrystalline silicon is in-situ doped or ion implanted to form the source channel 112 and the source region 113.

[0122] In this embodiment, the epitaxial process can be a selective epitaxial process.

[0123] It should be noted that the drain region 111, the source channel 112, and the source region 113 constitute the drain, channel, and source of a vertical memory transistor, respectively. The drain region 111, source channel 112, and source region 113 each include a first dopant, a second dopant, and a third dopant. The first and third dopants are of a first conductivity type, and the second dopant is of a second conductivity type opposite to the first conductivity type. The first conductivity type dopant can be P-type and the second conductivity type dopant can be N-type, or vice versa. The source region 113 is used to connect to a memory element (e.g., a memory capacitor).

[0124] In one embodiment, forming a word line 30 includes: forming a first insulating dielectric layer 131 on an oxide insulating layer 122, and making the first insulating dielectric layer 131 cover the sidewalls of the drain region 111; forming a gate oxide layer 132 on the first insulating dielectric layer 131, the gate oxide layer 132 covering the top of the drain region 111, the sidewalls of the source channel 112, and the bottom and sidewalls of the source region 113; forming a conductive material layer 44 on the surface of the gate oxide layer 132; etching the conductive material layer 44 outside the region where the word line 30 is located, the remaining conductive material layer 44 serving as the word line 30; and forming a second insulating dielectric layer 133 on the first insulating dielectric layer 131, such that the source channel 112, the source region 113, and the word line 30 are all located within the second insulating dielectric layer 133, the first insulating dielectric layer 131 and the second insulating dielectric layer 133 serving as an isolation structure 13.

[0125] exist Figure 9 and Figure 10 Based on this, that is, after the drain region 111 is formed, a first insulating dielectric layer 131 is formed on the oxide insulating layer 122, and the first insulating dielectric layer 131 covers the sidewall of the drain region 111, such as... Figure 11 and Figure 12 As shown.

[0126] exist Figure 11 and Figure 12 Based on this, a fourth semiconductor layer 42 is formed on the drain region 111, such as Figure 13 and Figure 14As shown, a source channel 112 and a source region 113 are formed by selectively etching the fourth semiconductor layer 42. The width of the source channel 112 is smaller than the width of the drain region 111, and the width of the source channel 112 is also smaller than the width of the source region 113. Figure 15 and Figure 16 As shown.

[0127] exist Figure 15 and Figure 16 Based on this, form such Figure 17 and Figure 18 The gate oxide layer 132 shown covers the first insulating dielectric layer 131, the top of the drain region 111, the sidewall of the source channel 112, and the bottom, sidewall, and top of the source region 113.

[0128] exist Figure 17 and Figure 18 Based on this, the space between the active regions 11 is filled with a conductive material layer 44, thus forming a structure like... Figure 19 and Figure 20 The structure involves forming a mask layer above the conductive material layer 44 and the active region 11, and forming a mask pattern on the mask layer. The mask pattern corresponds to the area where the word line 30 is located. By etching the area outside the mask pattern, a structure is formed as shown in the image. Figure 21 and Figure 22 The character line shown is 30.

[0129] Finally in Figure 21 and Figure 22 Based on this, form such Figure 23 and Figure 24 The second insulating dielectric layer 133 shown has a hole at its top for connecting the source region 113 to a storage element (e.g., a storage capacitor). The second insulating dielectric layer 133 covers a portion of the top of the source region 113.

[0130] It should be noted that when forming the second insulating dielectric layer 133, the gate oxide layer 132 located on the first insulating dielectric layer 131 needs to be removed, so that the second insulating dielectric layer 133 is formed on the first insulating dielectric layer 131, and the gate oxide layer 132 only covers the active region 11.

[0131] Specifically, the conductive material layer 44 may include tungsten (W), and the first insulating dielectric layer 131, the gate oxide layer 132, and the second insulating dielectric layer 133 may all be insulating materials, such as silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbide nitride (SiCN), etc., which are not limited here.

[0132] It should be noted that the first insulating dielectric layer 131, the gate oxide layer 132, and the second insulating dielectric layer 133 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, plasma nitriding, thermal oxidation, in-situ steam generation (ISSG), spin ondielectric (SOD) coating, etc., and no limitation is made here.

[0133] It should be noted that the chemical mechanical polishing (CMP) process is a commonly used process that can be used in conjunction with the formation of semiconductor structures. For example, after the formation of the third semiconductor layer 41, the polishing process can be used to grind and flatten it. Similarly, the first insulating dielectric layer 131, the gate oxide layer 132 and the second insulating dielectric layer 133 can also be ground and flattened in conjunction with the polishing process during their formation. There is no limitation here, and the choice can be made according to specific needs.

[0134] One embodiment of the present invention provides a semiconductor structure, please refer to... Figure 23 and Figure 24 The semiconductor structure includes: a semiconductor substrate 10, which includes a substrate 12 and an isolation structure 13, the isolation structure 13 being located above the substrate 12 and used to isolate the active region 11; a bit line 20, which is located within the substrate 12 and connected to the active region 11; and a word line 30, which is located on the isolation structure 13, intersects with the active region 11, and surrounds the active region 11.

[0135] In one embodiment of the present invention, the bit line 20 of the semiconductor structure is located within the substrate 12 and connected to the active region 11, while the word line 30 intersects the active region 11 and surrounds the active region 11. This allows for a smaller cell configuration size on the semiconductor substrate 10, i.e., a further reduction in the size of the semiconductor structure, and stronger control over the embedded bit line 20, thereby improving the performance of the semiconductor structure.

[0136] In one embodiment, such as Figure 24 As shown, bit line 20 includes: bit line isolation layer 21, which is located within substrate 12; barrier layer 22, which covers the inner surface of bit line isolation layer 21; and conductive layer 23, which is disposed within barrier layer 22 and covers the upper surface of conductive layer 23; wherein, barrier layer 22 is connected to active region 11.

[0137] In one embodiment, there are multiple bit lines 20 and word lines 30. The bit lines 20 extend along a first preset direction, and the word lines 30 extend along a second preset direction. The first preset direction and the second preset direction can be perpendicular to each other.

[0138] In one embodiment, substrate 12 is an SOI substrate, i.e., bit line 20 is located within the SOI substrate.

[0139] In one embodiment, a portion of the active region 11 is formed by an SOI substrate, or the active regions 11 do not include an SOI substrate.

[0140] In one embodiment, the substrate 12 includes: a first semiconductor layer 121; an insulating oxide layer 122 located on the first semiconductor layer 121, with bit lines 20 located within the insulating oxide layer 122; a second semiconductor layer 123 located on the insulating oxide layer 122, with an isolation structure 13 located on the insulating oxide layer 122 and covering the second semiconductor layer 123; wherein the active region 11 includes the second semiconductor layer 123.

[0141] It should be noted that the first semiconductor layer 121, the oxide insulating layer 122, and the second semiconductor layer 123 form a silicon-on-insulator (SOI), that is, the bit line 20 is disposed in the silicon-on-insulator. During the fabrication of the semiconductor structure, part of the second semiconductor layer 123 is removed, and the remaining part is used as the active region 11.

[0142] In one embodiment, the substrate 12 includes a first semiconductor layer 121 and an oxide insulating layer 122, meaning that the second semiconductor layer 123 is removed during the fabrication of the semiconductor structure.

[0143] In one embodiment, the bottom end of bit line 20 is in contact with oxide insulating layer 122, that is, bit line 20 is located inside oxide insulating layer 122, thereby ensuring reliable isolation of bit line 20.

[0144] In one embodiment, the top of the bit line 20 is not higher than the lower surface of the second semiconductor layer 123, that is, the top of the bit line 20 may be flush with the upper surface of the oxide insulating layer 122, or the top of the bit line 20 may be located below the upper surface of the oxide insulating layer 122.

[0145] In one embodiment, the thickness of the oxide insulating layer 122 is greater than 100 nm in a first direction, which is perpendicular to the first semiconductor layer 121.

[0146] In one embodiment, the thickness of bit line 20 in the first direction is 40nm-70nm.

[0147] In one embodiment, the thickness of the bit line 20 in the second direction is 30nm-70nm, and the first direction is perpendicular to the second direction.

[0148] It should be noted that the first direction can be understood as the vertical direction, while the second direction can be understood as the horizontal direction, and in combination with... Figure 24 This can be further explained as the second direction being the horizontal direction parallel to the longitudinal cross-section of the semiconductor structure.

[0149] In one embodiment, such as Figure 24 As shown, the active region 11 includes: a drain region 111, which is connected to the bit line 20 and is formed by an epitaxial growth process; a source channel 112, which is located above the drain region 111; and a source region 113, which is located above the source channel 112. A portion of the drain region 111 is formed by the substrate 12.

[0150] Specifically, the active region 11 includes a drain region 111, a source channel 112, and a source region 113, which respectively constitute the drain, channel, and source of the vertical storage transistor. The drain region 111, source channel 112, and source region 113 are arranged vertically along the height direction. The drain region 111 is located above the bit line 20 and is connected to the bit line 20, thus eliminating the need for a bit line contact hole to connect to the bit line 20. Furthermore, the cell configuration size of the vertical storage transistor on the substrate 12 is relatively small (e.g., the cell configuration size can reach 4F). 2 Therefore, the size of the memory can be further reduced accordingly.

[0151] In one embodiment, the thickness of the drain region 111 in the second direction is greater than the thickness of the bit line 20 in the second direction. In this embodiment, the thickness of the drain region 111 in the second direction is 3nm-10nm greater than the thickness of the bit line 20 in the second direction.

[0152] In one embodiment, the thickness of the drain region 111 in the second direction is greater than the thickness of the source channel 112 in the second direction, the thickness of the source region 113 in the second direction is greater than the thickness of the source channel 112 in the second direction, and the word line 30 intersects with the source channel 112. That is, from a spatial perspective, the word line 30 is located between the drain region 111 and the source region 113, and the thickness of the word line 30 in the second direction may not increase due to the presence of the source channel 112.

[0153] It should be noted that each character line 30 intersects with multiple active areas 11. The intersection here refers to the spatial relationship of the intersection, not specifically to the contact between the two.

[0154] In one embodiment, both the active region 11 and the word line 30 are located within the isolation structure 13.

[0155] In one embodiment, such as Figure 24As shown, the semiconductor structure further includes a gate oxide layer 132, which is located on the drain region 111 and covers the top of the drain region 111, the sidewalls of the source channel 112, and the bottom and sidewalls of the source region 113. The gate oxide layer 132 is disposed between the word line 30 and the source channel 112. The active region 11 and the word line 30 are isolated by the gate oxide layer 132. The gate oxide layer 132 can be an oxide layer, i.e., the gate oxide layer 132 forms a ring-shaped gate oxide layer, thereby isolating the active region 11 from the word line 30.

[0156] In one embodiment, such as Figure 24 As shown, the isolation structure 13 includes a first insulating dielectric layer 131, which is located on the substrate 12 and covers the sidewall of the drain region 111, that is, the drain region 111 is enclosed in the first insulating dielectric layer 131.

[0157] In one embodiment, such as Figure 24 As shown, the isolation structure 13 further includes a second insulating dielectric layer 133, which is located on the first insulating dielectric layer 131. The source channel 112, the source region 113, and the word line 30 are all located within the second insulating dielectric layer 133. A gate oxide layer 132 is disposed between the second insulating dielectric layer 133 and the sidewall of the source region 113. The second insulating dielectric layer 133 achieves isolation between two adjacent word lines 30, that is, the word line 30 and the active region 11 are embedded within the isolation structure 13.

[0158] It should be noted that the top of the source region 113 is used to connect storage elements (e.g., storage capacitors, etc.). Therefore, the second insulating dielectric layer 133 may partially cover the top of the source region 113, or the second insulating dielectric layer 133 may not cover the top of the second insulating dielectric layer 133 at all.

[0159] In one embodiment, a vertical storage transistor is formed in the overlapping region where the bit line 20 and word line 30 intersect. The vertical storage transistor is located on and connected to the bit line 20. One overlapping region corresponds to one vertical storage transistor. The cell configuration size of the vertical storage transistor on the semiconductor substrate 10 is greater than or equal to four times the square of the minimum feature size.

[0160] In one embodiment, a vertical storage transistor is formed in the overlapping region where the bit line 20 and word line 30 intersect. The vertical storage transistor is located on and connected to the bit line 20. The width dimension D1 of the vertical storage transistor in the direction perpendicular to the bit line 20 is twice the minimum feature size, and the width dimension D2 in the direction perpendicular to the word line 30 is twice the minimum feature size.

[0161] It should be noted that bit lines 20 and word lines 30 form a minimum feature size F, and the spacing between adjacent bit lines 20 and adjacent word lines 30 is also greater than or equal to the minimum feature size F. Therefore, the width of a vertical memory transistor perpendicular to both the bit and word lines is 2F. Consequently, the cell configuration size of the vertical memory transistor can reach 4F² (2F*2F, i.e., a 2×2 buried bit line structure). That is, the cell configuration size of the vertical memory transistor is greater than or equal to four times the square of the minimum feature size. Compared to a 3×2 buried word line structure, the cell configuration size is smaller, resulting in a higher stacking density.

[0162] In one embodiment, the semiconductor structure can be obtained by the method described above for fabricating the semiconductor structure.

[0163] It should be noted that the materials of each structural layer in a semiconductor structure can be found in the materials provided in the semiconductor structure fabrication method, and will not be elaborated here.

[0164] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and exemplary embodiments are to be considered merely illustrative, and the true scope and spirit of the invention are indicated by the preceding claims.

[0165] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor substrate (10) includes a substrate (12) and an isolation structure (13) located above the substrate (12) and used to isolate multiple active regions (11). Bit line (20), the bit line (20) is located in the substrate (12), and the bit line (20) is connected to the active region (11); The word line (30) intersects with the active region (11) and surrounds the active region (11). The substrate (12) includes: First semiconductor layer (121); An oxide insulating layer (122) is located on the first semiconductor layer (121), and the bit line (20) is located within the oxide insulating layer (122); A second semiconductor layer (123) is located on the oxide insulating layer (122); The active region (11) includes the second semiconductor layer (123), the bottom end of the bit line (20) is in contact with the oxide insulating layer (122), and the top end of the bit line (20) is not higher than the lower surface of the second semiconductor layer (123).

2. The semiconductor structure according to claim 1, characterized in that, The oxide insulating layer (122) has a thickness greater than 100 nm in a first direction, which is perpendicular to the first semiconductor layer (121).

3. The semiconductor structure according to claim 2, characterized in that, The bit line (20) has a thickness of 40nm-70nm in the first direction; and / or, the bit line (20) has a thickness of 30nm-70nm in the second direction, wherein the first direction is perpendicular to the second direction.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The active region (11) includes: Drain region (111), the drain region (111) is connected to the bit line (20), and the drain region (111) is formed by epitaxial growth process; Source channel (112), the source channel (112) is located above the drain region (111); Source region (113) is located above source channel (112).

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: A gate oxide layer (132) covers the top of the drain region (111), the sidewall of the source channel (112), and the bottom and sidewall of the source region (113). The word line (30) intersects with the source channel (112), and the gate oxide layer (132) is disposed between the word line (30) and the source channel (112).

6. The semiconductor structure according to claim 5, characterized in that, The isolation structure (13) includes: A first insulating dielectric layer (131) is located on the substrate (12) and covers the sidewall of the drain region (111).

7. The semiconductor structure according to claim 6, characterized in that, The isolation structure (13) also includes: The second insulating dielectric layer (133) is located on the first insulating dielectric layer (131), and the source channel (112), the source pole region (113) and the word line (30) are all located within the second insulating dielectric layer (133); The gate oxide layer (132) is disposed between the second insulating dielectric layer (133) and the sidewall of the source region (113).

8. The semiconductor structure according to claim 4, characterized in that, The thickness of the drain region (111) in the second direction is 3nm-10nm greater than the thickness of the bit line (20) in the second direction; and / or, the thickness of the drain region (111) in the second direction is greater than the thickness of the source channel (112) in the second direction, and the thickness of the source region (113) in the second direction is greater than the thickness of the source channel (112) in the second direction. The second direction is parallel to the substrate (12).

9. The semiconductor structure according to claim 1, characterized in that, Vertical storage transistors are formed in the overlapping regions where the bit line (20) and the word line (30) intersect. The vertical storage transistors are located on the bit line (20) and connected to the bit line (20). One overlapping region corresponds to one vertical storage transistor. The cell configuration size of the vertical storage transistor on the semiconductor substrate (10) is greater than or equal to 4 times the square of the minimum feature size.

10. A method for fabricating a semiconductor structure, characterized in that, include: A substrate (12) is formed, the substrate (12) including a first semiconductor layer (121), an oxide insulating layer (122) and a second semiconductor layer (123), the oxide insulating layer (122) being located on the first semiconductor layer (121) and the second semiconductor layer (123) being located on the oxide insulating layer (122); Bit lines (20) are formed in the substrate (12), the bit lines (20) are located in the oxide insulating layer (122), and the top of the bit lines (20) is not higher than the lower surface of the second semiconductor layer (123); Multiple active regions (11) are formed on the bit line (20), the bit line (20) is connected to the active regions (11), the active regions (11) include the second semiconductor layer (123), and the bottom end of the bit line (20) is in contact with the oxide insulating layer (122); A word line (30) is formed above the bit line (20), the word line (30) intersects with the active region (11), and the word line (30) surrounds the active region (11).

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, Forming the substrate (12) includes: A first semiconductor layer (121) is provided; The oxide insulating layer (122) is formed on the first semiconductor layer (121). The second semiconductor layer (123) is formed on the oxide insulating layer (122).

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Forming the bit line (20) includes: An opening (40) is formed on the substrate (12), the bottom surface of the opening (40) being located within the oxide insulating layer (122); The bit line (20) is formed within the opening (40).

13. The method for fabricating a semiconductor structure according to claim 11 or 12, characterized in that, The formation of the active region (11) includes: A third semiconductor layer (41) is formed on the second semiconductor layer (123), the third semiconductor layer (41) covering the upper surface of the bit line (20); The second semiconductor layer (123) and the third semiconductor layer (41) are partially etched, and the remaining second semiconductor layer (123) and the third semiconductor layer (41) serve as the drain region (111). A fourth semiconductor layer (42) is formed on the drain region (111). The fourth semiconductor layer (42) is partially etched, and the remaining fourth semiconductor layer (42) serves as the source channel (112) and the source region (113). The drain region (111), the source channel (112), and the source region (113) serve as the active region (11).

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, Forming the word line (30) includes: A first insulating dielectric layer (131) is formed on the oxide insulating layer (122), and the first insulating dielectric layer (131) covers the sidewall of the drain region (111); A gate oxide layer (132) is formed on the first insulating dielectric layer (131), the gate oxide layer (132) covering the top of the drain region (111), the sidewall of the source channel (112) and the bottom and sidewall of the source region (113); A conductive material layer (44) is formed on the surface of the gate oxide layer (132); The conductive material layer (44) outside the area where the word line (30) is located is etched, and the remaining conductive material layer (44) serves as the word line (30). A second insulating dielectric layer (133) is formed on the first insulating dielectric layer (131) so that the source channel (112), the source region (113) and the word line (30) are all located in the second insulating dielectric layer (133), and the first insulating dielectric layer (131) and the second insulating dielectric layer (133) serve as an isolation structure (13).

15. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The third semiconductor layer (41) is a single crystal silicon. After generating the single crystal silicon based on the second semiconductor layer (123) through an epitaxial process, the single crystal silicon is in-situ doped or ion implanted to form the drain region (111); and / or, the fourth semiconductor layer (42) is a single crystal silicon. After generating the single crystal silicon based on the drain region (111) through an epitaxial process, the single crystal silicon is in-situ doped or ion implanted to form the source channel (112) and the source region (113).

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