A semiconductor device, a manufacturing method thereof, and a three-dimensional memory

Abstract

The application discloses a semiconductor device, a preparation method thereof and a three-dimensional memory. The semiconductor device comprises a stack structure, a channel structure penetrating through the stack structure along a first direction, and a source and a drain respectively located at two ends of the channel structure. The channel structure comprises a storage body, a dielectric layer and a channel layer. The storage body extends along the first direction and has a first sidewall, a first end close to the source and a second end connected with the drain. The dielectric layer surrounds the first end and the first sidewall of the storage body, and the channel layer surrounds the dielectric layer and connects the source and the drain. Therefore, the dielectric layer separates the storage body from the channel layer and the source, the leakage of holes in the storage body in a non-operation state can be inhibited, the hole retention capability is improved, and the storage capability of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates generally to the field of electronic devices, and more specifically to a semiconductor device, a method for fabricating the same, and a three-dimensional memory. Background Technology

[0002] With the continuous growth of demand in the semiconductor market, semiconductor memory technology has developed rapidly, especially Dynamic Random Access Memory (DRAM) technology, which has achieved rapid development and occupies the most important position in the memory market. A common DRAM cell consists of a transistor and a capacitor, forming a 1T1C structure. The logic state is distinguished by whether the capacitor stores charge.

[0003] Currently, the size of traditional 1T1C DRAM is approaching the limits of process technology. For example, at smaller nodes, capacitor manufacturing processes are more complex, leakage current becomes more significant, hold time decreases, static power consumption increases, and operating voltage margin degrades.

[0004] Therefore, there is an urgent need for a capacitor-free DRAM to replace the 1T1C structure and reduce the size of the DRAM. However, how to improve the storage capacity of the capacitor-free DRAM is a problem that needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device, a method for fabricating the same, and a three-dimensional memory, which aim to reduce charge leakage and improve storage capacity.

[0006] On one hand, embodiments of the present invention provide a semiconductor device, comprising:

[0007] The stacked structure includes alternating stacked gate structures and interlayer insulating layers;

[0008] A channel structure that penetrates the stacked structure along a first direction;

[0009] The source and drain are located at opposite ends of the channel structure, respectively.

[0010] The channel structure includes:

[0011] The memory cell extending along the first direction has a first sidewall, a first end near the source, and a second end connected to the drain.

[0012] The dielectric layer surrounding the first end and the first sidewall; and

[0013] A channel layer surrounds the dielectric layer, the channel layer connecting the source and the drain.

[0014] Furthermore, the dielectric layer has a second sidewall connected to the channel layer, a third end connected to the source, and a fourth end near the drain; the memory cell has a first sidewall external portion not surrounded by the dielectric layer at a position corresponding to the fourth end and the drain; the channel layer covers the second sidewall and the fourth end, and connects to the first sidewall external portion.

[0015] Furthermore, the gate structure is divided into a first gate structure and a second gate structure, with the second gate structure located on the side of the first gate structure closer to the source. The number of the first gate structure is at least one layer, and the number of the second gate structure is multiple layers, with the number of the second gate structure being greater than the number of the first gate structure.

[0016] Furthermore, the semiconductor device also includes:

[0017] The first gate contact is connected to the first gate structure;

[0018] The second gate contact is connected to the second gate structure;

[0019] The first gate contact is connected to the word line, and the second gate contact is connected to the disk line.

[0020] Furthermore, the semiconductor device also includes:

[0021] A drain lead-out contact is connected to the drain electrode;

[0022] A source lead-out contact is connected to the source electrode;

[0023] The array passes through the contact and connects to the drain lead-out contact.

[0024] Furthermore, the semiconductor device also includes:

[0025] The peripheral circuit chip has multiple bonding contacts;

[0026] The plurality of bonding contacts are bonded to the first gate contact, the second gate contact, the source lead-out contact, and the array through-contact in a one-to-one correspondence.

[0027] Furthermore, the dielectric layer is made of silicon oxide and / or aluminum oxide.

[0028] On the other hand, embodiments of the present invention provide a method for fabricating a semiconductor device, comprising:

[0029] Provide substrate;

[0030] A stacked layer is formed on the substrate;

[0031] Forming a channel hole that penetrates the stacked layer along a first direction and extends to the substrate;

[0032] A drain electrode is formed at the bottom of the channel hole;

[0033] A channel layer, a first dielectric layer, and a memory cell are sequentially formed on the sidewall of the channel hole. The memory cell has a first sidewall, a first end, and a second end connected to the drain. The channel layer is connected to the drain.

[0034] A second dielectric layer is formed covering the first end of the memory cell;

[0035] A source is formed on the second dielectric layer, and the source is connected to the channel layer.

[0036] Furthermore, the step of sequentially forming a channel layer, a first dielectric layer, and a memory cell on the sidewall of the channel hole includes:

[0037] The channel layer and the first dielectric layer are sequentially deposited on the sidewall of the channel hole and the upper surface of the drain electrode;

[0038] The bottom of the channel layer and the first dielectric layer are punched to expose a portion of the upper surface of the drain electrode;

[0039] The memory cell is formed on the inner surface of the first dielectric layer and the upper surface of the drain.

[0040] Furthermore, prior to the step of forming a channel hole that penetrates the stacked layer along a first direction and extends to the substrate, the method for fabricating the semiconductor device further includes:

[0041] A first insulating layer is formed on the stacked layers, and the channel hole also penetrates the first insulating layer;

[0042] The step of forming a second dielectric layer covering the first end of the memory cell includes:

[0043] The first end of the memory cell is oxidized to form a dielectric material, the thickness of which is greater than the thickness of the first dielectric layer.

[0044] A portion of the dielectric material is removed to form a second dielectric layer, while the first dielectric layer located above the second dielectric layer is also removed.

[0045] Furthermore, the step of forming the source electrode on the second dielectric layer includes:

[0046] Semiconductor material is deposited on the second dielectric layer and the sidewalls of the channel layer;

[0047] The semiconductor material and a portion of the channel layer are subjected to ion implantation and activation processes to form the source electrode connected to the channel layer.

[0048] Furthermore, the stacked layers include alternately stacked interlayer sacrificial layers and interlayer insulating layers, and the method for fabricating the semiconductor device further includes:

[0049] A gate line slot is formed along the first direction, penetrating the stacked layer;

[0050] The interlayer sacrificial layer is replaced with a gate structure through the gate line gap to form a stacked structure;

[0051] A dielectric layer is filled into the gaps in the grid lines;

[0052] The gate structure is divided into a first gate structure and a second gate structure, with the second gate structure located on the side of the first gate structure closer to the source. The number of the first gate structure is at least one layer, and the number of the second gate structure is multiple layers, with the number of the second gate structure being greater than the number of the first gate structure.

[0053] Furthermore, the method for fabricating the semiconductor device further includes:

[0054] The edges of the stacked layers are etched to form a stepped structure, which exposes the interlayer insulating layers at the steps;

[0055] A second insulating layer is formed to cover the stepped structure.

[0056] Furthermore, the method for fabricating the semiconductor device further includes:

[0057] A first gate contact is formed that penetrates the second insulating layer along the first direction and is connected to the first gate structure, and a second gate contact is formed that penetrates the second insulating layer along the first direction and is connected to the second gate structure;

[0058] A word line is formed that is connected to the first gate contact, and a disk line is formed that is connected to the second gate contact;

[0059] Form an array of through contacts that penetrate the second insulating layer along the first direction;

[0060] A source lead-out contact is formed that is connected to the source electrode.

[0061] Furthermore, the method for fabricating the semiconductor device further includes:

[0062] A peripheral circuit chip is formed, the peripheral circuit chip having multiple bonding contacts;

[0063] The plurality of bonding contacts are bonded one-to-one with the first gate contact, the second gate contact, the source lead-out contact, and the array through-contact.

[0064] Furthermore, the method for fabricating the semiconductor device further includes:

[0065] Remove the substrate to expose the array of through contacts and the drain.

[0066] A drain lead-out contact is formed to connect with the drain electrode, and the drain lead-out contact is electrically connected to the array through-contact through an interconnect layer.

[0067] Furthermore, the materials of the first dielectric layer and the second dielectric layer are silicon oxide and / or aluminum oxide.

[0068] In another aspect, embodiments of the present invention provide a three-dimensional memory, including any of the semiconductor devices described above.

[0069] The beneficial effects of this invention are: it provides a semiconductor device, a method for fabricating the same, and a three-dimensional memory. The semiconductor device includes a stacked structure, a channel structure extending through the stacked structure along a first direction, and source and drain electrodes located at opposite ends of the channel structure. The channel structure includes a memory cell, a dielectric layer, and a channel layer. The memory cell extends along the first direction and has a first sidewall, a first end near the source electrode, and a second end connected to the drain electrode. The dielectric layer surrounds the first end and the first sidewall of the memory cell, and the channel layer surrounds the dielectric layer and connects the source and drain electrodes. Therefore, the dielectric layer separates the memory cell from the channel layer and the source electrode, which can suppress hole leakage in the memory cell under no-operation conditions, thereby improving hole retention capability and thus improving the storage capability of the semiconductor device. Attached Figure Description

[0070] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0071] Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in the embodiment of the present invention;

[0072] Figure 2 This is a schematic flowchart of the semiconductor device fabrication method provided in the embodiments of the present invention;

[0073] Figures 3a-3r This is a schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0075] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0076] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0077] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0078] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0079] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in an embodiment of the present invention. Figure 1 The two sides of the middle arc are two cross sections in different directions (and) Figure 3l-3r(The cross-sectional directions are the same). The semiconductor device includes a stacked structure 10 and a channel structure 20 extending through the stacked structure 10 along a first direction. The stacked structure 10 includes alternately stacked gate structures 11 and interlayer insulating layers 12. The first direction can be the direction in which the gate structures 11 and interlayer insulating layers 12 are alternately stacked, and is represented by X in the figure. Figure 1 Taking two channel structures 20 as an example, the specific structure of the channel structure 20 will be described. It can be understood that the number of channel structures 20 in this semiconductor device is not limited by this embodiment.

[0080] The semiconductor device also includes a source 30 and a drain 40 located at opposite ends of the channel structure 20, respectively. Figure 1 The source electrode 30 is located at the top of the channel structure 20, and the drain electrode 40 is located at the bottom of the channel structure 20. Figure 1 Rotating it 180° will reverse the source 30 and drain 40.

[0081] The channel structure 20 includes a memory cell 21, a dielectric layer 22, and a channel layer 23. The memory cell 21 extends along the first direction (X) and has a first sidewall 211, a first end 212 near the source 30, and a second end 213 connected to the drain 40. The dielectric layer 22 surrounds the first end 212 and the first sidewall 211 of the memory cell 21, and the channel layer 23 surrounds the dielectric layer 22. The dielectric layer 22 is made of silicon oxide and / or aluminum oxide, or other insulating materials or combinations thereof, for electrical isolation.

[0082] In one embodiment, the dielectric layer 22 can completely surround the first end 212 and the first sidewall 211 of the memory body 21, that is, the dielectric layer 22 covers all surfaces of the first end 212 and the first sidewall 211 of the memory body 21. The channel layer 23 can completely surround the dielectric layer 22, and its bottom is connected to the drain 40 and its top is connected to the source 30. Therefore, the dielectric layer 22 can completely isolate the channel layer 23 and the memory body 21, and also completely isolate the memory body 21 from the source 30, which can reduce the leakage of holes into the channel layer 23 and the source 30 when the semiconductor device is in a hold state.

[0083] In this embodiment, as Figure 1As shown, the dielectric layer 22 has a second sidewall 221 connected to the channel layer 23, a third end 222 connected to the source 30, and a fourth end 223 near the drain 40. The memory cell 21 has a first sidewall external portion 2111 not surrounded by the dielectric layer 22 at a position corresponding to the fourth end 223 and the drain 40. The channel layer 23 covers the second sidewall 221 and the fourth end 223 of the dielectric layer 22 and connects to the first sidewall external portion 2111. Therefore, the dielectric layer 22 isolates most of the memory cell 21 from the channel layer 23 (almost completely isolates it) and also completely isolates the memory cell 21 from the source 30. This not only reduces hole leakage to the channel layer 23 and the source 30 in the inactive state, improving hole retention, but also facilitates hole flow to the memory cell 21 for storage during write operations.

[0084] In this embodiment, the material of the memory cell 21 can be a P-type doped semiconductor material (e.g., polysilicon), and correspondingly, the materials of the source 30 and drain 40 can be N-type doped semiconductor materials. The material of the channel layer 23 can be a lightly doped P-type semiconductor material or an undoped semiconductor material. In this embodiment, holes can be stored in the memory cell 21 to achieve data storage.

[0085] In another embodiment, when the memory cell 21 is made of an N-type doped semiconductor material, the source 30 and drain 40 can be made of a P-type doped semiconductor material. The channel layer 23 can be made of a lightly doped N-type semiconductor material or an undoped semiconductor material. In this embodiment, electrons can be stored in the memory cell 21 to achieve data storage.

[0086] In one embodiment, the interlayer insulating layer 12 may be made of silicon oxide or other suitable insulating materials. Each gate structure 11 may include a dielectric layer 111 and a conductive layer 112 formed sequentially, with the dielectric layer 111 isolating the conductive layer 112 from other structures (such as the interlayer insulating layer 12). The dielectric layer 111 may be made of a high-k dielectric material (such as alumina). "High-k dielectric material" refers to a material with a high K value, where "K value" refers to the dielectric constant. The conductive layer 112 may include a first conductive layer and a second conductive layer (not shown) formed sequentially, i.e., the first conductive layer is located between the dielectric layer 111 and the second conductive layer. The first conductive layer may be made of titanium nitride, and the second conductive layer may be made of tungsten or polysilicon. The primary function of the first conductive layer is to prevent the second conductive layer from diffusing into the dielectric layer 111 and to enhance the adhesion between the second conductive layer and the dielectric layer 111.

[0087] In one embodiment, such as Figure 1As shown, all gate structures 11 can be divided into a first gate structure 1101 and a second gate structure 1102, with the second gate structure 1102 located on the side of the first gate structure 1101 closer to the source 30. The first gate structure 1101 has at least one layer, and the second gate structure 1102 has multiple layers, with the number of second gate structures 1102 exceeding the number of first gate structures 1101. The total length of each of the first and second gate structures 1101 can be adjusted by selecting the number of layers. For example, if the number of gate structures 11 is 64 layers, the number of second gate structures 1102 is 63 layers, the number of first gate structures 1101 is 1 layer, and the second gate structure 1102 is located above the first gate structure 1101. Figure 1 The bottom gate structure 11 is used as the first gate structure 1101, and the other gate structures 11 are used as the second gate structure 1102. The main difference between the first gate structure 1101 and the second gate structure 1102 is that the connected electrical signals are different.

[0088] like Figure 1 As shown, the stacked structure 10 includes a core region 10c and a stepped region 10b adjacent to the core region 10c. The stacked structure 10 has a stepped structure in the stepped region 10b, and the stepped structure exposes part of the surface of each interlayer insulating layer 12. The bottom of the stacked structure 10 can be an interlayer insulating layer 12, and the thickness of the bottom interlayer insulating layer 12 can be greater than the thickness of the other intermediate interlayer insulating layers 12.

[0089] The semiconductor device further includes a first insulating layer 50, a second insulating layer 60, a third insulating layer 70, and a fourth insulating layer 80. The second insulating layer 60 covers the stepped structure, and the first insulating layer 50 is located on the second insulating layer 60 and the stacked structure 10. The third insulating layer 70 is located on the side of the stacked structure 10 away from the first insulating layer 50, and the second insulating layer 60 also partially covers the third insulating layer 70. The fourth insulating layer 80 covers the first insulating layer 50 and the source 30. The source 30 is formed in the first insulating layer 50, and multiple sources 30 are isolated from each other in the first insulating layer 50. Therefore, each channel structure 20 connects to an independent source 30. Compared to a structure where the channel structure 20 is connected to a common source, the independent source 30 in the semiconductor device of this embodiment can suppress crosstalk during operation.

[0090] The semiconductor device also includes a first gate contact 1101a and a second gate contact 1102a extending along a first direction (X). The first gate contact 1101a is connected to the first gate structure 1101, and the second gate contact 1102a is connected to the second gate structure 1102. The first gate contact 1101a connects the first gate structure 1101 to a word line (not shown), and the second gate contact 1102a connects the second gate structure 1102 to a disk line (not shown). In a channel structure 20, the main function of the first gate structure 1101 is to turn on the channel structure 20 when a certain voltage is applied to the first gate structure 1101 through the word line, thus achieving a selection function. During a storage (write) operation, applying a fixed voltage (less than the voltage of the first gate structure 1101) to the second gate structure 1102 through the disk line allows holes to be retained in the memory bank 21.

[0091] Specifically, when storing data, a word line voltage can be applied to the first gate structure 1101, a disk line voltage lower than the word line voltage can be applied to the second gate structure 1102, and a high voltage relative to the source 30 can be applied to the drain 40. Under the action of the electric field, electron-hole pairs are generated at the position between the second gate structure 1102 and the first gate structure 1101 in the channel layer 23 (i.e., near the bottom of the channel layer 23). Electrons flow to the drain 40, and holes flow from the channel layer 23 to the memory cell 21 for storage, thereby realizing the storage function of the device.

[0092] In one embodiment, when the dielectric layer 22 completely isolates the channel layer 23 and the memory body 21, holes can flow from the channel layer 23 through the drain 40 to the memory body 21 for storage. Figure 1 In one embodiment, when the bottom of the channel layer 23 is connected to the outer portion 2111 of the first sidewall of the storage body 21, holes can flow directly from the channel layer 23 to the storage body 21 for storage.

[0093] The semiconductor device may further include a source lead-out contact 31, a drain lead-out contact 41, and an array through-contact 61. The source lead-out contact 31 is formed in the fourth insulating layer 80 and is located on and connected to the source 30. The drain lead-out contact 41 is formed in the third insulating layer 70 and is located at the bottom of the drain 40 and connected to the drain 40. The array through-contact 61 is located on the periphery of the stacked structure 10 and penetrates the first insulating layer 50 and the second insulating layer 60 along a first direction (X). The bottom of the array through-contact 61 is electrically connected to the drain lead-out contact 41 via a pad (not shown).

[0094] The semiconductor device may further include a peripheral circuit chip 90, which may include a complementary metal-oxide-semiconductor (CMOS) and a bonding surface 91, the bonding surface 91 having a plurality of bonding contacts 92. The plurality of bonding contacts 92 are bonded one-to-one with a first gate contact 1101a, a second gate contact 1102a, a source lead-out contact 31, and an array of through contacts 61, thereby enabling the peripheral circuit chip 90 to control the operation of the channel structure 20.

[0095] The semiconductor device may also include a gate line gap structure A that extends through the first insulating layer 50 and the stacked structure 10. The gate line gap structure A may include a dielectric layer (such as silicon oxide) or a dielectric layer and a conductive layer (such as polysilicon) surrounded by the dielectric layer.

[0096] The semiconductor device provided in this embodiment of the invention adds a U-shaped dielectric layer 22 to the channel structure 20 to separate the memory body 21 from the channel layer 23 and the source 30. This can suppress the leakage of charge in the memory body 21 in the inactive state, thereby improving the charge retention capability and thus improving the storage capability of the semiconductor device.

[0097] Please see Figure 2 , Figure 2 This is a schematic flowchart illustrating the method for fabricating a semiconductor device according to an embodiment of the present invention. Please also refer to... Figures 3a-3r , Figures 3a-3r This is a schematic diagram of the semiconductor device fabrication process provided in this embodiment of the invention. This embodiment uses the fabrication of the aforementioned semiconductor device as an example to illustrate the fabrication method of the semiconductor device, which includes the following steps S1-S7.

[0098] Please see Figure 2 Steps S1-S2 and Figure 3a .

[0099] Step S1: Provide substrate 101.

[0100] The substrate 101 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The semiconductor substrate can also be a substrate containing other elemental semiconductors or compound semiconductors, and can also be a stacked layer, such as Si / SiGe.

[0101] Step S2: Form a stacked layer 10a on the substrate 101.

[0102] Interlayer sacrificial layer 11a and interlayer insulating layer 12 can be deposited alternately on substrate 101. Specifically, interlayer insulating layer 12 can be deposited first, followed by interlayer sacrificial layer 11a and interlayer insulating layer 12 in sequence. The thickness of the bottom interlayer insulating layer 12 can be greater than the thickness of the other interlayer insulating layers 12.

[0103] The method for fabricating the semiconductor device further includes: 1) etching the edges of the stacked layer 10a to form a stepped structure, wherein the stepped structure exposes the interlayer insulating layers 12 at the steps; 2) forming a second insulating layer 60 covering the stepped structure, wherein the upper surfaces of the second insulating layer 60 and the stacked layer 10a may be flat; 3) depositing a first insulating layer 50 on the second insulating layer 60 and the stacked layer 10a.

[0104] Please see Figure 2 Step S3 and Figure 3b .

[0105] Step S3: Form a channel hole 201 that runs through the stacked layer 10a along the first direction (X) and extends to the substrate 101.

[0106] Specifically, the first insulating layer 50, the stacked layer 10a and a portion of the substrate 101 can be etched sequentially to form a channel hole 201 that penetrates the first insulating layer 50, the stacked layer 10a and the portion of the substrate 101.

[0107] Please see Figure 2 Step S4 and Figure 3c .

[0108] Step S4: Form a drain electrode 40 at the bottom of the channel hole 201.

[0109] In one embodiment, a silicon epitaxial growth process can be performed on the surface where the channel hole 201 contacts the substrate 101 to form an epitaxial layer at the bottom of the channel hole 201, and then the epitaxial layer is N-type ion doped to form a drain 40. The upper surface of the drain 40 may be lower than, equal to or higher than the lower surface of the bottom interlayer sacrificial layer 11a.

[0110] In another embodiment, the ion doping process of the epitaxial layer can be performed after the subsequent removal of the substrate 101, reducing the process difficulty.

[0111] Please see Figure 2 Step S5 and Figure 3d-3f .

[0112] Step S5: A channel layer 23, a first dielectric layer 22 and a memory body 21 are sequentially formed on the sidewall of the channel hole 201. The memory body 21 has a first sidewall 211, a first end 212 and a second end 213 connected to the drain 40. The channel layer 23 is connected to the drain 40.

[0113] Specifically, step S5 may include: 1) such as Figure 3d As shown, the channel layer 23 and the first dielectric layer 22a are sequentially deposited on the sidewall of the channel hole 201 and the upper surface of the drain electrode 40. During this process, the channel layer 23 and the first dielectric layer 22a are also deposited on the upper surface of the first insulating layer 50. Therefore, a chemical mechanical polishing process can be performed after the deposition process to remove the channel layer 23 and the first dielectric layer 22a located on the first insulating layer 50; 2) As Figure 3e As shown, a hole is punched at the bottom of the channel layer 23 and the first dielectric layer 22a, that is, the channel layer 23 and the first dielectric layer 22a located at the bottom of the channel hole 201 are etched to expose part of the upper surface of the drain electrode 40; 3) as Figure 3f As shown, the memory cell 21 is formed on the inner surface of the first dielectric layer 22a and the upper surface of the drain 40. Specifically, an amorphous semiconductor (e.g., amorphous silicon) can be deposited first, and then the amorphous silicon can be converted into polycrystalline silicon by a crystallization method (e.g., solid-state crystallization, metal-induced lateral crystallization, or laser annealing). The memory cell 21 has a first sidewall 211, a first end 212, and a second end 213 connected to the drain 40.

[0114] The channel layer 23 can be made of polysilicon, the first dielectric layer 22a can be made of silicon dioxide, and the memory cell 21 can be made of P-type polysilicon. The height of the memory cell 21 can exceed the uppermost interlayer sacrificial layer 11a in the stacked layers 10a, so that after the interlayer sacrificial layer 11a is replaced by the gate structure in subsequent processes, it is beneficial for the gate structure to control the operation of the memory cell 21.

[0115] Please see Figure 2 Step S6 and Figure 3g-3h .

[0116] Step S6: Form a second dielectric layer 22b covering the first end 212 of the memory cell 21.

[0117] In one embodiment, such as Figure 3g As shown, an oxidation process can be used to oxidize the first end 212 of the memory cell 21 to form a dielectric material 22c (such as silicon dioxide) covering the remaining memory cell 21, wherein the thickness of the dielectric material 22c is greater than the thickness of the first dielectric layer 22a. Figure 3hAs shown, the first dielectric layer 22a and a portion of the dielectric material 22c are then etched through the channel hole 201 to remove a portion of the dielectric material 22c to form the second dielectric layer 22b. At the same time, the first dielectric layer 22a located above the second dielectric layer 22b is removed. The second dielectric layer 22b and the remaining first dielectric layer 22a are combined to form a U-shaped dielectric layer 22.

[0118] When the thickness of dielectric material 22c is greater than the thickness of the first dielectric layer 22a, during the etching of the first dielectric layer 22a and dielectric material 22c, it can be ensured that dielectric material 22c is not completely removed to form the second dielectric layer 22b, and the first dielectric layer 22a above the second dielectric layer 22b is completely removed to expose the channel layer 23.

[0119] Since the height of the memory cell 21 formed in step S4 can be adjusted, after its top is oxidized into a second dielectric layer 22b, the height of the remaining memory cell 21 can also be higher than the uppermost interlayer sacrificial layer 11a.

[0120] In another embodiment, a deposition process can be used to deposit a dielectric material 22c on top of the memory cell 21, the thickness of the dielectric material 22c being greater than the thickness of the first dielectric layer 22a. Then, the first dielectric layer 22a and the dielectric material 22c are etched to remove a portion of the dielectric material 22c to form a second dielectric layer 22b, while simultaneously removing the first dielectric layer 22a located above the second dielectric layer 22b.

[0121] Please see Figure 2 Step S7 and Figure 3i-3j .

[0122] Step S7: A source 30 is formed on the second dielectric layer 22b, and the source 30 is connected to the channel layer 23.

[0123] Specifically, step S7 may include: 1) such as Figure 3i As shown, semiconductor material 30a is deposited on the second dielectric layer 22b and the sidewalls of the channel layer 23; 2) as Figure 3j As shown, the semiconductor material 30a and a portion of the second channel layer 23 (the channel layer 23 located above the second dielectric layer 22b) are subjected to an N-type ion implantation and activation process to form the source 30 connected to the lower portion of the channel layer 23.

[0124] After step S7, please refer to Figure 3k-3o The method for fabricating this semiconductor device may further include: 1) as follows Figure 3k-3l As shown ( Figure 3k It is a top view. Figure 3l The left side is Figure 3k Along the cross section at C-C1, Figure 3lThe right side is Figure 3k Along the cross section at B-B1), a gate wire slot 102 is formed along the first direction (X) penetrating the stacked layer 10a. The gate wire slot 102 extends along the Y direction (X, Y, and Z are perpendicular to each other). The contact point CT is a contact structure that will be formed on the step later, so it is represented by a dashed hole; 2) as Figure 3m-3n As shown, the interlayer sacrificial layer 11a is replaced with a gate structure 11 through the gate line gap 102 to form a stacked structure 10. Specifically, the interlayer sacrificial layer 11a can be removed first to form a cavity. Figure 3l ), and then a dielectric layer 111 (such as alumina) and a conductive layer 112 are sequentially deposited in the cavity. The conductive layer 112 may include a first conductive layer (such as titanium nitride) and a second conductive layer (such as tungsten) deposited sequentially; 3) such as Figure 3o As shown, a dielectric layer (such as silicon dioxide) can be filled in the gate gap 102, or a dielectric layer and a conductive layer can be filled in sequence to form a gate gap structure A.

[0125] like Figure 3n As shown, after forming the gate structure 11, all the gate structures 11 can be divided into a first gate structure 1101 and a second gate structure 1102. The second gate structure 1102 is located on the side of the first gate structure 1101 near the source 30. The number of the first gate structure 1101 is at least one layer, and the number of the second gate structure 1102 is multiple layers, with the number of the second gate structure 1102 being greater than the number of the first gate structure 1101.

[0126] Please see Figure 3p The method for fabricating the semiconductor device may further include: 1) forming a fourth insulating layer 80 on the first insulating layer 50 and the source electrode 30; 2) forming a first gate contact 1101a and a second gate contact 1102a extending along a first direction (X), wherein the first gate contact 1101a and the second gate contact 1102a penetrate the fourth insulating layer 80, the first insulating layer 50 and the second insulating layer 60 along the first direction (X), wherein the first gate contact 1101a is connected to the first gate structure 1101, and the second gate contact 1102a is connected to the first gate structure 1101. Point 1102a is connected to the second gate structure 1102; 3) A word line (not shown) is formed to connect to the first gate contact 1101a, and a disk line (not shown) is formed to connect to the second gate contact 1102a; 4) An array of through contacts 61 are formed to penetrate the fourth insulating layer 80, the first insulating layer 50 and the second insulating layer 60 along the first direction (X); 5) A source lead-out contact 31 is formed to penetrate the fourth insulating layer 80, wherein the source lead-out contact 31 connects the source 30 to the source line.

[0127] Please see Figure 3qThe method for fabricating the semiconductor device further includes: forming a peripheral circuit chip 90, the peripheral circuit chip 90 having a bonding surface 91 and a plurality of bonding contacts 92; and bonding the plurality of bonding contacts 92 one-to-one with the first gate contact 1101a, the second gate contact 1102a, the source lead-out contact 31 and the array through contact 61.

[0128] Please see Figure 3r and Figure 1 The method for fabricating the semiconductor device further includes: 1) as follows Figure 3r As shown, the substrate 101 is removed to expose the array through-contact 61 and the drain 40; 2) the bottom of the drain 40 is planarized to make the drain 40, the gate gap structure A, and the array through-contact 61 flush with the bottom surface of the stacked structure 10; 3) as shown Figure 1 As shown, a third insulating layer 70 is formed at the bottom of the stacked structure 10. A drain lead-out contact 41 connected to the drain 40 is formed in the third insulating layer 70. The drain lead-out contact 41 is electrically connected to the array through contact 61 through an interconnect layer (not shown).

[0129] The semiconductor device fabrication method provided in this embodiment of the invention forms a U-shaped dielectric layer 22 that separates the memory cell 21 from the channel layer 23 and the source 30, thereby reducing hole leakage and improving hole retention or storage capability. Each channel structure 20 has an independent source 30, thus allowing for independent control of each source 30 and reducing crosstalk during operation.

[0130] This fabrication method first forms a stacked layer 10a, then a channel structure 20, and finally replaces the interlayer sacrificial layer 11a with a gate structure 11, thus achieving compatibility between capacitor-free DRAM fabrication and NAND fabrication processes. By selecting the number of layers, the total length of the first gate structure 1101 and the total length of the second gate structure 1102 can be set. Furthermore, after removing the substrate 101, the epitaxial layer can be doped on the back side to form a drain 40, which is a low-difficulty process. Moreover, the drain 40 can be led out on the back side and connected to the bit line. This fabrication method also uses a bonding process to bond the peripheral circuit chip 90 to the memory array (including the channel structure 20), achieving electrical connection between the memory array and the peripheral circuit chip 90.

[0131] This invention also provides a three-dimensional memory, which includes the semiconductor device provided in any of the above embodiments. The three-dimensional memory can be a capacitor-free DRAM memory.

[0132] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: The stacked structure includes alternating stacked gate structures and interlayer insulating layers; A channel structure that penetrates the stacked structure along a first direction; The source and drain are located at opposite ends of the channel structure, respectively. The channel structure includes: The memory cell extending along the first direction has a first sidewall, a first end near the source, and a second end connected to the drain. The dielectric layer surrounding the first end and the first sidewall; and A channel layer surrounding the dielectric layer, the channel layer at least covering the sidewalls of the dielectric layer, and the channel layer connecting the source and the drain.

2. The semiconductor device according to claim 1, characterized in that, The dielectric layer has a second sidewall connected to the channel layer, a third end connected to the source, and a fourth end near the drain; the memory cell has a first sidewall external portion not surrounded by the dielectric layer at a position corresponding to the fourth end and the drain. The channel layer covers the second sidewall and the fourth end, and connects to the outer portion of the first sidewall.

3. The semiconductor device according to claim 1, characterized in that, The gate structure is divided into a first gate structure and a second gate structure, with the second gate structure located on the side of the first gate structure closer to the source. The number of the first gate structure is at least one layer, and the number of the second gate structure is multiple layers, with the number of the second gate structure being greater than the number of the first gate structure.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: The first gate contact is connected to the first gate structure; The second gate contact is connected to the second gate structure; The first gate contact is connected to the word line, and the second gate contact is connected to the disk line.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: A drain lead-out contact is connected to the drain electrode; A source lead-out contact is connected to the source electrode; The array passes through the contact and connects to the drain lead-out contact.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes: The peripheral circuit chip has multiple bonding contacts; The plurality of bonding contacts are bonded to the first gate contact, the second gate contact, the source lead-out contact, and the array through-contact in a one-to-one correspondence.

7. The semiconductor device according to claim 1, characterized in that, The dielectric layer is made of silicon oxide and / or aluminum oxide.

8. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A stacked layer is formed on the substrate; Forming a channel hole that penetrates the stacked layer along a first direction and extends to the substrate; A drain electrode is formed at the bottom of the channel hole; A channel layer, a first dielectric layer, and a memory cell are sequentially formed on the sidewall of the channel hole. The memory cell has a first sidewall, a first end, and a second end connected to the drain. The channel layer at least covers the sidewall of the first dielectric layer and is connected to the drain. A second dielectric layer is formed covering the first end of the memory cell; A source is formed on the second dielectric layer, and the source is connected to the channel layer.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of sequentially forming a channel layer, a first dielectric layer, and a memory cell on the sidewall of the channel hole includes: The channel layer and the first dielectric layer are sequentially deposited on the sidewall of the channel hole and the upper surface of the drain electrode; The bottom of the channel layer and the first dielectric layer are punched to expose a portion of the upper surface of the drain electrode; The memory cell is formed on the inner surface of the first dielectric layer and the upper surface of the drain.

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, Prior to the step of forming a channel hole that penetrates the stacked layer along a first direction and extends to the substrate, the method for fabricating the semiconductor device further includes: A first insulating layer is formed on the stacked layers, and the channel hole also penetrates the first insulating layer; The step of forming a second dielectric layer covering the first end of the memory cell includes: The first end of the memory cell is oxidized to form a dielectric material, the thickness of which is greater than the thickness of the first dielectric layer. A portion of the dielectric material is removed to form a second dielectric layer, while the first dielectric layer located above the second dielectric layer is also removed.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The step of forming a source electrode on the second dielectric layer includes: Semiconductor material is deposited on the second dielectric layer and the sidewalls of the channel layer; The semiconductor material and a portion of the channel layer are subjected to ion implantation and activation processes to form the source electrode connected to the channel layer.

12. The method for fabricating a semiconductor device according to claim 8, characterized in that, The stacked layers include alternating stacked interlayer sacrificial layers and interlayer insulating layers, and the method for fabricating the semiconductor device further includes: A gate line slot is formed along the first direction, penetrating the stacked layer; The interlayer sacrificial layer is replaced with a gate structure through the gate line gap to form a stacked structure; A dielectric layer is filled into the gaps in the grid lines; The gate structure is divided into a first gate structure and a second gate structure, with the second gate structure located on the side of the first gate structure closer to the source. The number of the first gate structure is at least one layer, and the number of the second gate structure is multiple layers, with the number of the second gate structure being greater than the number of the first gate structure.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The method for fabricating the semiconductor device further includes: The edges of the stacked layers are etched to form a stepped structure, which exposes the interlayer insulating layers at the steps; A second insulating layer is formed to cover the stepped structure.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The method for fabricating the semiconductor device further includes: A first gate contact is formed that penetrates the second insulating layer along the first direction and is connected to the first gate structure, and a second gate contact is formed that penetrates the second insulating layer along the first direction and is connected to the second gate structure; A word line is formed that is connected to the first gate contact, and a disk line is formed that is connected to the second gate contact; Form an array of through contacts that penetrate the second insulating layer along the first direction; A source lead-out contact is formed that is connected to the source electrode.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The method for fabricating the semiconductor device further includes: A peripheral circuit chip is formed, the peripheral circuit chip having multiple bonding contacts; The plurality of bonding contacts are bonded one-to-one with the first gate contact, the second gate contact, the source lead-out contact, and the array through-contact.

16. The method for fabricating a semiconductor device according to claim 14, characterized in that, The method for fabricating the semiconductor device further includes: Remove the substrate to expose the array of through contacts and the drain. A drain lead-out contact is formed to connect with the drain electrode, and the drain lead-out contact is electrically connected to the array through-contact through an interconnect layer.

17. The method for fabricating a semiconductor device according to claim 8, characterized in that, The materials of the first dielectric layer and the second dielectric layer are silicon oxide and / or aluminum oxide.

18. A three-dimensional memory, characterized in that, Includes the semiconductor device according to any one of claims 1-7.

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