Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The preparation method of the three-dimensional memory comprises the following steps: alternately stacking a first insulating layer and a first sacrificial layer to form a first stack structure; forming a plurality of first sub-contact holes respectively extending to the first sacrificial layers located at different heights in the first stack structure; alternately stacking a second insulating layer and a second sacrificial layer on the first stack structure to form a second stack structure; forming a plurality of first extended contact holes penetrating through the second stack structure and connected to the first sub-contact holes, and forming a plurality of second contact holes respectively extending to the second sacrificial layers located at different heights in the second stack structure; and filling the first sub-contact holes and the first extended contact holes to form a first contact structure, and filling the second contact holes to form a second contact structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and its fabrication method. Background Technology

[0002] As memory size decreases and storage density increases, planar memory faces significant challenges due to process technology limitations and reliability issues. Meanwhile, 3D memory has emerged, offering solutions to the density and performance limitations of planar memory.

[0003] In 3D memory, stepped structures (located in the stepped area) are typically used to provide electrical contact between the word lines and control gates of vertically stacked memory cells (located in the memory array area). However, as the storage capacity in 3D memory continues to increase, the number of vertically stacked memory cells has increased significantly, and correspondingly, the lateral dimensions of the stepped structures have also increased. This reduces the effective storage capacity per unit area. Furthermore, larger stepped structures can lead to higher mechanical stress between the memory array area and the stepped area, which may reduce the internal reliability of the 3D memory.

[0004] It should be understood that this background section is intended to provide some useful context for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not part of what a person skilled in the art knew or understood prior to the relevant valid application date of the subject matter disclosed herein. Summary of the Invention

[0005] This application provides a method for fabricating a three-dimensional memory, the method comprising: alternately stacking a first insulating layer and a first sacrificial layer to form a first stacked structure; forming a plurality of first sub-contact holes in the first stacked structure that extend to the first sacrificial layer at different heights; alternately stacking a second insulating layer and a second sacrificial layer on the first stacked structure to form a second stacked structure; forming a plurality of first extended contact holes that penetrate the second stacked structure and connect to the first sub-contact holes, and forming a plurality of second contact holes in the second stacked structure that extend to the second sacrificial layer at different heights; and filling the first sub-contact holes and the first extended contact holes to form a first contact structure, and filling the second contact holes to form a second contact structure.

[0006] In one embodiment, forming a plurality of first sub-contact holes in the first stacked structure that extend to the first sacrificial layer at different heights includes: forming a patterned first hard mask on the top surface of the first stacked structure; etching a first insulating layer at the top of the first stacked structure using the patterned first hard mask as a mask to form a plurality of first insulating layer openings; and successively masking portions of the patterned first hard mask and etching the plurality of first insulating layer openings using the unmasked portions of the patterned first hard mask as a mask to form a plurality of first sub-contact holes that extend to the first sacrificial layer at different heights.

[0007] In one embodiment, forming a patterned first hard mask on the top surface of the first stacked structure includes: forming a first hard mask on the top surface of the first stacked structure; and forming a plurality of first insulating layer opening patterns in the first hard mask to form the patterned first hard mask.

[0008] In one embodiment, alternatingly stacking a second insulating layer and a second sacrificial layer on the first stacked structure to form a second stacked structure includes: filling a plurality of first sub-contact holes with a dielectric material; and alternatingly stacking a second insulating layer and a second sacrificial layer on one side of the first stacked structure in which the plurality of first sub-contact holes are formed.

[0009] In one embodiment, forming a plurality of first extended contact holes penetrating the second stacked structure and connected to the first sub-contact holes, and forming a plurality of second contact holes extending to the second sacrificial layer at different heights in the second stacked structure, includes: forming a patterned second hard mask on the top surface of the second stacked structure; etching a second insulating layer at the top of the second stacked structure using the patterned second hard mask as a mask to form a plurality of second insulating layer openings; and successively masking portions of the patterned second hard mask, and etching the plurality of second insulating layer openings using the unmasked portions of the patterned second hard mask as a mask to form a plurality of second contact holes extending to the second sacrificial layer at different heights; and a plurality of first extended contact holes penetrating the second stacked structure and connected to the first sub-contact holes.

[0010] In one embodiment, forming a patterned second hard mask on the top surface of the second stacked structure includes: forming a second hard mask on the top surface of the second stacked structure; and forming a plurality of first extended contact hole patterns and a plurality of second insulating layer opening patterns in the second hard mask to form the patterned second hard mask.

[0011] In one embodiment, filling the first sub-contact hole and the first extended contact hole to form a first contact structure includes: removing the dielectric material via the first extended contact hole; forming a first dielectric layer on the inner walls of the first sub-contact hole and the first extended contact hole; forming a first conductive layer extending to the first sacrificial layer inside the first dielectric layer; and filling the space formed by the first conductive layer with a first filler material.

[0012] In one embodiment, filling the second contact hole to form a second contact structure includes: forming a second dielectric layer on the inner wall of the second contact hole; forming a second conductive layer extending to the second sacrificial layer on the inner side of the second dielectric layer; and filling the space formed by the second conductive layer with a second filler material.

[0013] In one embodiment, forming a first dielectric layer on the inner walls of the first sub-contact hole and the first extended contact hole includes: forming a first dielectric layer on the inner walls of the first sub-contact hole and the first extended contact hole, and on the bottom surface of the first sub-contact hole; and removing the first dielectric layer from the bottom surface of the first sub-contact hole.

[0014] In one embodiment, forming a second dielectric layer on the inner wall of the second contact hole includes: forming a second dielectric layer on the inner wall and bottom surface of the second contact hole; and removing the second dielectric layer from the bottom surface of the second contact hole.

[0015] In one embodiment, the method further includes: forming a virtual channel structure that runs through the first stacked structure and the second stacked structure.

[0016] In one embodiment, the method further includes replacing the first sacrificial layer and the second sacrificial layer with a first gate layer and a second gate layer, respectively.

[0017] In one embodiment, the first insulating layer and the second insulating layer are made of oxides; and the first sacrificial layer and the second sacrificial layer are made of nitrides.

[0018] In one embodiment, the materials of the first gate layer and the second gate layer include metal.

[0019] This application also provides a three-dimensional memory, comprising: a first stacked structure including alternating first insulating layers and first gate layers; a second stacked structure located on the first stacked structure, including alternating second insulating layers and second gate layers; a plurality of first contact structures penetrating the second stacked structure and extending to the plurality of first gate layers at different heights; and a plurality of second contact structures located in the second stacked structure and extending to the plurality of second gate layers at different heights.

[0020] In one embodiment, the first contact structure includes: a first filling material; a first conductive layer located outside the first filling material and extending to the first gate layer; and a first dielectric layer located on the sidewall of the first conductive layer.

[0021] In one embodiment, the second contact structure includes: a second filler material; a second conductive layer located outside the second filler material and extending to the second gate layer; and a second dielectric layer located on the sidewall of the second conductive layer.

[0022] In one embodiment, the first filler material and the second filler material comprise oxides; the first conductive layer and the second conductive layer comprise metals; and the first dielectric layer and the second dielectric layer comprise oxides.

[0023] In one embodiment, the first insulating layer and the second insulating layer are made of oxide; and the first gate layer and the second gate layer are made of metal.

[0024] In one embodiment, the three-dimensional memory further includes a substrate, wherein the first stacked structure is located on one side of the substrate.

[0025] In one embodiment, the three-dimensional memory further includes a virtual channel structure that extends through the second stacked structure and the first stacked structure and extends to the substrate.

[0026] The three-dimensional memory and its fabrication method provided according to one or more embodiments of this application may have at least one of the following advantages: 1) By forming multiple first sub-contact holes in the first stacked structure that extend to the first sacrificial layer at different heights, it is possible to connect each first sub-contact hole to the first sacrificial layer at a height without setting up a step. 2) By forming a plurality of first extended contact holes that penetrate the second stacked structure and connect to the first sub-contact hole, the connection between the first sacrificial layer and the peripheral circuit can be achieved through the first sub-contact hole and the first extended contact hole; and 3) By forming multiple second contact holes in the second stacked structure that extend to the second sacrificial layer at different heights, it is possible to connect each second sub-contact hole to the second sacrificial layer at a certain height without setting up a step, and it is also possible to have a large area in the first stacked layer for setting other structures (such as virtual channel structures), which helps to reduce the problem of large contact hole area when there are many stacked layers. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application; and Figures 2 to 36 This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application. Detailed Implementation

[0028] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0029] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first filling material discussed herein may also be referred to as the second filling material, and vice versa.

[0030] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0031] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0032] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0033] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0034] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0035] Typically, forming a stepped structure involves creating a photoresist layer on a stacked structure and then using exposure, development, and etching processes to create multiple steps of varying heights. A dielectric layer is then filled onto these steps to facilitate the formation of multiple contact structures that penetrate the dielectric layer and extend to different heights of the steps, electrically connecting the word lines of the memory cells (located in the memory array area). However, as the number of vertically stacked memory cells increases significantly, the lateral dimensions of the stepped structure also increase, leading to an increase in the number and depth of the steps. When the step depth is large, the corresponding development area needs to be increased to form contact structures that penetrate the dielectric layer and extend to deeper steps. Furthermore, the thickness of the dielectric layer on deeper steps also increases. Due to limitations in actual manufacturing processes, a thicker dielectric layer can lead to difficulties in the filling process and may result in uneven filling density.

[0036] To address the above problems, this application provides a method for fabricating a three-dimensional memory, which can solve at least one of the above problems.

[0037] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application.

[0038] like Figure 1 As shown, the method 1000 for fabricating a three-dimensional memory provided in this application may include: S1, alternately stacking a first insulating layer and a first sacrificial layer to form a first stacked structure; S2, forming a plurality of first sub-contact holes in the first stacked structure that extend to the first sacrificial layer at different heights; S3, alternately stacking a second insulating layer and a second sacrificial layer on the first stacked structure to form a second stacked structure; S4, forming a plurality of first extended contact holes that penetrate the second stacked structure and connect to the first sub-contact holes, and forming a plurality of second contact holes in the second stacked structure that extend to the second sacrificial layer at different heights; and S5, filling the first sub-contact holes and the first extended contact holes to form a first contact structure, and filling the second contact holes to form a second contact structure. Steps S1 to S5 will be described in detail below.

[0039] Step S1

[0040] like Figure 2 As shown, the first insulating layer 110 and the first sacrificial layer 120 can be alternately stacked to form the first stacked structure 100. Exemplarily, the first insulating layer 110 and the first sacrificial layer 120 can be alternately stacked on one side of the substrate 200 to form the first stacked structure 100.

[0041] In exemplary embodiments of this application, the substrate 200 may be, for example, a polycrystalline silicon substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 200 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 200 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0042] In an exemplary embodiment of this application, forming the first stacked structure 100 on the substrate 200 can be achieved through one or more deposition processes. The deposition processes for forming the first stacked structure 100 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the first insulating layer 110 and the first sacrificial layer 120 are not limited to... Figure 2The quantities and thicknesses shown can be varied by those skilled in the art without departing from the concept of this application. Furthermore, the materials of the first insulating layer 110 and the first sacrificial layer 120 can be selected from suitable materials known in the art. For example, the first insulating layer 110 may be an oxide layer (such as silicon oxide), and the first sacrificial layer 120 may be a nitride layer (such as silicon nitride).

[0043] Step S2

[0044] A plurality of first sub-contact holes may be formed in the first stacked structure 100, extending to the first sacrificial layer 120 located at different heights. For example, as shown... Figure 8 As shown, a plurality of first sub-contact holes 510-570 extending to first sacrificial layers 121-127 at different heights can be formed in the first stacked structure 100. This application exemplarily illustrates eight first sacrificial layers and seven first sub-contact holes; however, it should be understood that this application does not specifically limit the number of first sacrificial layers or the number of first sub-contact holes. The number of first sacrificial layers and the number of first sub-contact holes can be adjusted as needed, depending on the size of the three-dimensional memory. As an example, the following description uses the formation of seven first sub-contact holes.

[0045] For example, firstly, a first hard mask may be formed on the top surface of the first stacked structure 100, and a plurality of first insulating layer opening patterns a may be formed in the first hard mask to form a patterned first hard mask 300. Figure 3A and Figure 3B ). Figure 3B An exemplary top view of the patterned first hard mask 300 is shown. Next, the first insulating layer 111 on top of the first stacked structure 100 is etched using the patterned first hard mask 300 as a mask to form eight first insulating layer openings 410-480. Figure 4 ); then, as Figures 5 to 7 As shown, the patterned first hard mask 300 can be partially masked in turn, and the unmasked portion of the patterned first hard mask 300 is used as a mask to etch eight first insulating layer openings 410-480 in turn, so as to form seven first sub-contact holes 510-570 and one first insulating layer opening 430 extending to the first sacrificial layers 121-127 located at different heights.

[0046] In an exemplary embodiment of this application, firstly, as Figure 5As shown, a first contact mask 610 can be used to cover half of the first hard mask 300, such as covering the area of ​​the first hard mask 300 near the openings 410-440 of the first insulating layer. Then, the uncovered half of the first hard mask 300 is used as a mask to cover the openings 450-480 of the first insulating layer. Figure 4 Etching is performed to form the first sub-contact hole 510 extending to the first sacrificial layer 121 and the primary etched holes 311~313. Figure 5 For example, the etching depth can be controlled by controlling, such as etching time, so that the first sub-contact hole 510 and the primary etch holes 311-313 extend to the first sacrificial layer 121. For example, the first contact mask 610 can be formed by depositing any suitable material, such as photoresist or carbon-based polymer material, in half of the first hard mask 300 using a deposition process.

[0047] In an exemplary embodiment of this application, a formation is formed Figure 5 After the structure shown, the first contact mask 610 can be removed by a process such as dry etching using O2 or CF4 plasma or wet etching using a resist / polymer photoresist remover (e.g., a solvent-based chemical agent). Then, as Figure 6 As shown, a second contact mask 620 can be used to mask the middle region of the first hard mask 300, such as the region of the first hard mask 300 near the first sub-contact hole 510, the first etched hole 311, and the openings 430 and 440 of the first insulating layer. Then, the unmasked sides of the first hard mask 300 are used as a mask to mask the openings 410 and 420 of the first insulating layer. Figure 5 ) and the first etched holes 312, 313 ( Figure 5 Etching is performed to form a first sub-contact hole 520 and a secondary etched hole 321 extending to the first sacrificial layer 122, and a first sub-contact hole 530 and a secondary etched hole 322 extending to the first sacrificial layer 123, respectively. Exemplarily, the etching depth can be controlled by controlling the etching time, such as an etching depth equal to the thickness of two stacked layers, so that the first sub-contact hole 520 and the secondary etched hole 321 extend to the first sacrificial layer 122, and the first sub-contact hole 530 and the secondary etched hole 322 extend to the first sacrificial layer 123. It should be understood that a stacked layer includes adjacent first insulating layers and first sacrificial layers, the thickness of a stacked layer is the sum of the thicknesses of one first insulating layer and one first sacrificial layer, the thickness of two stacked layers is the sum of the thicknesses of two first insulating layers and two first sacrificial layers, and so on. Exemplarily, the second contact mask 620 can be formed by depositing any suitable material, such as photoresist or a carbon-based polymer material, in the middle region of the first hard mask 300 using a deposition process.

[0048] In an exemplary embodiment of this application, a formation is formed Figure 6 After the structure shown, the second contact mask 620 can be removed by a process such as dry etching using O2 or CF4 plasma or wet etching using a resist / polymer photoresist remover (e.g., a solvent-based chemical agent). Then, as Figure 7 As shown, a third contact mask 630 can be used to mask two regions of the first hard mask 300, such as the region of the first hard mask 300 near the first sub-contact holes 510 and 530, and the region near the first sub-contact hole 520 and the first insulating layer opening 430. Then, the unmasked region of the first hard mask 300 is used as a mask to etch the secondary etching holes 321 and 322. Figure 6 ), First insulation layer opening 440 ( Figure 6 ) and the first etched hole 311 ( Figure 6 Etching is performed to form a first sub-contact hole 540 extending to the first sacrificial layer 124, a first sub-contact hole 550 extending to the first sacrificial layer 125, a first sub-contact hole 560 extending to the first sacrificial layer 126, and a first sub-contact hole 570 extending to the first sacrificial layer 127, respectively. Exemplarily, the etching depth can be controlled by controlling the etching time, such as in this step, where the etching depth is the thickness of four stacked layers, so that the first sub-contact hole 540 extends to the first sacrificial layer 124, the first sub-contact hole 550 extends to the first sacrificial layer 125, the first sub-contact hole 560 extends to the first sacrificial layer 126, and the first sub-contact hole 570 extends to the first sacrificial layer 127. Exemplarily, the third contact mask 630 can be formed by depositing any suitable material, such as photoresist or a carbon-based polymer material, in an appropriate area of ​​the first hard mask 300 using a deposition process.

[0049] For example, forming Figure 7 After the structure shown, the third contact mask 630 can be removed by processes such as dry etching using O2 or CF4 plasma or wet etching using resist / polymer photoresist removers (e.g., solvent-based chemical agents). Exemplarily, in the formation of... Figure 7 The first hard mask 300 can be removed after the structure shown to form Figure 8 The structure shown.

[0050] Step S3

[0051] like Figure 10 As shown, a second insulating layer 710 and a second sacrificial layer 720 can be alternately stacked on a first stacked structure 100 to form a second stacked structure 700. Exemplarily, firstly, a dielectric material 10 can be filled into the first sub-contact holes 510-570 and the first insulating layer opening 430. Figure 9Then, the second insulating layer 710 and the second sacrificial layer 720 may be alternately stacked on the side of the first stacked structure 100 where the first sub-contact holes 510-570 and the first insulating layer opening 430 are formed.

[0052] For example, after the dielectric material 10 is filled into the first sub-contact holes 510-570 and the first insulating layer opening 430, the top surface of the first laminated structure 100 can be planarized using processes such as chemical mechanical polishing. For example, the dielectric material 10 can be any suitable material, such as an insulating material.

[0053] In an exemplary embodiment of this application, the formation of a second stacked structure 700 on the first stacked structure 100 can be achieved through one or more deposition processes. The deposition processes for forming the second stacked structure 700 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the second insulating layer 710 and the second sacrificial layer 720 are not limited to... Figure 10 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to provide any number and thickness of the second insulating layer 710 and the second sacrificial layer 720 as needed. Furthermore, the materials of the second insulating layer 710 and the second sacrificial layer 720 may be selected from suitable materials known in the art. For example, the second insulating layer 710 may be an oxide layer (such as silicon oxide), and the second sacrificial layer 720 may be a nitride layer (such as silicon nitride).

[0054] Step S4

[0055] A plurality of first extended contact holes may be formed penetrating the second stacked structure 700 and connected to the first sub-contact holes, and a plurality of second contact holes may be formed in the second stacked structure 700 extending to the second sacrificial layer 720 at different heights. For example, a plurality of first extended contact holes 5841-5848 may be formed penetrating the second stacked structure 700 and connected to the first sub-contact holes 510-570 and the first insulating layer opening 430. Figure 23 ), and in the second stacked structure 700, a plurality of second contact holes 1010-1070 and second insulating layer openings 930 are formed respectively extending to the second sacrificial layers 721-727 located at different heights. Figure 22This application exemplarily illustrates eight first extended contact holes, eight second sacrificial layers, and seven second contact holes. However, it should be understood that this application does not specifically limit the number of second sacrificial layers or the number of first extended contact holes and second contact holes. The number of first extended contact holes can be the same as the number of first sub-contact holes. The number of second sacrificial layers and the number of second contact holes can be adjusted as needed, depending on the size of the three-dimensional memory. As an example, the following description will use the formation of eight first extended contact holes and seven second contact holes as an example.

[0056] For example, firstly, a second hard mask may be formed on the top surface of the second stacked structure 700, and a plurality of first extended contact hole patterns b and a plurality of second insulating layer opening patterns c may be formed in the second hard mask to form a patterned second hard mask 800. Figure 11 and Figure 12 ). Figure 12 An exemplary top view of the patterned second hard mask 800 is shown, i.e., a structural schematic diagram of the patterned second hard mask 800 in the XZ plane. A plurality of first extended contact hole patterns b are identical to a plurality of first insulating layer opening patterns a, and the projections of the plurality of first extended contact hole patterns b onto the first sub-contact holes 510-570 and the first insulating layer opening 430, respectively. Exemplarily, the plurality of first extended contact hole patterns b and the plurality of second insulating layer opening patterns c may have a certain spacing. For example, the plurality of first extended contact hole patterns b and the plurality of second insulating layer opening patterns c may be staggered. It should be understood that this application does not specifically limit the positional distribution of the plurality of first extended contact hole patterns b and the plurality of second insulating layer opening patterns c; the plurality of first extended contact hole patterns b and the plurality of second insulating layer opening patterns c may be disposed in the stepped area. Alternatively, the plurality of first extended contact hole patterns b and the plurality of second insulating layer opening patterns c may also be disposed in the core region.

[0057] Next, using a patterned second hard mask 800 as a mask, the second insulating layer 711 located on top of the second stacked structure 700 is etched to form eight second insulating layer openings 910-980. Figure 13 ) and 8 primary first extension contact holes 5811~5818 ( Figure 14 It should be understood that... Figure 13 For the three-dimensional memory Figure 12 The diagram shows the structure in the CC direction; Figure 14 For the three-dimensional memory Figure 12 A schematic diagram of the structure in the BB direction is shown. For example, Figure 15A schematic diagram of the structure of a three-dimensional memory perpendicular to the CC and BB directions is shown, that is, a schematic diagram of the structure of the three-dimensional memory in the XY plane. Specifically, the first extended contact holes 5811~5818 can extend along the Y direction to the first sub-contact holes 510~570, and the first extended contact holes 5811~5818 and the second insulating layer openings 910~980 have a certain distance in the X direction.

[0058] Then, as Figures 16 to 21 As shown, a partially patterned second hard mask 800 can be sequentially masked, and the unmasked portions of the patterned second hard mask 800 are used as masks to sequentially etch eight second insulating layer openings 910-980 to form seven second contact holes 1010-1070 and one second insulating layer opening 930 extending to second sacrificial layers 721-727 at different heights. Exemplarily, during the formation of the seven second contact holes 1010-1070, eight primary first extension contact holes 5811-5818 can also be sequentially etched to form eight first extension contact holes 581-588 connected to the first sub-contact holes 510-570.

[0059] In an exemplary embodiment of this application, firstly, as Figure 16 As shown (along) Figure 12 (Cross-sectional view taken along the center line CC) Half of the second hard mask 800 can be masked using the top first contact mask 1240, such as masking the area of ​​the second hard mask 800 near the openings 910-940 of the second insulating layer. Then, the unmasked half of the second hard mask 800 is used as a mask to cover the openings 950-980 of the second insulating layer. Figure 13 Etching is performed to form a second contact hole 1010 extending to the second sacrificial layer 721 and top primary etched holes 811-813. Exemplarily, during the formation of the second contact hole 1010 and the top primary etched holes 811-813, as... Figure 17 As shown (along) Figure 12 (A cross-sectional view taken along the centerline BB) may also be etched with eight primary first extension contact holes 5811-5818 to form eight secondary first extension contact holes 5821-5828 extending to the second sacrificial layer 721. Exemplarily, the etching depth can be controlled by adjusting the etching time, such as by adjusting the etching time, so that the second contact hole 1010 and the top primary etched holes 811-813 extend to the second sacrificial layer 721; and the secondary first extension contact holes 5821-5828 extend to the second sacrificial layer 721. Exemplarily, the top first contact mask 1240 can be formed by depositing any suitable material, such as photoresist or a carbon-based polymer material, in half of the second hard mask 800 using a deposition process.

[0060] In an exemplary embodiment of this application, a formation is formed Figure 16 and 17 After the structure shown, the top first contact mask 1240 can be removed by a process such as dry etching using O2 or CF4 plasma or wet etching using a resist / polymer photoresist remover (e.g., a solvent-based chemical agent). Then, as Figure 18 As shown (along) Figure 12 (Cross-sectional view taken from the center line CC) The middle area of ​​the second hard mask 800 can be masked using the top second contact mask 1250, such as masking the area of ​​the second hard mask 800 near the second contact hole 1010, the top first etched hole 811, and the second insulating layer openings 930 and 940. Then, the unmasked side areas of the first hard mask 300 are used as masks to mask the second insulating layer openings 910 and 920 ( Figure 16 ) and the top primary etched holes 812 and 813 ( Figure 16 Etching is performed to form a second contact hole 1020 extending to the second sacrificial layer 722 and a top secondary etched hole 821, and a second contact hole 1030 extending to the second sacrificial layer 723 and a top secondary etched hole 822, respectively. Exemplarily, during the formation of the second contact holes 1020, 1030 and the top secondary etched holes 821, 822, as... Figure 19 As shown (along) Figure 12 (A cross-sectional view taken along the centerline BB) may also be etched with eight secondary first extension contact holes 5821-5828 to form eight tertiary first extension contact holes 5831-5838 extending to the second sacrificial layer 723. Exemplarily, the etching depth can be controlled by controlling factors such as etching time, so that the second contact hole 1020 and the top secondary etched hole 821 extend to the second sacrificial layer 722; the second contact hole 1030 and the top secondary etched hole 822 extend to the second sacrificial layer 723; and the tertiary first extension contact holes 5831-5838 extend to the second sacrificial layer 723. For example, the etching depth can be controlled by the etching time, such as an etching depth equal to the thickness of two top stacked layers, so that the second contact hole 1020 and the top secondary etched hole 821 extend to the second sacrificial layer 722; the second contact hole 1030 and the top secondary etched hole 822 extend to the second sacrificial layer 723; and the third first extended contact holes 5831-5838 extend to the second sacrificial layer 723. It should be understood that a top stacked layer includes adjacent second insulating layers and second sacrificial layers, the thickness of a top stacked layer is the sum of the thicknesses of a second insulating layer and a second sacrificial layer, the thickness of two top stacked layers is the sum of the thicknesses of two second insulating layers and two second sacrificial layers, and so on. For example, the top second contact mask 1250 can be formed by depositing any suitable material, such as photoresist or a carbon-based polymer material, in the middle region of the second hard mask 800 using a deposition process.

[0061] In an exemplary embodiment of this application, a formation is formed Figure 18 and 19 After the structure shown, the top second contact mask 1250 can be removed by a process such as dry etching using O2 or CF4 plasma or wet etching using a resist / polymer photoresist remover (e.g., a solvent-based chemical agent). Then, as Figure 20 As shown (along) Figure 12 (Cross-sectional view taken from the center line CC) Two regions of the second hard mask 800 can be masked using the top third contact mask 1230, such as the regions of the second hard mask 800 near the second contact holes 1010 and 1030, and the regions near the second contact hole 1020 and the second insulating layer opening 930. Then, the unmasked areas of the second hard mask 800 are used as masks to etch the top secondary etching holes 821 and 822 ( Figure 18 ), second insulation layer opening 940 ( Figure 18 ) and the top primary etching hole 811 ( Figure 18 Etching is performed to form second contact holes 1040 extending to the second sacrificial layer 724, second contact holes 1050 extending to the second sacrificial layer 725, second contact holes 1060 extending to the second sacrificial layer 726, and second contact holes 1070 extending to the second sacrificial layer 727, respectively. For example, during the formation of the second contact holes 1040-1070, eight tertiary first extension contact holes 5831-5838 may also be etched so that the eight tertiary first extension contact holes 5831-5838 extend to the second sacrificial layer 727, respectively. Then, the eight tertiary first extension contact holes 5831-5838 extending to the second sacrificial layer 727 are etched again to form eight first extension contact holes 5841-5848 penetrating the second stacked structure 700 and extending to the first sub-contact holes 510-570 and the first insulating layer opening 430, respectively (e.g., ...). Figure 21 As shown along Figure 12(Cross-sectional view taken along the centerline BB). Exemplarily, the etching depth can be controlled, such as by controlling the first etching time, so that the second contact hole 1040 extends to the second sacrificial layer 724; the second contact hole 1050 extends to the second sacrificial layer 725; the second contact hole 1060 extends to the second sacrificial layer 726; the second contact hole 1070 extends to the second sacrificial layer 727; and eight third-order first-extension contact holes 5831-5838 each extend to the second sacrificial layer 727. Exemplarily, the etching depth can be controlled, such as by controlling the second etching time, so that the first-order extension contact holes 5841-5848 penetrate the second stacked structure 700 and extend to the first sub-contact holes 510-570 and the first insulating layer opening 430, respectively. Exemplarily, the top third contact mask 1230 can be formed by depositing any suitable material, such as photoresist or a carbon-based polymer material, in an appropriate area of ​​the second hard mask 600 using a deposition process.

[0062] For example, forming Figure 20 and 21 After the structure shown, the top third contact mask 1230 can be removed by a process such as dry etching using O2 or CF4 plasma or wet etching using a resist / polymer photoresist remover (e.g., a solvent-based chemical agent). Exemplarily, in the formation of... Figure 20 and 21 The second hard mask 800 can be removed after the structure shown to form Figure 22 (along Figure 12 (Cross-sectional view taken from the center line CC) and Figure 23 (along Figure 12 The structure shown in the cross-sectional view taken along the center line BB.

[0063] Step S5

[0064] The first sub-contact holes 510-570, the first insulating layer opening 430, and the first extended contact holes 5841-5848 can be filled to form a first contact structure, and the second contact holes 1010-1070 and the second insulating layer opening 930 can be filled to form a second contact structure.

[0065] For example, firstly, the dielectric material 10 filling the first sub-contact holes 510-570 and the first insulating layer opening 430 can be removed via the first extended contact holes 5841-5848. Figure 9 ), to form Figure 24 The structure shown. Exemplarily, the dielectric material 10 within the first sub-contact holes 510-570 and the first insulating layer opening 430 can be removed by an etching process, such as etching.

[0066] In an exemplary embodiment of this application, a formation is formed Figure 22 and24 After the structure shown, a second dielectric layer 1200 can be formed on the inner walls of the second contact holes 1010-1070 and the second insulating layer opening 930. Exemplarily, the second dielectric layer 1200 can be formed on the inner walls and bottom surfaces of the second contact holes 1010-1070 and the second insulating layer opening 930 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Figure 25 Then, a deep-hole etching process is used to remove the second dielectric layer 1200 on the bottom surface of the second contact holes 1010-1070 and the second insulating layer opening 930, and to extend the second contact holes 1010-1070 and the second insulating layer opening 930 to their respective next second sacrificial layer. Figure 27 As shown, after deep hole etching, the second insulating layer opening 930 extends to the second sacrificial layer 721, the second contact hole 1010 extends to the second sacrificial layer 722, the second contact hole 1020 extends to the second sacrificial layer 723, the second contact hole 1030 extends to the second sacrificial layer 724, the second contact hole 1040 extends to the second sacrificial layer 725, the second contact hole 1050 extends to the second sacrificial layer 726, the second contact hole 1060 extends to the second sacrificial layer 727, and the second contact hole 1070 extends to the second sacrificial layer 728. Exemplarily, the material of the second dielectric layer 1200 may include an insulating material such as silicon oxide. The second dielectric layer 1200 is formed on the inner wall of the second contact holes 1010-1070, which can isolate the second contact holes 1010-1070 from the second sacrificial layers 721-727 connected to the sidewalls of the second contact holes.

[0067] Exemplarily, a first dielectric layer 1100 may be formed on the inner walls of the first sub-contact holes 510-570, the first insulating layer opening 430, and the first extended contact holes 5841-5848. Exemplarily, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form the first dielectric layer 1100 on the inner walls of the first sub-contact holes 510-570, the first insulating layer opening 430, and the first extended contact holes 5841-5848, as well as on the bottom surface of the first sub-contact holes 510-570 and the first insulating layer opening 430. Figure 26 Then, a deep-hole etching process is used to remove the first dielectric layer 1100 on the bottom surface of the first sub-contact holes 510-570 and the first insulating layer opening 430. For example... Figure 28As shown, after deep hole etching, the first insulating layer opening 430 extends to the first sacrificial layer 121, the first sub-contact hole 510 extends to the first sacrificial layer 122, the first sub-contact hole 520 extends to the first sacrificial layer 123, the first sub-contact hole 530 extends to the first sacrificial layer 124, the first sub-contact hole 540 extends to the first sacrificial layer 125, the first sub-contact hole 550 extends to the first sacrificial layer 126, the first sub-contact hole 560 extends to the first sacrificial layer 127, and the first sub-contact hole 570 extends to the first sacrificial layer 128. Exemplarily, the material of the first dielectric layer 1100 may include an insulating material such as silicon oxide. A first dielectric layer 1100 is formed on the inner walls of the first sub-contact holes 510-570 and the first extended contact holes 5841-5848. The first dielectric layer 1100 can separate the first sub-contact holes 510-570 from the first sacrificial layers 121-127 connected to the sidewalls of the first sub-contact holes 510-570, and also separate the first extended contact holes 5841-5848 from the second sacrificial layers 721-727 connected to the sidewalls of the first extended contact holes 5841-5848. It should be understood that in the preparation method provided in this application, the first dielectric layer 1100 and the second dielectric layer 1200 can be formed in the same process step, i.e., the first dielectric layer 1100 and the second dielectric layer 1200 can be formed simultaneously; of course, the first dielectric layer 1100 and the second dielectric layer 1200 can also be formed in different process steps, i.e., the first dielectric layer 1100 and the second dielectric layer 1200 can be formed separately.

[0068] In an exemplary embodiment of this application, a second conductive layer 1210 extending to the second sacrificial layer may be formed inside the second dielectric layer 1200. Specifically, as Figure 29 As shown, a second conductive layer 1210 can be formed on the inner wall and bottom surface of the second contact holes 1010-1070 and the second insulating layer opening 930, and the second conductive layer 1210 is located inside the second dielectric layer 1200. Exemplarily, a first conductive layer 1110 extending to the first sacrificial layer can be formed inside the first dielectric layer 1100. Specifically, as... Figure 30As shown, a first conductive layer 1110 can be formed on the inner walls of the first sub-contact holes 510-570, the first insulating layer opening 430, and the first extended contact holes 5841-5848, as well as on the bottom surface of the first sub-contact holes 510-570 and the first insulating layer opening 430. The first conductive layer 1110 is located inside the first dielectric layer 1100. It should be understood that in the preparation method provided in this application, the first conductive layer 1110 and the second conductive layer 1210 can be formed in the same process step, that is, the first conductive layer 1110 and the second conductive layer 1210 are formed simultaneously; of course, the first conductive layer 1110 and the second conductive layer 1210 can also be formed in different process steps, that is, the first conductive layer 1110 and the second conductive layer 1210 are formed separately. In this application, by providing a first conductive layer 1110 and a second conductive layer 1210, the first conductive layer 1110 and the second conductive layer 1210 can be respectively connected to the first sacrificial layers 121-128 and the second sacrificial layers 721-728 located at different heights. For example, the first conductive layer 1110 and the second conductive layer 1210 may be made of tungsten metal to achieve electrical connection with the first gate layer and the second gate layer (formed by replacing the first sacrificial layers and the second sacrificial layer).

[0069] In an exemplary embodiment of this application, a first filler material 1120 may be filled within the space formed by the first conductive layer 1110. Figure 32 For example, a second filler material 1220 can be filled within the space formed by the second conductive layer 1210. Figure 31 Exemplarily, the first filler material 1120 and the second filler material 1220 may comprise silicon oxide. Exemplarily, the first filler material 1120 and the second filler material 1220 may be filled using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form the first contact structures 1-8 and the second contact structures 11-18. Optionally, one or more air gaps may be formed during the filling process by controlling the filling process to mitigate the impact on the first contact structures 1-8. Figure 32 ) and second contact structures 11~18 ( Figure 31 Structural stress.

[0070] In an exemplary embodiment of this application, such as Figure 33 and 34 As shown, a virtual channel structure 2000 can be formed that penetrates the first stacked structure 100 and the second stacked structure 700. Exemplarily, the virtual channel structure 2000, penetrating the first stacked structure 100 and the second stacked structure 700 and extending to the substrate 200, can be formed using, for example, dry or wet etching processes. The virtual channel structure 2000 can serve a supporting function to prevent the overall structure from collapsing after the removal of the first sacrificial layers 121-128 and the second sacrificial layers 721-728.

[0071] In an exemplary embodiment of this application, such as Figure 35 and 36 As shown, the first sacrificial layers 121-128 and the second sacrificial layers 721-728 can be replaced with the first gate layers 131-138 and 731-738, respectively. Exemplarily, the first sacrificial layers 121-128 and the second sacrificial layers 721-728 can be replaced with the first gate layers 131-138 and 731-738, respectively, through vias (such as gate gaps). Specifically, the first sacrificial layers 121-128 and the second sacrificial layers 721-728 are first removed by an etching process, and then the first gate layers 131-138 and 731-738 are deposited in the removed space by a deposition process. Exemplarily, the material of the first gate layer and the second gate layer may include tungsten. By replacing the first sacrificial layers 121-128 and the second sacrificial layers 721-728 with the first gate layers 131-138 and 731-738 respectively, electrical connections can be achieved between the first contact structures 1-8 and the second contact structures 11-18 and the first gate layers 131-138 and 731-738 located at different heights.

[0072] The method for fabricating a three-dimensional memory provided in this application, by forming a first stacked structure and a second stacked structure, can sequentially form a plurality of first sub-contact holes and a plurality of second contact holes extending to a first sacrificial layer and a second sacrificial layer located at different heights. This effectively avoids the problem of large development areas and large contact hole sizes caused by the depth of some contact holes when there are many stacked structures, thereby reducing the problem of insufficient space for subsequent formation of virtual channel structures due to the large area occupied by the contact holes in the stacked structure. In addition, the method for fabricating a three-dimensional memory provided in this application can form a plurality of first sub-contact holes and a plurality of second contact holes extending to a first sacrificial layer and a second sacrificial layer located at different heights without the need to create stepped steps, thus further eliminating the process of filling a dielectric layer on the stepped steps. In this application, since it is not necessary to form stepped steps, the step of forming silicon nitride on the stepped steps to increase the thickness of the subsequently formed gate layer is further eliminated. Furthermore, the plurality of first extended contact holes formed in this application only need to ensure that they can extend into the plurality of first sub-contact holes, without strictly controlling the actual depth of the plurality of first extended contact holes. Therefore, in this application, it is not necessary to strictly control the thickness of the insulating layer between the first and second stacked structures, as well as the etching depth when etching the insulating layer.

[0073] This application also provides a three-dimensional memory. Figure 35 and 36 A schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application is shown.

[0074] like Figure 35 and 36 As shown, the three-dimensional memory may include a first stacked structure 100, a second stacked structure 700, a plurality of first contact structures 1 to 8, and a plurality of second contact structures 11 to 18.

[0075] The first stacked structure 100 may include alternately stacked first insulating layers 110 and first gate layers 131-138. A second stacked structure 700 may be located on the first stacked structure 100. The second stacked structure 700 may include alternately stacked second insulating layers 710 and second gate layers 731-738. It should be understood that the number and thickness of the first insulating layers 110, first gate layers 131-138, second insulating layers 710, and second gate layers 731-738 are not limited to... Figure 35 and 36 The quantities and thicknesses shown can be varied by those skilled in the art without departing from the concept of this application. Any number and thickness of the first insulating layer 110, first gate layers 131-138, second insulating layer 710, and second gate layers 731-738 can be provided as needed. Furthermore, the materials of the first insulating layer 110, first gate layers 131-138, second insulating layer 710, and second gate layers 731-738 can be suitable materials known in the art. For example, the first insulating layer 110 and second insulating layer 710 can be oxide layers (such as silicon oxide), and the first gate layers 131-138 and second gate layers 731-738 can be metallic layers (such as tungsten metal).

[0076] Multiple first contact structures 1-8 can penetrate the second stacked structure 700 and extend to multiple first gate layers 131-138 located at different heights. Multiple second contact structures 11-18 can be located in the second stacked structure 700 and can extend to multiple second gate layers 731-738 located at different heights. The first contact structures 1-8 and the second contact structures 11-18 can be electrically connected to the first gate layers 131-138 and 731-738 located at different heights, respectively.

[0077] In an exemplary embodiment of this application, such as Figure 36 As shown, the first contact structures 1-8 may include a first filling material 1120, a first conductive layer 1110, and a first dielectric layer 1100. The first conductive layer 1110 may be located outside the first filling material 1120 and extend to the first gate layers 131-138. The first dielectric layer 1100 may be located on the sidewall of the first conductive layer 1110.

[0078] In an exemplary embodiment of this application, such as Figure 35As shown, the second contact structures 11-18 may include a second filler material 1220, a second conductive layer 1210, and a second dielectric layer 1200. The second conductive layer 1210 may be located outside the second filler material 1220 and extend to the second gate layers 731-738. The second dielectric layer 1200 may be located on the sidewall of the second conductive layer 1210.

[0079] For example, the first filler material 1120 and the second filler material 1220 may include oxides; the first conductive layer 1110 and the second conductive layer 1210 may be made of metal; and the first dielectric layer 1100 and the second dielectric layer 1200 may be made of oxides.

[0080] In an exemplary embodiment of this application, Figure 35 and 36 As shown, the three-dimensional memory may also include a substrate 200. A first stacked structure 100 may be located on one side of the substrate 200. The substrate 200 may be, for example, a polycrystalline silicon substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 200 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 200 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0081] In an exemplary embodiment of this application, Figure 35 and 36 As shown, the three-dimensional memory may also include a virtual channel structure 2000. The virtual channel structure 2000 may penetrate the second stacked structure 700 and the first stacked structure 100 and extend to the substrate 200. The virtual channel structure 2000 may serve a supporting function.

[0082] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated here.

[0083] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0084] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Alternately stacking the first insulating layer and the first sacrificial layer to form a first laminated structure; In the first stacked structure, a plurality of first sub-contact holes are formed that extend to the first sacrificial layer at different heights; A second insulating layer and a second sacrificial layer are alternately stacked on the first stacked structure to form a second stacked structure; A plurality of first extended contact holes are formed that penetrate the second stacked structure and are connected to the first sub-contact holes, and a plurality of second contact holes are formed in the second stacked structure that extend to the second sacrificial layer at different heights; as well as The first sub-contact hole and the first extended contact hole are filled to form a first contact structure, and the second contact hole is filled to form a second contact structure. The formation of the plurality of first sub-contact holes includes: forming a patterned first hard mask on the top surface of the first stacked structure; and successively masking portions of the patterned first hard mask, and successively etching the first stacked structure using the unmasked portions of the patterned first hard mask as a mask to form the plurality of first sub-contact holes; and Forming the plurality of second contact holes includes: forming a patterned second hard mask on the top surface of the second stacked structure; and successively masking portions of the patterned second hard mask, and successively etching the second stacked structure with the unmasked portions of the patterned second hard mask as a mask to form the plurality of second contact holes.

2. The preparation method according to claim 1, characterized in that, The patterned first hard mask is sequentially masked, and the first stacked structure is sequentially etched using the unmasked portions of the patterned first hard mask as a mask to form the plurality of first sub-contact holes, including: Using the patterned first hard mask as a mask, the first insulating layer on top of the first stacked structure is etched to form a plurality of first insulating layer openings; and The patterned first hard mask is successively masked, and the first stacked structure is etched through a plurality of first insulating layer openings using the unmasked portions of the patterned first hard mask as a mask to form the plurality of first sub-contact holes.

3. The preparation method according to claim 2, characterized in that, Forming a patterned first hard mask on the top surface of the first stacked structure includes: A first hard mask is formed on the top surface of the first stacked structure; and A plurality of first insulating layer opening patterns are formed in the first hard mask to form the patterned first hard mask.

4. The preparation method according to claim 1, characterized in that, Alternatingly stacking a second insulating layer and a second sacrificial layer on the first laminated structure to form a second laminated structure includes: Fill the plurality of first sub-contact holes with dielectric material; and A second insulating layer and a second sacrificial layer are alternately stacked on one side of the first stacked structure where a plurality of first sub-contact holes are formed.

5. The preparation method according to claim 1, characterized in that, The patterned second hard mask is sequentially masked, and the unmasked portions of the patterned second hard mask are used as masks to sequentially etch the second stacked structure to form the plurality of second contact holes, including: Using the patterned second hard mask as a mask, the second insulating layer at the top of the second stacked structure is etched to form a plurality of second insulating layer openings; and The patterned second hard mask is successively masked, and the unmasked portions of the patterned second hard mask are used as masks to etch the second stacked structure through multiple openings in the second insulating layer to form the multiple second contact holes. The plurality of first extended contact holes are formed during the process of forming the plurality of second contact holes.

6. The preparation method according to claim 5, characterized in that, Forming a patterned second hard mask on the top surface of the second stacked structure includes: A second hard mask is formed on the top surface of the second stacked structure; and A plurality of first extended contact hole patterns and a plurality of second insulating layer opening patterns are formed in the second hard mask to form the patterned second hard mask.

7. The preparation method according to claim 4, characterized in that, Filling the first sub-contact hole and the first extended contact hole to form the first contact structure includes: The dielectric material is removed via the first extended contact hole; A first dielectric layer is formed on the inner walls of the first sub-contact hole and the first extended contact hole; A first conductive layer extending to the first sacrificial layer is formed inside the first dielectric layer; and The space formed by the first conductive layer is filled with a first filler material.

8. The preparation method according to claim 4, characterized in that, Filling the second contact hole to form the second contact structure includes: A second dielectric layer is formed on the inner wall of the second contact hole; A second conductive layer extending to the second sacrificial layer is formed inside the second dielectric layer; and The space formed by the second conductive layer is filled with a second filler material.

9. The preparation method according to claim 7, characterized in that, Forming a first dielectric layer on the inner walls of the first sub-contact hole and the first extended contact hole includes: A first dielectric layer is formed on the inner wall of the first sub-contact hole and the first extended contact hole, and on the bottom surface of the first sub-contact hole; and Remove the first dielectric layer from the bottom surface of the first sub-contact hole.

10. The preparation method according to claim 8, characterized in that, Forming a second dielectric layer on the inner wall of the second contact hole includes: A second dielectric layer is formed on the inner wall and bottom surface of the second contact hole; and Remove the second dielectric layer from the bottom surface of the second contact hole.

11. The preparation method according to claim 1, characterized in that, The method further includes: A virtual channel structure is formed that runs through the first stacked structure and the second stacked structure.

12. The preparation method according to claim 11, characterized in that, The method further includes: The first sacrificial layer and the second sacrificial layer are replaced with the first gate layer and the second gate layer, respectively.

13. The preparation method according to any one of claims 1-12, characterized in that, The materials of the first insulating layer and the second insulating layer include oxides; and The materials of the first sacrificial layer and the second sacrificial layer include nitrides.

14. The preparation method according to claim 12, characterized in that, The materials of the first gate layer and the second gate layer include metal.

15. A three-dimensional memory, characterized in that, include: The first stacked structure includes an alternately stacked first insulating layer and a first gate layer; The second stacked structure is located on the first stacked structure and includes an alternately stacked second insulating layer and a second gate layer. Multiple first contact structures penetrate the second stacked structure and extend to multiple first gate layers located at different heights; as well as Multiple second contact structures are located in the second stacked structure and extend to multiple second gate layers at different heights. Wherein, at least one sidewall of the first contact structure extending along the stacking direction of the first stacked structure contacts the first insulating layer and the first gate layer, and at least one sidewall of the second contact structure extending along the stacking direction of the second stacked structure contacts the second insulating layer and the second gate layer.

16. The three-dimensional memory according to claim 15, characterized in that, The first contact structure includes: First filler material; A first conductive layer is located outside the first filling material and extends to the first gate layer; and The first dielectric layer is located on the sidewall of the first conductive layer.

17. The three-dimensional memory according to claim 16, characterized in that, The second contact structure includes: Second filler material; A second conductive layer is located outside the second filling material and extends to the second gate layer; and The second dielectric layer is located on the sidewall of the second conductive layer.

18. The three-dimensional memory according to claim 17, characterized in that, The first filler material and the second filler material both comprise oxides; The materials of the first conductive layer and the second conductive layer include metal; and The materials of the first dielectric layer and the second dielectric layer include oxides.

19. The three-dimensional memory according to claim 15, characterized in that, The materials of the first insulating layer and the second insulating layer include oxides; and The materials of the first gate layer and the second gate layer include metal.

20. The three-dimensional memory according to any one of claims 15-19, characterized in that, The three-dimensional memory also includes: The substrate, wherein the first stacked structure is located on one side of the substrate.

21. The three-dimensional memory according to claim 20, characterized in that, The three-dimensional memory also includes: A virtual channel structure extends through the second stacked structure and the first stacked structure and extends to the substrate.

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