Three-dimensional memory and methods of making the same, memory systems, electronic devices

Abstract

The application provides a three-dimensional memory, a preparation method thereof, a storage system and an electronic device. The preparation method of the three-dimensional memory comprises the following steps: alternately stacking a barrier layer and a stop layer to form a composite structure, wherein the stop layer comprises a first stop layer; alternately stacking an insulating layer and a sacrificial layer on the composite structure to form a laminated structure; forming a first channel hole extending along a layer stacking direction of the laminated structure and a second channel hole extending through the laminated structure and extending to the first stop layer; and etching the first channel hole so that the first channel hole extends to the first stop layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and its fabrication methods, memory systems, and electronic devices. Background Technology

[0002] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges, such as physical limits and limits on the density of stored electrons. Against this backdrop, three-dimensional memory, which extends vertically, has emerged to address the difficulties encountered by planar flash memory. However, limitations in actual fabrication processes have brought significant challenges to the formation of channel structures with different radial dimensions in three-dimensional memory. Summary of the Invention

[0003] This application provides a method for fabricating a three-dimensional memory, the method comprising: alternately stacking a barrier layer and a stop layer to form a composite structure, wherein the stop layer includes a first stop layer; alternately stacking an insulating layer and a sacrificial layer on the composite structure to form a stacked structure; forming a first channel hole extending along the stacking direction of the stacked structure and a second channel hole penetrating the stacked structure and extending to the first stop layer; and etching the first channel hole to extend the first channel hole to the first stop layer.

[0004] In one embodiment, the aperture of the first channel hole is in the range of 95 to 120 angstroms; and the aperture of the second channel hole is in the range of 150 to 200 angstroms.

[0005] In one embodiment, etching the first channel hole to extend the first channel hole to the first stop layer includes: covering the second channel hole and etching the first channel hole to extend the first channel hole to the first stop layer.

[0006] In one embodiment, the first stop layer is the stop layer furthest from the stacked structure.

[0007] In one embodiment, the barrier layer is made of oxide; and the stop layer is made of polycrystalline silicon.

[0008] In one embodiment, the insulating layer is made of an oxide; and the sacrificial layer is made of a nitride.

[0009] In one embodiment, the method further includes filling the first channel hole and the second channel hole to form a first channel structure and a second channel structure, respectively.

[0010] In one embodiment, the method further includes: forming a gate line gap, through which the sacrificial layer is replaced with a gate layer.

[0011] In one embodiment, the gate layer is made of tungsten metal.

[0012] This application also provides a three-dimensional memory, comprising: a composite structure including alternatingly stacked barrier layers and stop layers, wherein the stop layers include a first stop layer; a stacked structure located on the composite structure and including alternatingly stacked insulating layers and gate layers; a first channel structure extending through the stacked structure and to the first stop layer; and a second channel structure extending through the stacked structure and to the first stop layer, wherein the radial dimension of the second channel structure is greater than the radial dimension of the first channel structure.

[0013] In one embodiment, the radial dimension of the first channel structure is in the range of 95 to 120 angstroms; and the radial dimension of the second channel structure is in the range of 150 to 200 angstroms.

[0014] In one embodiment, the first stop layer is the stop layer furthest from the stacked structure.

[0015] This application also provides a storage system. The storage system includes a controller and the aforementioned three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory.

[0016] Another aspect of this application provides an electronic device, including the aforementioned storage system.

[0017] In one embodiment, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted device, wearable device, and power bank.

[0018] The three-dimensional memory and its fabrication method provided according to one or more embodiments of this application may have at least one of the following advantages:

[0019] 1) The composite structure formed by alternating stacked barrier layers and stop layers facilitates the subsequent formation of the first and second channel holes, stopping at the stop layer; and

[0020] 2) The successive formation of a second channel hole that penetrates the stacked structure and extends to the first stop layer and a first channel hole that penetrates the stacked structure and extends to the first stop layer is beneficial to achieve that channel holes of different diameters can have approximately the same channel depth. Attached Figure Description

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0022] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application; and

[0023] Figures 2 to 6 This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0024] Figure 7 This is a schematic diagram of the structure of a storage system according to one embodiment of this application; and

[0025] Figure 8 This is a schematic diagram of the structure of an electronic device according to one embodiment of this application. Detailed Implementation

[0026] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0027] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first channel hole discussed herein may also be referred to as the second channel hole, and vice versa.

[0028] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0029] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0030] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0031] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0032] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0033] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application.

[0034] like Figure 1 As shown, the fabrication method 1000 of the three-dimensional memory provided in this application may include: S1, alternately stacking a barrier layer and a stop layer to form a composite structure, wherein the stop layer includes a first stop layer; S2, alternately stacking an insulating layer and a sacrificial layer on the composite structure to form a stacked structure; S3, forming a first channel hole extending along the stacking direction of the stacked structure and a second channel hole penetrating the stacked structure and extending to the first stop layer; and S4, etching the first channel hole to extend the first channel hole to the first stop layer. Steps S1 to S4 will be described in detail below.

[0035] like Figure 2As shown, barrier layer 110 and stop layer 120 can be alternately stacked to form composite structure 100. Exemplarily, barrier layer 110 may include a first barrier layer 111 and a second barrier layer 112. Stop layer 120 may include a first stop layer 121 and a second stop layer 122. Exemplarily, the first barrier layer 111, the first stop layer 121, the second barrier layer 112, and the second stop layer 122 can be alternately stacked on one side of substrate 200 to form composite structure 100. Exemplarily, barrier layer 110 and stop layer 120 may be two dielectric layers with different materials. The materials of barrier layer 110 and stop layer 120 may have different etch selectivity ratios to facilitate sequential removal of barrier layer 110 and stop layer 120 in subsequent processes. Exemplarily, the material of barrier layer 110 may include oxide (such as silicon oxide), and the material of stop layer 120 may include polysilicon. In other words, the materials of the first barrier layer 111 and the second barrier layer 112 may include silicon oxide, and the materials of the first stop layer 121 and the second stop layer 122 may include polycrystalline silicon.

[0036] In an exemplary embodiment of this application, the substrate 200 may be, for example, a silicon substrate. Exemplarily, a first barrier layer 111 may be grown by oxidation on the silicon substrate 200. The first barrier layer 111 can effectively reduce the stress on the substrate 200 caused by the first stop layer 121 formed in subsequent processes. Exemplarily, the first stop layer 121 may be formed on the first barrier layer 111 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first stop layer 121 has a higher etch selectivity than the first barrier layer 111 and can serve as an etch stop layer for the first barrier layer 111.

[0037] It should be understood that the number and thickness of the barrier layer 110 and the stop layer 120 are not limited to... Figure 2 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to set any number and thickness of barrier layers 110 and stop layers 120 as needed.

[0038] like Figure 2 As shown, insulating layers 310 and sacrificial layers 320 can be alternately stacked on composite structure 100 to form a stacked structure 300. Exemplarily, forming the stacked structure 300 on composite structure 100 can be achieved through one or more deposition processes. Deposition processes for forming the stacked structure 300 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of insulating layers 310 and sacrificial layers 320 are not limited to... Figure 2The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to create any number and thickness of insulating layers 310 and sacrificial layers 320 as needed. Furthermore, the materials of insulating layers 310 and sacrificial layers 320 may be suitable materials known in the art. Exemplarily, insulating layers 310 and sacrificial layers 320 may be two dielectric layers with different materials. The materials of insulating layers 310 and sacrificial layers 320 may have different etch selectivity ratios to facilitate removal of sacrificial layer 320 in subsequent processes. Exemplarily, the material of sacrificial layer 320 may include nitrides, and the material of insulating layer 310 may include oxides. For example, insulating layer 310 may be such as silicon oxide, and sacrificial layer 320 may be such as silicon nitride.

[0039] like Figure 3 As shown, a first channel hole 400 extending along the stacking direction Z of the laminated structure 300 and a second channel hole 500 penetrating the laminated structure 300 and extending to the first stop layer 121 can be formed. Exemplarily, the aperture of the first channel hole 400 can be in the range of 95 to 120 angstroms, and the aperture of the second channel hole 500 can be in the range of 150 to 200 angstroms. Figure 3 As shown, the first stop layer 121 can be the stop layer 120 furthest from the stack structure 300.

[0040] In an exemplary embodiment of this application, a first channel hole 400 and a second channel hole 500 can be formed by an etching process. Exemplarily, a patternable etching mask layer (not shown) can be used to mask the etching stack structure 300. Since the apertures of the first channel hole 400 and the second channel hole 500 are different, for example, the aperture of the first channel hole 400 is smaller than the aperture of the second channel hole 500, in the actual etching process, the etching depth of the smaller-diameter first channel hole 400 can be less than the etching depth of the larger-diameter second channel hole 500. That is, the first channel hole 400 can extend into the stack structure 300, and the second channel hole 500 can penetrate the stack structure 300 and extend to the first stop layer 121. It should be understood that in the actual etching process, the larger the aperture of the channel hole, the greater the etching rate of the underlying stack layer, resulting in a greater etching depth for the larger-diameter channel hole. In other words, in the actual etching process, the etching depth of the channel hole increases with the increase of the aperture diameter. Multiple first channel holes 400 may have different etching depths due to different hole diameters.

[0041] In an exemplary embodiment of this application, the first channel hole 400 may be etched to extend the first channel hole 400 to the first stop layer 121. Exemplarily, as... Figure 5 As shown, the first channel hole 400 can be etched again using an etching process to extend the first channel hole 400 to the first stop layer 121. Specifically, firstly, the second channel hole 500 can be covered by a mask 600. Figure 4Then, the first channel hole 400 can be etched to extend the first channel hole 400 to the first stop layer 121. Figure 5 For example, mask 600 may include photoresist or carbon-based polymer material, and may be formed using a patterning process such as photolithography.

[0042] For example, after forming the first channel hole 400 that extends through the stacked structure 300 and into the first stop layer 121, the mask 600 can be removed by techniques such as dry etching using plasmas such as O2 or CF4 or wet etching using resist / polymer photoresist removers (e.g., solvent-based chemical agents).

[0043] In an exemplary embodiment of this application, the first channel hole 400 and the second channel hole 500 may be filled to form the first channel structure 410 and the second channel structure 510, respectively. Figure 6 The radial dimension of the first channel structure 410 is in the range of 95 to 120 angstroms, and the radial dimension of the second channel structure 510 is in the range of 150 to 200 angstroms. Exemplarily, the first channel structure 410 can be used as a storage cell. The second channel structure 510 may have the same structure as the first channel structure 410, and the second channel structure 510 can be used to balance the overall stress of the three-dimensional memory and reduce stress concentration. Furthermore, the second channel structure 510 may also have a supporting function to prevent partial collapse of the three-dimensional memory.

[0044] Specifically, a first channel structure 410 and a second channel structure 510, comprising a functional layer (not shown) and a channel layer (not shown), can be sequentially formed in the first channel hole 400 and the second channel hole 500. The functional layer includes a barrier layer (not shown), a charge trapping layer (not shown), and a tunneling layer (not shown) sequentially disposed in the channel hole. Exemplarily, the barrier layer, the charge trapping layer, and the tunneling layer can be sequentially formed on the inner walls of the first channel hole 400 and the second channel hole 500, and the channel layer can be formed on the surface of the tunneling layer. The functional layer and the channel layer can be formed in the first channel hole 400 and the second channel hole 500 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0045] Specifically, the functional layer may include a barrier layer that blocks charge outflow, a charge trapping layer formed on the surface of the barrier layer to store charge during operation of the three-dimensional memory, and a tunneling layer formed on the surface of the charge trapping layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or another wide-bandgap material. The charge trapping layer may include one or more layers, which may include one or more materials. Materials for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, or another wide-bandgap material. The tunneling layer may include one or more layers, which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or another wide-bandgap material. In some embodiments, the functional layer may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer may have a structure different from the ONO configuration. For example, the functional layer may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0046] The channel layer can be used to transport the required charge (electrons or holes). According to an exemplary embodiment of this application, the channel layer can be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer includes, but is not limited to, p-type doped polycrystalline silicon.

[0047] In an exemplary embodiment of this application, such as Figure 6 As shown, a gate line gap 700 can be formed through the stacked structure 300 and extending to the first stop layer 121. Exemplarily, the gate line gap 700 can be formed through photolithography and etching processes. Exemplarily, the sacrificial layer 320 is replaced with the gate layer 330 through the gate line gap 700. Specifically, firstly, the sacrificial layer 320 can be removed via the gate line gap 700; then, a conductive material can be filled into the removed space to form the gate layer 330. For example, tungsten metal can be filled into the removed space to form the gate layer 330. Exemplarily, during the replacement of the sacrificial layer 320 with the gate layer 330, the gate line gap 700 can serve as a pathway for providing etchant and chemical precursors, and all of the sacrificial layer 320 in the stacked structure 300 can be removed using processes such as wet etching.

[0048] This application also provides a three-dimensional memory. Figure 6A schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application is shown.

[0049] like Figure 6 As shown, the three-dimensional memory may include a composite structure 100, a stacked structure (including alternating stacked insulating layers 310 and gate layers 330), a first channel structure 410, and a second channel structure 510.

[0050] In an exemplary embodiment of this application, the composite structure 100 may include alternately stacked barrier layers 110 and stop layers 120. Exemplarily, barrier layer 110 may include a first barrier layer 111 and a second barrier layer 112. Stop layer 120 may include a first stop layer 121 and a second stop layer 122. Exemplarily, the three-dimensional memory may also include a substrate 200. The first barrier layer 111, the first stop layer 121, the second barrier layer 112, and the second stop layer 122 may be sequentially located on one side of the substrate 200. Exemplarily, the substrate 200 may be, for example, a silicon substrate, and barrier layer 110 and stop layer 120 may be two dielectric layers with different materials. The materials of barrier layer 110 and stop layer 120 may have different etch selectivity ratios to facilitate sequential removal of barrier layer 110 and stop layer 120 in subsequent processes. Exemplarily, the material of barrier layer 110 may include oxide (such as silicon oxide), and the material of stop layer 120 may include polysilicon. In other words, the materials of the first barrier layer 111 and the second barrier layer 112 may include silicon oxide, and the materials of the first stop layer 121 and the second stop layer 122 may include polycrystalline silicon.

[0051] In an exemplary embodiment of this application, the first stop layer 121 may be the stop layer 120 furthest from the stacked structure 300. The first barrier layer 111 can effectively reduce the stress on the substrate 200 caused by the first stop layer 121 formed in subsequent processes. Exemplarily, the first stop layer 121 can be formed on the first barrier layer 111 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first stop layer 121 has a higher etch selectivity than the first barrier layer 111 and can serve as an etch stop layer for the first barrier layer 111. It should be understood that the number and thickness of the barrier layer 110 and the stop layer 120 are not limited to those specified in the original text. Figure 2 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to set any number and thickness of barrier layers 110 and stop layers 120 as needed.

[0052] In an exemplary embodiment of this application, the stacked structure may be located on the composite structure 100. The number and thickness of the insulating layer 310 and the gate layer 330 are not limited to... Figure 6The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to create any number and thickness of insulating layers 310 and gate layers 330 as needed. Furthermore, the materials of insulating layers 310 and gate layers 330 may be selected from suitable materials known in the art. Exemplarily, the material of gate layer 330 may include a conductive material, and the material of insulating layer 310 may include an oxide. For example, insulating layer 310 may be such as silicon oxide, and gate layer 330 may be such as tungsten metal.

[0053] In an exemplary embodiment of this application, the first channel structure 410 can penetrate the stacked structure and extend to the first stop layer 121. The second channel structure 510 can penetrate the stacked structure and extend to the first stop layer 121. Exemplarily, the radial dimension of the second channel structure 510 can be larger than the radial dimension of the first channel structure 410. Exemplarily, the radial dimension of the first channel structure 410 is in the range of 95 to 120 angstroms, and the radial dimension of the second channel structure 510 is in the range of 150 to 200 angstroms. Exemplarily, the first channel structure 410 can be used as a storage cell. The second channel structure 510 can have the same structure as the first channel structure 410, and the second channel structure 510 can be used to balance the overall stress of the three-dimensional memory and reduce stress concentration. In addition, the second channel structure 510 can also have a supporting function to prevent partial collapse of the three-dimensional memory.

[0054] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated here.

[0055] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0056] Figure 7 This is a schematic diagram of the structure of a storage system 2000 according to one embodiment of this application.

[0057] like Figure 7 As shown, at least one embodiment of this application also provides a storage system 2000. The storage system 2000 may include a memory 2100 and a controller 2200. The memory 2100 may be the same as the memory described in any of the embodiments above, and will not be described again in this application. The storage system 2000 may be a two-dimensional storage system or a three-dimensional storage system; the following description uses a three-dimensional storage system as an example.

[0058] The three-dimensional storage system 2000 may include a three-dimensional memory 2100, a controller 2200, and a host 2300. The three-dimensional memory 2100 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be repeated here. The controller 2200 controls the three-dimensional memory 2100 via channel CH, and the three-dimensional memory 2100 can perform operations based on the control of the controller 2200 in response to requests from the host 2300. The three-dimensional memory 2100 receives commands CMD and addresses ADDR from the controller 2300 via channel CH and accesses a region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 2100 can perform internal operations corresponding to commands on the region selected by the address.

[0059] In some implementations, the three-dimensional storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC and Micro MMC, a Secure Digital Card in the form of SD, Mini SD and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card or Memory Stick, etc.

[0060] Figure 8 This is a schematic diagram of the structure of the electronic device 3000 provided in the embodiments of this application.

[0061] like Figure 8 As shown, at least one embodiment of this application also provides an electronic device 3000. The electronic device 3000 includes a memory 3100. The memory 3100 may be the same as the memory described in any of the embodiments above, and will not be repeated here. The electronic device 3000 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, power bank, or other device with storage capabilities. Therefore, other modules of the electronic device 3000, such as a controller, can be determined according to the specific device type of the electronic device 3000. Other modules can control the three-dimensional memory 3100 through channels, and the three-dimensional memory 3100 can receive commands CMD and addresses ADDR from other modules through channels, and access the region selected from the memory cell array in response to the address. This application does not limit this.

[0062] This application provides peripheral circuits, memory, storage systems, and electronic devices. Due to the metal interconnect structure provided in this application, they have the same beneficial effects as the metal interconnect structure described above, which will not be elaborated here.

[0063] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Alternatingly stacked barrier layers and stop layers to form a composite structure, wherein the stop layer includes a first stop layer; An insulating layer and a sacrificial layer are alternately stacked on the composite structure to form a laminated structure; A first channel hole extending along the stacking direction of the stacked structure and a second channel hole penetrating the stacked structure and extending to the first stop layer are formed; as well as The first channel hole is etched to extend the first channel hole to the first stop layer. The diameter of the first channel hole is smaller than the diameter of the second channel hole.

2. The preparation method according to claim 1, characterized in that, The aperture of the first channel hole is in the range of 95 to 120 angstroms; and The diameter of the second channel hole is in the range of 150 to 200 angstroms.

3. The preparation method according to claim 2, characterized in that, Etching the first channel hole to extend the first channel hole to the first stop layer includes: The second channel hole is covered, and the first channel hole is etched to extend the first channel hole to the first stop layer.

4. The preparation method according to claim 1, characterized in that, The first stop layer is the stop layer furthest from the stacked structure.

5. The preparation method according to any one of claims 1-4, characterized in that, The barrier layer is made of an oxide material; and The material of the stop layer includes polycrystalline silicon.

6. The preparation method according to any one of claims 1-4, characterized in that, The insulating layer is made of an oxide material; and The material of the sacrificial layer includes nitrides.

7. The preparation method according to any one of claims 1-4, characterized in that, The method further includes: The first channel hole and the second channel hole are filled to form a first channel structure and a second channel structure, respectively.

8. The preparation method according to claim 7, characterized in that, The method further includes: A gate line gap is formed, through which the sacrificial layer is replaced with a gate layer.

9. The preparation method according to claim 8, characterized in that, The gate layer is made of tungsten metal.

10. A three-dimensional memory, characterized in that, include: A composite structure comprising alternating stacked barrier layers and stop layers, wherein the stop layers include a first stop layer; A stacked structure is located on the composite structure and includes alternating stacked insulating layers and gate layers; A first channel structure penetrates the stacked structure and extends to the first stop layer; as well as A second channel structure extends through the stacked structure and to the first stop layer, wherein the radial dimension of the second channel structure is greater than the radial dimension of the first channel structure.

11. The three-dimensional memory according to claim 10, characterized in that, The radial dimension of the first channel structure is in the range of 95 to 120 angstroms; and The radial dimension of the second channel structure is in the range of 150 to 200 angstroms.

12. The three-dimensional memory according to claim 10, characterized in that, The first stop layer is the stop layer furthest from the stacked structure.

13. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory according to any one of claims 10-12, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

14. An electronic device, characterized in that, include: The storage system of claim 13.

15. The electronic device according to claim 14, characterized in that, The electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

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