Semiconductor device and method of manufacturing semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device includes a stack including first conductive layers and insulating layers alternately stacked; second conductive layers provided on the stack; a separation insulating structure provided on the stack and configured to insulate the respective second conductive layers from each other; first trench layers passing through the stack; memory layers surrounding sidewalls of the first trench layers; second trench layers provided on the stack and passing through the second conductive layers, a width of each of the second trench layers being smaller than a width of the first trench layers; gate insulating layers surrounding sidewalls of the second trench layers; and third trench layers configured to couple the respective first trench layers and the respective second trench layers and extend into the second trench layers, respectively.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to electronic devices, and more particularly to semiconductor devices and methods of manufacturing such semiconductor devices. Background Technology

[0002] Recently, due to limitations in improving the integration of two-dimensional memory elements comprising memory cells formed as a single layer on a substrate, three-dimensional (3D) memory elements comprising memory cells stacked vertically on a substrate have been proposed. Various structures and manufacturing methods have been developed to improve the operational reliability of such memory elements with a three-dimensional structure. Summary of the Invention

[0003] Embodiments of this disclosure may provide a semiconductor device that may include: a stack including alternating stacked first conductive layers and insulating layers; a second conductive layer disposed on the stack; a separation insulating structure disposed on the stack and configured to insulate each of the second conductive layers from each other; a first channel layer through the stack; a memory layer surrounding the sidewalls of the first channel layer; a second channel layer disposed on the stack and through the second conductive layers, each of the second channel layers having a width smaller than the width of the first channel layer; a gate insulating layer surrounding the sidewalls of the second channel layer; and a third channel layer configured to respectively connect each of the first channel layers to each of the second channel layers and extend into the second channel layers.

[0004] Embodiments of this disclosure may provide a semiconductor device that may include: a stack including alternately stacked word lines and insulating layers; a first channel layer through the stack; a memory layer surrounding the sidewalls of the first channel layer; a second channel layer disposed on the stack; a gate insulating layer surrounding the sidewalls of the second channel layer; a third channel layer configured to respectively connect each of the first channel layers to each of the second channel layers; select lines, each select line including a first portion disposed on the stack and a second portion respectively surrounding each of the second channel layers and protruding into the stack toward the first channel layer; and a separation insulating structure disposed on the stack and configured to insulate each of the select lines from each other.

[0005] Embodiments of this disclosure may provide a method for manufacturing a semiconductor device, which may include the following steps: forming a stack comprising alternating stacked first and second material layers; forming a sacrificial layer on the stack; forming a separation insulating structure passing through the sacrificial layer and disposed on the first material layer; forming a first opening passing through the sacrificial layer, the separation insulating structure, and the stack; forming a first channel layer in the first opening; forming a sacrificial spacer connected to the sacrificial layer in the first opening; forming a second channel layer in the sacrificial spacer with a width smaller than the width of the first channel layer; and forming a third channel layer in the first opening, the third channel layer being configured to connect the first channel layer to the second channel layer and extend into the second channel layer. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2A , Figure 2B and Figure 2C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B This is a diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0009] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 16G , Figure 16H and Figure 16IThis is a view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 17 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0011] Figure 18 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 19 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 20 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0014] Figure 21 This is a diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0015] The specific structural or functional descriptions of the embodiments of this disclosure incorporated in this specification or application are for the purpose of describing embodiments of this disclosure only. These descriptions should not be construed as limiting the scope of the embodiments described in the specification or application.

[0016] Various embodiments of this disclosure relate to semiconductor devices having stable structures and improved properties, as well as methods of manufacturing such semiconductor devices.

[0017] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0018] Reference Figure 1 The semiconductor device may include a stack (ST), a second conductive layer 13, a separation insulating structure 24, and a channel structure (CH). The semiconductor device may also include a source structure 10, an insulating layer 14, a protective layer 21, or a slot structure (SLS), or a combination thereof.

[0019] The stacked ST includes first conductive layers 11 and insulating layers 12 alternately stacked on top of each other. Each first conductive layer 11 may be a word line or a select line. In one embodiment, at least one bottommost first conductive layer 11 may be a source select line, and the other first conductive layers 11 may each be a word line. The first conductive layers 11 may include conductive materials such as polysilicon, tungsten, molybdenum, or metal. Insulating layers 12 may be provided to insulate the stacked first conductive layers 11 from each other, and the insulating layers 12 may include insulating materials such as oxides, nitrides, or air gaps. In one embodiment, the bottommost first conductive layer 11 may be located closest to the source structure 10 than the other first conductive layers 11.

[0020] The second conductive layer 13 may be disposed on the stack ST. Each second conductive layer 13 may be a word line or a select line. In one embodiment, each second conductive layer 13 may be a drain select line. The second conductive layer 13 may comprise a conductive material such as polysilicon, tungsten, molybdenum, or a metal.

[0021] An insulating layer 14 may be disposed on the second conductive layer 13. In a plan view, the insulating layer 14 may have a shape corresponding to the shape of the second conductive layer 13. The insulating layer 14 may include an insulating material such as an oxide, a nitride, or an air gap.

[0022] A separation insulation structure 24 may be disposed on the stack ST. The separation insulation structure 24 may insulate the second conductive layers 13 disposed adjacent to each other along the first direction I. The separation insulation structure 24 may extend through the insulating layer 14 and between the second conductive layers 13. The separation insulation structure 24 may extend into the uppermost insulating layer 12 of the stack ST. The separation insulation structure 24 may be disposed at a location spaced apart from the uppermost first conductive layer 11. The separation insulation structure 24 may include an insulating material such as an oxide, nitride, or air gap. In one embodiment, the uppermost first conductive layer 11 may be located closest to the second conductive layer 13 than the other first conductive layers 11.

[0023] The channel structure CH can pass through the stack ST and the second conductive layer 13. The channel structure CH can extend in a third direction III. The third direction III can intersect with the first direction I. In one embodiment, the third direction III can be the direction in which the first conductive layer 11 and the insulating layer 12 are stacked. The channel structure CH can protrude compared to the upper surface of the second conductive layer 13. The channel structure CH can pass through the insulating layer 14.

[0024] Each channel structure CH may include a first channel structure CH1, a second channel structure CH2, and a third channel structure CH3. Each channel structure CH may also include a contact pad CP. The first channel structure CH1 may pass through the stack ST, and the second channel structure CH2 may pass through the second conductive layer 13. The third channel structure CH3 can connect the corresponding first channel structure CH1 and the corresponding second channel structure CH2.

[0025] The first channel structure CH1 may include a first channel layer 15. The first channel structure CH1 may also include a memory layer 16 or a first insulating core 17, or a combination thereof. The first channel layer 15 may include a semiconductor material, such as silicon (Si), germanium (Ge), or a nanostructure material. The memory layer 16 may be interposed between the first channel layer 15 and the first conductive layer 11. The memory layer 16 may be formed as a sidewall surrounding the first channel layer 15. The first insulating core 17 may be formed in the first channel layer 15. The first insulating core 17 may include an insulating material such as an oxide, nitride, or air gap.

[0026] The second channel structure CH2 may include a second channel layer 25. The second channel structure CH2 may also include a gate insulating layer 26 or a second insulating core 27, or a combination thereof. The second channel layer 25 may include a semiconductor material, such as silicon (Si), germanium (Ge), or a nanostructure material. The gate insulating layer 26 may be interposed between the second channel layer 25 and the second conductive layer 13. The gate insulating layer 26 may be formed as a sidewall surrounding the second channel layer 25. The gate insulating layer 26 may include an insulating material such as an oxide, nitride, or air gap. The second insulating core 27 may be formed in the second channel layer 25. The second insulating core 27 may include an insulating material such as an oxide, nitride, or air gap.

[0027] Contact pads CP can be disposed on the second channel structure CH2. Contact pads CP can be connected to the second channel layer 25. In one embodiment, contact pads CP can be configured to connect the channel structure CH to a bit line. Contact pads CP can include a conductive material, such as polysilicon, tungsten, molybdenum, or metal.

[0028] The source structure 10 may be a single layer or include multiple layers. In one embodiment, the source structure 10 may include a first source layer 10A, a second source layer 10C, and a third source layer 10B. The third source layer 10B may be interposed between the first source layer 10A and the second source layer 10C. The third source layer 10B may pass through the memory layer 16 and be connected to the first channel layer 15. The first source layer 10A, the second source layer 10C, and the third source layer 10B may include conductive materials, such as polysilicon, tungsten, molybdenum, or metal.

[0029] The slit structure SLS can pass through the insulating layer 14, the second conductive layer 13, and the stacked ST. The slit structure SLS may include a source contact structure 23 and an insulating spacer 22. The source contact structure 23 may be electrically connected to the source structure 10. The source contact structure 23 may include a single layer or multiple layers. The source contact structure 23 may include a conductive material, such as polysilicon, tungsten, molybdenum, or metal. The insulating spacer 22 may be inserted between the source contact structure 23 and the second conductive layer 13. In one embodiment, the insulating spacer 22 may be formed as a sidewall surrounding the source contact structure 23. The insulating spacer 22 may include an insulating material such as an oxide, nitride, or air gap.

[0030] The protective layer 21 can be configured to protect the second conductive layer 13 and cover the sidewalls of the second conductive layer 13. The protective layer 21 can be interposed between the slit structure SLS and the second conductive layer 13. The protective layer 21 may include an insulating material such as oxide, nitride, or air gap.

[0031] According to the above structure, memory cells can be disposed in the region where the channel structure CH and the first conductive layer 11 intersect. Select transistors can be disposed in the region where the channel structure CH and the second conductive layer 13 intersect. Memory cells and select transistors sharing each channel structure CH can form a single memory string. Thus, the integration density of the semiconductor device can be increased by stacking memory cells.

[0032] Figures 2A to 2C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2A and 2B It can be a floor plan. Figure 2C It can be along Figure 2A and 2B The cross-sectional view taken by line A-A'. In the following text, repeated descriptions will be omitted if deemed redundant.

[0033] Reference Figures 2A to 2C The channel structure CH can be arranged in a first direction I and a second direction II intersecting the first direction I. The channel structure CH can be arranged in a matrix type or in a staggered type where the centers are not aligned with each other.

[0034] The separation insulation structure 24 can be disposed between the channel structures CH. In a plane defined by a first direction I and a second direction II, the separation insulation structure 24 can extend along the second direction II.

[0035] The first channel structure CH1 may include a first channel layer 15, a memory layer 16, and a first insulating core 17. The memory layer 16 may include a barrier layer 16A, a data storage layer 16B, or a tunnel insulating layer 16C, or a combination thereof. The second channel structure CH2 may include a second channel layer 25, a gate insulating layer 26, and a second insulating core 27.

[0036] The width of the second channel structure CH2 may be smaller than the width of the first channel structure CH1. In a first direction I, the width of the gate insulating layer 26 may be smaller than the width of the memory layer 16. In the first direction I, the width of the second channel layer 25 may be smaller than the width of the first channel layer 15 (W2<W1). In the first direction I, the width of the second insulating core 27 may be smaller than the width of the first insulating core 17.

[0037] The second channel structure CH2 may extend into the first channel structure CH1. The gate insulating layer 26 may extend into the first channel structure CH1. The gate insulating layer 26 may include a first portion P1B and a second portion P2B. The first portion P1B may be interposed between the second channel layer 25 and the memory layer 16. The second portion P2B may be interposed between the second channel layer 25 and the second conductive layer 13. In the first direction I, the width of the first portion P1B may be greater than the width of the second portion P2B.

[0038] The third channel structure CH3 may include a third channel layer 18 configured to couple the first channel layer 15 and the second channel layer 25. The third channel structure CH3 may include a first portion P1A in contact with the first channel layer 15 and a second portion P2A in contact with the second channel layer 25. In the first direction I, the width of the first portion P1A may be greater than the width of the second portion P2A. The first portion P1A may be in contact with an inner surface of the first channel layer 15 and in contact with an upper surface of the first insulating core 17. The second portion P2A may be in contact with an inner surface of the second channel layer 25 and extend along the inner surface of the second channel layer 25 in a third direction III. An upper surface of the second portion P2A and an upper surface of the second channel layer 25 may be disposed on substantially the same plane.

[0039] The second channel layer 25 may extend into the first channel structure CH1. A lower surface of the second channel layer 25 may be disposed at a height lower than the height of an upper surface of the first channel layer 15. The second channel layer 25 may extend into the third channel structure CH3. A lower portion of the second channel layer 25 may be interposed between the first portion P1A and the second portion P2A.

[0040] The second conductive layer 13 may include a first portion P1C formed on the stack ST and a second portion P2C surrounding each of the second channel structures CH2. In a cross-section defined by the first direction I and the third direction III, the second portion P2C may protrude toward the first channel structure CH1 into the stack ST. The second portion P2C may protrude into the uppermost insulating layer 12 and contact the separate insulating structure 24.

[0041] In a plane defined along the first direction I and the second direction II, the second portion P2C can protrude into the separation insulating structure 24. Therefore, the separation insulating structure 24 can have wavered sidewalls. In a plane, the second portion P2C can surround the entire sidewall of the second channel structure CH2. Therefore, the selection transistor disposed at the intersection region of the second conductive layer 13 and the second channel structure CH2 can have a gate all around (GAA) structure.

[0042] The second conductive layer 13 can contact the memory layer 16. The second portion P2C can protrude into the top insulating layer 12 of the stacked ST. The second portion P2C can contact the memory layer 16. The outer wall P2C_OW of each second portion P2C can be aligned with the outer wall 16_OW of the corresponding memory layer 16.

[0043] According to the above structure, the second distance D2 between adjacent second channel structures CH2 in the first direction I is greater than the first distance D1 between adjacent first channel structures CH1 in the first direction I. This ensures sufficient space for forming the separation insulating structure 24 and the second conductive layer 13 between the second channel structures CH2. Therefore, the selection transistor disposed adjacent to the separation insulating structure 24 can be used as a real transistor instead of a dummy transistor. Furthermore, the selection transistor can have a uniform shape, thus exhibiting uniform characteristics.

[0044] Figures 3A to 15A and Figures 3B to 15B These are figures used to describe a method of manufacturing a semiconductor device according to embodiments of the present disclosure. The figure labeled A represents a plan view, and the figure labeled B represents a cross-sectional view taken along line B-B' of the figure labeled A. In the following, repeated descriptions will be omitted if deemed redundant.

[0045] Reference Figure 3A and Figure 3BThis forms a stack ST comprising alternating first material layers 31 and second material layers 32. The first material layer 31 may comprise a material with high etch selectivity relative to the second material layer 32. For example, the first material layer 31 may comprise a sacrificial material such as a nitride, while the second material layer 32 may comprise an insulating material such as an oxide. Alternatively, the first material layer 31 may be a conductive material, such as polysilicon, tungsten, or molybdenum, while the second material layer 32 may comprise an insulating material, such as an oxide. The second material layers 32 may have a uniform thickness or different thicknesses. In one embodiment, the thickness of the uppermost second material layer 32 may be greater than the thickness of the other second material layers 32.

[0046] Subsequently, a sacrificial layer 33 is formed on the stacked ST. The sacrificial layer 33 may include a material with high etch selectivity relative to the second material layer 32. In one embodiment, the sacrificial layer 33 may include a nitride layer, a carbon layer, an amorphous carbon layer, etc.

[0047] Subsequently, at least one separation insulation structure 34 is formed through the sacrificial layer 33. The separation insulation structure 34 may be disposed on the stack ST. In a plan view, the separation insulation structure 34 may have a linear shape extending in the second direction II. In a cross-sectional view, the separation insulation structure 34 may extend into the stack ST and contact the uppermost second material layer 32. The separation insulation structure 34 may be spaced apart from the uppermost first material layer 31 in the third direction III.

[0048] Subsequently, a first opening OP1 is formed through the sacrificial layer 33 and the stacked layer ST. When the first opening OP1 is formed, the separation insulation structure 34 can be etched. The first opening OP1 can pass through the separation insulation structure 34. The separation insulation structure 34 can be exposed through the first opening OP1. In the first direction I, the width X2 of the separation insulation structure 34 can be greater than the distance X1 between the first openings OP1.

[0049] Reference Figure 4A and 4B A first channel structure CH1 is formed in the first opening OP1. Each first channel structure CH1 may include a first channel layer 35, a memory layer 36, and a first insulating core 37. The memory layer 36 may include a barrier layer 36A, a data memory layer 36B, or a tunnel insulating layer 36C, or a combination thereof. In one embodiment, after the memory layer 36, the first channel layer 35, and the first insulating core 37 are formed sequentially, the first channel structure CH1 may be formed by performing a planarization process until the surface of the sacrificial layer 33 is exposed.

[0050] Reference Figure 5A and 5BThe second opening OP2 is formed by etching the first channel structure CH1. In one embodiment, the first channel layer 35 is exposed by etching the first insulating core 37, and the memory layer 36 is exposed by etching the exposed first channel layer 35. The second opening OP2 can then be formed by etching the exposed memory layer 36. Thus, the memory layer 36AA, the first channel layer 35A, and the first insulating core 37A can be formed.

[0051] The second opening OP2 can be formed to have a predetermined depth, thereby preventing the uppermost first material layer 31 from being exposed. The bottom of each second opening OP2 can be located between the lower surface of the sacrificial layer 33 and the upper surface of the uppermost first material layer 31. The sacrificial layer 33 and the separation insulation structure 34 can be exposed through the second opening OP2.

[0052] Reference Figure 6A and 6B A sacrificial spacer 38 is formed in the second opening OP2. The sacrificial spacer 38 may include a material with high etch selectivity relative to the second material layer 32. In one embodiment, the sacrificial layer 33 may include a nitride layer, a carbon layer, an amorphous carbon layer, etc.

[0053] The sacrificial spacer 38 may be coupled to the sacrificial layer 33. The sacrificial spacer 38 may be formed on the first channel structure CH1. The sacrificial spacer 38 may be disposed on the first channel layer 35 and the memory layer 36 and configured to expose the first insulating core 37A. In one embodiment, after forming a sacrificial material layer along the inner surface of the second opening OP2, the sacrificial spacer 38 may be formed by etching the entire surface of the sacrificial material layer. When etching the sacrificial material layer, the first insulating core 37A may be partially etched. The upper surface of the etched first insulating core 37B may be disposed at a position below the upper surface of the first channel layer 35A. The first channel layer 35A may be exposed through the second opening OP2.

[0054] Reference Figure 7A and 7B The third opening OP3 is formed by etching the first channel layer 35A through the second opening OP2. The first channel layer 35A exposed from the sacrificial spacer 38 and the first insulating core 37B can be selectively etched. The upper surface of the etched first channel layer 35B can be positioned at substantially the same height as the upper surface of the first insulating core 37B. The third opening OP3 can be connected to the second opening OP2. The memory layer 36AA can be exposed through the third opening OP3.

[0055] Reference Figure 8A and 8BA gate insulating layer 46 is formed in the second opening OP2. Each gate insulating layer 46 may be disposed on a corresponding first channel structure CH1 and extend into the third opening OP3. Each gate insulating layer 46 may include a first portion P1B in the corresponding third opening OP3 and a second portion P2B in the corresponding second opening OP2.

[0056] Subsequently, a second channel layer 45 is formed in each of the second openings OP2. In one embodiment, after forming a channel material layer along the inner surface of the second opening OP2, the second channel layer 45 can be formed by etching the entire surface of the channel material layer. When etching the channel material layer, the first insulating core 37B can be partially etched. Because the gate insulating layer 46 and the second channel layer 45 are formed after the width of the second opening OP2 has been reduced due to the sacrificial spacer 38, the width of the second channel layer 45 can be smaller than the width of the first channel layer 35B.

[0057] Reference Figure 9A and 9B The fourth opening OP4 is formed by etching the first insulating core 37B via the second opening OP2. The first insulating core 37B exposed from the second channel layer 45 can be selectively etched. The upper surface of the etched first insulating core 37B can be positioned below the upper surface of the first channel layer 35B. The first channel layer 35B can be exposed through the fourth opening OP4.

[0058] Reference Figure 10A and 10B A third channel structure CH3 is formed. Each of the third channel structures CH3 may include a third channel layer 48. The third channel layer 48 may be formed in the fourth opening OP4 and connect each of the first channel layers 35B to each of the second channel layers 45. The third channel layer 48 may extend into the second opening OP2. Each third channel layer 48 may include a first portion P1A formed in the corresponding fourth opening OP4 and a second portion P2A formed in the corresponding second opening OP2.

[0059] Subsequently, a second insulating core 47 is formed in the second opening OP2. The second insulating core 47 can be disposed in the second portion P2A. Finally, a second channel structure CH2, each including a second channel layer 45, a gate insulating layer 46, and a second insulating core 47, can be formed.

[0060] Reference Figure 11A and 11BContact pads 49 are formed. In one embodiment, after forming a fifth opening OP5 by etching the gate insulating layer 46, the second channel layer 45, the second insulating core 47, and the third channel layer 48, contact pads 49 are formed in the fifth opening OP5. Contact pads 49 may be disposed on the second channel layer 45A, the gate insulating layer 46A, the second insulating core 47A, and the third channel layer 48A. Contact pads 49 may be connected to the second channel layer 45A.

[0061] Reference Figure 12A and 12B The sixth opening OP6 is formed by removing the sacrificial layer 33 and the sacrificial spacer 38. The sixth opening OP6 can also be formed by selectively etching the sacrificial layer 33 and the sacrificial spacer 38. The sixth opening OP6 can be separated from each other by the separating insulating structure 34. The uppermost second material layer 32 and the second channel structure CH2 can be exposed through the sixth opening OP6. The sixth opening OP6 can extend into the second material layer 32 and expose the memory layer 36AA.

[0062] Reference Figure 13A and 13B Conductive layers 53 are formed in each of the sixth openings OP6. The conductive layers 53 can be separated from each other by the separation insulating structure 34. Each conductive layer 53 may include a first portion P1D disposed on the stack ST and a second portion P2D surrounding each of the second channel structures CH2. The second portion P2D may protrude toward the first channel structure CH1 into the stack ST.

[0063] Reference Figure 14A and 14B The seventh opening OP7 is formed by etching the conductive layer 53. In one embodiment, the seventh opening OP7 can be formed by etching back the conductive layer 53. The seventh opening OP7 can be separated from each other by the separation insulating structure 34. The etched conductive layer 53A can be spaced apart from the contact pad 49 on the third direction III. The second channel structure CH2 can protrude from the upper surface of the conductive layer 53A. Thereafter, an insulating layer 54 can be formed in the seventh opening OP7.

[0064] Reference Figure 15A and 15BThe first material layer 31 is replaced by a third material layer 51. For example, if the first material layer 31 includes a sacrificial material and the second material layer 32 includes an insulating material, the third material layer 51 may include a conductive material, such as polysilicon, tungsten, molybdenum, or a metal. After forming the eighth opening OP8 by forming a slit through the stack ST and removing the first material layer 31 through the slit, the third material layer 51 may be formed in the eighth opening OP8. Alternatively, if the first material layer 31 includes a conductive material and the second material layer 32 includes an insulating material, the third material layer 51, including a metal silicide material, may be formed by silicifying the first material layer 31.

[0065] Subsequently, impurities can be incorporated into the contact pad 49. Ultimately, channel structures CH can be formed, each comprising a first channel structure CH1, a second channel structure CH2, a third channel structure CH3, and a contact pad 49A.

[0066] According to the manufacturing method described above, the conductive layer 53A can be formed after the separation insulation structure 34 is formed. Therefore, the conductive layer 53A can be formed in a self-aligned manner. Furthermore, the conductive layer 53A can be formed by filling the sixth opening OP6 with material, so that even if there are multiple separation insulation structures 34 on the stack ST, the sacrificial spacer 38 and the sacrificial layer 33 can be replaced by multiple conductive layers 53A.

[0067] Figures 16A to 16I This is a view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Repeated descriptions will be omitted hereinafter if deemed redundant.

[0068] Reference Figure 16A A source structure 60 is formed. The source structure 60 may include at least one source layer and at least one sacrificial layer. In one embodiment, the source structure 60 may include a first source layer 61 and a second source layer 65, and further include a first sacrificial layer 63 interposed between the first source layer 61 and the second source layer 65. Additionally, the source structure 60 may include a second sacrificial layer 62 interposed between the first source layer 61 and the first sacrificial layer 63, or a third sacrificial layer 64 interposed between the first sacrificial layer 63 and the second source layer 65. The first source layer 61 and the second source layer 65 may include conductive materials, such as polysilicon, tungsten, molybdenum, or metal. The first sacrificial layer 63 may include a material with high etch selectivity relative to the second sacrificial layer 62 and the third sacrificial layer 64. In one embodiment, the first sacrificial layer 63 may include polysilicon or a nitride. The second sacrificial layer 62 and the third sacrificial layer 64 may include oxides.

[0069] Subsequently, a stack ST is formed on the source structure 60. The stack ST may include alternating stacked first material layers 71 and second material layers 72. The stack ST can be formed through multiple operations. In one embodiment, after forming a first stack including at least one first material layer 71 and at least one second material layer 72, a first opening OP1 is formed to pass through the first stack. Thereafter, a sacrificial pillar 67 is formed in the first opening OP1. Subsequently, a second stack including at least one first material layer 71 and at least one second material layer 72 is formed. Thus, a stack ST including the first stack and the second stack can be formed.

[0070] Subsequently, a sacrificial layer 73 is formed on the stack ST. The sacrificial layer 73 may comprise a material with high etch selectivity relative to the second material layer 72. Thereafter, at least one separation insulating structure 74 is formed through the sacrificial layer 73. The separation insulating structure 74 may comprise a first separation insulating structure 74A formed in a memory block MB and a second separation insulating structure 74B disposed at the boundary between memory blocks MB. The width of the first separation insulating structure 74A may be smaller than the width of the second separation insulating structure 74B. Multiple first separation insulating structures 74A may be formed in each memory block MB. The memory block MB may be a unit for performing erase operations and includes multiple memory strings.

[0071] Reference Figure 16B A first channel structure CH1 is formed to pass through the sacrificial layer 73 and the stack ST. In one embodiment, a second opening OP2 is formed to pass through the sacrificial layer 73 and the stack ST and expose the corresponding sacrificial pillar. Subsequently, after removing the sacrificial pillar through the second opening OP2, the first channel structure CH1 is formed in the first opening OP1 and the second opening OP2. The first channel structure CH1 may overlap with the first separation insulation structure 74A. The first channel structure CH1 may be spaced apart from the second separation insulation structure 74B. Each first channel structure CH1 may include a first channel layer 75, a memory layer 76, and a first insulating core 77.

[0072] Reference Figure 16C The third opening OP3 is formed by etching the first channel structure CH1. Subsequently, a sacrificial spacer 78 is formed in the third opening OP3. The sacrificial spacer 78 can be bonded to the sacrificial layer 73 and comprises a material substantially the same as that of the sacrificial layer 73. When forming the sacrificial spacer 78, the first insulating core 77 can be partially etched.

[0073] Reference Figure 16DA second channel structure CH2 is formed in the third opening OP3. After etching the first channel layer 75 through the third opening OP3, a corresponding gate insulating layer 86 is formed. Then, the second channel layer 85 is formed in each of the third openings OP3. Subsequently, the first insulating core 77 is etched, and then the third channel layer 88 is formed. A third channel structure CH3, each including the third channel layer 88, can be formed. Then, the second insulating core 87 is formed in each of the third openings OP3. Finally, a second channel structure CH2, each including the second channel layer 85, the gate insulating layer 86, and the second insulating core 87, can be formed. Each first channel layer 75 and each second channel layer 85 are connected via the third channel layer 88. The third channel layer 88 can extend along the inner surface of the second channel layer 85, as shown in Figure 1. Figure 10B The third channel layer 48 is shown. Subsequently, after etching the second channel structure CH2, contact pads 89 are formed.

[0074] Reference Figure 16E The fourth opening OP4 is formed by removing the sacrificial layer 73 and the sacrificial spacer 78. The fourth opening OP4 can be separated from each other by separating the insulating structures 74A and 74B. The uppermost second material layer 72 and the second channel structure CH2 can be exposed through the fourth opening OP4.

[0075] Reference Figure 16F The conductive layer 93 can be formed in each of the fourth openings OP4. The conductive layer 93 can be separated from each other by separating the insulating structures 74A and 74B. Then, the conductive layer 93 is etched, and then the insulating layer 94 is formed.

[0076] Reference Figure 16G A cover layer 101 is formed on the insulating layer 94. The cover layer 101 may be formed to cover the contact pads 89. The cover layer 101 may include an insulating material such as an oxide or a nitride.

[0077] Subsequently, a fifth opening OP5 is formed to expose the source structure 60. The fifth opening OP5 can be located at the boundary between memory blocks MB. The fifth opening OP5 can penetrate the cover layer 101, the second separation insulating structure 74B, and the stacked ST. When the fifth opening OP5 is formed, the second separation insulating structure 74B can be etched, and a protective layer 74BA can be formed. The protective layer 74BA can prevent the conductive layer 93 from being exposed through the fifth opening OP5 and protect the conductive layer 93.

[0078] Subsequently, a sixth opening OP6 is formed by removing the first sacrificial layer 63 via the fifth opening OP5. Then, the first channel layer 75 is exposed by etching the memory layer 76 exposed via the sixth opening OP6. When etching the memory layer 76, the second sacrificial layer 62 and the third sacrificial layer 64 can be etched together with the memory layer 76. Subsequently, a third source layer 66 is formed in the sixth opening OP6. The third source layer 66 may include a conductive material, such as polysilicon, tungsten, molybdenum, or a metal. The third source layer 66 may be directly connected to the first channel layer 75.

[0079] Reference Figure 16H The first material layer 71 is replaced by a third material layer 91 through the fifth opening OP5. For example, if the first material layer 71 includes a sacrificial material and the second material layer 72 includes an insulating material, the third material layer 91 may include a conductive material, such as polysilicon, tungsten, molybdenum, or a metal. After the seventh opening OP7 is formed by removing the first material layer 71 through the fifth opening OP5, the third material layer 91 may be formed in the seventh opening OP7. Alternatively, if the first material layer 71 includes a conductive material and the second material layer 72 includes an insulating material, the third material layer 91, comprising a metal silicide material, may be formed by silicideding the first material layer 71.

[0080] Reference Figure 16I A slit structure SLS is formed in the fifth opening OP5. The slit structure SLS may include a source contact structure 103 and an insulating spacer 102. The insulating spacer 102 may be inserted between the source contact structure 103 and the first conductive layer 91. The insulating spacer 102 may include an insulating material such as an oxide, nitride, or air gap. The source contact structure 103 may be electrically connected to the source structure 60. The source contact structure 103 may include a conductive material, such as polysilicon, tungsten, molybdenum, or metal. In one embodiment, after the source contact layer is formed in the fifth opening OP5 and on the capping layer 101, the source contact structure 103 may be formed by performing a planarization process until the insulating layer 94 is exposed.

[0081] Subsequently, impurities can be doped into the contact pad 89. The contact pad 89A doped with impurities can include a junction. Finally, a channel structure CH can be formed, each including a first channel structure CH1, a second channel structure CH2, a third channel structure CH3, and a contact pad 89A.

[0082] According to the manufacturing method described above, conductive layers 93 can be formed by separating the insulating structures 84A from each other.

[0083] Figure 17 This is a diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0084] Reference Figure 17The memory system 1000 may include a memory device 1200 configured to store data and a controller 1100 configured to perform communication between the memory device 1200 and the host 2000.

[0085] The host 2000 may be a device or system configured to store data in or retrieve data from the memory system 1000. The host 2000 may generate requests for various operations and output these requests to the memory system 1000. These requests may include programming requests for programming operations, read requests for reading operations, and erase requests for erasing operations. The host 2000 may communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0086] The host 2000 may include at least one of a computer, portable digital device, tablet PC, digital camera, digital audio player, television, wireless communication device and cellular phone, but embodiments of this disclosure are not limited thereto.

[0087] Controller 1100 controls the overall operation of memory system 1000. Controller 1100 can control memory device 1200 in response to requests from host 2000. Controller 1100 can control memory device 1200 to perform programming, reading, and erasing operations in response to requests from host 2000. Even when there are no requests from host 2000, controller 1100 can perform background operations to improve the performance of memory system 1000.

[0088] The controller 1100 can send control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. The control signals and data signals can be sent to the memory device 1200 via different input / output lines. Data signals can include commands, addresses, or data. Control signals can be used to separate the time periods of input data signals from other time periods.

[0089] The memory device 1200 can perform operations such as programming, reading, and erasing under the control of the controller 1100. The memory device 1200 can be implemented as a volatile memory device where data stored therein is lost upon power failure, or a non-volatile memory device where data stored therein can be retained even during a power outage. The memory device 1200 can be a reference... Figures 1 to 2C The semiconductor device described herein. The memory device 1200 can be configured as described by reference to... Figures 3A to 16I A semiconductor device manufactured by the described manufacturing method. In one embodiment, the semiconductor device may include: a stack comprising alternating stacked first conductive layers and insulating layers; a second conductive layer formed on the stack; a separation insulating structure disposed on the stack and configured to insulate the second conductive layers from each other; a first channel layer through the stack; a memory layer surrounding the sidewalls of the first channel layer; a second channel layer disposed on the stack and through the second conductive layer, wherein the width of each second channel layer is smaller than the width of the first channel layer; a gate insulating layer surrounding the sidewalls of the second channel layer; and a third channel layer configured to respectively connect each of the first channel layers to each of the second channel layers and extend into the second channel layers.

[0090] Figure 18 This is a diagram illustrating a memory system 30000 according to an embodiment of the present disclosure.

[0091] See Figure 18 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 configured to control the operation of the memory device 2200.

[0092] The controller 2100 can control the data access operations of the memory device 2200, such as programming operations, erasing operations, or reading operations, under the control of the processor 3100.

[0093] Data programmed into memory device 2200 can be output via display 3200 under the control of controller 2100.

[0094] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed in the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the controller 2100 or the display 3200. The controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Furthermore, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the modified radio signals to an external device via the antenna ANT. The input device 3400 can be used to input control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device such as a touchpad and computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that the display 3200 outputs data from the controller 2100, data from the radio transceiver 3300, or data from the input device 3400.

[0095] In one embodiment, the controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 3100 or as a separate chip from the processor 3100.

[0096] Figure 19 This is a diagram illustrating a memory system 40000 according to an embodiment of the present disclosure.

[0097] Reference Figure 19 The memory system 40000 can be implemented as a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0098] The memory system 40000 may include a memory device 2200 and a controller 2100 configured to control data processing operations of the memory device 2200.

[0099] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input from the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0100] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. In one embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100.

[0101] Figure 20 This is a diagram illustrating a memory system 50000 according to an embodiment of the present disclosure.

[0102] Reference Figure 20 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet PC equipped with a digital camera.

[0103] The memory system 50000 may include a memory device 2200 and a controller 2100 configured to control data processing operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 2200.

[0104] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be sent to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output via the display 5300 or stored in the memory device 2200 via the controller 2100. Data stored in the memory device 2200 can be output via the display 5300 under the control of the processor 5100 or the controller 2100.

[0105] In one embodiment, the controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 5100 or as a separate chip from the processor 5100.

[0106] Figure 21 This is a diagram illustrating a memory system 70000 according to an embodiment of the present disclosure.

[0107] Reference Figure 21 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0108] The controller 2100 can control the data exchange between the memory device 2200 and the card interface 7100. In one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but this disclosure is not limited thereto.

[0109] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. In one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Here, card interface 7100 can refer to hardware capable of supporting the protocol used by host 60000, software installed in the hardware, or signal transmission method.

[0110] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box), the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0111] The various embodiments of this disclosure can provide semiconductor devices with stable structures and improved reliability. Furthermore, the manufacturing process can be simplified and manufacturing costs can be reduced when manufacturing semiconductor devices.

[0112] Examples of embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

[0113] Cross-reference to related applications

[0114] This application claims priority to Korean Patent Application No. 10-2020-0126714, filed on September 29, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A stack comprising alternating stacked first conductive layers and insulating layers; A second conductive layer is disposed on the stack; A separation insulation structure is disposed on the stack and insulates each of the second conductive layers from each other; A first trench layer, the first trench layer passing through the stack; A memory layer, the memory layer surrounding the sidewall of the first channel layer; A second channel layer is disposed on the stack and passes through the second conductive layer, and the width of each second channel layer is smaller than the width of the first channel layer; A gate insulating layer, the gate insulating layer surrounding the outer wall of the second channel layer; as well as A third channel layer connects each of the first channel layers and each of the second channel layers. Each of the third channel layers includes a first portion disposed between the first channel layer and the second channel layer and a second portion extending along the inner sidewall of the second channel layer.

2. The semiconductor device according to claim 1, wherein, The memory layer is in contact with the second conductive layer.

3. The semiconductor device according to claim 1, wherein, Each of the gate insulating layers includes: The first portion inserted between the second channel layer and the memory layer; and The second portion is inserted between the second channel layer and the second conductive layer.

4. The semiconductor device according to claim 3, wherein, The width of the first part is greater than the width of the second part.

5. The semiconductor device according to claim 1, wherein, The first portion of each of the third channel layers is in contact with the corresponding first channel layer; and The second portion of each of the third channel layers is in contact with the corresponding second channel layer.

6. The semiconductor device according to claim 5, wherein, The width of the first part is greater than the width of the second part.

7. The semiconductor device according to claim 5, wherein, The upper surface of the second portion of each of the third channel layers and the upper surface of the corresponding second channel layer are disposed on the same plane.

8. The semiconductor device according to claim 1, wherein, Each of the second conductive layers includes: The first portion disposed on the stack; and The second portion of each second channel layer protrudes into the stack towards the first channel layer.

9. The semiconductor device according to claim 8, wherein, The second part is in contact with the memory layer.

10. The semiconductor device according to claim 8, wherein, The outer wall of each second part is aligned with the outer wall of the corresponding memory layer.

11. A semiconductor device comprising: A stack comprising alternating stacked word lines and insulating layers; A first trench layer, the first trench layer passing through the stack; A memory layer, the memory layer surrounding the sidewall of the first channel layer; A second trench layer is disposed on the stack; A gate insulating layer, the gate insulating layer surrounding the sidewall of the second channel layer; A third channel layer connects each of the first channel layers and each of the second channel layers respectively; Selection lines, each of the selection lines including a first portion disposed on the stack and a second portion respectively surrounding each of the second channel layers and protruding into the stack toward the first channel layer; as well as A separate insulation structure is disposed on the stack and insulates each of the select lines from each other. Wherein, the thickness of the second portion along the stacking direction of the word line and the insulating layer is greater than the thickness of the first portion along the stacking direction, and Each of the second channel layers extends through the second portion.

12. The semiconductor device according to claim 11, wherein, The second portion of the selection line contacts the memory layer.

13. The semiconductor device according to claim 11, wherein, The outer wall of each of the second portions is aligned with the outer wall of the corresponding memory layer.

14. The semiconductor device according to claim 11, wherein, The width of each second channel layer is smaller than the width of each first channel layer.

15. The semiconductor device according to claim 11, wherein, Each of the gate insulating layers includes: The first portion inserted between the second channel layer and the memory layer; and The second portion is inserted between the second channel layer and the selection line.

16. The semiconductor device according to claim 15, wherein, The width of the first portion of each gate insulating layer is greater than the width of the second portion.

17. The semiconductor device according to claim 11, wherein, Each of the third channel layers includes: The first portion in contact with the corresponding first channel layer; and It extends to the second part in the corresponding second channel layer.

18. The semiconductor device according to claim 17, wherein, The width of the first portion of each of the third channel layers is greater than the width of the second portion.

19. The semiconductor device according to claim 17, wherein, The upper surface of the second portion of each of the third channel layers and the upper surface of the corresponding second channel layer are disposed on the same plane.

20. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a stack comprising alternating layers of first and second materials; A sacrificial layer is formed on the stack; A separate insulating structure is formed that passes through the sacrificial layer and is disposed on the first material layer; A first opening is formed through the sacrificial layer, the separation insulation structure, and the stack; A first channel layer is formed in the first opening; A sacrificial spacer is formed in the first opening to connect with the sacrificial layer; A second channel layer with a width smaller than that of the first channel layer is formed in the sacrificial spacer; as well as A third channel layer is formed in the first opening, the third channel layer connecting the first channel layer and the second channel layer. The third channel layer includes a first portion disposed between the first channel layer and the second channel layer, and a second portion extending along the inner sidewall of the second channel layer.

21. The method of claim 20, further comprising the step of: A memory layer is formed in the first opening before the first channel layer is formed; as well as Before forming the second channel layer, a gate insulating layer disposed on the first channel layer is formed in the first opening.

22. The method of claim 21, further comprising the step of: Before forming the gate insulating layer, a second opening exposing the memory layer is formed by etching the first channel layer exposed via the sacrificial spacer.

23. The method according to claim 22, wherein, The gate insulating layer extends into the second opening.

24. The method of claim 20, further comprising the step of: Before the sacrificial spacer is formed, a first insulating core is formed in the first channel layer; as well as After the second channel layer is formed, a third opening is formed to expose the first channel layer by etching the first insulating core.

25. The method according to claim 24, wherein, The third channel layer extends into the third opening.

26. The method of claim 20, further comprising the step of: Contact pads disposed on the second channel layer are formed in the first opening.

27. The method of claim 20, further comprising the step of: The fourth opening is formed by removing the sacrificial layer and the sacrificial spacer; as well as A conductive layer is formed in the fourth opening.

28. The method according to claim 27, wherein, The fourth opening is separated from each other by the separating insulation structure.

29. The method according to claim 27, wherein, Each of the conductive layers includes: The first portion disposed on the stack; and The second portion of each second channel layer protrudes into the stack towards the first channel layer.

30. The method of claim 27, further comprising the step of: The fifth opening is formed by etching the conductive layer to make the second channel layer protrude. as well as An insulating layer is formed in the fifth opening.

31. The method of claim 27, further comprising the step of: After the conductive layer is formed, the first material layer is replaced with a third material layer.

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