Three-dimensional memory and methods of manufacturing the same

Abstract

A three-dimensional memory and a method of manufacturing the same are provided. The method includes forming a stack structure including alternating stacks of dielectric layers and sacrificial layers on a substrate, the stack structure including a stepped structure at a stepped region, at least a portion of the sacrificial layers at the stepped structure being exposed; forming a first cap layer including nitrogen-doped silicon carbide on the exposed at least a portion of the sacrificial layers; forming a second cap layer including silicon-rich silicon oxide on the first cap layer; and forming a fill layer on the second cap layer to provide a planar surface for the stepped region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a three-dimensional memory and a method for manufacturing the same. Background Technology

[0002] Planar NAND devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, 3D NAND memory devices have been proposed. In the structure of 3D NAND memory devices, dielectric and conductive layers can be stacked alternately vertically or approximately vertically to form a stacked structure. The stacked structure includes a core region and a step region. The core region can be used to form an array of channel structures, and the step region can be used to form a step structure.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a method for fabricating a three-dimensional memory, comprising: forming a stacked structure on a substrate comprising alternating stacked dielectric layers and sacrificial layers, the stacked structure comprising a stepped structure located in a stepped region, wherein at least a portion of the sacrificial layers in the stepped structure is exposed; forming a first capping layer comprising nitrogen-doped silicon carbide on the exposed at least portion of the sacrificial layer; forming a second capping layer comprising silicon-rich silicon oxide on the first capping layer; and forming a filling layer on the second capping layer.

[0005] In one embodiment of this application, at least a portion of the second cover layer that is in contact with the first cover layer is converted into a bonding layer, the bonding layer comprising silicon oxide.

[0006] In one embodiment of this application, the silicon-rich silicon oxide comprises elemental silicon, and at least a portion of the elemental silicon located in the second capping layer is oxidized to the bonding layer.

[0007] In one embodiment of this application, during the formation of the first capping layer, hydrocarbon dangling bonds are formed on the exposed surface of the first capping layer; and during the formation of the second capping layer, the hydrocarbon dangling bonds react with at least a portion of the oxygen atoms in the second capping layer to form water vapor.

[0008] In one embodiment of this application, the wet oxidation of at least a portion of the elemental silicon into the bonding layer comprises: the water vapor wet oxidizing the at least a portion of the elemental silicon into the bonding layer.

[0009] In one embodiment of this application, the second capping layer is formed using an atomic layer deposition process or a high-density plasma chemical vapor deposition process.

[0010] In one embodiment of this application, forming the second cover layer includes an annealing process, wherein the temperature range of the annealing process is 600°C to 1400°C.

[0011] In one embodiment of this application, the method further includes: forming a gate gap that extends through the stacked structure and into the substrate; and replacing the sacrificial layer with a conductive layer via the gate gap.

[0012] In one embodiment of this application, the method further includes: forming word line contacts that sequentially penetrate the fill layer, the second cover layer, and the first cover layer and extend into the corresponding conductive layer.

[0013] In one embodiment of this application, forming the word line contact portion includes: forming a contact hole above the stepped structure that penetrates the filler layer and extends into the first cover layer; and further processing the contact hole extending into the first cover layer to extend it into the corresponding conductive layer.

[0014] In one embodiment of this application, forming the word line contact portion includes filling the contact hole with a conductive material to form the word line contact portion.

[0015] Another aspect of this application provides a three-dimensional memory, comprising: a first semiconductor layer; a stacked structure located on the first semiconductor layer, the stacked structure comprising alternately stacked dielectric layers and conductive layers, the stacked structure including a stepped structure located in a stepped region; a first capping layer comprising nitrogen-doped silicon carbide, the first capping layer covering at least a portion of the conductive layer located in the stepped structure; a second capping layer comprising silicon-rich silicon oxide, the second capping layer located on the first capping layer; and a filling layer located on the second capping layer.

[0016] In one embodiment of this application, the three-dimensional memory further includes a bonding layer located between the first cover layer and the second cover layer.

[0017] In one embodiment of this application, the ratio of silicon atoms to oxygen atoms in the silicon-rich silicon oxide included in the second capping layer is between 1:1 and 2.

[0018] In one embodiment of this application, the three-dimensional memory further includes: a word line contact portion that sequentially penetrates the filling layer, the second cover layer, and the first cover layer and extends into the corresponding conductive layer.

[0019] In one embodiment of this application, the three-dimensional memory further includes a gate gap structure, comprising an insulating layer and a conductor layer disposed sequentially from the outside to the inside. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0021] Figure 1 This is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of this application;

[0022] Figures 2-10 This is a partial schematic diagram of a method for manufacturing a three-dimensional memory according to some embodiments of this application after performing certain steps;

[0023] Figure 11 A schematic diagram of a three-dimensional memory according to some embodiments of this application;

[0024] Figure 12 This is a schematic diagram of a three-dimensional memory according to some other embodiments of this application. Detailed Implementation

[0025] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0026] Note that references to "one implementation," "implementation," "example implementation," "some implementations," "exemplary," etc., in the specification indicate that the described implementation may include a specific feature, structure, or characteristic, but each implementation may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same implementation. Additionally, when a specific feature, structure, or characteristic is described in connection with an implementation, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other implementations will be within the knowledge of those skilled in the art.

[0027] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0028] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0029] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s)(s)(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein may be interpreted similarly.

[0030] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple sublayers.

[0031] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the terms “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0032] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising" as used in this specification indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to indicate "one or more embodiments of this application."

[0033] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] In some exemplary 3D NAND processes, as the number of stacked layers increases, the step structure of the 3D NAND (e.g., step structure 142 hereinafter) has an increasing number of steps (e.g., step 130 hereinafter), and each step becomes thinner, making it difficult for the subsequently formed word line contact holes (not shown) to stop at the corresponding conductive layer (e.g., conductive layer 204 hereinafter). They are prone to breaking through the corresponding conductive layer 204 and contacting the adjacent conductive layer 204, thereby causing word line leakage and signal crosstalk problems.

[0036] In some embodiments, a capping layer of a certain thickness (e.g., a first capping layer 143 of nitrogen-doped silicon carbide hereinafter) can be formed on the stepped structure 142. The first capping layer 143 can cover the corresponding conductive layer 204, and can act as a buffer when forming word line contact holes (not shown). Alternatively, the word line contact hole can first stop in the first capping layer 143 and then continue to extend into the corresponding conductive layer 204, thereby increasing the process window for the word line contact hole to land on the conductive layer 204 and reducing the risk of the word line contact hole breaking through the corresponding conductive layer 204. Other embodiments of this application propose a method for manufacturing a three-dimensional memory. Figure 1 A flowchart of the three-dimensional memory manufacturing method 300 is shown. Figures 2-10 This is a partial schematic diagram showing the device structure after certain steps have been performed according to the manufacturing method 300 described above. In detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure are not enlarged to scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application.

[0037] The manufacturing method 300 described above will now be described in conjunction with the accompanying drawings. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the operations described.

[0038] Reference Figure 1 The manufacturing method 300 includes operation S310, wherein a stacked structure comprising alternating stacked dielectric layers and sacrificial layers can be formed on a substrate, the stacked structure including a stepped structure located in a stepped region, and at least a portion of the sacrificial layer located in the stepped structure being exposed.

[0039] like Figure 2 As shown, the material of substrate 10 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof. In some examples, substrate 10 may include a base 100 and a stop layer 101 and a first sacrificial layer 102 sequentially formed on the base 100. Exemplarily, the base 100 may have a relatively thicker thickness than the stop layer 101 and the first sacrificial layer 102, thereby enabling the base 100 to serve as a structural support for a device structure (e.g., a stacked structure 200) formed thereon.

[0040] In some embodiments, the method for forming the stop layer 101 and the first sacrificial layer 102 may include one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, and thermal oxidation. Exemplarily, the material of the substrate 100 may include silicon, the material of the stop layer 101 may include silicon dioxide, and the material of the first sacrificial layer 102 may include polycrystalline silicon.

[0041] In this operation, a stacked structure 200 may be formed on a substrate 10. The stacked structure 200 may include a plurality of dielectric layers 201 and a plurality of sacrificial layers 202 alternately stacked in a direction perpendicular to or substantially perpendicular to the substrate 10. Optionally, the plurality of dielectric layers 201 and the plurality of sacrificial layers 202 may be alternately stacked on the substrate 10 by one or more deposition processes, such as CVD, PVD, and ALD.

[0042] It should be understood that the number of dielectric layers 201 and sacrificial layers 202 is not limited to... Figure 2 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to create any number and thickness of dielectric layers 201 and sacrificial layers 202 as needed. Furthermore, the materials of dielectric layers 201 and sacrificial layers 202 may be selected from suitable materials known in the art. For example, dielectric layer 201 may be an oxide layer (e.g., silicon oxide), and sacrificial layer 202 may be a nitride layer (e.g., silicon nitride).

[0043] For example, substrate 10 can be used for forming structures such as channel structures 111 thereon. Figure 2 The grid line gap structure (not shown) provides mechanical support and is removed in subsequent processes.

[0044] Refer again Figure 2 Optionally, prior to forming the stacked structure 200, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to sequentially form an oxide layer (e.g., silicon oxide) 103 and a polysilicon layer 104 on the substrate 10, for example, on the first sacrificial layer 102.

[0045] The stacked structure 200 may include a core region 120 and a stepped region 140. In some examples, the stepped region 140 may be located on both sides of the core region 120, and in other examples, the stepped region 140 may be located in the middle of the core region 120. It should be noted that in the accompanying drawings of the embodiments of this application, only the stepped region 140 on one side of the stacked structure 200 and the portion of the core region 120 connected to the stepped region 140 on that side are shown.

[0046] Optionally, the core region 120 may include a channel structure 111. As an example, the channel structure 111 may extend vertically or substantially vertically through the dielectric layer 201 and the sacrificial layer 202; optionally, the channel structure 111 may extend into the first sacrificial layer 102. In some embodiments, the channel structure 111 includes a barrier layer 112, a storage layer 114, a tunneling layer 116, and a channel layer 118, arranged sequentially from the outside in. Optionally, the channel layer 118 may include polysilicon. The tunneling layer 116 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 114 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 112 may include silicon oxide, silicon oxynitride, a high-dielectric-constant dielectric, or any combination thereof.

[0047] In some examples, photolithography and etching processes (e.g., dry or wet etching), CMP processes, or any combination thereof, can be used in appropriate steps to remove (e.g., sequentially remove) the substrate 100, stop layer 101, and first sacrificial layer 102 from the side of the substrate 10 opposite to the stacked layer 200, thereby exposing the portion of the channel structure 111 extending into the substrate 10. Optionally, the stop layer 101 can stop the process of removing the substrate 10 at this layer, thereby facilitating the control of the process uniformity of removing the substrate 10. Similarly, the first sacrificial layer 102 can stop the process of removing the stop layer 101 at this layer, thereby facilitating the control of the process uniformity of removing the stop layer 101.

[0048] Exemplarily, portions of the barrier layer 112, storage layer 114, and tunneling layer 116 extending into the substrate 10 can be removed, thereby exposing portions of the channel layer 118 extending into the substrate 10. In an example including a polysilicon layer 104, the polysilicon layer 104 can serve as a stop layer for the process exposing portions of the channel layer 118 extending into the substrate 10. In some cases, the polysilicon layer 104 can be removed in subsequent processes. As an example, a first semiconductor layer 401 electrically in contact with the channel layer can also be formed on the side exposing the channel layer 118. Figure 11 The first semiconductor layer 401 includes, for example, polysilicon.

[0049] Continue to refer to Figure 2 The step region 140 may include a step structure 142, wherein the step structure 142 may include a plurality of stepped steps 130. In some examples, each stepped step 130 includes the thickness of at least one dielectric layer 201 / sacrificial layer 202 pair, the sidewalls of the at least one sacrificial layer 202 / dielectric layer 220 pair being exposed, and at least a portion of the surface of the sacrificial layer 202 included in each stepped step 130 remote from the substrate 10 being exposed. As an example, the stacked structure 200 can be formed by repeatedly etching-trimming processes using a patterned mask layer (not shown). Figure 2The step structure 142 is shown. Optionally, the patterned mask may include a photoresist or a carbon-based polymer material and may be removed after the step structure 142 is formed.

[0050] In some examples, the step structure 142 can be a single step structure that increases sequentially in one direction along the plane of the substrate 10. In other examples, the step structure 142 can also be a staircase partition scheme (SDS). The partition scheme has stepped steps 130 formed in two orthogonal directions along the plane of the substrate 10. The partition scheme can have different partitions, such as 3 partitions, 4 partitions or more partitions. For example, different partition plates can be used. The partition scheme is formed by multiple trimmings of the photoresist in two orthogonal directions, with each trimming followed by an etching of the stacked structure 200.

[0051] Continue to refer to Figure 1 Manufacturing method 300 includes operation S320, wherein a first capping layer comprising nitrogen-doped silicon carbide may be formed on at least a portion of the exposed portion of the sacrificial layer. Figure 3 As shown, after forming the step structure 142, a first capping layer 143 can be formed on the exposed portions of the sacrificial layer 202, such as on the exposed sidewalls of the sacrificial layer 202 and on a portion of the surface away from the substrate 10. Optionally, the first capping layer 143 can also be formed on the exposed surface of the core region 120. In one example, the first capping layer 143 can be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the first capping layer 143 may comprise, for example, nitrogen-doped silicon carbide (SiCN). In some examples, the thickness of the first capping layer 143 can be from a few nanometers to tens of nanometers. The NDC in the first capping layer 143 can be a relatively dense film with good step coverage.

[0052] Since the first capping layer 143 can be formed on the stepped structure 142 and the subsequently deposited filler layer 145 ( Figure 6 Therefore, the first cover layer 143 can serve as a barrier layer between the fill layer 145 and the stacked structure 200, preventing impurities (e.g., free radicals of H and OH) in the fill layer 145 from diffusing into the stepped structure 142, thereby preventing erosion of the sacrificial layer 202 in the stepped structure 142.

[0053] In some examples where the first capping layer 143 comprises nitrogen-doped silicon carbide, the exposed surface of the first capping layer 143 is typically prone to forming hydrocarbon dangling bonds.

[0054] Continue to refer to Figure 1Manufacturing method 300 includes operation S330, wherein a second capping layer comprising silicon-rich silicon oxide can be formed on the first capping layer. For example... Figure 4 As shown, a second capping layer 144 in contact with the exposed surface of the first capping layer 143 can be formed on the first capping layer 143 by a thin film deposition process such as CVD, PVD, ALD, high-density plasma-chemical vapor deposition (HDP-CVD), ion-enhanced chemical vapor deposition (PECVD), magnetron sputtering (RMS), pulsed laser deposition (PLD), or any combination thereof. As an example, the second capping layer 144 can be formed using an ALD process with a high-temperature annealing treatment at 600°C to 1400°C.

[0055] A filler layer 145 comprising silicon dioxide is formed directly on the first capping layer 143. Figure 6 In the example, because hydrocarbon dangling bonds can combine with more reactive oxygen radicals (O) or hydroxyl radicals (OH) in silica to form water vapor, water vapor can adhere to the interface between the first capping layer 143 and the filler layer 145, thereby reducing the bonding force between the first capping layer 143 and the filler layer 145, making the first capping layer 143 prone to splitting or even falling off.

[0056] To address the aforementioned issues, some embodiments of this application may form a second capping layer 144 comprising silicon-rich silicon oxide on the first capping layer 143 before forming the filler layer 145. Although water vapor is generated during the formation of the second capping layer 144, the water vapor is consumed in a timely manner, ensuring the bonding force between the first capping layer 143 and the second capping layer 144.

[0057] In an example of forming the second capping layer 144 via an ALD process, the ratio of oxygen-based (e.g., oxygen) and silicon-based (e.g., silane) gas sources can be increased, and a suitable annealing temperature can be controlled so that the formed second capping layer 144 comprises silicon-rich silicon oxide, in which the ratio of silicon atoms to oxygen atoms is greater than 1:2, for example, between 1:1 and 2. Optionally, the ratio of silicon atoms to oxygen atoms in the silicon-rich silicon oxide can be between 1:1.5 and 1:1.8. Optionally, the suitable annealing temperature is between 600°C and 1400°C. Optionally, the suitable annealing temperature range can also be between 700°C and 1200°C.

[0058] Since the ratio of silicon atoms to oxygen atoms in silicon-rich silicon oxide is greater than 1:2, the second capping layer 144 can contain elemental silicon. During the high-temperature annealing process, at least a portion of the elemental silicon in the second capping layer 144, for example, at least a portion of the elemental silicon on the surface of the second capping layer 144 in contact with the first capping layer 143, can undergo a wet oxidation reaction with the water vapor generated at the interface to form a... Figure 5The diagram shows a bonding layer 146 comprising silicon dioxide.

[0059] Refer again Figure 1 Manufacturing method 300 includes operation S340, wherein a filler layer may be formed on the second cover layer. For example... Figure 6 As shown, in some examples, a fill layer 145 covering the stepped structure 142 may be formed on the second cover layer 144, and the material of the fill layer 145 may include, for example, silicon oxide. Optionally, the fill layer 145 may fill the stepped step 130 ( Figure 2 The second capping layer 144 extends up to the top of the stacked structure 200. In the example where the filler layer 145 includes silicon oxide, the bonding strength between the two is relatively high due to the small difference in materials between the second capping layer 144 and the filler layer 145.

[0060] Some embodiments of this application form a second cover layer 144 comprising silicon-rich silicon oxide between the first cover layer 143 and the filler layer 145. Compared with the bonding force between the first cover layer 143 and the filler layer 145, the bonding force between the first cover layer 144 and the second cover layer 144 and the filler layer 145 are improved, thereby improving the problem of splitting or even falling off of the first cover layer 143.

[0061] In one example, a first filler layer (not shown) with good step coverage can be formed on the second capping layer 144 using an HDP-CVD or ALD deposition process. The first filler layer may include, for example, silicon oxide. Optionally, a second filler layer (not shown) with high fill efficiency can be formed on the first filler layer. The second filler layer may be, for example, TEOS (Tetea-Ethyl-Ortho-Silicate) based silicon oxide. Optionally, the filler layer 145 can be further planarized using processes such as chemical mechanical polishing (CMP) to provide a substantially flat upper surface for the step region 140 of the stacked structure 200.

[0062] In subsequent manufacturing processes of 3D memory, such as virtual channel vias, word line contact vias, and metal interconnects, amorphous carbon (aC) may be formed above the step region 140 as a hard mask. OH radicals diffused from the filling layer 140 can break down the amorphous carbon hard mask, resulting in arcing. This can cause the 3D memory film structure to split, peel off, or even break, thus affecting the device performance. Therefore, it is necessary to release the OH radicals.

[0063] During the formation of the filler layer 145 or after planarization, a high-temperature annealing process can be performed to make the filler layer 145 more compact, thereby preventing brittle fracture of the filler layer 145. At the same time, OH free radicals in the filler layer 145 are released. These OH free radicals can react with the active silicon in the silicon-rich silicon oxide to generate a thin layer of silicon dioxide, thereby blocking the OH radicals in the filler layer 145 from eroding the sacrificial layer 202.

[0064] Refer again Figure 1 The manufacturing method 300 includes operation S350, wherein a gate line gap can be formed through the stacked structure and extending into the substrate, and a sacrificial layer is replaced with a conductive layer via the gate line gap. Figure 7 As shown, in some embodiments, after forming the fill layer 145, a plurality of dummy channel structures 113 extending into the substrate 10 can be formed in the stacked structure 200. In some examples, dummy channel vias (not shown) extending into the first sacrificial layer 102 can be formed in the stacked structure 200 using etching processes such as dry etching and wet etching. Optionally, insulating material can be filled into the dummy channel vias to form the dummy channel structures 113. It should be understood that... Figure 7 The image shows only one example of a dummy channel structure 113 located in the core area 120. In other examples, multiple dummy channel structures 113 may be formed in the step area 140. The dummy channel structure 113 may sequentially penetrate the filling layer 145, the second covering layer 144, the first covering layer 143, and the stepped step 130 in the step area 140. Figure 2 The function of the dummy channel structure 113 may include, for example, providing structural support to alleviate stress.

[0065] In some embodiments, etching processes such as dry etching and wet etching can be used to form gate gaps (not shown) in the stacked structure 200. The gate gaps can penetrate the stacked structure 200 along the thickness direction of the stacked structure 200 and extend into the substrate 10.

[0066] like Figure 8 As shown, in some embodiments, the gate gap can be used as an etching channel, and the sacrificial layer 202 in the stacked structure 200 can be removed by, for example, an isotropic wet etching process, thereby forming the sacrificial gap 203.

[0067] like Figure 9 As shown, the gate gap can be used as a deposition channel, and conductive material can be filled into the sacrificial gap 203 to form a conductive layer 204. Optionally, the conductive layer 204 can be deposited inside the sacrificial gap 203 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, the material of the conductive layer 204 includes, for example, tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides, or any combination thereof.

[0068] In other examples, prior to forming the conductive layer 204, at least one TiN layer and at least one dielectric layer, such as a high-dielectric-constant layer, may be formed in the sacrificial gap 203 to reduce leakage current of the word lines and to block impurity diffusion into the conductive layer 204. Optionally, the conductive layer 204 may be formed on the high-dielectric-constant dielectric layer.

[0069] In some examples, the gate gap may be filled in a suitable step to form a gate gap structure (not shown). Optionally, an insulating layer (not shown) and a conductor layer (not shown) may be sequentially formed on the inner wall and bottom of the gate gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The conductor layer may include, for example, tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides, or any combination thereof.

[0070] Continue to refer to Figure 1 Manufacturing method 300 includes operation S360, wherein word line contacts can be formed sequentially through a fill layer, a second cover layer, and a first cover layer, and extending into a corresponding conductive layer. For example... Figure 10 As shown, it can be found in the stepped structure 142 ( Figure 9 Multiple penetrating filling layers 145 are formed above and extend to word line contacts 115 in the corresponding conductive layer 204.

[0071] Including bonding layer 146 ( Figure 5 In the example, photolithography and plasma etching processes can be used to form, sequentially penetrating the filling layer 145, the second capping layer 144, the bonding layer 146, the first capping layer 143, and the stepped step 130 above the stepped structure 142. Figure 2 And extends to the contact hole (not shown) in the corresponding conductive layer 204.

[0072] In the process of forming the contact holes, for example, using plasma etching, the depth to which the contact holes extend into the conductor layers 204 of each step 130 varies due to the height differences of the various steps 130. For instance, the plasma can first contact the conductor layers 204 away from the substrate 10, resulting in the contact holes extending deeper into those conductor layers 204 than into the conductor layers 204 closer to the substrate 10. Therefore, the contact holes are more likely to break through the conductor layers 204 away from the substrate 10, allowing the contact holes to stop in the dielectric layer 201 under the corresponding conductor layer 204 or extend into the adjacent conductor layer 204. As a result of this breakdown, the word line contacts subsequently formed in the contact holes are prone to poor contact or word line leakage problems.

[0073] In some embodiments of this application, the contact holes extending into the corresponding conductive layer 204 can be formed in steps. Optionally, for example, photolithography and plasma etching processes can be used to form sequentially penetrating the filling layer 145 and the stepped step 130 above the stepped structure 142. Figure 2 The contact holes (not shown) extend into the second cover layer 144. Optionally, the contact holes may also penetrate the second cover layer 144 and stop within the first cover layer 143. Compared to the second cover layer 144, the first cover layer 143 may have a relatively thicker thickness, thus allowing for easier adjustment of the depth to which the contact holes extend by controlling the thickness of the first cover layer 143. As an example, the contact holes can be further processed using etching or other processes to extend them into the corresponding conductive layer 204. Since the first cover layer 143 and the second cover layer 144 have a certain blocking and buffering effect, the contact holes at different heights can extend into the corresponding conductive layer 204 almost simultaneously, reducing the depth difference of the contact holes at different heights extending into the conductive layer 204.

[0074] As an example, after forming contact holes extending to the corresponding conductive layers 204, conductive material can be filled into these contact holes using ALD, PVD, CVD, or any combination thereof to form word line contacts 115. The word line contacts 115 can be electrically connected to their respective conductive layers 204, thereby allowing the conductive layers 204 to be electrically led out to interact with peripheral circuitry (not shown) for electrical signals. Optionally, the conductive material filling these contact holes can be at least one of tungsten, copper, silver, platinum, iron, and cobalt, or an alloy thereof.

[0075] Some embodiments of this application use two stepped capping layers (first capping layer 143 and second capping layer 144) as landing buffer layers to form contact holes, which can better control different stepped steps 130 ( Figure 2 The contact hole at the location lands to the depth of the conductive layer 204, reducing the problems of poor contact (contact hole, for example, landing in the dielectric layer 201) or word line leakage (contact hole, for example, landing in the adjacent conductive layer 204) caused by the contact hole breaking through the conductive layer 204.

[0076] Other embodiments of this application provide a three-dimensional memory 400, which can be manufactured by the method 300 described above. For example... Figure 11 As shown, the three-dimensional memory 400 may include: a first semiconductor layer 401 and a stacked structure 200' located on the first semiconductor layer 401, wherein the stacked structure 200' may include a plurality of alternately stacked dielectric layers 201 and conductive layers 204. Alternatively, the first semiconductor layer 401 may include, for example, polysilicon.

[0077] As an example, the stacked structure 200' may include a core region 120 and stepped regions 140 located on either side of the core region 120; optionally, the stepped regions 140 may also be located in the middle of the core region 120. It is understood that this is done for clarity. Figure 11 Only the stepped area 140 located on one side of the core area 120 is shown.

[0078] In some examples, the stacked structure 200' further includes a channel structure 111 located in the core region 120. Optionally, the channel structure 111 may pass through alternating dielectric layers 201 and conductive layers 204. In some embodiments, the channel structure 111 may include a barrier layer 112, a storage layer 114, a tunneling layer 116, and a channel layer 118 arranged sequentially from the outside to the inside. Optionally, a first semiconductor layer may be electrically contacted with the channel layer 118. In other examples, the stacked structure 200' may also include a dummy channel structure 113.

[0079] In some examples, the stacked structure 200' includes a step structure 142 located in the step region 140. The step structure 142 may include a plurality of stepped steps (not shown), each stepped step may include the thickness of at least one conductive layer 204 / dielectric layer 201 pair.

[0080] In some examples, such as Figure 11 As shown, the three-dimensional memory 400 also includes a first capping layer 143 located on the stepped structure 142, the material of which includes, for example, nitrogen-doped silicon carbide. Exemplarily, the first capping layer 143 may cover each step of the stepped structure; as an example, the first capping layer 143 may cover at least a portion of the conductive layer 204 located on each step. Optionally, the first capping layer 143 may cover the surface of the conductive layer 204 located on each step away from the first semiconductor layer 401; optionally, the first capping layer 143 may also cover the sidewalls of each step.

[0081] In some examples, such as Figure 11 As shown, the three-dimensional memory 400 also includes a second cover layer 144 located on the first cover layer 143. As an example, the material of the second cover layer 144 may include silicon-rich silicon oxide, where the ratio of silicon atoms to oxygen atoms is, for example, 1:1 to 2. Optionally, the three-dimensional memory 400 may also include a bonding layer (e.g., between the first cover layer 143 and the second cover layer 144) located between them. Figure 5 The bonding layer 146 is shown.

[0082] In some examples, such as Figure 11 As shown, the three-dimensional memory 400 also includes a filling layer 145 located above the step structure 142, which can provide a relatively flat surface for the step area 140.

[0083] In some examples, the three-dimensional memory 400 may also include a gate gap structure (not shown) that penetrates the stacked structure 200' in the core region 120 and the step region 140, respectively. Optionally, the gate gap structure may include an insulating layer (not shown) and a conductor layer (not shown) disposed sequentially from the outside to the inside.

[0084] Continue to refer to Figure 11 In some examples, the 3D memory 400 further includes word line contacts 115, which optionally extend through the fill layer 145, the second cover layer 144, and the first cover layer 143 in sequence to the corresponding conductive layer 204. In some examples where the 3D memory 400 includes a bonding layer 146, the word line contacts 115 extend through the fill layer 145, the second cover layer 144, the bonding layer 146, and the first cover layer 143 in sequence to the corresponding conductive layer 204.

[0085] Since the content and structure described in the preparation method 300 above are fully or partially applicable to the three-dimensional memory 400 described herein, related or similar content will not be repeated.

[0086] Further embodiments of this application provide a three-dimensional memory 500, which can be manufactured by the method 300 described above. For example... Figure 12 As shown, unlike the first semiconductor layer 401 included in the three-dimensional memory 400, the three-dimensional memory 500 may include a second semiconductor layer 502 and a third semiconductor layer 503 located thereon. Optionally, the stacked structure 200' may be disposed on the third semiconductor layer 503.

[0087] In some examples, the channel structure 111 may extend into the second semiconductor layer 502, and the third semiconductor layer 503 may sequentially pass through the barrier layer 112, the storage layer 114, and the tunneling layer 116 to make electrical contact with the channel layer 118. Optionally, the second semiconductor layer 502 and the third semiconductor layer 503 may be electrically contacted, so that the channel layer 118 can be electrically connected to the second semiconductor layer 502 through the third semiconductor layer 503.

[0088] Since the content and structure described above regarding the preparation method 300 and the three-dimensional memory 400 are fully or partially applicable to the three-dimensional memory 500 described herein, related or similar content will not be repeated.

[0089] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely illustrative.

[0090] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a three-dimensional memory, including: A stacked structure comprising alternating stacked dielectric layers and sacrificial layers is formed on a substrate, the stacked structure including a stepped structure located in a stepped region, wherein at least a portion of the sacrificial layer is exposed in the stepped structure; A first capping layer comprising nitrogen-doped silicon carbide is formed on at least a portion of the exposed portion of the sacrificial layer; A second capping layer comprising silicon-rich silicon oxide is formed on the first capping layer, wherein at least a portion of the second capping layer in contact with the first capping layer is converted into a bonding layer; as well as A fill layer is formed on the second cover layer.

2. The method according to claim 1, wherein, The bonding layer comprises silicon oxide.

3. The method according to claim 2, wherein, The silicon-rich silicon oxide comprises elemental silicon, and at least a portion of the elemental silicon located in the second capping layer is oxidized to the bonding layer.

4. The method according to claim 1, wherein, The second capping layer is formed using atomic layer deposition or high-density plasma chemical vapor deposition.

5. The method according to claim 1, wherein, The formation of the second cover layer includes an annealing process, wherein the temperature range of the annealing process is 600°C to 1400°C.

6. The method according to claim 1, further comprising: A gate line gap is formed that extends through the stacked structure and into the substrate; as well as The sacrificial layer is replaced with a conductive layer via the gate gap.

7. The method according to claim 6, further comprising: A word line contact is formed that sequentially penetrates the fill layer, the second cover layer, and the first cover layer and extends into the corresponding conductive layer.

8. The method according to claim 7, wherein, The word line contact portion includes: A contact hole is formed above the stepped structure, penetrating the filler layer and extending into the first cover layer; and The contact holes extending into the first cover layer are processed so that they extend into the corresponding conductive layer.

9. The method according to claim 8, wherein, The word line contact portion includes: The contact hole is filled with conductive material to form the word line contact portion.

10. A three-dimensional memory, comprising: A stacked structure comprising alternating stacked dielectric and conductive layers, the stacked structure including a stepped structure located in a stepped region; A first capping layer, comprising nitrogen-doped silicon carbide, covers at least a portion of the conductive layer located in the stepped structure; The second capping layer includes silicon-rich silicon oxide, and the second capping layer is located on the first capping layer; A bonding layer is located between the first cover layer and the second cover layer; as well as A filler layer is located on the second cover layer.

11. The three-dimensional memory according to claim 10, wherein, The ratio of silicon atoms to oxygen atoms in the silicon-rich silicon oxide included in the second capping layer is between 1:1 and 2.

12. The three-dimensional memory according to claim 10, further comprising: The word line contact portion sequentially penetrates the filling layer, the second cover layer, and the first cover layer, and extends into the corresponding conductive layer.

13. The three-dimensional memory according to claim 10, further comprising: The gate gap structure includes an insulating layer and a conductor layer arranged sequentially from the outside to the inside.

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