Silicon carbide device with transistor cell and clamping region

Abstract

A silicon carbide device (500) includes a transistor cell (TC) having a source region (110) and a gate electrode (155). The source region (110) is formed in a silicon carbide body (100) and has a first conductivity type. A first low resistance ohmic path (901) electrically connects the source region (110) and a doped region (120) having a second conductivity type. The doped region (120) and a floating well (410) having the first conductivity type form a pn junction. A first clamp region (411) having the second conductivity type extends into the floating well (410). A second low resistance ohmic path (902) electrically connects the first clamp region (411) and the gate electrode (155).

Description

Technical Field

[0001] Examples of this disclosure relate to silicon carbide devices having transistor cells, and more particularly to semiconductor devices having insulated-gate transistor cells and clamps between the gate electrode and the source electrode of the transistor cells. Background Technology

[0002] Power semiconductor devices are commonly used as switches and rectifiers in circuits for converting electrical energy (e.g., in DC / AC converters, AC / AC converters, or AC / DC converters) and in circuits driving heavily inductive loads (e.g., in motor drive circuits). Because silicon carbide (SiC) has a higher dielectric breakdown field than silicon (Si), SiC power devices can be much thinner and exhibit lower on-state resistance compared to silicon power devices. Integrated protection elements and / or protection circuitry improve device reliability at the cost of additional process complexity.

[0003] There is a need to improve the reliability of silicon carbide devices effortlessly. Summary of the Invention

[0004] Embodiments of this disclosure relate to silicon carbide devices. A silicon carbide device includes a transistor cell having a gate electrode and a source region. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistance ohmic path electrically connects the source region and a doped region of a second conductivity type. A floating well and the doped region form a pn junction. A first clamping region of the second conductivity type extends into the floating well. A second low-resistance ohmic path electrically connects the first clamping region and the gate electrode.

[0005] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0006] The accompanying drawings are included to provide a further understanding of this embodiment and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of silicon carbide devices and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

[0007] Figures 1A to 1B A schematic vertical cross-sectional view of a portion of the clamping region of a silicon carbide device with a bidirectional clamp according to an embodiment is shown.

[0008] Figure 1C It shows Figures 1A to 1B A simplified circuit diagram of a silicon carbide device.

[0009] Figures 2A to 2BA schematic vertical cross-sectional view of a portion of a silicon carbide device according to another embodiment, having a clamping region, a gate metallization, a first load metallization, and a second load metallization, is shown.

[0010] Figure 3A A schematic vertical cross-sectional view of a portion of a silicon carbide device according to an embodiment is shown, wherein a first clamping region and a second clamping region extend into a floating trap.

[0011] Figure 3B Explanation is shown Figure 3A A schematic diagram of the breakdown characteristics of a bidirectional clamp.

[0012] Figure 3C A schematic vertical cross-sectional view of a portion of a silicon carbide device according to an embodiment is shown, wherein the bidirectional clamp includes two clamp portions connected in series.

[0013] Figure 4 A schematic vertical cross-sectional view of a portion of a silicon carbide device according to an embodiment, including a transistor cell and an integrated bidirectional clamp, is shown.

[0014] Figure 5 A schematic plan view of a silicon carbide device is shown, indicating the possible areas of a bidirectional clamp according to an embodiment.

[0015] Figures 6A to 6B A schematic vertical cross-sectional view of a portion of a silicon carbide device according to an embodiment is shown, wherein an integrated bidirectional clamp is formed below the gate channel and the edge conductor.

[0016] Figure 7 A schematic vertical cross-sectional view of a portion of a silicon carbide device according to an embodiment is shown, wherein an integrated bidirectional clamp is formed between two pad portions of a gate channel and a discrete load pad.

[0017] Figures 8A to 8B A simplified plan view and a corresponding simplified vertical cross-sectional view of a portion of a silicon carbide device with a bidirectional clamp according to an embodiment are shown, wherein a first clamping region is connected to a gate pad and a second clamping region is connected to a load pad.

[0018] Figures 9A to 9B A simplified plan view and a corresponding simplified vertical cross-sectional view of a portion of a silicon carbide device according to another embodiment, having an integrated bidirectional clamp, are shown, wherein a first clamping region is connected to a gate pad. Detailed Implementation

[0019] In the following detailed description, reference is made to the accompanying drawings, which form part of this document, and in which specific embodiments of silicon carbide devices can be practiced illustrated by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. For example, features shown or described for one embodiment may be used in or in combination with other embodiments to produce yet another embodiment. This disclosure is intended to include these modifications and variations. Examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements are indicated by the same reference numerals in different drawings.

[0020] The terms “having,” “containing,” “including,” “comprising,” etc., are open-ended and indicate the presence of the stated structure, element, or feature, but do not exclude additional elements or features. The articles I, a, and the intended use are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0021] The term "electrical connection" describes a permanent low-resistance ohmic connection between electrically connected components, such as a direct contact between related components or a low-resistance ohmic connection via a metal and / or heavily doped semiconductor material. The term "electrical coupling" includes one or more intermediate elements suitable for signal and / or power transmission that can be connected between electrically coupled components, such as elements controllable to temporarily provide a low-resistance connection in a first state and a high-resistance connection in a second state. An "ohmic contact" is a non-rectified junction with linear or near-linear current-voltage characteristics.

[0022] The accompanying diagram illustrates relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" indicates a lower doping concentration than the "n" doped region, while an "n+" doped region has a higher doping concentration than the "n" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions can have the same or different absolute doping concentrations.

[0023] Two adjacent doped regions with the same conductivity type but different dopant concentrations form a unipolar junction, such as an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At the unipolar junction, the dopant concentration distribution orthogonal to the unipolar junction can exhibit a step or inflection point, where the dopant concentration distribution changes from concave to convex, and vice versa.

[0024] The range given for physical dimensions includes boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value (such as "at most" and "at least").

[0025] The term “on” should not be interpreted as “directly on”. Rather, if an element is “on” another element (e.g., a layer is “on” another layer or on a substrate), then additional components (e.g., additional layers) may be located between the two elements (e.g., if a layer is “on” the substrate, then another layer may be located between that layer and the substrate).

[0026] The terms “power semiconductor device” and “silicon carbide power device” refer to semiconductor devices having a high voltage blocking capability of at least 30V (e.g., 100V, 600V, 1.6kV, 3.3kV or higher) and a nominal on-state current or forward current of at least 1A (e.g., 10A or more).

[0027] An ohmic contact describes a nonrectified junction between two conductors. According to Ohm's law, an ohmic contact has a linear or approximately linear current-voltage (IV) curve in the first and third quadrants of an IV diagram.

[0028] Silicon carbide devices may include transistor cells having source regions. The source regions may be formed in the silicon carbide body and have a first conductivity type.

[0029] The silicon carbide body can have two substantially parallel main surfaces and a transverse surface connecting the edges of these two main surfaces, which can have approximately the same shape and size. For example, the silicon carbide body can be a cylinder or a polyhedron, such as a rectangular prism or a hexagonal prism with or without rounded edges. The silicon carbide body can have surfaces extending along two horizontal directions and can have a thickness along a vertical direction perpendicular to the horizontal directions. The horizontal direction is also referred to as the transverse direction below.

[0030] The silicon carbide bulk material can be single-crystal silicon carbide, such as 15R-SiC (15R-polymorphic silicon carbide), or hexagonal polymorphic silicon carbide, such as 2H-SiC, 4H-SiC, or 6H-SiC. In addition to the main components silicon and carbon, the silicon carbide bulk may also include dopant atoms such as nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), and / or gallium (Ga). The silicon carbide bulk may include additional impurities such as hydrogen, fluorine, and / or oxygen.

[0031] The transistor cell may be or may include an insulated gate transistor cell having an insulated gate electrode. The gate electrode may be a planar gate electrode formed on the main surface of the silicon carbide body, or it may be a trench gate electrode formed in a trench extending from the main surface into the silicon carbide body.

[0032] The transistor cell may include a body region, and the silicon carbide body may also include a drain / drift region. At least a portion of the drain / drift region may have a first conductivity type, and the drain of the transistor cell may be active.

[0033] The body region can have a complementary second conductivity type. The body region can spatially separate the source region from a portion of the drain / drift region having a first conductivity type. A gate dielectric can be formed between the gate electrode and the body region. The potential applied to the gate electrode controls the distribution of mobile charge carriers in the body region via a field effect.

[0034] Silicon carbide devices may also include doped regions formed in the silicon carbide body. The doped regions have a second conductivity type. The doped regions may be, or may include, horizontally continuous structures comprising portions with different vertical extensions and / or different vertical dopant distributions.

[0035] The doped region can be a single-part structure or a multi-part structure. For example, the doped region may include two or more separate parts that are laterally and / or vertically separated within the silicon carbide body. The individual parts of a multi-part doped region can be electrically connected through a low-resistance ohmic path.

[0036] The first low-resistance ohmic path can electrically connect the doped region and the source region. The ohmic resistance of the first low-resistance ohmic path can be at most 2Ω, for example, at most 1Ω, or at most 0.5Ω.

[0037] Silicon carbide devices may also include a floating well formed within the silicon carbide body. The floating well has a first conductivity type. The floating well and the doped region form a pn junction. The floating well may have no additional ohmic connection or only a high-ohmic connection to another conductive structure of the silicon carbide device. For example, an equalization current in the nA range may flow at least temporarily between the floating well and the source region. The maximum equalization current between the floating well and the source region may be greater than 0.1 nA, for example, greater than 0.1 nA or greater than 1 nA. The maximum equalization current may be less than 100 nA, less than 10 nA, or less than 5 nA.

[0038] The first clamping region may extend into the floating well. The first clamping region may have a second conductivity type. For example, the first clamping region may have a second conductivity type, and the floating well and the first clamping region may form a pn junction. The floating well may laterally surround the first clamping region within the silicon carbide body.

[0039] The second low-resistance ohmic path can electrically connect the first clamping region and the gate electrode. The ohmic resistance of the second low-resistance ohmic path can be up to 2Ω, for example, up to 1Ω, or up to 0.5Ω.

[0040] A doped region, a floating well, and a first clamping region form an effective bidirectional clamp, for example, between the gate metallization and the first load metallization, wherein an avalanche breakdown of one of the pn junctions between the doped region and the first clamping region limits the clamping breakdown voltage. The bidirectional clamp can protect the transistor cell from overvoltage events. In particular, the bidirectional clamp can protect the gate dielectric, which in silicon carbide power devices may be highly susceptible to overvoltage events such as electrostatic discharge (ESD).

[0041] Due to the high inherent breakdown voltage of silicon carbide, the bidirectional clamp formed in the silicon carbide bulk may short-circuit and dissipate overvoltage events such as ESD events without being damaged. Due to the large bandgap and low intrinsic hot carrier generation of silicon carbide, leakage through the bidirectional clamp is lower compared to equivalent circuits in monocrystalline or polycrystalline silicon.

[0042] The floating trap allows the characteristics of the bidirectional clamp to be effectively decoupled from the blocking voltage applied between the first load metallization and the drain / drift region.

[0043] According to an embodiment, a silicon carbide device may include a gate metallization. The gate metallization may be formed on a first main surface on the front side of the silicon carbide body. The gate metallization may include a gate pad made of a metallic material and / or one or more gate conductors made of a metallic material. The metallic material may include: one or more elemental metals, such as copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta); one or more metal alloys, such as copper-aluminum (CuAl); and / or one or more metallization compounds, such as metal silicides or metal nitrides.

[0044] The gate metallization and the gate electrode can be electrically connected to each other. For example, the gate pad and / or gate conductor can be formed directly on a portion of the gate, wherein the gate electrode and the gate pad and / or the gate electrode and the gate conductor form a low-resistance ohmic contact. Alternatively, the gate metallization may include a metal gate contact structure extending from the gate pad and / or the gate conductor to the gate electrode, wherein the gate contact structure and the gate electrode form a low-resistance ohmic contact.

[0045] Furthermore, the gate metallization and the first clamping region can form an ohmic contact, such as a low-resistance ohmic contact. The gate pad and / or gate conductor can be directly formed on a portion of the first clamping region, wherein the first clamping region and the gate pad and / or the first clamping region and the gate conductor form a low-resistance ohmic contact. Alternatively, the gate metallization may include a metal clamping contact structure extending from the gate pad and / or the gate conductor to the first clamping region, wherein the clamping contact structure and the first clamping region form a low-resistance ohmic contact.

[0046] By forming the first clamping region directly below the gate metallization portion, a bidirectional clamp can be integrated in a space-saving and area-efficient manner.

[0047] According to an embodiment, a silicon carbide device may include a first load metallization. The first load metallization may be formed on a first main surface on the front side of the silicon carbide body. The first load metallization may include a load pad made of a metallic material and / or one or more edge conductors made of a metallic material. The metallic material may include: one or more elemental metals, such as copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta); one or more metal alloys, such as copper-aluminum (CuAl); and / or one or more metallization compounds, such as silicides or nitrides.

[0048] The first load metallization and the source region can be electrically connected to each other. For example, the load pad can be formed directly on a portion of the source region, wherein the source region and the load pad form a low-resistance ohmic contact. Alternatively, the first load metallization may include a metal load contact structure extending from the load pad to the source region, wherein the load contact structure and the source region form a low-resistance ohmic contact.

[0049] Furthermore, the first load metallization and the doped region can form an ohmic contact, such as a low-resistance ohmic contact. The load pad and / or edge conductor can be formed directly on a portion of the doped region, wherein the doped region and the load pad and / or the doped region and the edge conductor form a low-resistance ohmic contact.

[0050] According to other embodiments, the first load metallization portion includes one or more additional metal load contact structures.

[0051] For example, the source region and the doped region can be formed side by side, and a single metal load contact structure extends from the load pad to the source region and the doped region, forming a low-resistance ohmic contact with both the source region and the doped region.

[0052] According to another example, the source region and the doped region can be formed with a lateral distance between them. The first load metallization may include a first load contact structure of metal and a second load contact structure of metal. The first load contact structure and the source region can form a low-resistance ohmic contact. The second load contact structure and the doped region can form another ohmic contact, such as a low-resistance ohmic contact. Alternatively or additionally, the first load metallization may include an edge contact structure extending from the edge conductor through the interlayer dielectric to the doped region, wherein the doped region and the edge conductor structure form a low-resistance ohmic contact.

[0053] By using a portion of the doped region as part of the bidirectional clamp, the latter can be integrated in a space-saving and area-efficient manner.

[0054] According to an embodiment, the doped region may include a second clamping region within the floating trap, wherein the second clamping region and the first load metallization portion may be electrically connected.

[0055] The first load metallization and the second clamping region can form an ohmic contact, such as a low-resistance ohmic contact. For example, the load pad and / or edge conductor can be directly formed on the second clamping region, wherein the second clamping region and the load pad and / or the second clamping region and the edge conductor form an ohmic contact, such as a low-resistance ohmic contact. Alternatively, the first load metallization may include a metal load contact structure extending from the load pad to the second clamping region, wherein the load contact structure and the second clamping region form a low-resistance ohmic contact. Alternatively, the first load metallization may include a metal edge contact structure extending from the edge conductor to the second clamping region, wherein the edge contact structure and the second clamping region form a low-resistance ohmic contact.

[0056] The second clamping region forms a separate portion of the doped region. In addition to the second clamping region, the doped region may include one or more additional portions located outside the floating well. The first load metallization may include additional load contact structures, wherein the additional load contact structures and the additional portions of the doped region may form a low-resistance ohmic contact.

[0057] By forming a first clamping region and a second clamping region within the same floating well, the performance of the bidirectional clamp can be highly decoupled from the characteristics and operating modes of the transistor cell. The breakdown characteristics can be highly symmetrical with respect to the voltage polarity.

[0058] According to the embodiment, the floating trap, the first clamping region, and the second clamping region can extend from the first main surface of the silicon carbide body into the silicon carbide body, wherein the bidirectional clamp can be formed in a cost-effective manner and by using an implantation mask formed on the same main surface. Furthermore, the number of oppositely doped layers can be kept small, and side effects caused by parasitic bipolar transistors and / or thyristor structures can be largely avoided.

[0059] According to an embodiment, the floating well may include a main portion and an enhancement portion. The average net dopant concentration in the enhancement portion may be higher than the average net dopant concentration in the main portion but lower than the average net dopant concentration in the source region. The enhancement portion may extend from the first main surface into the floating well or may be formed at a certain distance from the first main surface.

[0060] A first portion of the reinforcement may be formed between the first clamping region and the second clamping region. The reinforcement may exclusively include the first portion or may include other portions. The first portion may be formed only along a portion of the line connecting the first clamping region and the second clamping region.

[0061] The enhanced portion allows for fine-tuning of the breakdown characteristics of the bidirectional clamp and fixation of the breakdown path position along the first main surface.

[0062] According to an implementation, the first portion of the enhancement can extend from the first clamping region to the second clamping region.

[0063] In this way, the breakdown of the bidirectional clamp can be located between the first clamping area and the second clamping area and within the floating trap, so that the functional components outside the floating trap are almost unaffected by the breakdown of the bidirectional clamp.

[0064] According to an embodiment, the reinforcement portion may laterally surround the first clamping region and the second clamping region. For example, a second portion of the reinforcement portion between the first clamping region and the lateral sidewall of the floating trap, and between the second clamping region and the lateral sidewall of the floating trap, may reduce the influence of adjacent structures on the characteristics of the bidirectional clamper.

[0065] According to the implementation, the reinforcing portion, particularly the second portion of the reinforcing portion, can be laterally separated from the lateral sidewall of the floating trap.

[0066] According to one embodiment, the bidirectional clamp, including a first clamping region and a floating well, can be configured to carry a breakdown current of at least 0.5 A and, for example, up to 10 A, wherein the breakdown current flows through the floating well between the first clamping region and the doped region. The breakdown current can be in the range of 0.5 A to 2 A. A properly configured first clamping region and floating well facilitate the dissipation of standard ESD pulses according to a human body model without continuously damaging the silicon carbide body and transistor cells.

[0067] According to one embodiment, the second low-resistance ohmic path may include a metal gate conductor. The gate conductor may include a strip-shaped portion and may intersect with the gate electrode. For example, a portion of the gate conductor may extend longitudinally perpendicular to the longitudinal extension of the gate electrode.

[0068] A low-resistance ohmic contact can be formed between the gate conductor and the gate electrode. The gate conductor can be in direct contact with the gate electrode, whereby the gate conductor and the gate electrode form a low-resistance ohmic contact. Alternatively, a metal gate contact structure can extend from the gate conductor to the gate electrode, whereby the gate contact structure and the gate electrode form a low-resistance ohmic contact.

[0069] Another low-resistance ohmic contact can be formed between the gate conductor and the first clamping region. The gate conductor can be in direct contact with the first clamping region, wherein the gate conductor and the first clamping region form a low-resistance ohmic contact. Alternatively, a metal clamping contact structure can extend from the gate conductor to the first clamping region, wherein the gate contact structure and the first clamping region form a low-resistance ohmic contact.

[0070] By using the silicon carbide portion below the gate conductor, a bidirectional clamp can be formed with little or no loss of effective chip area.

[0071] According to one embodiment, the first low-resistance ohmic path may include an edge conductor. The edge conductor may be strip-shaped and may be formed between the gate conductor and the lateral surface 103 of the silicon carbide body.

[0072] A low-resistance ohmic contact can be formed between the edge conductor and a portion of the doped region. For example, the doped region may include a junction termination portion between the lateral edge of the gate conductor and the silicon carbide body, and a low-resistance ohmic contact can be formed between the edge conductor and the junction termination portion.

[0073] The edge conductor can be in direct contact with the doped region, where the edge conductor and the doped region can form a low-resistance ohmic contact. Alternatively, a metallic edge contact structure can extend from the edge conductor to the doped region, where the edge contact structure and the doped region form a low-resistance ohmic contact.

[0074] According to an embodiment, the doped region may include a second clamping region within the floating well, wherein a low-resistance ohmic contact between the edge conductor and the doped region is formed between the edge conductor and the second clamping region.

[0075] Integrating the bidirectional clamp fully into the floating well can help reduce the impact of transistor cells on the characteristics of the bidirectional clamp.

[0076] According to one embodiment, the first low-resistance ohmic path may include a load pad. The load pad may be configured as a bond wire base.

[0077] A low-resistance ohmic contact can be formed between the load pad and the source region. The load pad can directly contact the source region, where the load pad and source region form a low-resistance ohmic contact. Alternatively, a metallic load contact structure can extend from the load pad to the source region, where the load contact structure and source region form a low-resistance ohmic contact.

[0078] Furthermore, a low-resistance ohmic contact can be formed between the load pad and the doped region. The load pad can be in direct contact with the doped region, where the load pad and the doped region form a low-resistance ohmic contact. Alternatively, a metal load contact structure can extend from the load pad to the doped region, where the load contact structure and the doped region form a low-resistance ohmic contact.

[0079] For example, load pads and edge conductors can be formed on opposite sides of the gate conductor. A low-resistance ohmic contact can be formed between the load pad and the portion of the doped region oriented to the transistor cell, and another low-resistance ohmic contact can be formed between the junction termination portion of the doped region and the edge conductor.

[0080] The effective length of the floating well perpendicular to the gate conductor can be relatively small. A small effective length can reduce the risk of latch-up during dynamic switching of transistor cells.

[0081] By using the silicon carbide portion beneath the edge conductor, a bidirectional clamp can be provided with little or no loss of effective chip area.

[0082] Figures 1A to 1C The invention relates to a silicon carbide device 500 having a monolithically integrated bidirectional clamp 800. The silicon carbide device 500 may be or may include an IGFET (Insulated Gate Field Effect Transistor), such as a MOSFET (Metal-Oxide-Semiconductor FET) or an IGBT (Insulated Gate Bipolar Transistor) having multiple identical transistor cells TC connected in parallel.

[0083] Figures 1A to 1B The silicon carbide body 100 shown includes or is composed of single-crystal silicon carbide, for example, a silicon carbide crystal comprising silicon and carbon as its main components. The silicon carbide crystal may include dopant atoms and other impurities such as hydrogen, fluorine, and / or oxygen. The polymorphism of the silicon carbide crystal may be 15R or hexagonal, such as 2H, 6H, or 4H. The silicon carbide body 100 may include or be composed of a silicon carbide layer grown epitaxially.

[0084] The first primary surface 101 on the front side of the silicon carbide body 100 can be planar or ribbed. The average plane of the first primary surface 101 extends horizontally. The average plane of a flat first primary surface 101 is the same as that of a flat first primary surface 101. In the case of a non-planar first primary surface 101, such as a ribbed first primary surface 101, the average plane can be a least-squares plane. The position and orientation of the least-squares plane are defined such that the sum of the squares of the deviations of the surface points of the ribbed first primary surface 101 from the least-squares plane is minimized.

[0085] The vertical direction is orthogonal to the horizontal direction, for example, parallel to the surface normal on a mean plane. The horizontal direction will also be referred to as the transverse direction below.

[0086] The vertical direction can coincide with the principal lattice direction or can be tilted towards the principal lattice direction with an off-axis angle, wherein the off-axis angle can be in the range of 2° to 8°, particularly about 4°. The second principal surface opposite to the front surface can extend parallel to the flat first principal surface 101 or parallel to the least squares plane of the ribbed first principal surface 101.

[0087] An insulated gate transistor cell TC is formed on the front side of the silicon carbide body 100. A drain / drift region 130 extends laterally through the silicon carbide body 100 between the insulated gate transistor cell TC and the second main surface. The drain / drift region 130 may include a voltage sustaining structure, such as a lightly doped drift region 131.

[0088] The insulated-gate transistor cell TC includes a source region 110 and a body region 121. The source region 110 and body region 121 are doped portions of the silicon carbide body 100. The source region 110 has a first conductivity type. The body region 121 has a second conductivity type. For example, the source region 110 is n-conductive, while the body region 121 is p-conductive.

[0089] The body region 121 may form part of the doped region 120 of the second conductivity type. For example, the doped region 120 may include additional portions, such as junction termination portions, shielding portions, and / or contact portions.

[0090] The first low-resistance ohmic path 901 is electrically connected to the source region 110 and the doped region 120. The first load terminal S / E is electrically connected to the first low-resistance ohmic path 901. The first load terminal S / E can be the source terminal S of a MOSFET or the emitter terminal of an IGBT. The drain / drift region 130 is electrically connected to or coupled to the second load terminal D / C, which can be the drain terminal D of a MOSFET or the collector terminal of an IGBT.

[0091] A floating well 410 of a first conductivity type extends from the first main surface 101 into the doped region 120. The floating well 410 and the doped region 120 form a pn junction. The doped region 120 surrounds the floating well 410 on all sides within the silicon carbide body 100.

[0092] The first clamping region 411 of the second conductivity type extends from the first main surface 101 into the floating well 410. The first clamping region 411 and the floating well 410 form a pn junction. The floating well 410 surrounds the first clamping region 411 on all sides within the silicon carbide body 100.

[0093] The gate dielectric 159 separates the body region 121 from the gate electrode 155.

[0094] exist Figure 1A In the transistor unit TC, a planar gate electrode 155 is formed on the first main surface 101.

[0095] exist Figure 1B In the transistor cell TC, a trench gate electrode 155 is formed in a trench extending from the first main surface 101 into the silicon carbide body 100.

[0096] The second low-resistance ohmic path 902 electrically connects the gate electrode 155 and the first clamping region 411. Additionally, the gate terminal G can be electrically connected to the first clamping region 411 and the gate electrode 155 via a low-impedance path.

[0097] The silicon carbide device 500 includes a plurality of insulated gate transistor units TC connected in parallel and may include a plurality of spatially separated floating wells 410 having a first clamping region 411.

[0098] according to Figure 1C The bidirectional clamp 800 clamps the gate voltage VGS between the gate electrode 155 and the doped region 120. For the n-channel transistor cell TC, the positive clamp voltage is limited by the avalanche breakdown voltage of the pn junction between the floating well 410 and the doped region 120. The negative clamp voltage is limited by the avalanche breakdown voltage of the pn junction between the first clamping region 411 and the floating well 410.

[0099] exist Figures 2A to 2B In the above, the silicon carbide device 500 is an n-channel MOSFET having n conductive power electrode regions 110, n conductive drift regions 131, n conductive floating wells 410, and a p-conductive doped region 120 including p+ conductive first clamping regions 411.

[0100] An interlayer dielectric 210 is formed on a first main surface 101. A first load metallization 310 and a gate metallization 330 are formed on the front side. The first load metallization 310 includes a load pad 315 and an edge conductor 311 formed on the interlayer dielectric 210. The first load metallization 310 also includes a load contact structure 319 extending from the load pad 315 through an opening in the interlayer dielectric 210 to the source region 110 and to the doped region 120. Furthermore, the first load metallization 310 may include an edge contact structure 318 extending from the edge conductor 311 through an opening in the interlayer dielectric 210 to the doped region 120. Along the interface to the edge contact structure 318, the doped region 120 may include a heavily doped contact region 129, wherein the edge contact structure 318 and the heavily doped contact region 129 form a low-resistance ohmic metal / semiconductor contact.

[0101] The gate metallization portion 330 includes a gate pad 335 and a gate conductor 331 formed on the interlayer dielectric 210. The gate metallization portion 330 also includes a gate contact structure 339 extending from the gate pad 335 and / or from the gate conductor 331 through an opening in the interlayer dielectric 210 to the gate electrode 155. The gate metallization portion 330 may include a clamping contact structure 338 extending from the gate pad 335 and / or from the gate conductor 331 through an opening in the interlayer dielectric 210 to the first clamping region 411.

[0102] A first load metallization 310 on the front side is formed or electrically connected to the source terminal S. A second load metallization 320 contacts the second main surface 102 on the back side and is formed or electrically connected to the drain terminal D. The drain / drift region 130 includes a more heavily doped n+ conductive contact layer 139 along the second main surface 102, wherein the contact layer 139 and the second load metallization 320 form a low-resistance ohmic contact.

[0103] Figure 3A An example of a symmetrical bidirectional clamper 800 is shown. An n-conductive floating well 410 extends from a first main surface 101 into a p-conductive doped region 120. A p-conductive first clamping region 411 and a p-conductive second clamping region 412 extend from the first main surface 101 into the floating well 410. The first clamping region 411 and the second clamping region 412 are laterally separated from each other and are formed symmetrically with respect to a central plane orthogonal to the cross-section.

[0104] The floating well 410 includes a main portion 414 and an enhancement portion 415. The average net dopant concentration in the enhancement portion 415 is higher than the average net dopant concentration in the main portion 414. The enhancement portion 415 extends from the first main surface 101 into the floating well 410. A first portion of the enhancement portion 415 is formed between a first clamping region 411 and a second clamping region 412. The first portion of the enhancement portion 415 may extend from the first clamping region 411 to the second clamping region 412. A second portion of the enhancement portion 415 may surround the first clamping region 411, the second clamping region 412, and the first portion of the enhancement portion 415. The second portion of the enhancement portion 415 may be spaced apart from the lateral sidewalls of the floating well 410.

[0105] In an alternative embodiment, the reinforcement portion 415 may form a continuous layer below the first clamping region 411 and the second clamping region 412.

[0106] The first load metallization 310 is electrically connected to the doped region 120, the second clamping region 412, and the source terminal S via a heavily doped contact region 129. The heavily doped contact region 129 can directly contact the floating well 410 laterally or can be laterally spaced from the floating well 410 by a lighter doped portion of the doped region 120. The gate metallization 330 is electrically connected to the first clamping region 411. The second load metallization 320 on the back side is electrically connected to the drain terminal D.

[0107] Figure 3B It shows Figure 3A The breakdown characteristics of the bidirectional clamp 800, as the clamping current I CL The graph is relative to the gate-source voltage VGS. The first line, 491, represents the breakdown characteristics when the drain-source voltage VDS is 0V, and the second line, 492, represents the breakdown characteristics when the drain-source voltage VDS is 650V. The breakdown characteristics are highly decoupled from the current transistor blocking voltage. Furthermore, the deviation between the negative and positive breakdown voltages is less than 20% of the sum of the two values.

[0108] Figure 3C A bidirectional clamp 800 is shown, having a first clamp portion 810 and a second clamp portion 820. Each clamp portion 810, 820 includes a floating well 410, a first clamping region 411 extending into the floating well 410, and a second clamping region 412 extending into the floating well 410. A doped region 120 embeds the floating well 410 of the two clamp portions 810, 820. Embedding the first clamping region 411 and the second clamping region 412 in the floating well 410 embedded in the doped region 120 facilitates the series configuration of the first clamp portion 810 and the second clamp portion 820 and provides further space for adjusting the electrical characteristics of the bidirectional clamp 800.

[0109] For example, the first clamping region 411 of the first clamping portion 810 is electrically connected to the gate metallization portion 330. The second clamping region 412 of the second clamping portion 820 is electrically connected to the first load metallization portion 310. The first clamping portions 411 of the first clamping portion 810 and the second clamping portion 820 are electrically connected to each other via an auxiliary conductor 340.

[0110] The first clamping portion 810 and the second clamping portion 820 can be formed side by side, wherein the vertical portion of the doped region 120 can laterally separate the first clamping portion 810 and the second clamping portion 820. Alternatively, the first clamping portion 810 and the second clamping portion 820 can be formed in different portions of the silicon carbide body 100. The first clamping portion 810 and the second clamping portion 820 can have the same orientation or can be twisted relative to each other, for example, by 90 degrees.

[0111] Figure 4 A silicon carbide device 500 is shown, which includes a silicon carbide body 100, a first load metallization 310, a gate metallization 330, a drain / drift region 130, a doped region 120, and a bidirectional clamp 800 with a floating well 410, a first clamping region 411, and a second clamping region 412, as shown in the reference. Figures 2A to 2B and Figure 3A As stated above.

[0112] The silicon carbide device 500 includes a plurality of transistor cells TC having a strip trench gate structure 150. The vertical axis of the gate structure 150 extends along a horizontal direction parallel to the y-axis. Each gate structure 150 includes a conductive gate electrode 155 and a gate dielectric 159 between the gate electrode 155 and the silicon carbide body 100. The gate electrode 155 may comprise heavily doped polysilicon. The gate dielectric 159 may be composed of silicon oxide, silicon nitride, and / or silicon oxynitride, or may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

[0113] The active sidewall 151 of each gate structure 150 is parallel or at least approximately parallel to a crystal plane with high charge carrier mobility, such as parallel to a <11-20> lattice plane. The active sidewall 151 may be tilted relative to the vertical z-axis at an off-axis angle of approximately 4 degrees.

[0114] The source region 110 of each transistor cell TC is formed along the first main surface 101 and contacts the active sidewall 151. The body region 121, which forms a pn junction with the source region 110 and the drain / drift region 130, contacts the active sidewall 151 and vertically separates the source region 110 from the drain / drift region 130. The drain / drift region 130 may include a lightly doped drift region 131, a more heavily doped current diffusion region 137 between the drift region 131 and the body region 121, and a heavily doped contact portion 139 formed along the second main surface 102.

[0115] The shielding region 126 contacts the side of the bottom surface 153 of the gate structure opposite to the active sidewall 151 and can extend from the bottom surface 153 toward the second main surface 102. The shielding region 126 forms a pn junction with the drain / drift region 130.

[0116] A conductive connection region 125 with a shielding region 126 extends from the first main surface 101 into or within the shielding region 126 along the passive sidewall 152, and can form a unipolar junction with the body region 121 of the adjacent transistor cell TC. At least along the first main surface 101, the dopant concentration in the connection region 125 is sufficiently high such that the connection region 125 and the metal load contact structure 319 form a low-resistance ohmic semiconductor / metal contact.

[0117] The average net dopant concentration in the vertical portion 120v of the doped region 120 along the side of the floating well 410 and the average net dopant concentration in the horizontal portion 120h of the doped region 120 between the bottom of the floating well 410 and the drain / drift region 130 are sufficiently high to maintain a sufficiently low gain factor for the parasitic npn bipolar transistor structure formed by the floating well 410, the horizontal portion 120h, and the drain / drift region 130 to avoid dynamic latch-up. The formation of the vertical portion 120v and the horizontal portion 120h can share the implantation steps used to form the shielding region 126 and the connection region 125, and can be defined by modifying the existing implantation masks of the shielding region 126 and the connection region 125.

[0118] The average net dopant concentration in the main portion 414 of the floating well 410 is chosen to be sufficiently high to prevent punch-through of the space charge region in both the lateral and vertical directions. The average net dopant concentration in the main portion 414 of the floating well 410 depends on the predetermined breakdown voltage of the bidirectional clamp 800 and the geometry of the associated doped portion, and can be higher than the net dopant concentration in the current extension region 137. Forming the floating well 410 may require a specific injection mask defining the lateral extension of the floating well 410 and three or more injection steps for doping the main portion 414 of the floating well 410 at different acceleration energies. Forming the reinforcement portion 415 may require an additional injection mask defining the lateral extension of the reinforcement portion 415 and one or more injection steps for doping the reinforcement portion 415 at different acceleration energies.

[0119] The maximum net dopant concentration in the first clamping region 411 and the second clamping region 412 is selected to be sufficiently high to obtain low-resistance ohmic contacts between the first clamping region 411 and the gate metallization 330 and between the second clamping region 412 and the source metallization 310, and is selected to be sufficiently low to achieve the breakdown voltage required for the bidirectional clamp, such as at least 100V, 80V, 60V, or 50V. The maximum net dopant concentration in the first clamping region 411 and the second clamping region 412 may be lower than the maximum net dopant concentration in the corresponding vertical cross-section of the connection portion 125. The formation of the first clamping region 411 and the second clamping region 412 may require an additional injection mask that allows the dopant concentration in the first clamping region 411 and the second clamping region 412 to be defined independently of the dopant concentration in the corresponding vertical cross-section of the connection portion 125.

[0120] Figure 5 A plan view of the front side of the silicon carbide body 100 is shown, wherein a strip gate structure 150 is shown representing a plurality of trench gate structures extending parallel to the y-axis. The first main surface 101 and the lateral surface 103 of the silicon carbide body 100 on the front side can form a front chip edge having four straight lines orthogonally oriented to each other.

[0121] The gate metallization section 330 includes a gate pad 335, an integrated gate resistor 333, gate conductors 331 and 332, a gate contact structure, and a clamp contact structure.

[0122] Gate pad 335 may be formed near the edge of the chip, for example, at the center of a straight portion along the edge of the chip. Gate pad 335 may include a thin layer portion and a thick metallization layer formed on the thin layer portion. The thin layer portion may include element titanium, titanium compounds such as titanium nitride (TiN), element tantalum (Ta), and / or tantalum compounds such as tantalum nitride (TaN). The thick metallization layer may include element copper (Cu), copper alloy, element aluminum (Al), aluminum alloy, and / or copper-aluminum alloy.

[0123] The integrated gate resistor 333 may comprise doped polysilicon. A first side of the integrated gate resistor 333 may be electrically connected to a gate pad 335. The opposite second side of the integrated gate resistor 333 may be directly connected to at least one of the gate conductors 331 and 332. The gate conductors 331 and 332 may comprise or be composed of thin-layer portions. The thin-layer portions of the gate conductors 331 and 332 and the thin-layer portion of the gate pad 335 may have the same structural configuration. For example, the two thin-layer portions may comprise the same material and may have the same thickness or may be formed by the same stack.

[0124] Gate conductors 331 and 332 include a strip-shaped first gate channel 3311, a strip-shaped second gate channel 3312, and a strip-shaped gate finger 332. The first gate channel 3311 has a longitudinal extension parallel to the y-axis. The second gate channel 3312 has a longitudinal extension parallel to the x-axis. The first gate channel 3311 and the second gate channel 3312 form a frame along the edge of the chip, wherein the frame may have a gap 337. The longitudinal axis of the gate finger 332 is parallel to the x-axis and intersects the gate structure 150. Each gate finger 332 contacts at least one gate channel 331. Each gate finger 332 is electrically connected directly or through a gate contact structure to the gate electrodes 155 of a plurality of gate structures 150. Each gate electrode 155 may be directly connected to a plurality of gate fingers 332.

[0125] The first load metallization 310 includes a load pad 315, an edge conductor 311, a load contact structure, and an edge contact structure. The load pad 315 may include a thin layer portion and a power metallization layer formed on the thin layer portion. The thin layer portion may include element titanium, titanium compounds such as titanium nitride (TiN), element tantalum (Ta), and / or tantalum compounds such as tantalum nitride (TaN). The power metallization portion may include element copper (Cu), copper alloy, element aluminum (Al), aluminum alloy, or copper-aluminum alloy. The power metallization portion of the load pad 315 and the thick metallization portion of the gate pad 335 may have the same structural configuration.

[0126] The load pad 315 may cover the gate finger 332. Alternatively, the load pad 315 may include a plurality of interconnected load pad portions, wherein the gate finger 332 is formed in the gap between adjacent load pad portions.

[0127] Edge conductor 311 can form a frame surrounding load pad 315, wherein portions of the frame are formed between gate channels 3311, 3312 and the chip edge. Edge conductor 311 includes a thin layer portion and may include power metallization formed on the thin layer portion. The thin layer portion of edge conductor 311 and the thin layer portion of load pad 315 may have the same structural configuration and may form a continuous structure extending through the gap 337 in the gate channel frame.

[0128] The silicon carbide device 500 may include at least one of a first clamping portion 801 formed along a first gate runner 3311, a second clamping portion 802 formed along the edge of a gate pad 335, and a third clamping portion 803 formed along a second gate runner 3312.

[0129] The first clamping portion 801 may extend along one or both first gate channels 3311. A single portion of the first clamping portion 801 may be formed along each first gate channel 3311. The single portion may extend across at least half or at least 90% of the length of the first gate channel 3311. More than one portion may be formed along each first gate channel 3311.

[0130] The second clamping portion 802 may extend along one, two, three, or all edges of the gate pad 335. The second clamping portion 802 may be a continuous structure or may include two or more laterally separated portions.

[0131] The third clamping portion 803 may extend along one or both second gate channels 3312. A single portion of the third clamping portion 803 may be formed along each second gate channel 3312. The single portion may extend across at least half or at least 90% of the length of the second gate channel 3312. More than one portion may be formed along each second gate channel 3312.

[0132] The silicon carbide device 500 may include only the first clamping portion 801, the second clamping portion 802, or the third clamping portion 803, and may include any combination of two of the clamping portions 801, 802, and 803, or may include all three clamping portions 801, 802, and 803.

[0133] Figure 6A A first clamping portion 801 is shown, the first clamping portion 801 having extending to, as Figure 3A and Figure 4 The floating well 410 shown includes a first clamping region 411 and a second clamping region 412. The first clamping region 411 is formed directly below a first gate channel 3311 having a longitudinal axis parallel to the y-axis. The second clamping region 412 is formed directly below a portion of the edge conductor 311 between the first gate channel 3311 and the lateral surface 103 of the silicon carbide body 100. A first load contact structure 319 forms a low-resistance ohmic contact between a load pad 315 and a doped region 120 located on the side of the first gate channel 3311 opposite to the edge conductor 311. The second load contact structure 319 forms a low-resistance ohmic contact between the edge conductor 311 and the doped region 120 via a heavily doped contact region 129. The heavily doped contact region 129 is laterally separated from the floating well 410 by a lighter doped portion of the doped region 120.

[0134] The doped region 120 includes a laterally spaced guard ring 127 that extends from the first main surface 101 into the silicon carbide body 100 between the floating well 410 and the lateral surface 103. A dielectric passivation layer 220 extends inward from the lateral surface 103 beyond the outer edge of the load pad 315 to cover the edge conductor 311 and the first gate channel 3311. An imide layer 230 may cover a portion of the passivation layer 220.

[0135] exist Figure 6B In this configuration, the floating well 410 is formed below the first gate channel 3311 and is absent below the edge conductor 311. An edge contact structure 318 forms an ohmic contact between the edge conductor 311 and the doped region 120. The ohmic contact with the doped region 120 can be formed on the opposite side of the first clamping region 411, such as... Figure 6B As shown. Alternatively, the ohmic contact between the load pad 315 and the doped region 120 may be absent, and the transistor cell TC may be formed closer to the floating well 410 (not shown).

[0136] The length of the floating well 410 along the x-axis can be as short as possible to reduce the ohmic resistance between the portions of the doped region 120 on opposite sides of the floating well 410. Sufficiently low resistance in the horizontal portion 120h of the doped region 120 between the floating well 410 and the drain / drift region 130 can prevent latch-up during dynamic switching of the transistor cell TC.

[0137] Figure 7 A clamping portion 800 with a first clamping region 411 is shown directly below the gate conductor 331, the first clamping region 411 extending parallel to the gate electrode 150 between adjacent pad portions 3151, 3152 of the separated load pad 315.

[0138] Figure 8A and 8B A second clamping portion 802 is shown, wherein a first clamping region 411 is formed directly below the outside of the gate pad 335, and a second clamping region 412 is formed directly below a portion of the load pad 315 facing the gate pad 335. A floating well 410 spans the gap between the load pad 315 and the gate pad 335. A doped region 120 can extend from the gate structure 150 closest to the gate pad 335 to below the gate pad 335.

[0139] exist Figure 9A and Figure 9B In this configuration, the floating well 410 does not extend below the load pad 315. The load contact structure 319 closest to the gate pad 335 forms a low-resistance ohmic contact with the vertical portion 120V of the doped region 120.

Claims

1. A silicon carbide device, comprising: A transistor cell (TC) includes a gate electrode (155) and a source region (110) having a first conductivity type, wherein the source region (110) is formed in a silicon carbide body (100); A doped region (120) having a second conductivity type, wherein the doped region (120) includes a second clamping region (412), wherein the second clamping region (412) has the second conductivity type, and wherein a first low-resistance ohmic path (901) electrically connects the second clamping region (412) and the source region (110). A floating well (410) having the first conductivity type, wherein the floating well (410) extends from the first main surface (101) of the silicon carbide body (100) into the doped region (120), and wherein the floating well (410) and the doped region (120) form a pn junction; and A first clamping region (411) having the second conductivity type, wherein the first clamping region (411) extends into the floating trap (410), and wherein a second low-resistance ohmic path (902) electrically connects the first clamping region (411) and the gate electrode (155). The second clamping region (412) extends into the floating trap (410).

2. The silicon carbide device according to claim 1, in, The second low-resistance ohmic path (902) includes a gate metallization (330), wherein the gate metallization (330) is electrically connected to the gate electrode (155), and wherein the gate metallization (330) and the first clamping region (411) form a low-resistance ohmic contact.

3. The silicon carbide device according to claim 1 or 2, in, The first low-resistance ohmic path (901) includes a first load metallization (310), wherein the first load metallization (310) and the source region (110) form a low-resistance ohmic contact, and wherein the first load metallization (310) and the doped region (120) form a low-resistance ohmic contact.

4. The silicon carbide device according to claim 3, in, The first load metallization portion (310) and the second clamping region (412) form a low-resistance ohmic contact.

5. The silicon carbide device according to claim 4, in, The first clamping region (411) and the second clamping region (412) extend from the first main surface (101) of the silicon carbide body (100) into the silicon carbide body (100).

6. The silicon carbide device according to claim 4 or 5, in, The floating well (410) includes a main portion (414) and an enhancement portion (415), wherein the average net dopant concentration in the enhancement portion (415) is higher than the average net dopant concentration in the main portion (414) and lower than the average net dopant concentration in the source region (110), and wherein a first portion of the enhancement portion (415) is located between the first clamping region (411) and the second clamping region (412).

7. The silicon carbide device according to claim 6, in, The first portion of the reinforcement (415) extends from the first clamping region (411) to the second clamping region (412).

8. The silicon carbide device according to claim 6, in, The reinforcement portion (415) laterally surrounds the first clamping region (411) and the second clamping region (412).

9. The silicon carbide device according to claim 6, in, The reinforcing portion (415) is laterally separated from the lateral sidewall of the floating trap (410).

10. The silicon carbide device according to claim 1, in, The bidirectional clamp (800), which includes the first clamping region (411), the floating trap (410), and the second clamping region (412), is configured to carry a breakdown current of at least 0.5 A.

11. The silicon carbide device according to claim 1, in, The second low-resistance ohmic path (902) includes gate conductors (331, 332) that intersect with the gate electrode (155). A low-resistance ohmic contact is formed between the gate conductors (331, 332) and the gate electrode (155), and Another low-resistance ohmic contact is formed between the gate conductors (331, 332) and the first clamping region (411).

12. The silicon carbide device according to claim 11, in, The gate conductors (331, 332) include a first gate channel (3311) having a longitudinally extending strip parallel to the y-axis and a second gate channel (3312) having a longitudinally extending strip parallel to the x-axis. The first low-resistance ohmic path (901) includes an edge conductor (311) and a load pad (315). The edge conductor (311) forms an opening frame around the load pad (315). The frame is partially formed between each of the first gate channel (3311) and the second gate channel (3312) and the lateral surface (103) of the silicon carbide body (100), and A low-resistance ohmic contact is formed between the edge conductor (311) and a portion of the doped region (120).

13. The silicon carbide device according to claim 12, in, The portion of the doped region (120) is the second clamping region (412).

14. The silicon carbide device according to claim 1, in, The first low-resistance ohmic path (901) includes a load pad (315), and A low-resistance ohmic contact is formed between the load pad (315) and the doped region (120).

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