Structure for improving the breakdown voltage of SOI lateral power devices based on low carrier lifetime

Abstract

The present invention provides a structure for improving the breakdown voltage of SOI lateral power devices based on low carrier lifetime, which includes a source electrode, a gate electrode, and a drain electrode on the structure; there are p+ and n+ regions under the source electrode, the p+ region is used to eliminate the parasitic NPN transistor effect, and the n+ region is used to collect electrons flowing from the channel; there is a P-well formed by double diffusion under the gate electrode, which is an n-channel; when the gate voltage is greater than the threshold voltage, an electron layer is formed under the gate oxide layer and the device is turned on; the drain is under an n+ region; between the gate electrode and the drain electrode is a drift region, which is used to improve the breakdown voltage when the device is turned off; below the drift region is a low carrier lifetime layer; below the low carrier lifetime layer is a buried oxide layer, which electrically isolates the drift region and the substrate; below the buried oxide layer is a P-type substrate, and the bottom of the device is a substrate electrode. The invention is widely applied to high-voltage SOI lateral power devices and integrated circuits; it improves the breakdown voltage of SOI power devices at a relatively low cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of SOI lateral power devices, and particularly relates to a structure for improving the breakdown voltage of SOI lateral power devices based on low carrier lifetime. Background Art

[0002] SOI lateral power devices have advantages such as high speed, low power consumption, and radiation resistance, which enable them to be widely used in intelligent power integrated circuits. However, their relatively low breakdown voltage hinders their application in high-voltage power integrated circuits. Many researchers have proposed many new structures to solve this problem. Currently, the vast majority of research focuses on how to improve the static breakdown voltage, while SOI lateral power devices are often used as switching devices, especially when operating at relatively high switching frequencies. Therefore, the dynamic breakdown voltage index is also very important.

[0003] Research shows that when the silicon thickness is less than 0.5 microns, the longitudinal critical breakdown electric field of silicon will increase rapidly as the silicon thickness decreases. Using this principle, ultra-thin SOI devices combined with the drift region linear variable doping technology can greatly improve the static breakdown voltage of the devices. The disadvantages of this technology are as follows: 1. The doping of the drift region near the source end is too low, resulting in too large a specific on-resistance. Moreover, if optimized according to the dynamic breakdown voltage, the doping concentration of the drift region will be further reduced, thereby further increasing the specific on-resistance; 2. This method only improves the longitudinal critical breakdown electric field, and the longitudinal critical breakdown electric field is very sensitive to the thickness of the drift region, while it is very difficult to process an ultra-thin SOI layer with a uniform thickness, making the device cost too high.

[0004] The existing technology of ultra-thin SOI devices combined with the drift region linear variable doping technology has the following disadvantages:

[0005] 1. The ultra-thin SOI layer only improves the longitudinal breakdown electric field, and the surface transverse electric field is more likely to increase at both the source and drain ends;

[0006] 2. It is necessary to use linear variable doping to optimize the transverse electric field. As a result, the doping concentration of the drift region near the source end is too low, making the specific on-resistance too large;

[0007] 3. When optimized according to the dynamic breakdown voltage, the doping concentration of the drift region will be further reduced, and the specific on-resistance will be further increased;

[0008] 4. When the device is in the on state, the high resistance near the source end will cause high temperature, reducing the performance and reliability of the device;

[0009] 5. The ultra-thin SOI process is already relatively difficult to implement, and it is even more difficult to use linear variable doping in the drift region, greatly increasing the device cost;

[0010] The prior art etches grooves on the buried oxide layer. When the device is turned off, these grooves will trap positively charged holes, increasing the electric field in the buried oxide layer, thereby improving the breakdown voltage of the device. The disadvantages of this technology:

[0011] 1. The breakdown voltage of the device is related to the concentration of trapped charges in the groove and the density of the grooves. In device processing, it is required that the groove depth be deep enough and the groove pitch be small enough to obtain a high breakdown voltage. However, this requirement will increase the device processing difficulty and cost.

[0012] 2. For dynamic breakdown voltage, when the device is turned off, an electron inversion layer does not immediately appear under the buried oxide layer, but a deep depletion layer appears. This situation results in a relatively low concentration of trapped holes in the groove, which has a weak effect on enhancing the electric field of the buried oxide layer and is not very helpful for improving the dynamic breakdown voltage. Summary of the Invention

[0013] To improve the breakdown voltage of SOI lateral power devices, including both static and dynamic breakdown voltages, a silicon layer with a low carrier lifetime is introduced between the drift region and the buried oxide layer. When designing the breakdown voltage of SOI lateral power devices, device parameters are usually optimized to make the breakdown occur at the silicon side of the interface between the top silicon layer and the buried oxide layer under the drain electrode. The introduced silicon layer with a low carrier lifetime can just increase the critical breakdown electric field at the breakdown point of the device, thereby improving the breakdown voltage of the device. The simulation results show that this method is effective for improving both dynamic and static breakdown voltages, and there is no need to use an ultra-thin SOI layer with great processing difficulty.

[0014] The present invention solves the following problems:

[0015] 1. Keep the doping concentration of the drift region uniform, so that the on-resistance near the source end does not increase, and reduce the device implementation process difficulty;

[0016] 2. Increase the critical breakdown electric field at the silicon side of the interface between the top silicon layer and the buried oxide layer under the drain, so that the device can improve the breakdown voltage without an ultra-thin thickness of the top silicon layer. This method is effective for both static and dynamic breakdown voltages.

[0017] The specific technical solution is as follows:

[0018] A structure for improving the breakdown voltage of SOI lateral power devices based on a low carrier lifetime, including a source electrode, a gate electrode, and a drain electrode on the structure;

[0019] There are p+ and n+ regions under the source electrode. The p+ region is used to eliminate the parasitic NPN transistor effect, and the n+ region is used to collect electrons flowing from the channel;

[0020] There is a P well formed by double diffusion under the gate electrode, which is an n-channel; when the gate voltage is greater than the threshold voltage, an electron layer is formed under the gate oxide layer and the device conducts;

[0021] The drain is an n+ region below;

[0022] The drift region is between the gate electrode and the drain electrode, which is used to improve the breakdown voltage when the device is turned off;

[0023] Below the drift region is a low carrier lifetime layer, which is obtained by introducing deep level recombination centers into N-type silicon;

[0024] Below the low carrier lifetime layer is the buried oxide layer, which electrically isolates the drift region from the substrate;

[0025] Below the buried oxide layer is the P-type substrate, and the bottom of the device is the substrate electrode.

[0026] The length of the drift region is 30 μm, the thickness of the drift region is 4 μm, the thickness of the low carrier lifetime layer is 2 μm, and the thickness of the buried oxide layer is 3 μm.

[0027] When the device is turned off, the drift region is depleted to form a barrier region. Electron-hole pairs are generated in the barrier region. Under the action of a strong electric field, they gain sufficient kinetic energy and then collide with lattice atoms to generate more electron-hole pairs. When the electric field in the barrier region is high enough, the number of electrons and holes generated by collisions will increase sharply, and the current they form exceeds 10 -7 A and the device is broken down. In the present invention, by introducing deep level recombination centers, the electron and hole lifetimes are reduced, the increase in the number of electron-hole pairs in the barrier region is suppressed, and thus the critical breakdown electric field of silicon is increased. The concentration of the recombination centers is inversely proportional to the carrier lifetime. For example, when gold is doped in N-type silicon, its concentration increases from 10 14 cm -3 to 10 17 cm -3 , and the carrier lifetime decreases from 10 -7 s to 10 -9 s. Of course, increasing the concentration of gold can further reduce the carrier lifetime.

[0028] The present invention can be widely applied to high-voltage SOI lateral power devices and integrated circuits; the present invention improves the breakdown voltage of SOI power devices at a lower cost. Compared with the traditional methods for improving the breakdown voltage of SOI, the device process of the present invention is easier to implement, has a lower cost, and is effective for both static and dynamic breakdown voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic structural diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0030] The specific technical solution of the present invention will be described in conjunction with the accompanying drawings.

[0031] A structure for improving the breakdown voltage of an SOI lateral power device based on a low carrier lifetime, as Figure 1 shown, includes three electrodes: a source electrode 1, a gate electrode 2, and a drain electrode 3 on the structure;

[0032] There are p+ and n+ regions under the source electrode 1. The p+ region is used to eliminate the parasitic NPN transistor effect, and the n+ region is used to collect the electrons flowing from the channel.

[0033] There is a P well formed by double diffusion under the gate electrode 2, which is an n-channel. When the gate voltage is greater than the threshold voltage, an electron layer is formed under the gate oxide layer, and the device is turned on.

[0034] The region under the drain is an n+ region.

[0035] The region between the gate electrode 2 and the drain electrode 3 is a drift region, which is used to improve the breakdown voltage when the device is turned off.

[0036] Below the drift region 4 is a low carrier lifetime layer, which is obtained by introducing deep level recombination centers (such as gold doping) in N-type silicon, and the thickness is more than 2μm. The critical breakdown electric field of silicon in the low carrier lifetime layer is higher than that of silicon in the drift region 4. The key breakdown point of the SOI device is at the silicon side of the interface between the silicon and the buried oxide layer under the drain electrode 3. Therefore, the device structure of the present invention has a higher breakdown voltage than the conventional SOI device.

[0037] In order to reduce the influence of the low carrier lifetime semiconductor material on other performance of the device, the low carrier lifetime layer is only located between the drift region 4 and the buried oxide layer.

[0038] Below the low carrier lifetime layer 5 is the buried oxide layer 6, which provides good electrical isolation between the drift region 4 and the substrate.

[0039] Below the buried oxide layer 6 is the P-type substrate 7, and the bottom of the device is the substrate electrode.

[0040] What the present invention improves is the critical breakdown electric field at the key breakdown point of the device. Therefore, it is not only effective in improving the lateral and vertical breakdown voltages, but also effective in improving the dynamic and static breakdown voltages. The new device structure parameters are: the length of the drift region 4 is 30um, the thickness of the drift region 4 is 4um, the thickness of the low carrier lifetime layer 5 is 2um, and the thickness of the buried oxide layer 6 is 3um. By reducing the lifetimes of electrons and holes in the "low carrier lifetime layer 5", the static breakdown voltage of the device can reach 579V, while the conventional SOI device under the same parameters is only 414V, and the new structure is 39.85% higher than the conventional structure.

[0041] The main process of the device implementation is: doping gold in N-type silicon to form the low carrier lifetime layer 5; growing and depositing SiO 2 ; planarizing SiO 2 ; bonding with the P-type substrate 7. The remaining processes are the same as those of the conventional SOI device.

Claims

1. Structure for improving breakdown voltage of SOI lateral power device based on low carrier lifetime, including source electrode (1), gate electrode (2), and drain electrode (3) on the structure; There are p+ and n+ regions under the source electrode (1). The p+ region is used to eliminate the parasitic NPN transistor effect, and the n+ region is used to collect electrons flowing from the channel; There is a P well formed by double diffusion under the gate electrode (2), which is an n-channel. When the gate voltage is greater than the threshold voltage, an electron layer is formed under the gate oxide layer and the device conducts; The region under the drain electrode (3) is an n+ region; The drift region (4) is between the gate electrode (2) and the drain electrode (3), which is used to improve the breakdown voltage when the device is turned off; Its characteristics are as follows: Under the drift region (4) is a low carrier lifetime layer (5), which is obtained by introducing deep level recombination centers into N-type silicon; Below the low carrier lifetime layer (5) is a buried oxide layer (6), which electrically isolates the drift region (4) from the substrate; Below the buried oxide layer (6) is a P-type substrate (7), and the bottom of the device is the substrate electrode; By introducing a silicon layer with low carrier lifetime between the drift region (4) and the buried oxide layer (6); when designing the breakdown voltage of the SOI lateral power device, optimize the device parameters so that breakdown occurs at the silicon side of the interface between the top silicon and the buried oxide layer under the drain electrode; The introduced silicon layer with low carrier lifetime increases the critical breakdown electric field at the breakdown of the device, thereby improving the breakdown voltage of the device.

2. Structure for improving breakdown voltage of SOI lateral power device based on low carrier lifetime according to claim 1, Its characteristics are, The length of the drift region (4) is 30um, the thickness of the drift region (4) is 4um, the thickness of the low carrier lifetime layer (5) is 2um, and the thickness of the buried oxide layer (6) is 3um.

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