Semiconductor device

Abstract

A semiconductor device (1) includes a p-type region (14) including a superlattice pseudomorphically stacked region (14a, 14b) in which first layers (14a) and second layers (14b) alternate. The first layers include a gallium oxide-based semiconductor. The second layers include a p-type semiconductor made of a different material than the first layers.

Description

Technical Field

[0001] The technology disclosed in this article relates to a semiconductor device made of gallium oxide semiconductor. Background Technology

[0002] Semiconductor devices manufactured using gallium oxide-based semiconductors are expected to exhibit high withstand voltage, low loss, and high thermal resistance. Patent documents 1 to 3 disclose a semiconductor device manufactured using gallium oxide-based semiconductors.

[0003] Existing technical documents

[0004] [Patent Literature]

[0005] [Patent Document 1] JP 2018-170509 A

[0006] [Patent Document 2] JP 2019-36593 A

[0007] [Patent Document 3] JP 2019-192871 A Summary of the Invention

[0008] As noted in Patent Documents 1 to 3, a technique for forming highly active p-type gallium oxide-based semiconductors has not yet been established, and semiconductor devices with p-type regions exhibiting excellent conductivity have not been manufactured. One object of this specification is to provide a semiconductor device having a p-type region with excellent conductivity in a semiconductor device manufactured using gallium oxide-based semiconductors.

[0009] The semiconductor device in this embodiment includes a p-type region having a region made of a superlattice pseudo-mixed crystal in which a first layer and a second layer are alternately stacked. The first layer is made of a gallium oxide-based semiconductor. The second layer is a p-type semiconductor made of a material different from that of the first layer.

[0010] In the aforementioned semiconductor device, the p-type region is made of a superlattice pseudo-mixed crystal in which gallium oxide-based semiconductors and p-type semiconductors are alternately stacked. Therefore, the thickness of each layer of the gallium oxide-based semiconductor and the p-type semiconductor is sufficiently thin to possess the characteristics of a superlattice pseudo-mixed crystal. Thus, because these thicknesses are thin enough to allow hole carriers to provide a tunnel effect, the entire p-type region can possess p-type conductivity. As described above, the semiconductor device can be provided with a p-type region having excellent conductivity. Attached Figure Description

[0011] The above and other objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings:

[0012] Figure 1 This is a schematic cross-sectional view showing the main parts of the semiconductor device of the first embodiment;

[0013] Figure 2 It is a schematic diagram showing the electric field distribution near the boundary of a pn junction;

[0014] Figure 3 This is a schematic cross-sectional view showing the main parts of the semiconductor device of the second embodiment;

[0015] Figure 4 This is a schematic cross-sectional view showing the main parts of the semiconductor device of the third embodiment;

[0016] Figure 5 This is a schematic cross-sectional view showing the main parts of the semiconductor device of the fourth embodiment; and

[0017] Figure 6 This is a schematic cross-sectional view showing the main parts of the semiconductor device of the sixth embodiment. Detailed Implementation

[0018] The following lists the technical elements disclosed in this article. Each of these technical elements is independently useful.

[0019] The semiconductor device disclosed in this embodiment may include a p-type region having a region made of a superlattice pseudo-mixed crystal in which a first layer and a second layer are alternately stacked. The first layer is made of a gallium oxide-based semiconductor. The gallium oxide-based semiconductor includes gallium oxide and gallium oxide in which some atomic positions are replaced by other atoms. The second layer is a p-type semiconductor made of a material different from that of the first layer. There are no particular limitations on the crystal structure of the second layer, and various semiconductors with p-type conductivity can be used for the second layer. For example, the crystal structure of the second layer may include at least one selected from the group consisting of N, Mg, Zn, Ni, Cu, Rh, Ir, Cr, Fe, Co, Li, Bi, In, Al, Ga, P, Mn, As, Sb, S, and Se. The second layer including these atoms has a crystal structure for which techniques for forming highly active p-type atoms have been established.

[0020] The second layer can be made of a p-type oxide semiconductor or a p-type non-oxide Ga-based semiconductor. When the second layer is made of an oxide semiconductor, it may include at least one selected from the group consisting of NiO, Cu2O, Rh2O3, Ir2O3, Cr2O3, ZnMgO, ZnO, ZnGa2O4, ZnRh2O4, Fe2O3, ZnCo2O4, Li2O, Bi2O3, In2O3, and Mn2O3. When the second layer is made of a non-oxide Ga-based semiconductor, it may include at least one selected from the group consisting of GaN, GaP, GaAs, GaSb, CuGaS2, and Ga2Se3. The bandgap width of these example materials is narrower than that of the gallium oxide-based semiconductor in the first layer. Generally, a narrow bandgap width tends to exhibit p-type conductivity. Therefore, for example, when using only these example materials, regions with excellent p-type conductivity can be formed. Here, the regions formed solely by these example materials exhibit narrow bandgap widths and low dielectric breakdown electric field strengths. In the semiconductor device of this embodiment, the p-type region comprises a region made of superlattice pseudo-mixed crystals in the first and second layers. Therefore, the bandgap width of the p-type region is provided by the bandgap width between the material of the first layer and the material of the second layer. Thus, compared to the case where the p-type region comprises only the second layer (i.e., only the materials of the examples described above), the p-type region can have a wide bandgap width and a high dielectric breakdown electric field strength.

[0021] The semiconductor device may also include an n-type region in contact with the p-type region. Because the p-type region has a high dielectric breakdown electric field strength, breakdown at the pn junction surface between the p-type and n-type regions can be suppressed. The semiconductor device of this embodiment can have high voltage withstand characteristics.

[0022] In this semiconductor device, the pseudo-mixed crystal ratio, which is the ratio of the first layer to the unit volume of the p-type region, can monotonically decrease with increasing distance from the n-type region. For example, the thickness of the first layer can decrease with increasing distance from the n-type region. Alternatively or additionally, the thickness of the second layer can increase with increasing distance from the n-type region. By adjusting the pseudo-mixed crystal ratio of the first and second layers according to the electric field distribution in the p-type region, the semiconductor device of this embodiment achieves both high voltage withstand capability and low resistance.

[0023] At the pn junction boundary between the p-type and n-type regions, the first layer of the p-type region can contact the n-type region. Breakdown at the pn junction boundary between the p-type and n-type regions is suppressed. The semiconductor device of this embodiment can have high voltage withstand characteristics.

[0024] Example

[0025] In the following description, the techniques disclosed in this embodiment will be used as an example to illustrate the application of the techniques disclosed herein to the p-type anode region. However, the techniques disclosed herein are not limited to semiconductor devices of this type and can be applied to various p-type regions included in each semiconductor device. As an example, the techniques disclosed herein can be applied to the p-type regions (e.g., body regions and guard ring regions) of MOSFETs and IGBTs.

[0026] (First Embodiment)

[0027] like Figure 1 As shown, diode 1 includes a semiconductor substrate 10, a cathode electrode 22 configured to cover the lower surface of the semiconductor substrate 10, and an anode electrode 24 covering a portion of the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 has an n-type cathode region 12 and a p-type anode region 14. Diode 1 is a pn junction diode, wherein the n-type cathode region 12 and the p-type anode region 14 form a pn junction surface 13, and diode 1 has a rectification function that causes current to flow only from the anode electrode 24 to the cathode electrode 22. The cathode region 12 is an example of an n-type region, and the anode region 14 is an example of a p-type region.

[0028] The cathode region 12 is exposed on the lower surface of the semiconductor substrate 10 and is in ohmic contact with the cathode electrode 22. The crystal structure of the cathode region 12 is made of gallium oxide (Ga₂O₃). The crystal phase is not particularly limited, or it can be, for example, an α phase or a β phase. Furthermore, gallium sites or oxygen sites can be replaced by another atom. For example, the crystal structure of the cathode region 12 can be made of (InAlGa)₂O₃.

[0029] An anode region 14 is disposed on the surface of the cathode region 12, exposed on the upper surface of the semiconductor substrate 10, and in ohmic contact with the anode electrode 24. The anode region 14 has a plurality of first layers 14a and a plurality of second layers 14b, which are stacked alternately. The first layers 14a and the second layers 14b are formed by alternately growing crystals from the surface of the anode region 14 using known crystal growth techniques. Known crystal growth techniques include, for example, CVD (including atomized CVD) or MBE.

[0030] The first layer 14a is made of a gallium oxide-based semiconductor. For example, the crystal structure of the first layer 14a is made of gallium oxide (Ga₂O₃). The crystal phase is not particularly limited, or it can be, for example, an α phase or a β phase. Furthermore, gallium sites or oxygen sites can be replaced by another atom. For example, the crystal structure of the first layer 14a can be made of (InAlGa)₂O₃.

[0031] The first layer 14a is undoped or p-type. When the first layer 14a is p-type, the dopant introduced into the first layer 14a includes at least one selected from the group consisting of N, Mg, Zn, Ni, Cu, Rh, Ir, Cr, Fe, Co, Li, Bi, H, Be, Na, P, S, K, Ca, Mn, As, Se, Rb, Sr, Ru, Pd, Ag, Cd, Sb, Te, Cs, Ba, Pt, Au, Hg, Ti, Pb, Po, Fr, and Ra. The dopant can be introduced during crystal growth or after crystal growth using ion implantation techniques. Techniques for forming highly active p-type gallium oxide have not yet been established. Therefore, the activation rate of the dopant included in the first layer 14a is low.

[0032] The crystal structure of the second layer 14b is a metal oxide semiconductor or a non-oxide Ga-based semiconductor including at least one selected from the group consisting of N, Mg, Zn, Ni, Cu, Rh, Ir, Cr, Fe, Co, Li, Bi, In, Al, Ga, P, Mn, As, Sb, S, and Se. As the material for the second layer 14b, a metal oxide semiconductor or a non-oxide Ga-based semiconductor with established techniques for forming highly active p-type crystals is used. Therefore, the second layer 14b is a highly active p-type crystal. Dopants can be introduced during crystal growth or after crystal growth using ion implantation techniques.

[0033] When the second layer 14b is made of a metal oxide semiconductor, the second layer 14b may include at least one selected from the group consisting of NiO, Cu2O, Rh2O3, Ir2O3, Cr2O3, ZnMgO, ZnO, ZnGa2O4, ZnRh2O4, Fe2O3, ZnCo2O4, Li2O, Bi2O3, In2O3, and Mn2O3. When the second layer 14b is a non-oxide Ga-based semiconductor, the second layer 14b may include at least one selected from the group consisting of GaN, GaP, GaAs, GaSb, CuGaS2, and Ga2Se3.

[0034] The thickness of each of the first layer 14a and the second layer 14b (i.e., the thickness in the stacking direction and the thickness in the vertical direction of the pattern) is formed to be extremely thin. Therefore, the anode region 14 formed by alternately stacking the first layer 14a and the second layer 14b has the characteristics of a superlattice pseudo-mixed crystal. The thickness of each of the first layer 14a and the second layer 14b is not particularly limited, as long as the characteristics of a superlattice pseudo-mixed crystal can be obtained, and for example, 5 nm or less, 4 nm or less, 3 nm or less, or 2 nm or less.

[0035] In this embodiment, the term "superlattice pseudo-mixed crystal" refers to a state in which the band gaps of the anode region 14, comprising a first layer 14a and a second layer 14b made of different materials, are identified as having an equivalent band gap. Specifically, when the anode region 14 is measured using a photoluminescence method, it is evaluated as a superlattice pseudo-mixed crystal state when a single light peak is observed after excluding the influence of crystal defects and impurities.

[0036] As described above, in diode 1, the thickness of each of the first layer 14a and the second layer 14b constituting the anode region 14 is formed so thin that it possesses the characteristics of a superlattice pseudo-mixed crystal. Therefore, because these thicknesses are so thin that hole carriers can tunnel through, the entire anode region 14 can have p-type conductivity. As described above, although the material of the first layer 14a constituting the anode region 14 is gallium oxide (Ga2O3), this material can essentially have p-type conductivity. Because diode 1 contains an anode region 14 with excellent p-type conductivity, it can operate with low resistance.

[0037] Furthermore, due to the superlattice pseudo-mixed crystal characteristics of the anode region 14, it can possess the following properties: The band gap width of the superlattice pseudo-mixed crystal anode region 14 is at a level between the band gap width of the first layer 14a and the band gap width of the second layer 14b. For example, when the first layer 14a is made of β-gallium oxide (β-Ga₂O₃), its band gap width is 4.5 eV to 4.9 eV. The band gap width of the second layer 14b varies depending on the metal oxide semiconductor used, but it is narrower than the band gap width of the first layer 14a. For example, when the second layer 14b is made of nickel oxide (NiO), its band gap width is narrower than 4 eV. When the first layer 14a is β-gallium oxide (β-Ga₂O₃) and the second layer 14b is nickel oxide (NiO), the band gap width of the superlattice pseudo-mixed crystal anode region 14 is 4 eV or greater.

[0038] As described above, since the anode region 14 is made of a superlattice pseudo-mixed crystal of the first layer 14a and the second layer 14b, it has a wider band gap and a higher dielectric breakdown electric field strength compared to a structure in which the anode region 14 is made only of the second layer 14b (i.e., only of nickel oxide (NiO)). As a result, diode 1 can have high voltage withstand characteristics.

[0039] Figure 2The electric field distribution near the surface of the pn junction of diode 1 according to this embodiment and Comparative Examples 1 and 2 is schematically shown. The upper side of the pn junction corresponds to the area of ​​the anode region 14, and the lower side of the pn junction corresponds to the area of ​​the cathode region 12. Comparative Example 1 is an example in which the entire anode region 14 is made only of the material of the first layer 14a (i.e., the entire anode region 14 is made only of β-gallium oxide (β-Ga2O3)). Comparative Example 2 is an example in which the entire anode region 14 is made only of the material of the second layer 14b (i.e., the entire anode region 14 is made only of nickel oxide (NiO)). As for Comparative Example 1, since a technology for forming highly active p-type gallium oxide has not yet been established, such a diode cannot be realized at present.

[0040] E ref1 E ref2 and E embodiment The dielectric breakdown strengths are represented by E for Comparative Example 1, Comparative Example 2, and this embodiment, respectively. In Comparative Example 1, since the material used for the anode region 14 is β-gallium oxide (β-Ga2O3) with a wide bandgap, the dielectric breakdown strength E is... ref1 High. In Comparative Example 2, since the material used for the anode region 14 is nickel oxide (NiO) with a narrow band gap, the dielectric breakdown strength E is high. ref2 Low. In this embodiment, since the material used for the anode region 14 is a superlattice pseudo-mixed crystal of β-gallium oxide (β-Ga₂O₃) and nickel oxide (NiO), the dielectric breakdown strength E is low. embodiment Between E ref1 With E ref2 between.

[0041] In this type of diode, the electric field strength peaks at the pn junction surface. Therefore, breakdown occurs when the electric field at the pn junction surface exceeds the dielectric breakdown strength. Comparative Example 1 has the highest dielectric breakdown strength E. ref1 Therefore, the voltage that can be maintained between the anode and cathode (i.e., the integrated value of the electric field distribution between the anode and cathode, corresponding to the area of ​​the triangle of the electric field distribution) is large. However, Comparative Example 1 is a diode that cannot be manufactured under these conditions. Comparative Example 2 has the lowest dielectric breakdown strength E. ref2 Therefore, the voltage that can be maintained is small. Consequently, Comparative Example 2 cannot possess high withstand voltage characteristics. This embodiment has a higher dielectric breakdown strength E than Comparative Example 2. embodiment Therefore, this embodiment can have higher voltage withstand characteristics than Comparative Example 2.

[0042] As described above, the anode region 14 of diode 1 is made of a superlattice pseudo-mixed crystal formed by alternately stacking a first layer 14a with a wide bandgap and a second layer 14b with excellent p-type conductivity. Therefore, the material properties of the anode region 14 can have both a wide bandgap and good p-type conductivity. In diode 1, by constructing the anode region 14 as a superlattice pseudo-mixed crystal, it is possible to simultaneously achieve high voltage withstand and low resistance.

[0043] Furthermore, in diode 1 of this embodiment, the first layer 14a of the anode region 14 is located at the surface of the pn junction and contacts the n-type cathode region 12. Since the first layer 14a, made of β-gallium oxide (β-Ga2O3) and having a wide bandgap, is located at the position in contact with the pn junction surface where the electric field is highest, breakdown at the pn junction surface is suppressed. Therefore, diode 1 can have high voltage withstand characteristics.

[0044] Furthermore, the diode 1 of this embodiment features good crystallinity in the anode region 14. For example, as in Comparative Example 2 above, if the entire anode region 14 is made solely of nickel oxide (NiO), the anode region 14 can exhibit good p-type conductivity. However, in Comparative Example 2, the nickel oxide (NiO) anode region 14 is a different material from the underlying β-gallium oxide (β-Ga2O3) cathode region 12. Therefore, in Comparative Example 2, the crystallinity of the anode region 14 formed on the cathode region 12 is not good, and the electrical properties may deteriorate. On the other hand, in the diode 1 of this embodiment, since the anode region 14 is a superlattice pseudo-mixed crystal of β-gallium oxide (β-Ga2O3) and nickel oxide (NiO), the crystal structure of the anode region 14 is closer to the crystal structure of the cathode region 12. Therefore, in the diode 1 of this embodiment, the anode region 14 formed on the cathode region 12 exhibits good crystallinity and good electrical properties.

[0045] Second Embodiment

[0046] exist Figure 3 In the diode 2 shown, the thickness of the first layer 14a is configured to decrease with increasing distance from the cathode region 12. Each of the plurality of second layers 14b has the same thickness. Therefore, the diode 2 is configured such that the pseudo-mixed crystal ratio, which is the ratio of the unit volume of the first layer 14a to the anode region 14, decreases monotonically with increasing distance from the cathode region 12. Also in this example, the thickness of each of the first layer 14a and the second layer 14b is formed to be thin, such that the anode region 14 exhibits superlattice pseudo-mixed crystal characteristics.

[0047] For reference Figure 2As described, in this type of diode, the electric field strength peaks at the pn junction surface between the cathode region 12 and the anode region 14, and the electric field distribution in the anode region 14 decreases with increasing distance from the pn junction surface. Figure 3 In the diode 2 shown, in response to this electric field distribution, the thickness of the first layer 14a is larger on the side near the cathode region 12, where the electric field strength is high, and smaller on the side away from the cathode region 12, where the electric field strength is low. Since the pseudo-mixed crystal ratio of the first layer 14a is significantly adjusted on the side near the cathode region 12, the diode 2 can exhibit high voltage withstand characteristics. Furthermore, since the pseudo-mixed crystal ratio of the first layer 14a is smaller on the side away from the cathode region 12, in other words, the pseudo-mixed crystal ratio of the second layer 14b is significantly adjusted, the diode 2 exhibits low resistance characteristics. Thus, the diode 2 can improve the trade-off between high voltage withstand and low resistance.

[0048] Figure 3 The diode 2 shown is constructed such that the pseudo-mixed crystal ratio of the first layer 14a decreases monotonically with increasing distance from the cathode region 12, and the thickness of the first layer 14a decreases with increasing distance from the cathode region 12. Instead of this example, each of the plurality of first layers 14a may have the same thickness, but the thickness of the second layer 14b may increase with increasing distance from the cathode region 12. Alternatively, the thickness of the first layer 14a may decrease with increasing distance from the cathode region 12, while the thickness of the second layer 14b may increase with increasing distance from the cathode region 12. The thickness of each of the first layer 14a and the second layer 14b can be appropriately adjusted, as long as the pseudo-mixed crystal ratio of the first layer 14a decreases monotonically with increasing distance from the cathode region 12.

[0049] Third Embodiment

[0050] Figure 4 The diode 3 shown is characterized in that the anode region 14 further includes a p-type capping layer 14c. The capping layer 14c is disposed on the uppermost surface of the anode region 14, exposed to the upper surface of the semiconductor substrate 10, and in ohmic contact with the anode electrode 24. The capping layer 14c is made of the same material as the second layer 14b (e.g., nickel oxide (NiO)). Therefore, the capping layer 14c is a highly active p-type. The capping layer 14c has a relatively large thickness and does not form a superlattice pseudo-mixed crystal with the first layer 14a and the second layer 14b. The capping layer 14c is sufficiently separated from the cathode region 12 and arranged corresponding to regions with low electric fields. The diode 3 with such a capping layer 14c can have low resistance characteristics.

[0051] Fourth embodiment

[0052] Figure 5The diode 4 shown is characterized in that the anode region 14 further includes an undoped or p-type spacer layer 14d. The spacer layer 14d is disposed between the cathode region 12 and the anode region 14. The spacer layer 14d is disposed on the lowermost surface of the anode region 14 and contacts the cathode region 12. The spacer layer 14d is made of the same material as the first layer 14a (e.g., β-gallium oxide (β-Ga2O3)). The spacer layer 14d has a relatively large thickness and does not form a superlattice pseudo-mixed crystal together with the first layer 14a and the second layer 14b. In the disclosed technology, a superlattice pseudo-mixed crystal region is formed in the anode region 14, thereby forming a heterojunction surface in which different types of materials are bonded. In the diode 4, due to the presence of the spacer layer 14d, the heterojunction surface is located separately from the pn junction surface 13 of the cathode region 12 and the anode region 14. Since the heterojunction surface with many interface states is formed at a location far from the pn junction surface with the greatest electric field strength, it can suppress the degradation of electrical properties.

[0053] Fifth embodiment

[0054] Figure 6 The diode 5 shown is characterized in that the cathode region 12 further includes a low-concentration layer 12a. The low-concentration layer 12a is disposed on the uppermost surface of the cathode region 12 and contacts the anode region 14. The low-concentration layer 12a is made of the same material as the other cathode regions 12 and has a lower carrier concentration than the other cathode regions 12. In this diode 5, the pn junction surface 13 between the cathode region 12 and the anode region 14 is also a heterojunction surface. However, due to the provision of the low-concentration layer 12a, leakage current through the interface state can be suppressed.

[0055] Although specific examples of the techniques disclosed in this specification have been described in detail above, these are merely examples and do not limit the scope of the claims. The techniques described in the claims include various modifications and variations of the specific examples described above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The techniques shown in this specification or drawings are capable of achieving multiple objectives simultaneously, and achieving one of these objectives is itself technically practical.

[0056] While this disclosure has been described with reference to embodiments thereof, it should be understood that this disclosure is not limited to these embodiments and constructions. This disclosure is intended to cover various modifications and equivalent arrangements. Furthermore, although various combinations and configurations have been described, other combinations and configurations, including those with more, fewer, or only a single element, are also within the spirit and scope of this disclosure.

Claims

1. A semiconductor device (1, 2, 3, 4, 5), comprising: p-type region (14), which includes superlattice pseudo-mixed crystal regions (14a, 14b) in which a first layer (14a) and a second layer (14b) are stacked alternately. The n-type region (12) in contact with the p-type region, wherein: The first layer is a p-type dopant with low activation rate and comprises a gallium oxide-based semiconductor; and The second layer includes a p-type semiconductor made of a material different from the first layer. The superlattice pseudo-mixed crystal region indicates that the band gaps of the superlattice pseudo-mixed crystal region, which includes a first layer (14a) and a second layer (14b) composed of different materials, are identified as having the same band gap. The pseudo-mixed crystal ratio, which is the ratio of the unit volume of the first layer to the p-type region, decreases monotonically with increasing distance from the n-type region.

2. The semiconductor device according to claim 1, wherein: The crystal structure of the second layer includes at least one selected from the group consisting of N, Mg, Zn, Ni, Cu, Rh, Ir, Cr, Fe, Co, Li, Bi, In, Al, Ga, P, Mn, As, Sb, S and Se.

3. The semiconductor device according to claim 2, wherein: The second layer is made of p-type oxide semiconductor or p-type non-oxide Ga-based semiconductor.

4. The semiconductor device according to claim 3, wherein: When the second layer is made of an oxide semiconductor, the second layer comprises at least one selected from the group consisting of NiO, Cu2O, Rh2O3, Ir2O3, Cr2O3, ZnMgO, ZnO, ZnGa2O4, ZnRh2O4, Fe2O3, ZnCo2O4, Li2O, Bi2O3, In2O3, and Mn2O3; and When the second layer is made of a non-oxide Ga-based semiconductor, the second layer includes at least one selected from the group consisting of GaN, GaP, GaAs, GaSb, CuGaS2 and Ga2Se3.

5. The semiconductor device according to claim 1, wherein: The thickness of the first layer decreases as the distance from the n-type region increases.

6. The semiconductor device according to claim 1, wherein: The thickness of the second layer increases with increasing distance from the n-type region.

7. The semiconductor device according to claim 1, wherein: The first layer of the p-type region contacts the n-type region at the pn junction boundary (13) between the p-type region and the n-type region.

8. The semiconductor device according to claim 1, wherein: The thickness of each of the first and second layers is 5 nm or less.

9. The semiconductor device according to claim 8, wherein: The thickness of each of the first and second layers is 2 nm or less.

10. The semiconductor device according to any one of claims 1-9, wherein: The first layer is made of β-Ga2O3.

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