LDMOS transistor with vertical floating field plate and method for manufacturing the same

Abstract

The present invention provides an LDMOS transistor with a vertical floating field plate and a preparation method thereof. The vertical floating field plate comprises a floating field plate polysilicon layer and a laminated structure. The laminated structure comprises insulating material layers and ferroelectric material layers which are alternately laminated, and the outermost layer and the innermost layer of the laminated structure are both insulating material layers. In the present invention, a ferroelectric material layer with a polarization effect is provided in a vertical floating field plate with a smaller size, so that: in an off state, the polarization effect of the ferroelectric material layer can enhance a "charge sharing" effect to obtain a higher breakdown voltage; in an on state, the polarization effect of the ferroelectric material layer can induce more electrons in a drift region to reduce the on-resistance, thereby achieving the goal of effectively reducing the on-resistance while increasing the breakdown voltage.

Description

Technical Field

[0001] The invention belongs to the field of power semiconductors and relates to an LDMOS transistor with a vertical floating field plate and a preparation method thereof. Background Art

[0002] Power semiconductor devices have been widely used in consumer electronics, computers, network communications, LED displays, electronic lighting and other fields due to their high input impedance, low loss, fast switching speed and wide safe operating area.

[0003] In power device applications, DMOS (Double Diffused Metal Oxide Semiconductor) technology has many advantages, including high current driving capability, low on-resistance (R on ) and high breakdown voltage (BV). There are two main types of DMOS transistors: Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOSFET) and Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET). Compared with common field effect transistors, LDMOS transistors have obvious advantages in key device characteristics such as gain, linearity, switching performance, heat dissipation performance, and reduction of stages. At the same time, LDMOS transistors are easily compatible with CMOS processes, so they are widely used.

[0004] In LDMOS transistor devices, breakdown voltage and on-resistance are the two most important performance parameters in power devices. For these two performance parameters, the general design requirement is that the power device should not only have a high breakdown voltage, but also have a low on-resistance to reduce power consumption. However, current power devices are restricted by the breakdown voltage and on-resistance, which hinders the further improvement of LDMOS transistor device performance.

[0005] Therefore, it is necessary to provide a novel LDMOS transistor with a vertical floating field plate and a preparation method thereof to optimize the trade-off relationship between breakdown voltage and on-resistance. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, an object of the present invention is to provide an LDMOS transistor with a vertical floating field plate and a method for preparing the same, so as to solve the problem in the prior art that it is difficult to further optimize the trade-off relationship between breakdown voltage and on-resistance, making it difficult to further improve the performance of LDMOS transistor devices.

[0007] To achieve the above objectives and other related objectives, the present invention provides an LDMOS transistor with a vertical floating field plate, the LDMOS transistor comprising:

[0008] A semiconductor substrate, wherein the semiconductor substrate comprises a first conductive type doped region;

[0009] a second conductivity type well region, the second conductivity type well region being located in the first conductivity type doped region;

[0010] a source region, the source region being located in the second conductivity type well region;

[0011] a drain region, wherein the drain region is located in the first conductivity type doping region;

[0012] A vertical floating field plate, the vertical floating field plate is located between the second conductive type well region and the drain region, and extends vertically from the surface of the first conductive type doped region, wherein the vertical floating field plate comprises a floating field plate polysilicon layer and a stacked structure, the stacked structure comprises alternately stacked insulating material layers and ferroelectric material layers, and the outermost layer and the innermost layer of the stacked structure are both the insulating material layers;

[0013] A gate structure is in contact with the source region, the second conductivity type well region and the first conductivity type doped region.

[0014] Optionally, the ferroelectric material layer includes a hafnium oxide ferroelectric layer doped with one or a combination of aluminum and zirconium.

[0015] Optionally, the stacked structure includes two layers of the ferroelectric material layer, and the thickness of each layer of the ferroelectric material layer ranges from 10 nm to 300 nm.

[0016] Optionally, M≥2 vertical floating field plates are included; and a range of a cross-sectional width W of the vertical floating field plate includes 1000nm≥W≥100nm.

[0017] Optionally, the bottom of the vertical floating field plate is located in the first conductive type doping region or extends to below the first conductive type doping region.

[0018] Optionally, it further includes a metal piece arranged corresponding to the vertical floating field plate, wherein the metal piece and the vertical floating field plate include one of connection or insulation.

[0019] The present invention also provides a method for preparing an LDMOS transistor with a vertical floating field plate, which is characterized by comprising the following steps:

[0020] Providing a semiconductor substrate, the semiconductor substrate comprising a first conductivity type doped region;

[0021] forming a second conductivity type well region in the first conductivity type doped region;

[0022] Forming a vertical floating field plate, the vertical floating field plate extending vertically from the surface of the first conductive type doped region, wherein the vertical floating field plate comprises a floating field plate polysilicon layer and a stacked structure, the stacked structure comprises alternately stacked insulating material layers and ferroelectric material layers, and the outermost layer and the innermost layer of the stacked structure are both the insulating material layers;

[0023] A gate structure, a source region and a drain region are formed, the source region is located in the second conductivity type well region, the drain region is located in the first conductivity type doped region, the gate structure is in contact with the source region, the second conductivity type well region and the first conductivity type doped region, and the vertical floating field plate is located between the second conductivity type well region and the drain region.

[0024] Optionally, the ferroelectric material layer includes a hafnium oxide ferroelectric layer doped with one or a combination of aluminum and zirconium, and the thickness of the ferroelectric material layer ranges from 10 nm to 300 nm, wherein the method of forming the ferroelectric material layer includes PVD method or ALD method.

[0025] Optionally, before forming the vertical floating field plate, a step of forming a first conductive type well region is also included.

[0026] Optionally, the method further includes the step of forming a metal member arranged corresponding to the vertical floating field plate, wherein the formed metal member and the vertical floating field plate are connected or insulated.

[0027] As described above, the LDMOS transistor with a vertical floating field plate and the preparation method thereof of the present invention, in a vertical floating field plate with a smaller size, by setting a ferroelectric material layer with a polarization effect, can make: in the off state, the polarization effect of the ferroelectric material layer can enhance the "charge sharing" effect to obtain a higher BV; in the on state, the polarization effect of the ferroelectric material layer can induce more electrons in the drift region, thereby reducing the on-resistance Ron, and effectively reducing the on-resistance Ron while increasing the breakdown voltage BV of the LDMOS transistor device. The preparation process of the present invention is simple, the selected ferroelectric material layer has good compatibility with CMOS, and has a wide range of applications. In addition, by setting multiple layers of ferroelectric material layers in the vertical floating field plate, the total polarization after recrystallization can be further enhanced, so as to further increase the breakdown voltage BV of the LDMOS transistor device and reduce the on-resistance Ron. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a process flow chart of the method for preparing the LDMOS transistor in the present invention.

[0029] Figure 2 It is a schematic diagram of the structure after the second conductivity type well region is formed in the present invention.

[0030] Figure 3 It is a schematic diagram of the structure after forming a vertical floating field plate in the present invention.

[0031] Figure 4 It is a schematic structural diagram of an LDMOS transistor with a vertical floating field plate formed in the present invention.

[0032] Figure 5 It is a schematic structural diagram of another LDMOS transistor with a vertical floating field plate formed in the present invention.

[0033] Component number description

[0034] 101 P-type substrate

[0035] 102 N-type doping region

[0036] 103 STI structure

[0037] 104 P-type well

[0038] 105 Vertical Floating Field Plate

[0039] 1051 laminated structure

[0040] 1051a Insulation material layer

[0041] 1051b Ferroelectric material layer

[0042] 1052 Polysilicon layer

[0043] 106 Gate Structure

[0044] 107 Source region

[0045] 108 drain region

[0046] 109 P-type contact area

[0047] 110 Metal parts DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0050] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0051] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] See also Figure 1 The present embodiment provides a method for preparing an LDMOS transistor with a vertical floating field plate. By setting a ferroelectric material layer with a polarization effect in a vertical floating field plate with a smaller size, the following can be achieved: in the off state, the polarization effect of the ferroelectric material layer can enhance the "charge sharing" effect to obtain a higher BV; in the on state, the polarization effect of the ferroelectric material layer can induce more electrons in the drift region, thereby reducing the on-resistance Ron, thereby achieving the goal of effectively reducing the on-resistance Ron while increasing the breakdown voltage BV of the LDMOS transistor device.

[0054] For ease of understanding, this embodiment is described using an N-type LDMOS transistor as an example. Those skilled in the art may change the doping type in the corresponding layer in the transistor as needed to obtain a P-type LDMOS transistor with the same structure, and no excessive restrictions are made here.

[0055] First, a semiconductor substrate is provided, wherein the semiconductor substrate includes a first conductive type doping region.

[0056] For details, see Figure 2 In this embodiment, the semiconductor substrate includes a P-type substrate 101 and an N-type doping region 102 located on the P-type substrate 101. The semiconductor substrate also includes an STI structure 103. The preparation process of the N-type doping region 102 and the STI structure 103 is not overly limited here, and the structure of the semiconductor substrate is not limited thereto. For example, in another embodiment, the P-type substrate 101 can also be replaced by a SOI structure.

[0057] Next, a second conductive type well region is formed in the first conductive type doped region.

[0058] For details, see Figure 2 In this embodiment, after high-energy ion implantation and advancement of impurities, a P-type well region 104 can be formed, wherein before or after the formation of the P-type well region 104, a step of forming an N-type well region (not shown) can also be included. In this embodiment, the N-type doped region 102 is directly used as the N-type well region, thereby further reducing the process steps, reducing costs and improving operational convenience.

[0059] Next, a vertical floating field plate is formed, which extends vertically from the surface of the first conductive type doped region, wherein the vertical floating field plate includes a floating field plate polysilicon layer and a stacked structure, the stacked structure includes alternately stacked insulating material layers and ferroelectric material layers, and the outermost layer and the innermost layer of the stacked structure are both the insulating material layers.

[0060] For details, see Figure 3In this embodiment, the vertical floating field plate 105 extends vertically from the surface of the N-type doped region 102 to the P-type substrate 101, but it is not limited to this. In another embodiment, the bottom of the vertical floating field plate 105 can also be located in the N-type doped region 102, and it can be specifically set as needed. Among them, the vertical floating field plate 105 includes a floating field plate polysilicon layer 1052 and a stacked structure 1051, and the stacked structure 1051 includes alternately stacked insulating material layers 1051a and ferroelectric material layers 1051b, and the outermost layer and the innermost layer of the stacked structure 1051 are both the insulating material layer 1051a. In this embodiment, the step of forming the vertical floating field plate 105 is located after forming the P-type well region 104, but it is not limited to this. In another embodiment, it can also be formed before the P-type well region 104.

[0061] As an example, the method for forming the ferroelectric material layer 1051b includes a PVD method or an ALD method, and the ferroelectric material layer 1051b includes a hafnium oxide ferroelectric layer doped with one or a combination of aluminum elements and zirconium elements, so that the material of the ferroelectric material layer 1051b is a CMOS-friendly material, and the preparation process can have good compatibility with CMOS to expand the scope of application.

[0062] As an example, the thickness of the ferroelectric material layer 1051 b ranges from 10 nm to 300 nm, such as 20 nm, 30 nm, 50 nm, 100 nm, 200 nm, and any other value within the range.

[0063] As an example, the stacked structure may include two layers of the ferroelectric material layer 1051b, and the thickness range of each layer of the ferroelectric material layer 1051b may include 10nm to 300nm, so as to further enhance the total polarization after recrystallization by arranging multiple layers of the ferroelectric material layer 1051b in the vertical floating field plate 105.

[0064] As an example, M≥2 vertical floating field plates 105 are included; the cross-sectional width W of the vertical floating field plate 105 may range from 1000 nm≥W≥100 nm.

[0065] Specifically, it is preferred that the cross-sectional width W of the vertical floating field plate 105 is 100nm to reduce the resistance of the vertical floating field plate 105. The cross-sectional width W of the vertical floating field plate 105 is not limited thereto, and may also include values ​​within any range such as 200nm, 400nm, 500nm, 800nm, etc. The number M of the vertical floating field plates 105 may be selected as needed. In this embodiment, only four vertical floating field plates 105 are shown, but the number of the vertical floating field plates 105 is not limited thereto. For example, the vertical floating field plates 105 may include 10, 20, 50, etc. as needed. Among them, a plurality of the vertical floating field plates 105 may be arranged in an array, and it is preferred that the vertical floating field plates 105 have equal spacing in the horizontal and vertical directions, and the specific distribution morphology is not overly limited here. Further, the cross-sectional morphology of the vertical floating field plate 105 may include circular, square, rectangular, etc., and the specific morphology is not overly limited here.

[0066] Next, a gate structure, a source region and a drain region are formed, the source region is located in the second conductive type well region, the drain region is located in the first conductive type doped region, the gate structure is in contact with the source region, the second conductive type well region and the first conductive type doped region, and the vertical floating field plate is located between the second conductive type well region and the drain region.

[0067] See also Figure 4 In this embodiment, the gate structure 106 is formed in a gate-first manner, but it is not limited to this. It can also be prepared by a gate-last process, and no excessive restrictions are made here. Among them, the gate structure 106 includes a gate dielectric layer and a gate conductive layer. Further, the gate structure 106 may also include a sidewall structure (not shown) to improve the mechanical properties of the gate structure 106 and ensure the insulation between the gate structure 106 and the subsequently formed source and drain electrodes. In this embodiment, since the N-type doped region 102 is directly used as the N-type well region, the source region 107 is located in the second conductive type well region 104, and the drain region 108 is located in the first conductive type doped region 102.

[0068] Furthermore, after forming the gate sidewall, the step of forming an LDD doping region (not shown) and a halo doping region (not shown) may also be included, wherein the doping ion type of the LDD doping region is opposite to that of the halo doping region. Taking the manufacture of NMOS as an example, the ion type of the LDD doping region is N-type, and the ion type of the halo doping region is P-type.

[0069] As an example, the method further includes forming a metal member 110 corresponding to the vertical floating field plate 105 , wherein the metal member 110 and the vertical floating field plate 105 are connected or insulated.

[0070] For details, see Figure 5 , shown as a structure including the metal component 110, wherein the metal component 110 is connected to the vertical floating field plate 105, and after the vertical floating field plate 105 equidistant from the source and the drain is electrically connected to the metal component 110, an equipotential ring can be formed, but it is not limited to this. In another embodiment, the metal component 110 can also be insulated from the vertical floating field plate 105.

[0071] Next, the steps of forming a dielectric layer (not shown) and forming an interconnect metal layer (not shown) are also included. The specific steps can be set according to existing processes and are not overly limited here.

[0072] This embodiment further provides an LDMOS transistor with a vertical floating field plate. The LDMOS transistor can be manufactured using the above manufacturing method, but is not limited thereto.

[0073] The LDMOS transistor includes a semiconductor substrate, a second conductive type well region, a source region, a drain region, a vertical floating field plate and a gate structure. The semiconductor substrate has a first conductive type doped region; the second conductive type well region is located in the first conductive type doped region; the source region is located in the second conductive type well region; the drain region is located in the first conductive type doped region; the vertical floating field plate is located between the second conductive type well region and the drain region, and extends vertically from the surface of the first conductive type doped region, the vertical floating field plate includes a floating field plate polysilicon layer and a stacked structure, the stacked structure includes alternately stacked insulating material layers and ferroelectric material layers, and the outermost layer and the innermost layer of the stacked structure are both the insulating material layers; the gate structure is in contact with the source region, the second conductive type well region and the first conductive type doped region.

[0074] This embodiment is described by taking an N-type LDMOS transistor as an example, and those skilled in the art can change the doping type of the corresponding LDMOS transistor as needed to obtain a corresponding P-type LDMOS transistor. The N-type LDMOS transistor is prepared by the above method, so the description of the preparation process, material and structure of the LDMOS transistor can refer to the above preparation method.

[0075] For details, see Figure 4The LDMOS transistor includes a P-type substrate 101, an N-type doped region 102, an STI structure 103, a P-type well 104, a vertical floating field plate 105, a gate structure 106, a source region 107, a drain region 108 and a P-type contact region 109. The vertical floating field plate includes a stacked structure 1051 and a polysilicon layer 1052, and the stacked structure 1051 includes an insulating material layer 1051a and a ferroelectric material layer 1051b.

[0076] As an example, the ferroelectric material layer 105 includes a hafnium oxide ferroelectric layer doped with one or a combination of aluminum and zirconium.

[0077] As an example, the stacked structure includes two layers of the ferroelectric material layer 105 , and the thickness of each layer of the ferroelectric material layer 105 ranges from 10 nm to 300 nm.

[0078] As an example, M≥2 vertical floating field plates 105 are included; the range of the cross-sectional width W of the vertical floating field plate 105 includes 1000nm≥W≥100nm.

[0079] As an example, the bottom of the vertical floating field plate 105 is located in the first conductive type doping region or extends below the first conductive type doping region.

[0080] As an example, a metal member 110 is further included, which is arranged corresponding to the vertical floating field plate 105 , wherein the metal member 110 and the vertical floating field plate 105 are connected or insulated.

[0081] In summary, the LDMOS transistor with a vertical floating field plate and the preparation method thereof of the present invention, in a vertical floating field plate with a smaller size, by setting a ferroelectric material layer with a polarization effect, can make: in the off state, the polarization effect of the ferroelectric material layer can enhance the "charge sharing" effect to obtain a higher BV; in the on state, the polarization effect of the ferroelectric material layer can induce more electrons in the drift region, thereby reducing the on-resistance Ron, and effectively reducing the on-resistance Ron while increasing the breakdown voltage BV of the LDMOS transistor device. The preparation process of the present invention is simple, the selected ferroelectric material layer has good compatibility with CMOS, and has a wide range of applications. In addition, by setting multiple layers of ferroelectric material layers in the vertical floating field plate, the total polarization after recrystallization can be further enhanced, so as to further increase the breakdown voltage BV of the LDMOS transistor device and reduce the on-resistance Ron.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An LDMOS transistor with a vertical floating field plate, characterized in that: The LDMOS transistor comprises: A semiconductor substrate, wherein the semiconductor substrate comprises a first conductive type doped region; a second conductivity type well region, the second conductivity type well region being located in the first conductivity type doped region; a source region, the source region being located in the second conductivity type well region; a drain region, wherein the drain region is located in the first conductivity type doping region; A vertical floating field plate, the vertical floating field plate is located between the second conductive type well region and the drain region, and extends vertically from the surface of the first conductive type doped region, wherein the vertical floating field plate comprises a floating field plate polysilicon layer and a stacked structure, the stacked structure comprises alternately stacked insulating material layers and ferroelectric material layers, and the outermost layer and the innermost layer of the stacked structure are both the insulating material layers; A gate structure is in contact with the source region, the second conductivity type well region and the first conductivity type doped region.

2. The LDMOS transistor according to claim 1, characterized in that: The ferroelectric material layer includes a hafnium oxide ferroelectric layer doped with one or a combination of aluminum and zirconium.

3. The LDMOS transistor according to claim 1, characterized in that: The stacked structure includes two ferroelectric material layers, and the thickness of each ferroelectric material layer ranges from 10 nm to 300 nm.

4. The LDMOS transistor according to claim 1, characterized in that: The vertical floating field plates include M≥2; and the cross-sectional width W of the vertical floating field plates ranges from 1000nm≥W≥100nm.

5. The LDMOS transistor according to claim 1, characterized in that: The bottom of the vertical floating field plate is located in the first conductive type doping region or extends to below the first conductive type doping region.

6. The LDMOS transistor according to claim 1, characterized in that: It also includes a metal piece arranged corresponding to the vertical floating field plate, wherein the metal piece and the vertical floating field plate include one of connection or insulation.

7. A method for preparing an LDMOS transistor with a vertical floating field plate, characterized in that: The following steps are involved: Providing a semiconductor substrate, the semiconductor substrate comprising a first conductivity type doped region; forming a second conductivity type well region in the first conductivity type doped region; Forming a vertical floating field plate, the vertical floating field plate extending vertically from the surface of the first conductive type doped region, wherein the vertical floating field plate comprises a floating field plate polysilicon layer and a stacked structure, the stacked structure comprises alternately stacked insulating material layers and ferroelectric material layers, and the outermost layer and the innermost layer of the stacked structure are both the insulating material layers; A gate structure, a source region and a drain region are formed, the source region is located in the second conductivity type well region, the drain region is located in the first conductivity type doped region, the gate structure is in contact with the source region, the second conductivity type well region and the first conductivity type doped region, and the vertical floating field plate is located between the second conductivity type well region and the drain region.

8. The preparation method according to claim 7, characterized in that: The ferroelectric material layer includes a hafnium oxide ferroelectric layer doped with one or a combination of aluminum and zirconium elements, and the thickness of the ferroelectric material layer ranges from 10nm to 300nm. The method for forming the ferroelectric material layer includes PVD method or ALD method.

9. The preparation method according to claim 7, characterized in that: Before forming the vertical floating field plate, the method further includes forming a first conductive type well region.

10. The preparation method according to claim 7, characterized in that: The method further includes the step of forming a metal member corresponding to the vertical floating field plate, wherein the formed metal member and the vertical floating field plate are connected or insulated.

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