Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor element, an insulating doped region, and at least one insulating column. The substrate includes a base material and a composite material layer, the semiconductor epitaxial layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor epitaxial layer. The first semiconductor element is disposed on the substrate, wherein the first semiconductor element includes a first semiconductor cap layer disposed on the semiconductor barrier layer. The insulating doped region is located on one side of the first semiconductor element. At least part of the insulating column is located in the insulating doped region, and the insulating column surrounds at least part of the first semiconductor element and penetrates the composite material layer.

Description

Technical Field

[0001] The invention relates to a high-voltage semiconductor structure, in particular to a high-voltage semiconductor structure with an insulating structure. Background Art

[0002] With the development of 5G communication and electric vehicle industries, the demand for high-frequency and high-power semiconductor components is also growing. These high-frequency and high-power semiconductor components can be, for example, high-frequency transistors, high-power field-effect transistors, or high electron mobility transistors (HEMT). High-frequency and high-power semiconductor components generally use semiconductor compounds, such as III-V semiconductor compounds such as gallium nitride and silicon carbide, which have the characteristics of high frequency, high voltage resistance, and low on-resistance.

[0003] Among these devices, high electron mobility transistors have advantages such as high output power and high breakdown voltage, so they are widely used in high power applications. Although existing semiconductor structures and their formation methods can cope with their originally intended uses, they still have problems to be overcome in various technical aspects such as structure and use environment. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor structure to solve the technical problems faced by the prior art.

[0005] According to one embodiment of the present invention, a semiconductor structure is provided, comprising a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor element, an insulating doped region, and at least one insulating column. The substrate comprises a base material and a composite material layer, the semiconductor epitaxial layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor epitaxial layer. The first semiconductor element is disposed on the substrate, wherein the first semiconductor element comprises a first semiconductor cap layer disposed on the semiconductor barrier layer. The insulating doped region is disposed on one side of the first semiconductor element. At least part of the insulating column is disposed in the insulating doped region, and the insulating column surrounds at least part of the first semiconductor element and penetrates the composite material layer.

[0006] According to one embodiment of the present invention, a semiconductor structure is provided, the semiconductor structure comprising a substrate, a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, an insulating doped region, and at least one insulating column. The substrate comprises a base material and a composite material layer. The semiconductor channel layer is disposed on the substrate, the semiconductor barrier layer is disposed on the semiconductor channel layer, and the semiconductor cap layer is disposed on the semiconductor barrier layer. The insulating doped region is located in the semiconductor channel layer and the semiconductor barrier layer, and is located on at least one side of the semiconductor cap layer. The insulating column directly contacts the insulating doped region, and the insulating column penetrates the semiconductor barrier layer, the semiconductor channel layer, and the composite material layer.

[0007] According to another embodiment of the present invention, a chip structure is provided, the chip structure comprising a substrate, a high-voltage semiconductor structure, a low-voltage semiconductor structure, and at least one insulating column. The substrate comprises a base material and a composite material layer. The high-voltage semiconductor structure is disposed on the substrate, and the low-voltage semiconductor structure is disposed on the substrate and separated from the high-voltage semiconductor structure. The insulating column completely surrounds the high-voltage semiconductor structure and penetrates the composite material layer.

[0008] According to another embodiment of the present invention, a method for operating a high-voltage semiconductor structure is provided, the method comprising providing a high-voltage semiconductor structure, and applying an electronic signal to the high-voltage semiconductor structure at an ambient temperature higher than 150°C. The high-voltage semiconductor structure comprises a substrate, a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, an insulating doped region, and at least two insulating pillars. The substrate comprises a base material and a composite material layer. The semiconductor channel layer is disposed on the substrate, the semiconductor barrier layer is disposed on the semiconductor channel layer, and the semiconductor cap layer is disposed on the semiconductor barrier layer. The insulating doped region is located in the semiconductor channel layer and the semiconductor barrier layer, and is located on at least one side of the semiconductor cap layer. The insulating pillar directly contacts the insulating doped region, and the insulating pillar penetrates the semiconductor barrier layer, the semiconductor channel layer, and the composite material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. The specific embodiments of the present invention are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

[0010] Figure 1 FIG. 4 is a schematic top view of a high-voltage semiconductor structure according to an embodiment of the present invention.

[0011] Figure 2 According to an embodiment of the present invention, Figure 1 A schematic cross-sectional view of the high-voltage semiconductor structure is shown along the tangent line AA′.

[0012] Figure 3 FIG. 4 is a schematic top view of a high-voltage semiconductor structure according to an embodiment of the present invention.

[0013] Figure 4 According to an embodiment of the present invention, Figure 3 A schematic cross-sectional view of the high-voltage semiconductor structure is shown along the tangent line AA′.

[0014] Figure 5 and Figure 6It is the electrical property of the high voltage semiconductor structure of the embodiment of the present invention at room temperature.

[0015] Figure 7 and Figure 8 It is the electrical property of the high voltage semiconductor structure of the embodiment of the present invention at high temperature.

[0016] Fig. 9 FIG. 4 is a schematic top view of a chip structure according to an embodiment of the present invention.

[0017] Fig.10 FIG. 4 is a schematic top view of a chip structure according to an embodiment of the present invention.

[0018] Fig.11 According to an embodiment of the present invention, Fig.10 A schematic cross-sectional view of the high-voltage semiconductor structure is shown along the tangent line BB′.

[0019] The following are the descriptions of the reference numerals:

[0020] 1: Chip structure

[0021] 10: High voltage semiconductor structure

[0022] 10-1: The first high-voltage semiconductor device

[0023] 10-2: Second high voltage semiconductor element

[0024] 20: High voltage semiconductor components

[0025] 22: Insulation area

[0026] 30: Logic operation element

[0027] 40: Memory components

[0028] 100: Substrate

[0029] 100C: Base material

[0030] 100M: Composite material layer

[0031] 101: Silicon-containing semiconductor layer

[0032] 102: Semiconductor epitaxial layer

[0033] 103: Semiconductor buffer layer

[0034] 104: Semiconductor barrier layer

[0035] 105: Semiconductor channel layer

[0036] 110: Insulation doping region

[0037] 112: Interlayer dielectric layer

[0038] 120: Insulation column

[0039] 120_1: First insulating column

[0040] 120_2: Second insulating column

[0041] 120_3: The third insulating column

[0042] 200: Active area

[0043] 202: Source electrode

[0044] 204: Gate electrode

[0045] 206: Drain electrode

[0046] 210: Semiconductor cap layer

[0047] 300: Active area

[0048] 302: Source electrode

[0049] 304: Gate electrode

[0050] 306: Drain electrode

[0051] 310: Semiconductor cap layer

[0052] A: Chip area

[0053] B: Cutting area

[0054] L 1 :width

[0055] L 2 :width

[0056] L 3 :width

[0057] S 1 :spacing

[0058] S 2 :spacing

[0059] S 3 :spacing

[0060] S 4 :spacing DETAILED DESCRIPTION

[0061] The present invention provides a plurality of different embodiments that can be used to implement different features of the present invention. For the purpose of simplifying the description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only to illustrate, and not to impose any limitation.

[0062] In the present invention, the description of "a first component is formed on or above a second component" may refer to "the first component is in direct contact with the second component" or "another component exists between the first component and the second component", so that the first component and the second component are not in direct contact. In addition, various embodiments of the present invention may use repeated element symbols and / or text marks. The use of these repeated element symbols and text notes is to make the description more concise and clear, rather than to indicate the association between different embodiments and / or configurations.

[0063] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "over", "low", "high", "below", "above", "under", "above", "bottom", "top" and similar words, for the convenience of description, their usage is to describe the relative relationship between one component or feature and another (or multiple) components or features in the drawings. In addition to the swing directions shown in the drawings, these spatially related words are also used to describe the possible swing directions of the semiconductor structure during the manufacturing process, use and operation. For example, when the semiconductor structure is rotated 180 degrees, a component originally arranged "above" other components will become arranged "below" other components. Therefore, as the swing direction of the semiconductor structure changes (rotated 90 degrees or other angles), the spatially related descriptions used to describe its swing direction should also be interpreted in a corresponding manner.

[0064] Although the present invention uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. Such terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0065] The terms "coupled", "coupled", and "electrically connected" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0066] In the present invention, "group III-V semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Further, "group III-V semiconductor" may include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), and the like or a combination of the above compounds, but is not limited thereto. In addition, according to requirements, the III-V semiconductor may also include dopants to become a III-V semiconductor with a specific conductivity type, such as an N-type or P-type III-V semiconductor.

[0067] The specific steps or block levels in the steps / processes described below are for illustration purposes only. Based on design preferences, the specific steps or block levels in the steps / processes described below may be rearranged. Furthermore, some blocks may be merged or deleted.

[0068] Although the present invention is described below by specific embodiments, the principles of the present invention may also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

[0069] Figure 1 FIG. 1 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the present invention. Figure 1As shown, at least one high-voltage semiconductor structure 10 may be disposed on a substrate 100, and the high-voltage semiconductor structure 10 may include at least one semiconductor element, such as a first high-voltage semiconductor element 10-1 and a second high-voltage semiconductor element 10-2. According to one embodiment of the present invention, the first high-voltage semiconductor element 10-1 and the second high-voltage semiconductor element 10-2 may be semiconductor elements operated at a source voltage or a drain voltage greater than 600V, such as a high electron mobility transistor, but not limited thereto. According to one embodiment of the present invention, the first high-voltage semiconductor element 10-1 may include an active region 200, a source electrode 202, a gate electrode 204, and a drain electrode 206. The source electrode 202, the gate electrode 204, and the drain electrode 206 may be electrically connected to corresponding regions of the active region 200, respectively. Among them, electronic signals may be input and output from the active region 200 via the source electrode 202 and the drain electrode 206, and by applying an appropriate voltage to the gate electrode 204, the current conduction degree of the first high-voltage semiconductor element 10-1 may be controlled. Similarly, according to an embodiment of the present invention, the second high-voltage semiconductor element 10-2 may include an active region 300, a source electrode 302, a gate electrode 304, and a drain electrode 306. The source electrode 302, the gate electrode 304, and the drain electrode 306 may be electrically connected to corresponding regions of the active region 300, respectively. Since the first high-voltage semiconductor element 10-1 and the second high-voltage semiconductor element 10-2 operate at a high voltage, an insulating doped region 110 may be disposed around the first high-voltage semiconductor element 10-1 and the second high-voltage semiconductor element 10-2 to achieve an electrical insulation effect between the first high-voltage semiconductor element 10-1 and the second high-voltage semiconductor element 10-2.

[0070] Figure 2 According to an embodiment of the present invention, Figure 1 The cross-sectional view of the high voltage semiconductor structure is shown by the tangent line A-A'. Figure 2 As shown, according to one embodiment of the present invention, the high-voltage semiconductor structure 10 may include a substrate 100, a semiconductor epitaxial layer 102, a semiconductor barrier layer 104, an insulating doped region 110, at least two semiconductor cap layers 210, 310, an interlayer dielectric layer 112, and at least two gate electrodes 204, 304, but is not limited thereto.

[0071] According to an embodiment of the present invention, the substrate 100 may include a base material 100C and a composite material layer 100M covering the base material 100C. The base material 100C may be composed of silicon carbide (SiC), aluminum oxide (Al 2 O 3), sapphire, aluminum nitride or a ceramic material of a combination thereof. The composite material layer 100M can be disposed along the surface of the substrate 100C, for example, it is disposed on the top surface of the substrate 100C and the bottom surface of the substrate 100C in a forward direction, or even on the side of the substrate 100C, but is not limited thereto. Each composite material layer 100M may include a stacked insulating layer and a seed layer. According to one embodiment of the present invention, for the composite material layers 100M located on the top and bottom surfaces of the substrate 100C, respectively, in a direction away from the substrate 100C, the composite material layers 100M may each sequentially include a first insulating layer, a seed layer, and a second insulating layer. The first insulating layer and the second insulating layer may be a single or multiple insulating material layer, such as oxide, nitride, oxynitride, or other suitable insulating materials, and the seed layer may be a semiconductor material, such as silicon, but is not limited thereto. According to an embodiment of the present invention, in the direction away from the substrate 100C, each composite material layer 100M may include an oxide layer, a semiconductor layer, a nitride layer, and an oxide layer stacked in sequence, but the invention is not limited thereto. In the case where the substrate 100C is a ceramic substrate, since its mechanical strength is higher than that of a single crystal silicon substrate, the substrate 100 is less likely to be broken or bent. In addition, since the electrical insulation of the ceramic substrate is higher than that of the single crystal silicon substrate, the substrate 100 can withstand a higher voltage.

[0072] According to an embodiment of the present invention, for the case where both the first high-voltage semiconductor element 10-1 and the second high-voltage semiconductor element 10-2 are high electron mobility transistors, a nitride layer, a super lattice layer, and a high resistance layer can be selectively arranged between the semiconductor epitaxial layer 102 and the substrate 100, but it is not limited thereto. Among them, the nitride layer can be arranged on the substrate 100, which has fewer lattice defects, so the epitaxial quality of the semiconductor layer (e.g., semiconductor epitaxial layer 102) arranged on the nitride layer can be improved. The super lattice layer can be used to reduce the degree of lattice mismatch between the substrate 100 and the semiconductor layer (e.g., semiconductor epitaxial layer 102) arranged on the super lattice layer, and reduce the stress generated by the lattice mismatch. The high resistance layer has a higher resistivity than other semiconductor layers, so leakage current can be avoided between the semiconductor layer (e.g., semiconductor epitaxial layer 102) arranged on the high resistance layer and the substrate 100.

[0073] The semiconductor epitaxial layer 102 may include one or more layers of III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN or InAlGaN, but is not limited thereto. According to one embodiment of the present invention, the semiconductor epitaxial layer 102 may include a semiconductor buffer layer and a semiconductor channel layer from bottom to top. The semiconductor channel layer is an undoped III-V semiconductor, such as undoped GaN (undoped-GaN, u-GaN). According to one embodiment of the present invention, the semiconductor channel layer may also be one or more doped III-V semiconductor layers, such as a P-type III-V semiconductor layer. For a P-type III-V semiconductor layer, its dopant may be Cd, Fe, Mg or Zn, but is not limited thereto.

[0074] The semiconductor barrier layer 104 may include one or more III-V semiconductor layers, and the composition thereof may be different from the III-V semiconductor of the semiconductor channel layer. For example, the semiconductor barrier layer 104 may include AlN, Al y Ga (1-y) N(0<y<1) or a combination thereof. According to one embodiment, the semiconductor barrier layer 104 may be an N-type III-V semiconductor, such as an AlGaN layer that is essentially N-type, but is not limited thereto.

[0075] In addition, according to an embodiment of the present invention, the semiconductor channel layer on the semiconductor epitaxial layer 102 can directly contact the semiconductor barrier layer 104, so the region of the semiconductor epitaxial layer 102 adjacent to the semiconductor barrier layer 104 can form a carrier flow region, such as a two-dimensional electron gas (2-DEG) region. The semiconductor cap layers 210 and 310 can be separated from each other, and each can be one or more layers of a P-type III-V semiconductor layer, such as a P-type GaN layer, and the dopant can be a metal dopant selected from Mg, Cd or Zn.

[0076] The insulating doped region 110 may be located in the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104 on both sides of the semiconductor cap layers 210 and 310, and the insulating doped region 110 is preferably located between the two mutually separated semiconductor cap layers 210 and 310, and does not overlap with the semiconductor cap layers 210 and 310. According to an embodiment of the present invention, the insulating doped region 110 may be formed by, for example, applying external energy to destroy the lattice of the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104, or by performing an ion implantation process to implant specific non-conductive dopants into the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104. The dopants used to form the insulating doped region 110 may include helium, argon, nitrogen, phosphorus, arsenic, oxygen or a combination thereof, but are not limited thereto.

[0077] The interlayer dielectric layer 112 may be disposed on the insulating doped region 110 and cover the semiconductor cap layers 210 and 310. An interconnect structure may be selectively disposed in the interlayer dielectric layer 112 to electrically connect to the semiconductor cap layers 210 and 310 or the semiconductor barrier layer 104, but is not limited thereto.

[0078] The gate electrodes 204 and 304 may be disposed on the top surface of the interlayer dielectric layer 112 and electrically connected to the corresponding semiconductor cap layers 210 and 310. According to an embodiment of the present invention, the gate electrodes 204 and 304 and other electrodes disposed in the first high-voltage semiconductor element 10-1 and the first high-voltage semiconductor element 10-2, such as the source electrode and the drain electrode, are conductive materials, such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi 2 , combinations of the foregoing or similar materials.

[0079] Figure 3 FIG. 1 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the present invention. Figure 3 As shown, similar Figure 2 The high voltage semiconductor structure 10 shown in the embodiment, Figure 3 The high-voltage semiconductor structure 10 shown includes, in addition to the insulating doped region 110, an insulating column 120 surrounding the active regions 200 and 300 of the high-voltage semiconductor elements 10-1 and 10-2. According to an embodiment of the present invention, the insulating column 120 can surround the periphery of the active regions 200 and 300. According to an embodiment of the present invention, the insulating column 120 can include a plurality of insulating columns (or sub-insulating columns), so that the insulating columns can be separately arranged and each surrounds the periphery of the active region 200 and the active region 300. In an embodiment of the present invention, the time point of forming the insulating column 120 can be earlier than the time point of forming the gate electrode 204, 304, the source electrode 202, 302, or the drain electrode 206, 306 to ensure the aspect ratio of the insulating column 120. By setting the size of the insulating column 120 and the insulating doped region 110 within a specific range, the best electrical performance can be achieved, which will be further explained in Table 1 below.

[0080] Figure 4 According to an embodiment of the present invention, Figure 3 The cross-sectional view of the high voltage semiconductor structure is shown by the tangent line A-A'. Figure 4As shown, according to an embodiment of the present invention, the insulating column 120 may include a plurality of insulating columns, such as a first insulating column 120_1, a second insulating column 120_2, and a third insulating column 120_3. The insulating column 120 may be located between the high-voltage semiconductor elements 10-1 and 10-2, for example, between the semiconductor cap layers 210 and 310. In addition, the insulating column 120 is not limited to being located only on one side of the semiconductor cap layer 210 or the semiconductor cap layer 310. The insulating column 120 may also be located on both sides of the semiconductor cap layer 210 or the semiconductor cap layer 310, or further surround the periphery of the semiconductor cap layer 210 or the semiconductor cap layer 310. According to an embodiment of the present invention, at least one of the first insulating column 120_1, the second insulating column 120_2, and the third insulating column 120_3 may penetrate the insulating doped region 110 and the composite material layer 100M, and directly contact the insulating doped region 110 and the substrate 100C. According to an embodiment of the present invention, when the insulating doped region 110 is disposed in the semiconductor barrier layer 104 and the semiconductor epitaxial layer 102, the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 can be regarded as penetrating the semiconductor barrier layer 104 and the semiconductor epitaxial layer 102 at the same time. The insulating pillar 120 can be a single-layer structure or a composite structure, for example, a single-layer structure including only insulating material, or a composite structure including both insulating material and conductive material buried in the insulating material, but not limited thereto. According to an embodiment of the present invention, the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 can each have a width L 1 , L 2 , L 3 , and the first insulating pillar 120_1 and the third insulating pillar 120_3 and the semiconductor cap layer 210 and the semiconductor cap layer 310 may have a spacing S respectively. 1 , spacing S 4 , and the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may have a spacing S between them. 2 , spacing S 3 According to an embodiment of the present invention, the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may be distributed at equal intervals, that is, the interval S 2 Equal to the spacing S 3 According to an embodiment of the present invention, the width L of the insulating column 120 is 1 , L 2 , L 3 It can be smaller than the spacing S between the insulating pillars 120 2 , S 3 .

[0081] According to an embodiment of the present invention, the insulating pillar 120 may be formed after the insulating doped region 110 is formed but before the interlayer dielectric layer 112 is formed, but it is not limited thereto. For example, after an ion implantation process is performed to form the insulating doped region 110, processes such as photolithography and etching may be used to form at least one trench in the insulating doped region 110, and the bottom depth of the trench may reach the top surface of the substrate 100C, so that the substrate 100C is exposed in the trench. Afterwards, an appropriate deposition process, such as a chemical vapor deposition process or a spin coating process, may be performed to fill the trench with insulating material to form a substrate such as Figure 4 The insulating pillar 120 is shown. Subsequently, an interlayer dielectric layer 112 may be further formed on the insulating pillar 120 , and at least one electrode, such as a gate electrode 204 or 304 , may be formed on a surface of the interlayer dielectric layer 112 .

[0082] According to one embodiment of the present invention, in order to further reduce the thickness of the substrate 100, after forming an electrode on the surface of the interlayer dielectric layer 112, a thinning process (grinding) can be performed on the back side of the substrate 100 to completely remove the composite material layer 100M located on the bottom surface of the substrate 100C, or further remove a portion of the substrate 100C until the substrate 100 is thinned to a predetermined thickness.

[0083] According to an embodiment of the present invention, a method for operating a high-voltage semiconductor structure is provided. First, a high-voltage semiconductor structure is provided, such as Figure 1 , Figure 2 or Figure 3 , Figure 4 The high-voltage semiconductor structure 10 shown. Afterwards, an electronic signal can be applied to the high-voltage semiconductor structure 10 when the ambient temperature is within a specific range. According to one example, a voltage higher than 200 volts (V) can be applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1 under the condition that the ambient temperature falls within the range of 15°C to 300°C, and the current transmitted from the drain electrode 302 of the second high-voltage semiconductor element 10-2 is measured. According to another example, a voltage gradually increasing from -800V to 800V can be applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1 under the condition that the ambient temperature falls within the range of 15°C to 300°C, and the I of the second high-voltage semiconductor element 10-2 is measured. D and V G relationship.

[0084] The electrical properties of the high voltage semiconductor structure of the present invention are described below. Figure 1 , Figure 2 or Figure 3 , Figure 4The high-voltage semiconductor structure 10 shown, and the high-voltage semiconductor elements 10 - 1 , 10 - 2 are both high electron mobility transistors.

[0085] According to an embodiment of the present invention, at a temperature of 25°C, Figure 2 and Figure 4 A voltage higher than 200V to 800V is applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1, and the current value transmitted from the drain electrode 302 of the second high-voltage semiconductor element 10-2 is measured. Figure 2 The high-voltage semiconductor structure shown can adjust the lateral dimensions of the insulating doped region 110 between adjacent high-voltage semiconductor elements 10-1 and 10-2 so that the insulating doped region 110 has different lateral dimensions, and perform the above measurement on the corresponding high-voltage semiconductor structure 10. Figure 4 The high-voltage semiconductor structure shown can adjust the number of insulating pillars 120, and perform the above measurement on the corresponding high-voltage semiconductor structure 10. The results of the above measurement are recorded in Table 1 below.

[0086] Table 1

[0087]

[0088] Note 1: The number of insulating pillars refers to the number of insulating pillars between two adjacent high-voltage semiconductor elements. Note 2: The overall insulating area width refers to the overall insulating area width between two adjacent active areas in the high-voltage semiconductor structure.

[0089] Note 3: When the drain of a high-voltage semiconductor device outputs a specified current value, the voltage value that should be applied to the drain of the adjacent high-voltage semiconductor device is

[0090] According to the results described in Table 1, it can be known that when the high-voltage semiconductor structure 10 includes an insulating doped region 110, or includes both an insulating doped region 110 and an insulating column 120, a voltage of at least 950V must be applied to the drain electrode 202 of the high-voltage semiconductor element 10-1, and the drain electrode 302 of the adjacent high-voltage semiconductor element 10-2 will generate a current of 1nA. In addition, for the high-voltage semiconductor structure 10 that includes both the insulating doped region 110 and the insulating column 120, its withstand voltage capability is higher than that of the high-voltage semiconductor structure 10 that only includes the insulating doped region 110. In addition, when the number of insulating columns 120 reaches 3, its withstand voltage capability reaches saturation. Therefore, in order to avoid the insulating column 120 occupying too much grain area, the size of the insulating column 120 and the insulating doped region 110 can be set within a specific range to achieve the best electrical performance.

[0091] According to an embodiment of the present invention, at a temperature of 25°C, Figure 2 and Figure 4A voltage of -200 V to 200 V is applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1, and the I D and V G The measurement results are recorded in Figure 5 and Figure 6 middle. Figure 5 and Figure 6 is the electrical property of the high voltage semiconductor structure of the embodiment of the present invention at room temperature. Figure 5 Corresponds to Figure 2 The electrical properties of the high voltage semiconductor structure 10 are shown. Figure 6 Corresponds to Figure 4 The electrical properties of the high voltage semiconductor structure 10 are shown in FIG. Figure 5 and Figure 6 As shown, no matter what the voltage applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1 is, the I D and V G In other words, the threshold voltage of the second high-voltage semiconductor element 10 - 2 will not change due to the voltage applied to the first high-voltage semiconductor element 10 - 1 .

[0092] Similarly, according to an embodiment of the present invention, at an ambient temperature of 150°C, Figure 2 and Figure 4 A voltage of -500 V to 500 V is applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1, and the I D and V G The measurement results are recorded in Figure 7 and Figure 8 middle. Figure 7 and Figure 8 is the electrical property of the high voltage semiconductor structure of the embodiment of the present invention at high temperature. Figure 7 Corresponds to Figure 2 The electrical characteristics of the high voltage semiconductor structure 10 are shown. Figure 8 Corresponds to Figure 4 The electrical properties of the high voltage semiconductor structure 10 are shown in FIG. Figure 7 As shown in FIG. 1 , when a negative voltage or a positive voltage is applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1, the I D and V GIn other words, the threshold voltage of the second high-voltage semiconductor element 10-2 will change due to the voltage applied to the first high-voltage semiconductor element 10-1. In addition, as the voltage applied to the first high-voltage semiconductor element 10-1 gradually increases, the threshold voltage of the second high-voltage semiconductor element 10-2 will shift more significantly. Figure 8 As shown, no matter what the voltage value applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1 is, the I D and V G In other words, the threshold voltage of the second high-voltage semiconductor element 10 - 2 will not change due to the voltage applied to the first high-voltage semiconductor element 10 - 1 .

[0093] Fig. 9 FIG. 1 is a schematic top view of a chip structure according to an embodiment of the present invention. Fig. 9 As shown, the chip structure 1 can be arranged in the chip area A of the wafer, and the chip area A can be surrounded by the saw road area B. The chip structure 1 can include at least one high-voltage semiconductor element 20 and a low-voltage semiconductor element (for example: a logic operation element 30 or a memory element 40), and the high-voltage semiconductor element 20 can be surrounded by an insulating area 22. Among them, the high-voltage semiconductor element 20 can be the high electron mobility transistor described in the above embodiment, and the above-mentioned insulating doped region and / or insulating column can be arranged in the insulating area 22.

[0094] Fig.10 FIG. 4 is a schematic top view of a chip structure according to an embodiment of the present invention. Fig.10 Chip structure 1 and Fig. 9 The main difference in chip structure 1 is that Fig.10 The chip structure 1 in the embodiment may include at least two high-voltage semiconductor components 20 , and each of the high-voltage semiconductor components 20 may be surrounded by an insulating region 22 .

[0095] Fig.11 According to an embodiment of the present invention, Fig.10 The cross-sectional view of the high voltage semiconductor structure is shown by the tangent line BB'. Fig.11As shown, according to one embodiment of the present invention, each high-voltage semiconductor element 20 may include a substrate 100, a silicon-containing semiconductor layer 101, a semiconductor epitaxial layer 102, a semiconductor barrier layer 104, and semiconductor cap layers 210 and 310 from bottom to top, and a two-dimensional electron gas may exist at the interface between the semiconductor channel layer 105 and the semiconductor barrier layer 104 (as indicated by the dotted line). In addition, adjacent high-voltage semiconductor elements 20 may be connected in series to the drain electrode 206 of another high-voltage semiconductor element 20 through a wire 320, but the present invention is not limited thereto. According to one embodiment of the present invention, an insulating doped region 110 and an insulating column 120 may be provided between and around adjacent high-voltage semiconductor elements 20. Among them, the insulating doped region 110 may be obtained by doping or destroying the semiconductor barrier layer 104, the semiconductor channel layer 105, and / or a portion of the semiconductor buffer layer 103. The upper portion of the insulating column 120 may be disposed in the insulating doped region 110 , and the lower portion of the insulating column 120 may penetrate the semiconductor buffer layer 103 and the silicon-containing semiconductor layer 101 , or further penetrate the composite material layer 100M.

[0096] According to the above embodiments, by providing an insulating doped region in the high-voltage semiconductor structure, or providing an insulating doped region and an insulating column at the same time, it is possible to prevent the high-voltage semiconductor element in the high-voltage semiconductor structure from affecting the electrical performance of other high-voltage semiconductor elements and low-voltage semiconductor elements. In addition, for the high-voltage semiconductor structure including the insulating doped region and the insulating column, the high-voltage semiconductor structure is less likely to have a threshold voltage shift problem at high temperatures.

[0097] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, comprising a base material and a composite material layer; a semiconductor epitaxial layer disposed on the substrate, wherein the composite material layer is at least partially disposed between the substrate and the semiconductor epitaxial layer; a semiconductor barrier layer disposed on the semiconductor epitaxial layer; a first semiconductor element disposed on the substrate, wherein the first semiconductor element comprises a first semiconductor cap layer, and the first semiconductor cap layer is located on the semiconductor barrier layer; an insulating doped region located on one side of the first semiconductor element; and A plurality of insulating pillars, wherein at least one of the insulating pillars is located in the insulating doped region, the plurality of insulating pillars surround at least a portion of the first semiconductor element and penetrate the composite material layer, and the width of the plurality of insulating pillars is smaller than the spacing between the plurality of insulating pillars.

2. The semiconductor structure according to claim 1, wherein: The substrate includes aluminum nitride, silicon carbide, aluminum oxide, or a combination thereof.

3. The semiconductor structure according to claim 1, wherein: The first semiconductor element includes a first gate electrode, a first source electrode, and a first drain electrode, and the plurality of insulating pillars do not extend beyond the top surface of the first gate electrode.

4. The semiconductor structure according to claim 1, wherein: The invention also comprises an interlayer dielectric layer, wherein the interlayer dielectric layer is arranged on the plurality of insulating pillars.

5. The semiconductor structure according to claim 3, wherein: The semiconductor structure further includes a second semiconductor element disposed adjacent to the first semiconductor element, wherein the second semiconductor element includes a second gate electrode, a second source electrode and a second drain electrode, and the plurality of insulating pillars surround at least a portion of the first semiconductor element and the second semiconductor element respectively.

6. The semiconductor structure according to claim 5, characterized in that The number of the plurality of insulating pillars is 3.

7. The semiconductor structure according to claim 5, characterized in that The number of insulating pillars between the first semiconductor element and the second semiconductor element is greater than the number of insulating pillars on the outer sides of the first semiconductor element and the second semiconductor element.

8. The semiconductor structure according to claim 1, wherein: The insulating doped region is formed by applying external energy to destroy the lattices of the semiconductor epitaxial layer and the semiconductor barrier layer.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises a second semiconductor element disposed on the substrate, wherein the second semiconductor element comprises a second semiconductor cap layer, the second semiconductor cap layer is located on the semiconductor barrier layer, and the insulating doped region is located between the first semiconductor element and the second semiconductor element.

10. The semiconductor structure according to claim 9, wherein: The insulating doped region surrounds at least a portion of the first semiconductor element and the second semiconductor element and includes a portion located between the first semiconductor cap layer and the second semiconductor cap layer, and at least a portion of the plurality of insulating pillars is located in the portion between the first semiconductor cap layer and the second semiconductor cap layer in the insulating doped region.

11. The semiconductor structure according to claim 10, characterized in that The first semiconductor element is a high voltage element, and the second semiconductor element is a low voltage element.

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