A starting inrush current suppression circuit

Abstract

The application discloses a starting inrush current suppression circuit, comprising a rectifier bridge, a first current-limiting starting circuit, a second current-limiting starting circuit and a Boost circuit; the input end of the rectifier bridge is connected with an AC power supply, the output positive end is connected with the input positive end of the first current-limiting starting circuit and the input positive end of the Boost circuit, and the output negative end is connected with the input negative end of the first current-limiting starting circuit and the source electrode of a MOSFET tube of the second current-limiting starting circuit; the first output end of the first current-limiting starting circuit is connected with the input end of the second current-limiting starting circuit, and the second output end of the first current-limiting starting circuit is connected with the output negative end of the Boost circuit; the output negative end of the Boost circuit is connected with the drain electrode of the MOSFET tube of the second current-limiting starting circuit, and the output positive end of the Boost circuit is V OUT The application can effectively suppress the starting inrush current in a power factor correction circuit, limit the current within 4A and ensure the reliable operation of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of electronic and electrical technology, and in particular to a starting inrush current suppression circuit for electronic devices such as active power factor correction (APFC). Background Technology

[0002] To improve the quality and electromagnetic compatibility of switching power supplies, electronic devices commonly incorporate APFC (Advanced Power Factor Correction) circuits to eliminate current harmonics and improve power factor. Traditional APFC circuits use a Boost converter for the main power circuitry. AC mains power is converted to DC voltage by a rectifier bridge and input to the Boost circuit, which then boosts this voltage to approximately 380V for output. Typically, a large number of filter capacitors (energy storage capacitors in the Boost circuit) are added to the output of the APFC circuit to reduce the output ripple of the subsequent DC / DC converter. Therefore, during power-on startup, the capacitors draw a large current, known as the startup inrush current, which can typically be tens or even hundreds of times the steady-state operating current of the power supply. This huge startup inrush current can cause several problems:

[0003] 1. Components in the power input section (such as power switches, fuses, rectifiers, etc.) will be subjected to great electrical stress damage, which increases the failure rate of these components and leads to a significant decrease in the mean time between failures (MTBF) of the whole machine.

[0004] 2. It generates additional electromagnetic interference, which can interfere with other nearby electronic devices through conduction and radiation, potentially causing them to malfunction momentarily.

[0005] 3. It causes a transient drop in voltage on the power supply line, which can seriously affect equipment on the same power supply line and even cause it to malfunction.

[0006] To limit inrush current, a common method is to increase the input circuit resistance during startup, thereby reducing the capacitor charging current and achieving current limiting. In practical applications, for low-power power supplies, a resistor is connected in series in the input circuit. This resistor value should not be too large, otherwise it will affect the power supply's efficiency and stability. For high-efficiency, high-power power supplies, to reduce unnecessary losses in the resistor, a relay, thyristor, MOSFET, etc., are typically connected in parallel. After the capacitor has been basically charged (i.e., after the charging period), the resistor is short-circuited. Traditional methods for suppressing inrush current include the following three:

[0007] 1. The NTC resistor method for suppressing startup inrush current involves connecting one or more NTC (Negative Temperature Coefficient) power-type current-limiting resistors in series in the input circuit. When the power is turned on, the resistor is cold and exhibits high resistance, effectively limiting the amplitude of the startup inrush current. After a few seconds, it becomes hot due to its own heating, exhibiting low resistance; at this point, the resistance value is 1 / 10 to 1 / 100 of the cold-state resistance. This resolves the contradiction between current limiting and power consumption, and the circuit is simple. However, the current-limiting effect of the NTC resistor is greatly affected by ambient temperature. At low temperatures during startup, the resistance value is high, which, while effectively suppressing the startup inrush current, results in a small charging current for the capacitor, potentially affecting the power supply's startup. At high temperatures during startup, the resistance value becomes relatively small, reducing the ability to suppress the inrush current and potentially failing to achieve the required suppression effect. Therefore, this solution has high environmental requirements and cannot operate in high or low temperature environments. In addition, this method has requirements for the power-on time interval. Since the NTC resistor needs a certain amount of time to cool down and return to its nominal resistance value, the switching power supply must be prevented from restarting immediately after power failure, otherwise the NTC resistor will not be able to play the role of suppressing inrush current.

[0008] 2. The method of suppressing starting inrush current using a power resistor in parallel with a relay involves connecting a current-limiting power resistor in series in the input circuit, while simultaneously connecting a relay in parallel across the resistor. Upon power-up, the relay is in the open state, and the power resistor limits the current, charging the capacitor. Once the voltage across the capacitor reaches the normal operating voltage, a delay monitoring circuit controls the relay to close, short-circuiting the power resistor and entering normal operation. This method avoids the drawback of using NTC resistors, which prevents continuous starting, and offers excellent inrush current suppression. However, this method has disadvantages: the relay requires a control circuit, and the voltage of this circuit often affects circuit complexity. Furthermore, when the relay switches from open to closed, arcing can easily occur on high-voltage DC, leading to secondary inrush current. Mechanical relays also suffer from poor vibration resistance, making them unsuitable for harsh, vibrating environments. To prevent the power resistor from failing during startup, a wire-wound resistor with a power rating of approximately 5W to 20W is typically selected.

[0009] 3. Using a power resistor in parallel with a thyristor to suppress starting inrush current: This method involves connecting a current-limiting power resistor in series in the input circuit, and simultaneously connecting a thyristor in parallel across the resistor. The working principle is that when the power supply is turned on, the thyristor is not conducting, and the capacitor charges through the power resistor with current limitation. When the voltage across the capacitor rises to a certain value, the trigger circuit turns on the thyristor, short-circuiting the power resistor, and the power supply enters normal operating mode. This method of suppressing starting inrush current avoids the shortcomings of relays, such as their inability to operate in harsh environments with high vibration intensity and their inability to start continuously. It has a very good inrush current suppression effect. The resistor power should be selected at around 5W to 20W. The thyristor can also be replaced with a MOSFET. However, the traditional trigger circuit design is relatively complex and not easy to use flexibly. Furthermore, in switching power supplies using APFC circuits, the starting inrush current is very large, making it impossible to limit the starting current to the specified range.

[0010] In switching power supplies using APFC circuits, the value of the power resistor cannot be too large when employing the aforementioned traditional methods. Otherwise, at the instant the relay or thyristor closes, the impedance change in the circuit due to the capacitor charging voltage not reaching the input peak voltage will also cause a secondary inrush current during startup. The larger the power resistor value, the larger the secondary inrush current. Furthermore, in special power supply environments, due to limited space and relatively small generator capacity, there are specific restrictions on the input inrush current of various electronic devices using switching power supplies. For example, GJB 181B-2012 clearly specifies the requirements for the startup inrush current of airborne equipment power supplies, stipulating that the peak inrush current for equipment with a power greater than 200W should not exceed five times the rated current. In such cases, traditional inrush current suppression circuits may not be suitable for the switching power supplies of these devices. Summary of the Invention

[0011] The purpose of this invention is to provide a circuit for suppressing startup inrush current, which effectively suppresses the startup inrush current of a switching power supply using APFC and ensures reliable operation of the circuit.

[0012] The technical solution to achieve the objective of this invention is as follows: a startup inrush current suppression circuit, comprising a rectifier bridge, a first current-limiting startup circuit, a second current-limiting startup circuit, and a Boost circuit; the input terminal of the rectifier bridge is connected to an AC power supply, the positive output terminal of the rectifier bridge is connected to the positive input terminal of the first current-limiting startup circuit and the positive input terminal of the Boost circuit, and the negative output terminal of the rectifier bridge is connected to the negative input terminal of the first current-limiting startup circuit and the source of the MOSFET of the second current-limiting startup circuit; the first output terminal of the first current-limiting startup circuit is connected to the input terminal of the second current-limiting startup circuit, and the second output terminal of the first current-limiting startup circuit is connected to the negative output terminal of the Boost circuit; the negative output terminal of the Boost circuit is connected to the drain of the MOSFET of the second current-limiting startup circuit, and the positive output terminal of the Boost circuit is V.OUT .

[0013] Furthermore, the first current-limiting startup circuit includes a second capacitor, a third diode, a second MOSFET, a fourth transistor, and a first to a fifth resistor; one end of the second resistor is connected to the positive output terminal of the rectifier bridge, and the other end of the second resistor is connected to the cathode of the third diode, the anode of the second capacitor, the collector of the fourth transistor, the gate of the second MOSFET, and the second current-limiting startup circuit, respectively; the source of the second MOSFET is connected in series with the first resistor in the ground loop; the third and fourth resistors are connected in series and then in parallel across the first resistor; the voltage across the first resistor is divided by the third and fourth resistors and then connected in series with the fifth resistor to provide the base drive voltage for the fourth transistor; the third diode and the second capacitor are connected in parallel, with the anode of the third diode connected to the emitter of the fourth transistor and the cathode of the third diode connected to the collector of the fourth transistor.

[0014] Furthermore, the second current-limiting start-up circuit includes a delay control circuit and a third MOSFET. The input terminal of the delay control circuit is connected to the first current-limiting start-up circuit, and the other terminal is connected to the gate of the third MOSFET. The drain of the third MOSFET is connected to the negative output terminal of the Boost circuit, and the source is connected to the negative output terminal of the rectifier bridge.

[0015] Furthermore, the input terminal of the delay control circuit is connected to the collector of the fourth transistor in the first current-limiting start-up circuit.

[0016] Furthermore, the Boost circuit includes a first inductor, a first diode, a second diode, a first MOSFET, a first energy storage capacitor, and a load; the input terminal of the first inductor is connected to the positive output terminal of the rectifier bridge and the anode of the first diode, and the output terminal is connected to the anode of the second diode and the drain of the first MOSFET; the cathode of the second diode is connected to the cathode of the first diode and the positive output terminal of the Boost circuit; the source of the first MOSFET is connected to the negative output terminal of the Boost circuit; after the first energy storage capacitor is connected in parallel with the load, the positive terminal of the first energy storage capacitor is connected to the positive output terminal of the Boost circuit, and the negative terminal is connected to the negative output terminal of the Boost circuit.

[0017] Compared with the prior art, the significant advantages of this invention are:

[0018] 1) It can effectively suppress the starting inrush current in the APFC circuit and ensure the reliable operation of the circuit.

[0019] 2) The starting inrush current can be suppressed to within 4A.

[0020] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the inrush current suppression circuit in one embodiment.

[0022] Figure 2 Figure (a) shows the measured starting inrush current waveform of a 230V input, and Figure (b) shows the measured starting inrush current waveform of a 115V input. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0024] It should be noted that if the embodiments of the present invention involve descriptions such as "first" and "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0025] In one embodiment, refer to Figure 1 This explains the working principle of the inrush current suppression circuit of the present invention.

[0026] A specific embodiment provides a startup inrush current suppression circuit, including a rectifier bridge DB1, a first current-limiting startup circuit, a second current-limiting startup circuit, and a Boost circuit. The first current-limiting startup circuit includes a second capacitor C2, a third diode D3, a second MOSFET Q2, a fourth transistor Q4, and first to fifth resistors R1-R5; the second current-limiting startup circuit includes a delay control circuit and a third MOSFET Q3; the Boost circuit includes a first inductor L1, a first diode D1, a second diode D2, a first MOSFET Q1, an energy storage capacitor C1, and a load R. L .

[0027] The main power circuit of the APFC circuit is completed by a Boost converter. The AC power is converted into DC voltage by the rectifier bridge and input to the Boost circuit. The Boost circuit boosts the voltage to about 380V for output.

[0028] When the circuit is powered on, the current flows through the rectifier bridge DB1 and charges the second capacitor C2. When the voltage across C2 reaches the gate turn-on voltage of the second MOSFET Q2, the second MOSFET Q2 transitions from the off state to a linear operating state, meaning that the leakage current flowing through it increases with the increase of the gate voltage. When the second MOSFET Q2 is turned on, the current flows through the first diode D1, the second diode D2, the first inductor L1, the first energy storage capacitor C1, the second MOSFET Q2, and the first power resistor R1 to the negative output terminal of the rectifier bridge DB1. As the current flowing through the second MOSFET Q2 increases, the voltage across the power resistor R1 also increases. This voltage is detected and divided by the third resistor R3 and the fourth resistor R4, and then supplied to the fourth transistor Q4 via the fifth resistor R5 as the base drive voltage of the fourth transistor Q4. When the voltage reaches the base drive voltage of the fourth transistor Q4, Q4 turns on and pulls down the gate voltage of the second MOSFET Q2, turning Q2 off. Simultaneously, the voltage on the second capacitor C2 is rapidly discharged through the fourth transistor Q4. With the second MOSFET Q2 turned off, the current path through the first diode D1, the second diode D2, the first inductor L1, the first energy storage capacitor C1, the second MOSFET Q2, and the first power resistor R1 is cut off. The current recharges the second capacitor C2, thus restarting the second MOSFET Q2. By continuously restarting the second MOSFET Q2, the input startup current is limited. As the charging voltage of the first capacitor C1 rises to near the rectified peak voltage, the second current-limiting startup circuit is activated. A delay control circuit then turns on the third MOSFET Q3, bypassing the power resistor R1 and the second MOSFET Q2 from the main circuit.

[0029] At the initial stage of circuit startup, the controllability of the second MOSFET Q2 operating in the linear region in the first current-limiting startup circuit is utilized. The gate voltage of the second MOSFET Q2 is controlled by detecting the voltage across the power resistor R1, thereby controlling the line impedance and limiting the charging current of the first capacitor C1, thus limiting the startup inrush current to within 4A. Simultaneously, using the second current-limiting startup circuit, after a certain delay time and when the APFC starts working normally, the third MOSFET Q3 is turned on through the delay control circuit, bypassing the power resistor R1 and the second MOSFET Q2 from the main circuit, ensuring the reliability and efficiency of the power supply.

[0030] The first diode D1 is used to prevent the first inductor L1 from saturating due to excessive starting current, thus diverting some of the surge current; the third diode D3 is a Zener diode used to limit the gate voltage of MOSFET Q2, so that the gate of the second MOSFET Q2 operates in the safe voltage region; the second resistor R2 is used to limit the operating current of the third diode D3, and at the same time control the charging current of the second capacitor C2; the third resistor R3 and the fourth resistor R4 are used to detect the voltage across the first MOSFET Q1 and perform voltage division to control the conduction and turn-off of the fourth transistor Q4. By adjusting the resistance values ​​of the third resistor R3 and the fourth resistor R4, the turn-on time of the fourth transistor Q4 can be controlled; the fifth resistor R5 is used to limit the base current supplied to the fourth transistor Q4.

[0031] The switching power supply in this embodiment is a 300W 3U CPCI power supply, and its main circuit parameters are as follows:

[0032] The first MOSFET Q1 to the third MOSFET Q3 are SPA21N50C3; the third Zener diode D3 is BZX84C15. The first resistor R1 is 2W-4.7Ω, the second resistor R2 is 132kΩ, the third resistors R3 and R4 are 33kΩ, and the fifth resistor R5 is 20kΩ; the second inductor L2 is 220μH; the second capacitor C2 is 25V / 10μF, and the first energy storage capacitor C1 is 450V / 300μF.

[0033] Figure 2 The waveforms are the current waveforms of the circuit when it is turned on with an input of 115V / 50Hz and 230V / 50Hz AC power, and a full load of 300W with an AC phase of 90°. Figure 2 middle u i For an input voltage of 220V (or 115V) AC, u o i is the output voltage of APFC. i This represents the input startup current. The current grid is 2A / div. As can be seen from the current waveform, from the moment the voltage is applied until the output voltage is established, the input inrush current is consistently suppressed to below 4A.

[0034] In summary, the present invention can effectively suppress the starting inrush current in the power factor correction circuit and limit the current to within 4A, thus ensuring the reliable operation of the circuit.

[0035] The above embodiments are only used to more clearly illustrate the technical solution of the present invention. The scope of protection of the present invention includes, but is not limited to, the above specific embodiments. Any appropriate changes or substitutions made by a person skilled in the art that conform to the claims of the present invention should fall within the patent protection scope of the present invention.

Claims

1. An inrush current suppression circuit, comprising: The application relates to a rectifier bridge, a first current-limiting starting circuit, a second current-limiting starting circuit and a Boost circuit; the input end of the rectifier bridge is connected with an alternating current power supply, the output positive end V IN of the rectifier bridge is connected with the input positive end of the first current-limiting starting circuit and the input positive end of the Boost circuit, the output negative end GND1 of the rectifier bridge is connected with the input negative end of the first current-limiting starting circuit and the source electrode of a MOSFET tube of the second current-limiting starting circuit; the first output end of the first current-limiting starting circuit is connected with the input end of the second current-limiting starting circuit, the second output end of the first current-limiting starting circuit is connected with the output negative end GND of the Boost circuit; the output negative end of the Boost circuit is connected with the drain electrode of the MOSFET tube of the second current-limiting starting circuit, and the output positive end of the Boost circuit is V OUT . The first current-limiting starting circuit comprises a second capacitor C2, a third diode D3, a second MOSFET tube Q2, a fourth triode Q4, a first resistor R1 to a fifth resistor R5; one end of the second resistor R2 is connected with the output positive end of the rectifier bridge, and the other end of the second resistor R2 is connected with the cathode of the third diode D3, the anode of the second capacitor C2, the collector of the fourth triode Q4, the gate of the second MOSFET tube Q2 and the second current-limiting starting circuit respectively; the source of the second MOSFET tube Q2 is connected in series with the first resistor R1 in the ground loop; the third resistor R3 and the fourth resistor R4 are connected in series and then connected in parallel between the two ends of the first resistor R1; the voltage between the two ends of the first resistor R1 is divided by the third resistor R3 and the fourth resistor R4, and then the fifth resistor R5 is connected in series to provide a base driving voltage for the fourth triode Q4; the third diode D3 and the second capacitor C2 are connected in parallel, the anode of the third diode D3 is connected to the emitter of the fourth triode Q4, and the cathode of the third diode D3 is connected to the collector of the fourth triode Q4. The second current-limiting starting circuit comprises a delay control circuit and a third MOSFET tube Q3, the input end of the delay control circuit is connected with the first current-limiting starting circuit, the other end is connected with the gate of the third MOSFET tube Q3, the drain of the third MOSFET tube Q3 is connected with the output negative end of the Boost circuit, and the source is connected with the output negative end of the rectifier bridge.

2. The start-up inrush current suppressing circuit according to claim 1, wherein The input end of the delay control circuit is connected with the collector of the fourth triode Q4 in the first current-limiting starting circuit.

3. The start-up inrush current suppressing circuit according to claim 1, wherein The Boost circuit comprises a first inductor L1, a first diode D1, a second diode D2, a first MOSFET Q1, a first energy storage capacitor C1 and a load R L The input end of the first inductor L1 is connected with the positive output end of the rectifier bridge and the anode of the first diode D1, and the output end is connected with the anode of the second diode D2 and the drain of the first MOSFET Q1; the cathode of the second diode D2 is connected with the cathode of the first diode D1 and the positive output end of the Boost circuit; the source of the first MOSFET Q1 is connected with the negative output end of the Boost circuit; the first energy storage capacitor C1 is connected with the load R L After being connected in parallel, the positive pole of the first energy storage capacitor C1 is connected to the positive output end of the Boost circuit, and the negative pole is connected to the negative output end of the Boost circuit.

4. The inrush current suppressing circuit according to any one of claims 1 to 3, characterized by The model of the first MOSFET tube Q1 to the third MOSFET tube Q3 MOSFET tube is SPA21N50C3; the model of the third diode D3 is BZX84C15.

5. The start-up inrush current suppressing circuit according to claim 4, wherein The first resistor R1 is selected as 2W-4.7Ω, the second resistor R2 is 132kΩ resistor, the third resistor R3 and the fourth resistor R4 are 33kΩ, and the fifth resistor R5 is 20kΩ; the second inductor L2 is 220μH; the second capacitor C2 is 25V / 10μF, and the first energy storage capacitor C1 is 450V / 300μF.

Images