Capacitive data transmission over galvanic isolation

Abstract

Embodiments of the present disclosure relate to capacitive data transmission over galvanic isolation. In some examples, a device is arranged to include a galvanic isolation barrier between a first voltage domain and a second voltage domain. The device includes a first capacitor and a second capacitor arranged across the galvanic isolation barrier. The first capacitor and the second capacitor are configured to communicate a differential signal between the first domain and the second domain. The device also includes a common mode rejection circuit arranged in the second voltage domain and configured to reject a common mode signal communicated by the first capacitor and the second capacitor. The common mode rejection circuit includes a first passive RLC filter circuit coupled between the first capacitor and a low impedance node. The common mode rejection circuit also includes a second passive RLC filter circuit coupled between the second capacitor and the low impedance node.

Description

Technical Field

[0001] This disclosure relates to communication across current isolation barriers in electronic devices. Background Technology

[0002] Current isolation is used in electronic devices to separate two voltage domains. As an example, a microcontroller can generate and pass control signals to a low-side gate driver and a high-side gate driver for a half-bridge circuit. Current isolation is typically not required between the microcontroller and the low-side gate driver, but the microcontroller will often be current isolated from the high-side gate driver because they are driven by different power supplies. For example, the high-side gate driver typically has a different reference power supply (e.g., reference ground) than the microcontroller. The microcontroller will typically use the same reference power supply as the low-side gate driver, while the high-side gate driver can use the switching node of the half-bridge circuit as its reference power supply and / or reference ground node (e.g., floating ground). Summary of the Invention

[0003] This disclosure describes techniques for suppressing common-mode signals transmitted across a current isolation barrier. Differential signals can be transmitted across the current isolation barrier using a first capacitor and a second capacitor, but common-mode signals may be undesirable and can cause damage to sensitive circuitry. The common-mode suppression circuit of this disclosure may include two passive RLC filter circuits. A first passive RLC filter circuit may be coupled between the first capacitor and a low-impedance node, and a second passive RLC filter circuit may be coupled between the second capacitor and a low-impedance node.

[0004] In some examples, the device is arranged to include a current isolation barrier between a first voltage domain and a second voltage domain. The device includes a first capacitor and a second capacitor arranged across the current isolation barrier. The first and second capacitors are configured to transmit a differential signal between the first and second domains. The device also includes common-mode rejection circuitry arranged in the second voltage domain and configured to suppress common-mode signals transmitted by the first and second capacitors. The common-mode rejection circuitry includes a first passive RLC filter circuit coupled between the first capacitor and a low-impedance node. The common-mode rejection circuitry also includes a second passive RLC filter circuit coupled between the second capacitor and the low-impedance node.

[0005] In some examples, a method includes receiving a first signal from a first capacitor arranged across a current isolation barrier and receiving a second signal from a second capacitor arranged across a current isolation barrier. The method may also include filtering the first signal using a first passive RLC filter circuit coupled between the first capacitor and a low-impedance node. The method may further include filtering the second signal using a second passive RLC filter circuit coupled between the second capacitor and the low-impedance node.

[0006] In some examples, a system includes a first capacitor arranged across a current isolation barrier and a second capacitor arranged across a current isolation barrier. The system also includes an oscillator configured to generate a control signal; a first driver stage configured to generate a first driver signal based on the control signal and deliver the first driver signal to a first side of the first capacitor; and a second driver stage configured to generate a second driver signal based on the control signal and deliver the second driver signal to a first side of the second capacitor. The system also includes receiver circuitry and common-mode rejection circuitry, the common-mode rejection circuitry including a first passive RLC filter circuitry coupled between a second side of the first capacitor, the receiver circuitry, and a low-impedance node, wherein the second side of the first capacitor is different from the first side of the first capacitor, and wherein the first passive RLC filter circuitry is configured to receive the first driver signal from the first capacitor. The common-mode rejection circuitry also includes a second passive RLC filter circuitry coupled between the second capacitor, the receiver circuitry, and the low-impedance node, wherein the second side of the second capacitor is different from the first side of the second capacitor, and wherein the second passive RLC filter circuitry is configured to receive a second driver signal from the second capacitor.

[0007] Details of one or more examples are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0008] Figure 1 This is a conceptual block diagram and circuit diagram of a common-mode rejection circuit coupled to two capacitors arranged across a current isolation barrier, according to the technology disclosed herein.

[0009] Figure 2 This is a timing diagram illustrating the on / off key control coding according to the technology disclosed herein.

[0010] Figure 3 The present disclosure provides a conceptual block diagram and circuit diagram of a common-mode rejection circuit comprising two inductor coils.

[0011] Figure 4 The present disclosure provides a conceptual block diagram and circuit diagram of a common-mode rejection circuit comprising two interleaved inductors.

[0012] Figure 5 This is a diagram of two interleaved inductor coils according to the technology disclosed herein.

[0013] Figures 6A to 9 These are conceptual block diagrams and circuit diagrams of example common-mode suppression circuits based on the technology of this disclosure.

[0014] Figure 6B It is a graph of the frequency and gain of a differential signal transmitted across a current isolation barrier according to the technology of this disclosure.

[0015] Figures 10 to 12 These are conceptual block diagrams and circuit diagrams of an example package comprising two dies according to the technology disclosed herein.

[0016] Figure 13 This is a conceptual block diagram of an example package comprising two dies connected by bonding wires, according to the technology disclosed herein.

[0017] Figure 14 This is a flowchart illustrating an example technique for suppressing common-mode pulses according to the present disclosure. Detailed Implementation

[0018] This disclosure describes apparatus, methods, and techniques for suppressing common-mode signals transmitted across a current isolation barrier. An electronic device may include a current isolation barrier for separating circuit devices having two different voltage levels, protecting users, and / or protecting sensitive circuit devices. Two capacitors may be configured to transmit a differential signal across the current isolation barrier from a first voltage domain to a second voltage domain. However, common-mode pulses may occur on one side of the current isolation barrier. In some examples, common-mode pulses may be electrical noise caused by electrostatic discharge, test pulses applied during laboratory testing, and / or any other noise between the two current-separated power domains. If a sensitive circuit device on either side of the current isolation barrier experiences a common-mode pulse, the pulse may damage the sensitive circuit device.

[0019] This invention describes a common-mode rejection circuit for absorbing or suppressing the energy of common-mode signals. The common-mode rejection circuit may include a passive RLC filter circuit designed to suppress common-mode signals but not differential signals.

[0020] Figure 1 This is a conceptual block diagram of a common-mode rejection circuit (CMSC) 100 coupled to two capacitors 110A and 110B arranged across a current isolation barrier 120, according to the technology disclosed herein. Device 180 in Figure 1The device is depicted as including voltage domains 130 and 140 with different reference ground connections 134 and 144. Voltage domain 130 includes common-mode rejection circuitry 100 and receiver circuitry arrangement 132. Voltage domain 140 includes optional radio frequency (RF) driver stages 142A and 142B and logic circuitry arrangement 146. Voltage domains 130 and 140 may be part of a single die or distributed across two or more semiconductor dies within the device 180.

[0021] Common-mode rejection circuit 100 can be configured to suppress common-mode signals while allowing differential signals to travel from capacitors 110A and 110B to receiver circuitry 132. Common-mode rejection circuit 100 can have a low impedance for common-mode event 150, thereby allowing common-mode signals to travel to reference ground connection 134. Common-mode rejection circuit 100 can also have a high impedance for differential signals, such that differential signals bypass common-mode rejection circuit 100 as they travel from capacitors 110A and 110B to receiver circuitry 132.

[0022] Capacitors 110A and 110B can be configured to transmit signals between voltage domains 130 and 140. (The last part, "When capacitors 110A and 110B are used as...", appears to be a separate, unrelated sentence fragment.) Figure 1 In the example connection shown, capacitors 110A and 110B can be configured to allow high-frequency signals to pass through while blocking low-frequency signals such as DC signals. The common-mode transient (CMT) event 150 can have a high voltage slew rate that can travel across the current isolation barrier 120 via capacitors 110A and 110B. For example, the common-mode transient event 150 can have a slew rate of one hundred volts per nanosecond. In an example where capacitors 110A and 110B have a capacitance of one hundred nanofarads, the discharge current caused by the common-mode event 150 would be 10 mA, which could potentially damage the receiver circuitry 132.

[0023] Electrical isolation barrier 120 includes dielectric, insulating, and / or oxide materials for capacitors 110A and 110B. Current isolation barrier 120 may include a molding compound between two semiconductor dies and / or deep trenches within a semiconductor die. In some examples, current isolation barrier 120 may be configured to protect a user from electric shock. Additionally or alternatively, current isolation barrier 120 may be configured to allow communication between voltage domains with relatively low power dissipation, compared to resistor-based or transistor-based level shifters, both of which experience resistive power losses when boosting electrical signals.

[0024] Voltage domain 130 may have a different voltage range than voltage domain 140. For example, the ranges of voltage domains 130 and 140 may be separated by any voltage difference (e.g., a few volts or less, tens of volts or hundreds of volts). Each of voltage domains 130 and 140 may be on a separate semiconductor die within the package of device 180. Current isolation barrier 120 may extend between the separate dies and / or partially across one or both dies. In some examples, the first voltage domain may have a range of less than 10 volts, and the second voltage domain may have a range of hundreds or thousands of volts.

[0025] One example application of device 180 is for generating driver signals for the high-side switch of a power converter. For example, logic circuitry 146 may be part of a microcontroller that generates control signals for the high-side and low-side switches of the power converter. The low-side switch of the power converter may have the same reference ground connection 144 as logic circuitry 146. However, the high-side switch of the power converter may have a different floating potential than the power supply of logic circuitry 146, and reference ground connection 134 may be connected to the switching node of a half-bridge or full-bridge circuit. The floating potential of receiver circuitry 132 may be tens or hundreds of volts higher than the power supply of logic circuitry 146. When the high-side switch is activated, a common-mode event 150 may be generated, which increases the floating potential of the high-side switch. Other example applications of device 180 include isolated controller area networks or isolated couplers.

[0026] Receiver circuitry 132 can be configured to receive differential signals from capacitors 110A and 110B and generate output 136 based on the differential signals. In some examples, receiver circuitry 132 can be configured to tolerate very low voltage ranges, such as three or five volts. Receiver circuitry 132 may include sensitive input-output circuitry for receiving and processing signals from capacitors 110A and 110B.

[0027] Logic circuit device 146 can be configured to generate a differential signal for transmission across current isolation barrier 120 to voltage domain 130. Logic circuit device 146 can be configured to generate the differential signal based on input 148. In some examples, logic circuit device 146 and / or RF driver stages 142A and 142B may include an oscillator for generating the differential signal as an oscillating signal using, for example, amplitude shift keying (e.g., on / off keying). Logic circuit device 146 can pass the differential signal to RF driver stages 142A and 142B for amplification and / or encoding before transmitting the differential signal across current isolation barrier 120. Logic circuit device 146 and / or RF driver stages 142A and 142B can be configured to activate or deactivate a carrier frequency in response to a signal received from logic circuit device 146. RF driver stages 142A and 142B and logic circuit device 146 can each be coupled to reference ground connection 144.

[0028] Common-mode event 150 can have a sufficient amplitude to damage receiver circuitry 132. To prevent high-amplitude common-mode events from reaching the receiver circuitry, existing devices can activate clamping diodes to clamp the differential lines. However, clamping the differential lines prevents communication across the current isolation barrier because clamping prevents current from flowing across the differential lines.

[0029] Other existing devices include suppression circuitry with transistor networks to suppress common-mode signals from reaching the receiver circuitry. The transistor network can be connected to both the low-side and high-side power nodes, which can introduce noise and interference in one or both power nodes. Furthermore, the transistor network can use bias current to suppress common-mode signals, and because the transistors in the network are so fast, the bias current must be high.

[0030] According to the technology of the present invention, the common-mode rejection circuit 100 may include two passive RLC filter circuits coupled to a low-impedance node (e.g., reference ground connection 134). The common-mode rejection circuit 100 may include a first passive RLC filter circuit coupled between capacitor 110A and reference ground connection 134. The common-mode rejection circuit 100 may include a second passive RLC filter circuit coupled between capacitor 110b and reference ground connection 134. Each passive RLC filter circuit may include an inductor and a capacitor, wherein the resistance (R) may represent the inherent resistance of the inductor and / or discrete resistor.

[0031] Compared to active filters that include transistors and / or other active components, using a passive RLC filter circuit can result in reduced power consumption in suppressing common-mode signals. Furthermore, RLC filters can filter common-mode signals more effectively than RC filters that do not have inductors. Additionally, the common-mode rejection circuit 100 allows the use of less expensive capacitors 110A and 110B, which can lead to a reduction in the overall cost of the device 180.

[0032] Figure 2 This is a timing diagram illustrating the on-off keying (OOK) encoding according to the technology of the present invention. On-off keying is merely one example of encoding differential signals transmitted across a current isolation barrier. Other example encoding protocols include digital amplitude modulation, amplitude shift keying, phase shift keying, and / or quadrature amplitude modulation.

[0033] The logic circuit device can receive input signal 248 and generate differential signals 220A and 220B for transmission across a current isolation barrier. During pulse 210 of input signal 248, the logic circuit device can be configured to generate differential signals 220A and 220B that oscillate at a specific frequency. The logic circuit device can be configured to switch on a carrier frequency in response to input signal 210 having a logic one or a high value, and to turn off the carrier frequency in response to input signal 210 having a logic zero or a low value. The oscillation waveform of differential signal 220A can be the inverse of the oscillation waveform of differential signal 220B, such that signal 220A reaches its maximum amplitude when signal 220B reaches its minimum amplitude. When input signal 210 is between pulses or when input signal 210 has a low or inactive voltage, the logic circuit device can be configured to generate differential signals 220A and 220B as DC signals.

[0034] The receiver circuitry can be configured to receive differential signals 220A and 220B transmitted across a current isolation barrier. The receiver circuitry can then be configured to generate an output signal 236 based on the differential signals 220A and 220B, such that pulses 230 of the output signal 236 occur when the differential signals 220A and 220B oscillate. The receiver circuitry can also be configured to generate an output signal 236 with a low or inactive voltage (e.g., between pulses of the output signal 236) when the differential signals 220A and 220B are not oscillating.

[0035] In some examples, the common-mode rejection circuit can be designed to have a transfer function peak frequency that matches the carrier frequency of the differential signal transmitted across the current isolation barrier. More specifically, the frequency associated with the peak of the transfer function of the combined circuit including the common-mode rejection circuit, the first capacitor, and the second capacitor can be approximately equal to the carrier frequency of the differential signal. Therefore, the discharge current for common-mode interference will flow directly through the common-mode rejection circuit to ground, thus suppressing common-mode interference. The differential signal will experience a peak in the automatic transfer function, which will allow the differential signal to be transmitted from the common-mode rejection circuit to the receiver circuitry.

[0036] Figure 3 This is a conceptual block diagram and circuit diagram of a common-mode rejection circuit 300 comprising two inductors L1 and L1' according to the present invention. Figure 3 In the example device shown, the common-mode rejection circuit 300 includes two passive RLC filter circuits. The first passive RLC filter circuit includes an inductor coil L1, a resistor R1, and a capacitor C1 coupled between capacitor 310A and reference ground connection 334. The second passive RLC filter circuit includes an inductor coil L1', a resistor R1', and a capacitor C1' coupled between capacitor 310B and reference ground connection 334. Therefore, as Figure 3 As shown, the circuit elements of the common-mode rejection circuit 300 are arranged symmetrically about the reference ground connection 334.

[0037] Logic circuit device 346 can be configured to generate a differential signal based on input signal 348. Optional RF driver stages 342A and 342B can be configured to amplify and / or encode the differential signal generated by logic circuit device 346 for transmission across current isolation barrier 320. Common-mode rejection circuit 300 can be configured to present high impedance to differential signals received from capacitors 310A and 310B, while presenting low impedance to common-mode signals received from capacitors 310A and 310B. The low impedance of common-mode rejection circuit 300 allows common-mode signals to pass through common-mode rejection circuit 300 to reference ground connection 334, instead of traveling to receiver circuit device (RX) 332. Low-impedance nodes such as reference ground connection 334 can absorb most or all of the energy of common-mode pulse events, thereby preventing common-mode pulse events from reaching receiver circuit device 332.

[0038] Figure 3 The diagram depicts an inductor coil L1 and a resistor R1 coupled in parallel with capacitor C1, but other configurations are possible. For example, each of the inductor coil L1, resistor R1, and capacitor C1 may be coupled in parallel with each other between capacitor 310A and reference ground connection 334. Resistor R1 may be the inherent resistance of inductor coil L1, or resistor R1 may be a discrete resistor.

[0039] In some examples, the characteristics of the components of the first and second passive RLC filter circuits can be symmetrical or identical. For example, the inductance of inductor coil L1 can be equal to the inductance of inductor coil L1'. In other examples, the differences between the parameters and characteristics of the components of the first and second passive RLC filter circuits can be within tolerances, such as 20%, 10%, 5%, 2%, or 1%. The parameters and characteristics of the passive RLC filter circuit include the circuit's inductance, capacitance, and / or resistance.

[0040] Figure 4 This is a conceptual block diagram and circuit diagram of a common-mode rejection circuit 400 comprising two interleaved inductors L1 and L1' according to the present invention. The interleaved inductors L1 and L1' have a coupling coefficient K1, which represents the percentage of flux linked between the coils. To achieve a tightly coupled inductor pair and a high coupling coefficient, the inductors L1 and L1' can be interleaved and can overlap. To achieve a high coupling coefficient, the inductors L1 and L1' can be arranged symmetrically. Figure 5 An example technique for interleaved inductors L1 and L1' is shown in the figure.

[0041] Figure 5 This is a diagram of two interleaved inductor coils L1 and L1' according to the technology of the present invention. The inductor coils L1 and L1' are depicted as interleaved, overlapping coils having a connection to a reference ground connection 534 at the midpoint between the inductor coils L1 and L1'. Figure 5 Depicts a five-turn or four-turn square overlapping, symmetrical spiral configuration for inductor coils L1 and L1'. In some examples, another shape, such as a circle, ellipse, rectangle, or triangle, may be used for inductor coils L1 and L1'. Inductor coils L1 and L1' can be on-chip inductor coils.

[0042] In some examples, the inductances of inductor coils L1 and L1' may not be precisely symmetrical. It may be necessary to design inductor coils L1 and L1' with different levels of inductance, especially when other circuit components have asymmetrical characteristics (e.g., capacitors, resistors, etc.). Using an overlapping and / or interleaved pair of inductor coils can improve the performance of common-mode rejection circuits. For example, overlapping and / or interleaved inductor coils can lead to increased common-mode rejection and a higher slew rate for common-mode signal suppression.

[0043] Figures 6A to 9 These are conceptual block diagrams and circuit diagrams of example common-mode suppression circuits 600, 700, 800, 900, 902 and 904 according to the technology disclosed herein. Figures 6A-9Optional variations of common-mode rejection circuits 600, 700, 800, 900, 902, and 904, and oscillators 642, 742, 842, and 942 are depicted. For example, common-mode rejection circuit 600 includes oscillator 642 for generating a differential signal for transmission across current isolation barrier 620. Oscillator 642 can be configured to generate the differential signal based on a signal received at input node 648. Oscillator 642 may include a first output node coupled to capacitor 610A and a second output node coupled to capacitor 610B. In some examples, the output node of oscillator 642 may be coupled to an RF driver stage. As with some of the common-mode rejection circuits described in this disclosure, oscillator 642 may also include two interleaved inductor coils.

[0044] Oscillator 642 is depicted as including the same inductors L1 and L1', capacitors C1 and C1', and resistors R1 and R1' as the common-mode rejection circuit 600. Given the matching circuit characteristics, the resonant frequency of oscillator 642 (e.g., the transmission frequency of the differential signal generated by oscillator 642) can be equal to the frequency associated with the peak value of the transfer function of common-mode rejection circuit 600 and capacitors 610A and 620B. By aligning the resonant frequency of oscillator 642 with the frequency associated with the peak value of the transfer function, the differential signal generated by the oscillator can transmit the common-mode rejection circuit 600 to receiver circuit device 632. In some examples, these two frequencies may not be exactly equal, but can be alternatively selected within a threshold percentage, such as one percent, two percent, five percent, ten percent, or twenty percent. For example, if the resonant frequency of oscillator 642 is 500 MHz, and the frequency associated with the peak value of the transfer function of common-mode rejection circuit 600 and capacitors 610A and 610B is 510 MHz, then the difference between these two frequencies is within a tolerance of two percent.

[0045] Figure 6B This is a graph showing the frequency and gain of a differential signal transmitted across a current isolation barrier according to the technology of this disclosure. Curve 690 represents the automatic transfer function of the combined circuit including common-mode rejection circuit 600 and capacitors 610A and 610B. Curve 692 represents the transfer function of the common-mode signal transmitted across the current isolation barrier 620. The peak value 694 of curve 690 is associated with the frequency at which the signal is transmitted from capacitors 610A and 610B to receiver circuitry 632 with minimal voltage loss. Figure 6BThe example peak frequency shown is 1.08 GHz, but the common-mode rejection circuit 600 and capacitors 610A and 610B can be designed for any other peak frequency. The gain along curve 692 at the peak frequency (e.g., -37.4 dB at point 696) is much smaller than the gain of the automatic transfer function (e.g., -4.16 dB at point 694), which allows the differential signal at the peak frequency to be passed from capacitors 610A and 610B to the receiver circuitry 632. Therefore, for Figure 6B As shown in the example, the common-mode rejection circuit 600 can suppress the common-mode signal by approximately 33 dB at the peak frequency. Equation (1) is an example of the automatic transfer function of the capacitor 610A and the common-mode rejection circuit 600.

[0046]

[0047] The resonant frequency of the oscillator and the frequency associated with the peak of the transfer function of the common-mode rejection circuit and the differential capacitor can be tuned or adjusted to achieve a better match between these two frequencies. This better frequency matching can lead to better transmission of the differential signal and suppression of the common-mode signal. Furthermore, tuning can provide a better balance and match between the two sides of the oscillator 742 or between the two sides of the common-mode rejection circuit 800. For example, the oscillator 742 includes a tunable tuning capacitor (Ctune) coupled in parallel with capacitors C1 and C1'. Similarly, the common-mode rejection circuit 800 also includes a tunable capacitor coupled in parallel with capacitors C1 and C1'. In some examples, either or both of the oscillator and the common-mode rejection circuit may include a tunable capacitor, a resistor, and / or an inductor.

[0048] By tuning, adjusting, or modifying the capacitance of oscillator 742 and common-mode rejection circuit 800, the resonant frequency of oscillator 742 and the frequency associated with the peak values ​​of the transfer functions of common-mode rejection circuit 800 and capacitors 810a and 810b can be changed and / or matched. In some examples, the tunable elements of oscillator 742 and common-mode rejection circuit 800 can be circuit elements that can be connected or disconnected by activating or disabling switches. For example, additional capacitors can be connected in parallel to increase the equivalent capacitance by activating a switch on each side of the capacitors to connect the additional capacitors to other capacitors in the circuit.

[0049] Tuning of capacitors C1 and C1' can be performed in the manufacturing facility and / or in the field. Tuning of capacitors C1 and C1' can be an automated process performed by the logic circuitry within the device as part of test mode operation, or it can be performed by external test equipment or technicians. Capacitors C1 and C1' can be tested by internal logic, external test equipment, or technicians to determine if there is a mismatch between capacitors C1 and C1' in oscillator 742 and common-mode rejection circuit 800. To improve the matching between capacitors C1 and C1' in oscillator 742, capacitors on one or both sides of oscillator 742 can be tuned.

[0050] Mismatch between capacitors 710A and 710B, or between capacitors 810A and 810B, can cause amplitude mismatch in signals transmitted across current isolation barriers 720 or 820. For example, a balanced signal transmitted across an unbalanced capacitor can produce an unbalanced signal. Mismatch between capacitors arranged across current isolation barriers can be addressed by tuned oscillators 742 or 842 and / or common-mode rejection circuits 700 or 800. Tuned oscillators or common-mode rejection circuits may be simpler to adjust the characteristics of capacitors 710A, 710B, 810A, and 810B after manufacturing.

[0051] Figure 9 Depicting what can be used Figure 7 and 8 The tunable circuit shown is a supplementary or alternative variant. Figure 9 The device 980 shown includes three pairs of capacitors 910A, 910B, 912A, 912B, 914A, and 914B, three common-mode rejection circuits 900, 902, and 904, and receiver circuits 932-934. An oscillator 942 can be configured to generate differential signals for all three receiver circuits 932-934, with each capacitor pair transmitting a differential signal to a separate channel. The transmission of the differential signal to each receiver circuit in the receiver circuits 932-934 can be controlled by activating or disabling input signals T1, T2, and T3. Therefore, one oscillator 942 can be used for communication along three channels, each with a receiver circuit. The device 980 is depicted as containing a pair of driver stages for each channel, but in some examples, a single driver stage pair can be configured to pass the differential signal to each capacitor pair.

[0052] Figures 10-12These are conceptual block diagrams and circuit diagrams of example packages 1080, 1180, and 1280 comprising two dies according to the technology of this disclosure. Package 1080 includes, for example, dies 1090 and 1092. A current isolation barrier 1020 and capacitors 1010A and 1010B are arranged on die 1090 such that bond lines 1094A and 1094B are within voltage domain 1030. Voltage domain 1030 also includes common-mode rejection circuitry 1000, receiver circuitry 1032, and a reference ground connection 1034. Voltage domain 1040 includes transmitter circuitry 1042 and a reference ground connection 1044.

[0053] exist Figure 11 In the example shown, current isolation barrier 1120 and capacitors 1110A and 1110B are arranged on die 1192 such that bond lines 1194A and 1194B are within voltage domain 1140. Voltage domain 1140 also includes transmitter circuitry 1142 and a reference ground connection 1144. Voltage domain 1130 includes common-mode rejection circuitry 1100, receiver circuitry 1132, and a reference ground connection 1134.

[0054] Packages 1080, 1180, and 1280 may contain molding compound and / or any other insulating material between each pair of dies 1090 and 1092, 1190 and 1192, and 1290 and 1292. The molding compound or insulating material may partially or completely surround each of the dies 1090, 1092, 1190, 1192, 1290, and 1292. Figures 10-12 Each of the two dies shown can be arranged on a separate lead frame. Although not in Figures 10-12 As shown in the figure, another possibility is that a single die may include two voltage domains, a current isolation barrier, a transmitter, a receiver, and a common-mode rejection circuit, wherein the voltage domains are separated by a current isolation barrier that passes through the oxide of the capacitor and through deep trenches on the single die.

[0055] Package 1280 can provide maximum isolation between the two voltage domains due to capacitors 1210A, 1210B, 1212A, and 1212B. Voltage domain 1230 can be entirely on die 1290, and voltage domain 1240 can be entirely on die 1292. A third voltage domain can exist between voltage domains 1230 and 1240, wherein the third voltage domain includes bond lines 1294A and 1294B. By including a pair of capacitors on each die 1290 and 1292, the voltage experienced by each capacitor can be halved compared to the voltage experienced by a single capacitor pair (e.g., capacitors 1010A, 1010B, 1110A, and 1110B).

[0056] Figure 13This is a conceptual block diagram of an example package 1380 including two dies 1390 and 1392 connected by bonding wire 1394, according to the technology disclosed herein. Figure 13 Describing something similar to Figure 10 The example shown is of package 1080. Other examples are possible, where a capacitor is formed on die 1092 (similar to...). Figure 11 The package 1180 shown in the image or the dies 1090 and 1092 (similar to) Figure 12 The package shown is 1280.

[0057] Capacitor 1310A includes metal layers 1312 and 1316 separated by oxide 1314. An insulating material between oxide 1314 and dies 1390 and 1392 can form a current isolation barrier 1320. Oxide 1314 can be about 5 micrometers, 10 micrometers, 15 micrometers, or 20 micrometers thick. In some examples, the thickness of oxide 1314 is greater than ten micrometers, which can result in very high breakdown voltages. The spacing between other layers in die 1390 can be less than 1 micrometer (e.g., 300 nanometers).

[0058] In some examples, metal layer 1316 may be connected to transmitter circuitry. The transmitter circuitry can pass signals to metal layer 1316 for transmission across current isolation barrier 1320. For example, pushing a negative charge onto metal layer 1316 can attract a positive charge on metal layer 1312. Therefore, a signal can propagate from metal layer 1312 to die 1392 via bonding wire 1394, and die 1392 may include common-mode rejection circuitry for suppressing common-mode signals. Although Figures 10-13 The diagram depicts the connections between dies as bonding wires, but other connections are also possible, such as leadframe connections, metal pad or board connections, and / or post connections.

[0059] Figure 14 This is a flowchart illustrating an example technique for suppressing common-mode pulses according to the present invention. (Reference) Figure 1 The system description shown in the document Figure 14 The present invention may be performed using other components or devices, but similar techniques consistent with the present invention may be performed using other components or devices.

[0060] exist Figure 14In the example, the common-mode rejection circuit 100 receives a first signal (1400) from a capacitor 110a arranged across the current isolation barrier 120. The common-mode rejection circuit 100 also receives a second signal (1402) from a capacitor 110b arranged across the current isolation barrier 120. The first and second signals can be simultaneously received by the common-mode rejection circuit 100 as differential signals and / or common-mode signals. For example, a common-mode event 150 may include an increase or decrease in the voltage emitted by both capacitors 110a and 110b.

[0061] Common-mode rejection circuit 100 filters the first signal (1404) through a first passive RLC filter circuit coupled between capacitor 110A and reference ground connection 134. Common-mode rejection circuit 100 filters the second signal (1406) through a second passive RLC filter circuit coupled between capacitor 110B and reference ground connection 134. Reference ground connection 134 is an example of a low-impedance node; other examples include power connections and / or any other electrical conductor that can carry a large amount of charge. Common-mode rejection circuit 100 may have high impedance for the differential signal at the transmission frequency and low impedance for the common-mode signal, thereby allowing only the common-mode elements of the signal to pass through the passive RLC filter circuit to reference ground connection 134. Common-mode rejection circuit 100 may be configured to suppress the common-mode signal by at least 6 dB, preferably 10 dB or even 20 dB relative to the differential signal transmitted at the peak frequency.

[0062] The following numbered examples illustrate one or more aspects of this disclosure.

[0063] Example 1. A device is arranged to include a current isolation barrier between a first voltage domain and a second voltage domain. The device includes a first capacitor arranged across the current isolation barrier and a second capacitor arranged across the current isolation barrier. The first and second capacitors are configured to transmit a differential signal between the first and second domains. The device also includes a common-mode rejection circuit arranged in the second voltage domain and configured to suppress common-mode signals transmitted by the first and second capacitors. The common-mode rejection circuit includes a first passive RLC filter circuit coupled between the first capacitor and a low-impedance node. The common-mode rejection circuit also includes a second passive RLC filter circuit coupled between the second capacitor and the low-impedance node.

[0064] Example 2. According to the device of Example 1, the first passive RLC filter circuit includes a first inductor coil.

[0065] Example 3. The device according to Example 1 or Example 2, wherein the second passive RLC filter circuit includes a second inductor coil.

[0066] Example 4. A device based on Examples 1-3 or any combination thereof, wherein the first inductor coil is interleaved with the second inductor coil.

[0067] Example 5. A device according to Examples 1-4 or any combination thereof, wherein the first inductor coil overlaps with the second inductor coil.

[0068] Example 6. A device based on Examples 1-5 or any combination thereof, wherein the first and second inductors are symmetrical about the low-impedance node.

[0069] Example 7. A device according to Examples 1-6 or any combination thereof, wherein the difference between the electrical characteristics of the first passive RLC filter circuit and the electrical characteristics of the second passive RLC filter circuit is less than 20 percent, or less than 10 percent, or less than 5 percent, or less than 2 percent, or less than 1 percent.

[0070] Example 8. A device based on Examples 1-7 or any combination thereof, wherein the first passive RLC filter circuit and the second passive RLC filter circuit are symmetrical about the low-impedance node.

[0071] Example 9. The device according to Examples 1-8 or any combination thereof also includes an oscillator arranged in the first voltage domain.

[0072] Example 10. A device according to Examples 1-9 or any combination thereof, wherein the oscillator is configured to generate a differential signal at the transmission frequency.

[0073] Example 11. A device according to Examples 1-10 or any combination thereof, wherein the difference between the transmission frequency of the differential signal and the frequency associated with the peak value in the transfer function of the first capacitor, the second capacitor, and the common-mode rejection circuit is less than 20 percent, or less than 10 percent, or less than 5 percent, or less than 2 percent, or less than 1 percent.

[0074] Example 12. A device according to Examples 1-11 or any combination thereof, wherein the oscillator is tuned to adjust the transmission frequency of the differential signal.

[0075] Example 13. A device according to Examples 1-12 or any combination thereof, wherein the common-mode rejection circuit is tunable to adjust the frequency associated with the peak value in the transfer function of the first capacitor, the second capacitor, and the common-mode rejection circuit.

[0076] Example 14. A device according to Examples 1-13 or any combination thereof, wherein the first passive RLC filter circuit includes a first inductor and a third capacitor.

[0077] Example 15. A device according to Examples 1-14 or any combination thereof, wherein a first inductor coil is coupled in parallel with a third capacitor between the first capacitor and a low-impedance node.

[0078] Example 16. A device according to Examples 1-15 or any combination thereof, wherein the second passive RLC filter circuit includes a second inductor and a fourth capacitor.

[0079] Example 17. A device according to Examples 1-16 or any combination thereof, wherein a second inductor is coupled in parallel with a fourth capacitor between the second capacitor and a low-impedance node.

[0080] Example 18. A device according to Examples 1-17 or any combination thereof further includes a first set of driver stages arranged in a first voltage domain, wherein the first set of driver stages is configured to deliver a first set of signals to a first capacitor and a second capacitor.

[0081] Example 19. The device according to Examples 1-18 or any combination thereof also includes a fifth capacitor arranged across a current isolation barrier.

[0082] Example 20. The device according to Examples 1-19 or any combination thereof also includes a sixth capacitor arranged across a current isolation barrier.

[0083] Example 21. A device according to Examples 1-20 or any combination thereof further includes a second set of driver stages arranged in a first voltage domain, wherein the second set of driver stages is configured to deliver a second set of signals to a fifth capacitor and a sixth capacitor.

[0084] Example 22. The device according to Examples 1-21 or any combination thereof further includes a second common-mode rejection circuit arranged in the second voltage domain.

[0085] Example 23. A device according to Examples 1-22 or any combination thereof, wherein the first passive RLC filter circuit includes a third capacitor, a first inductor, and no transistors.

[0086] Example 24. A device according to Examples 1-23 or any combination thereof, wherein the second passive RLC filter circuit includes a fourth capacitor, a second inductor, and no transistors.

[0087] Example 25. The device according to Examples 1-24 or any combination thereof further includes a first driver stage arranged in a first voltage domain, wherein the first driver stage is configured to generate a first on / off keying signal based on an oscillation signal received from an oscillator.

[0088] Example 26. The device according to Examples 1-25 or any combination thereof further includes a second driver stage arranged in the first voltage domain, wherein the second driver stage is configured to generate a second on / off keying signal based on an oscillation signal received from an oscillator.

[0089] Example 27. The device according to Examples 1-26 or any combination thereof also includes receiver circuitry coupled to the first capacitor and the second capacitor.

[0090] Example 28. A device according to Examples 1-27 or any combination thereof, wherein a first passive RLC filter circuit is coupled between a first capacitor, a receiver circuit, and a low-impedance node.

[0091] Example 29. A device according to Examples 1-28 or any combination thereof, wherein a second passive RLC filter circuit is coupled between a second capacitor, a receiver circuit, and a low-impedance node.

[0092] Example 30. The device according to Examples 1-29 or any combination thereof also includes a package comprising a first die and a second die.

[0093] Example 31. An apparatus according to Examples 1-30 or any combination thereof, wherein a first capacitor and a second capacitor are arranged on a first die.

[0094] Example 32. A device according to Examples 1-31 or any combination thereof, wherein a common-mode rejection circuit is arranged on a second die.

[0095] Example 33. An apparatus according to Examples 1-32 or any combination thereof, wherein a first capacitor and a second capacitor are arranged on a second die.

[0096] Example 34. The device according to Examples 1-33 or any combination thereof also includes a package comprising a single die, wherein a deep trench is disposed on the single die, wherein a common-mode rejection circuit is disposed on a first side of the deep trench, and wherein an oscillator is disposed on a second side of the deep trench.

[0097] Example 35. A method includes receiving a first signal from a first capacitor arranged across a current isolation barrier and receiving a second signal from a second capacitor arranged across a current isolation barrier. The method may further include filtering the first signal by a first passive RLC filter circuit coupled between the first capacitor and a low-impedance node. The method may further include filtering the second signal by a second passive RLC filter circuit coupled between the second capacitor and the low-impedance node. Filtering the first and second signals includes suppressing common-mode signals transmitted by the first and second capacitors, and wherein the first and second passive RLC filter circuits are arranged in a second voltage domain.

[0098] Example 36. The method according to Example 35 further includes generating an oscillating signal at a transmission frequency in a first voltage domain.

[0099] Example 37. The method according to Example 35 or Example 36 further includes generating a first on / off keying signal based on the oscillation signal.

[0100] Example 38. The method according to Examples 35-37 or any combination thereof also includes generating a second on / off keying signal based on the oscillation signal.

[0101] Example 39. The method according to Examples 35-38 or any combination thereof further includes passing a first on / off switch signal to a first side of a first capacitor, wherein a second side of the first capacitor is coupled to a first passive RLC filter circuit, and wherein the first side of the first capacitor is different from the second side of the first capacitor.

[0102] Example 40. The method according to Examples 35-39 or any combination thereof further includes passing a second on / off switch signal to a first side of a second capacitor, wherein a second side of the second capacitor is coupled to a second passive RLC filter circuit, and wherein the first side of the second capacitor is different from the second side of the second capacitor.

[0103] Example 41. According to the method of Examples 35-40 or any combination thereof, the first passive RLC filter circuit includes a first inductor coil.

[0104] Example 42. According to the method of Examples 35-41 or any combination thereof, the second passive RLC filter circuit includes a second inductor coil.

[0105] Example 43. A method according to Examples 35-42 or any combination thereof, wherein the first inductor coil is interleaved with the second inductor coil.

[0106] Example 44. A method according to Examples 35-43 or any combination thereof, wherein the first inductor coil overlaps with the second inductor coil.

[0107] Example 45. A method based on Examples 35-44 or any combination thereof, wherein the first and second inductors are symmetrical about the low-impedance node.

[0108] Example 46. According to the method of Examples 35-45 or any combination thereof, the difference between the electrical characteristics of the first passive RLC filter circuit and the electrical characteristics of the second passive RLC filter circuit is less than 20 percent.

[0109] Example 47. A method according to Examples 35-46 or any combination thereof, wherein the first passive RLC filter circuit and the second passive RLC filter circuit are symmetrical about the low-impedance node.

[0110] Example 48. According to the method of Examples 35-47 or any combination thereof, the difference between the transmission frequency of the differential signal and the frequency associated with the peak value in the transfer function of the first and second capacitors and the common-mode rejection circuit is less than 20 percent, or less than 10 percent, or less than 5 percent, or less than 2 percent, or less than 1 percent.

[0111] Example 49. The method according to Examples 35-48 or any combination thereof also includes adjusting the transmission frequency of the differential signal by tuning the capacitor of the oscillator.

[0112] Example 50. The method according to Examples 35-49 or any combination thereof further includes adjusting the frequency associated with the peak value in the transfer function of the first capacitor, the second capacitor, and the common-mode rejection circuit by tuning the capacitor of the common-mode rejection circuit.

[0113] Example 51. A system includes: a first capacitor arranged across a current isolation barrier and a second capacitor arranged across a current isolation barrier. The system further includes an oscillator configured to generate a control signal; a first driver stage configured to generate a first driver signal based on the control signal and deliver the first driver signal to a first side of the first capacitor; and a second driver stage configured to generate a second driver signal based on the control signal and deliver the second driver signal to the first side of the second capacitor. The system also includes a receiver circuit and a common-mode rejection circuit, the common-mode rejection circuit including a first passive RLC filter circuit coupled between a second side of the first capacitor, the receiver circuit, and a low-impedance node, wherein the second side of the first capacitor is different from the first side of the first capacitor, and wherein the first passive RLC filter circuit is configured to receive the first driver signal from the first capacitor. The common-mode rejection circuit also includes a second passive RLC filter circuit coupled between the second capacitor, the receiver circuit, and the low-impedance node, wherein the second side of the second capacitor is different from the first side of the second capacitor, and wherein the second passive RLC filter circuit is configured to receive the second driver signal from the second capacitor.

[0114] Example 52. The system according to Example 51 also includes elements of the devices of Examples 1-34 or any combination thereof.

[0115] Example 53. A system comprising means for performing the methods of Examples 35-47 or any combination thereof.

[0116] Various examples of this disclosure have been described. Any combination of the described systems, operations, or functions is contemplated. These and other examples are within the scope of the appended claims.

Claims

1. A device arranged to include a current isolation barrier between a first voltage domain and a second voltage domain, the device comprising: A first capacitor is arranged across the current isolation barrier; A second capacitor is arranged across the current isolation barrier, wherein the first capacitor and the second capacitor are configured to transmit a differential signal at a transmission frequency between the first voltage domain and the second voltage domain, wherein the transmission frequency is determined by an oscillator disposed in the first voltage domain. as well as A common-mode rejection circuit is arranged in the second voltage domain and configured to suppress the common-mode signal transmitted by the first capacitor and the second capacitor. The difference between the transmission frequency of the differential signal and the frequency associated with the peak value in the transfer function of the first capacitor, the second capacitor, and the common-mode rejection circuit is less than 20 percent. The common-mode rejection circuit includes: The first passive RLC filter circuit is coupled between the first capacitor and the low-impedance node; as well as The second passive RLC filter circuit is coupled between the second capacitor and the low-impedance node.

2. The device according to claim 1, The first passive RLC filter circuit includes a first inductor coil. The second passive RLC filter circuit includes a second inductor coil, and The first inductor coil and the second inductor coil are interleaved.

3. The device according to claim 2, wherein the first inductor coil overlaps with the second inductor coil.

4. The device of claim 2, wherein the first inductor and the second inductor are symmetrical about the low-impedance node.

5. The device according to claim 1, wherein the difference between the electrical characteristics of the first passive RLC filter circuit and the electrical characteristics of the second passive RLC filter circuit is less than 20%.

6. The device of claim 1, wherein the first passive RLC filter circuit and the second passive RLC filter circuit are symmetrical about the low impedance node.

7. The device of claim 1, wherein the oscillator is tuned to adjust the transmission frequency of the differential signal.

8. The device of claim 1, wherein the common-mode rejection circuit is tuned to adjust the frequency associated with the peak value in the transfer function of the first capacitor, the second capacitor, and the common-mode rejection circuit.

9. The device according to claim 1, The first passive RLC filter circuit includes a first inductor and a third capacitor. The first inductor coil and the third capacitor are coupled in parallel between the first capacitor and the low-impedance node. The second passive RLC filter circuit includes a second inductor and a fourth capacitor, and The second inductor coil is coupled in parallel with the fourth capacitor between the second capacitor and the low-impedance node.

10. The device according to claim 1, further comprising: A first set of driver stages is arranged in the first voltage domain, wherein the first set of driver stages is configured to deliver a first set of signals to the first capacitor and the second capacitor; A third capacitor is arranged across the current isolation barrier; A fourth capacitor is arranged across the current isolation barrier; A second set of driver stages is arranged in the first voltage domain, wherein the second set of driver stages is configured to transmit a second set of signals to the third capacitor and the fourth capacitor; as well as The second common-mode rejection circuit is arranged in the second voltage domain.

11. The device according to claim 1, The first passive RLC filter circuit includes a third capacitor, a first inductor, and no transistors. The second passive RLC filter circuit includes a fourth capacitor, a second inductor, and no transistors.

12. The device according to claim 1, further comprising: A first driver stage is arranged in the first voltage domain, wherein the first driver stage is configured to generate a first on / off keying signal based on an oscillation signal received from the oscillator; as well as A second driver stage is arranged in the first voltage domain, wherein the second driver stage is configured to generate a second on / off keying signal based on the oscillation signal received from the oscillator. The differential signal includes the first on / off key signal and the second on / off key signal.

13. The device according to claim 1, further comprising a receiver circuit. The first passive RLC filter circuit is coupled between the first capacitor, the receiver circuit, and the low-impedance node, and The second passive RLC filter circuit is coupled between the second capacitor, the receiver circuit, and the low-impedance node.

14. The device according to claim 1, further comprising a packaging component, the packaging component comprising a first die and a second die, The first capacitor and the second capacitor are arranged on the first die, and The common-mode suppression circuit is arranged on the second die.

15. A method for suppressing common-mode signals transmitted across a current isolation barrier, comprising: An oscillation signal is generated using the transmission frequency in the first voltage domain; A first signal is received from a first capacitor arranged across a current isolation barrier at the transmission frequency, wherein the current isolation barrier separates the first voltage domain from the second voltage domain; A second signal is received from a second capacitor arranged across the current isolation barrier at the transmission frequency, wherein the first signal and the second signal comprise differential signals; The first signal is filtered by a first passive RLC filter circuit that is coupled between the first capacitor and the low-impedance node using a common-mode rejection circuit. as well as The second signal is filtered by a second passive RLC filter circuit coupled between the second capacitor and the low-impedance node, which is part of the common-mode rejection circuit. The difference between the transmission frequency of the differential signal and the frequency associated with the peak value in the transfer function of the first capacitor, the second capacitor, and the common-mode rejection circuit is less than 20%. The filtering of the first signal and the second signal includes suppressing the common-mode signal transmitted by the first capacitor and the second capacitor, and The first passive RLC filter circuit and the second passive RLC filter circuit are arranged in the second voltage domain.

16. The method of claim 15, further comprising: A first on / off key control signal is generated based on the oscillation signal; A second on / off key control signal is generated based on the oscillation signal; The first on / off keying signal is transmitted to a first side of the first capacitor, wherein a second side of the first capacitor is coupled to the first passive RLC filter circuit, and wherein the first side of the first capacitor is different from the second side of the first capacitor; and The second on / off key control signal is transmitted to the first side of the second capacitor. The differential signal includes the first on / off key signal and the second on / off key signal. The second side of the second capacitor is coupled to the second passive RLC filter circuit, and The first side of the second capacitor is different from the second side of the second capacitor.

17. A system arranged to include a current isolation barrier between a first voltage domain and a second voltage domain, comprising: A first capacitor is arranged across a current isolation barrier; A second capacitor is arranged across the current isolation barrier, wherein the first capacitor and the second capacitor are configured to transmit a differential signal between the first voltage domain and the second voltage domain. An oscillator is configured to generate a first control signal and a second control signal at a transmission frequency, wherein the oscillator is arranged in the first voltage domain; A first driver stage is configured to generate a first driver signal based on the first control signal and transmit the first driver signal to a first side of the first capacitor; A second driver stage is configured to generate a second driver signal based on the second control signal and transmit the second driver signal to a first side of the second capacitor, wherein the first driver stage and the second driver stage are arranged in the first voltage domain, and wherein the differential signal includes the first driver signal and the second driver signal; The receiver circuit is arranged in the second voltage domain; as well as A common-mode rejection circuit is arranged in the second voltage domain, the common-mode rejection circuit comprising: A first passive RLC filter circuit is coupled between a second side of the first capacitor, the receiver circuit, and a low-impedance node, wherein the second side of the first capacitor is different from the first side of the first capacitor, and wherein the first passive RLC filter circuit is configured to receive the first driver signal from the first capacitor. as well as A second passive RLC filter circuit is coupled between the second capacitor, the receiver circuit, and the low-impedance node, wherein the second side of the second capacitor is different from the first side of the second capacitor, and wherein the second passive RLC filter circuit is configured to receive the second driver signal from the second capacitor. For differential signals, the difference between the transmission frequency and the frequency associated with the peak value in the transfer function of the common-mode rejection circuit, the first capacitor, and the second capacitor is less than 20 percent.

18. The system according to claim 17, The first passive RLC filter circuit includes a first inductor coil. The second passive RLC filter circuit includes a second inductor coil. The first inductor coil and the second inductor coil are interleaved, and The first inductor coil overlaps with the second inductor coil.

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