Performing synapse -in -silicon operations related to pre-spike signals, and related methods and systems

Abstract

The present disclosure describes performing synapse -before-spike signal related in-memory computing operations, and related methods and systems. Spike events in a spiking neural network can be processed via a memory system. The memory system can store data corresponding to a set of destination neurons. The memory system can pass, at each time interval of the SNN, data corresponding to a set of synapse -before-spike events from a respective source neuron. The data corresponding to the set of synapse -before-spike events can then be stored in the memory system.

Description

[0001] Priority Claim

[0002] This application is a national phase entry application for International Patent Application PCT / US2020 / 048822, filed on August 31, 2020, with the People's Republic of China as the target country, and published in English on March 11, 2021, as International Patent Publication WO 2021 / 046000 A1. It claims the benefit of U.S. Provisional Patent Application No. 62 / 896,267, filed on September 5, 2019, for “Performing Processing-In-Memory Operations Related to Pre-Synaptic Spike Signals, and Related Methods and Systems”, pursuant to Article 8 of the Patent Cooperation Treaty. It also claims the benefit of “Performing Processing-In-Memory Operations Related to Pre-Synaptic Spike Signals, and Related Methods and Systems”. The benefit of the application date of U.S. Patent Application No. 17 / 007,588, filed on August 31, 2020, entitled “Systems”. Technical Field

[0003] Embodiments of this disclosure relate to in-memory computing, and more specifically, to performing in-memory computing integrated (PIM) operations related to spike events in a spike neural network (SNN). More specifically, some embodiments relate to methods for performing PIM operations within a memory device with in-memory computing capabilities, as well as related memory devices, memory systems, and electronic systems. Background Technology

[0004] Memory devices are typically provided as internal semiconductor-based integrated circuits in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, which allows access to stored information after a power cycle, may include flash memory, including NAND or NOR flash memory, among other types of memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), content-addressable memory (CAM), and thyristor random access memory (TRAM), as well as other types of memory.

[0005] Electronic systems typically include multiple processing resources (e.g., one or more processors) capable of retrieving and executing instructions and storing the results of executed instructions in appropriate locations. A processor may include, for example, multiple functional units that can execute instructions by performing operations on data (e.g., one or more operands), such as arithmetic logic unit (ALU) circuitry, floating-point unit (FPU) circuitry, and combinational logic blocks. As used herein, operations may include, for example, Boolean operations such as AND, OR, NOT, NOT, NAND, NOR, and XOR, and / or other operations (e.g., inversion, shift, arithmetic, statistical, and many other possible operations). For example, a functional unit circuitry can be used to perform arithmetic operations such as addition, subtraction, multiplication, and division on operands via multiple operations.

[0006] Providing instructions to a functional unit circuit system for execution may involve multiple components in an electronic system. Instructions may be executed, for example, by processing resources (e.g., a controller and / or a host processor). Data (e.g., data to which instructions can be executed) may be stored in a memory array accessible by the functional unit circuit system. Before the functional unit circuit system begins executing instructions on the data, instructions and / or data may be retrieved from the memory array and ordered and / or buffered.

[0007] In many cases, processing resources (e.g., processors and associated functional unit circuitry) can be located outside the memory array and access data via a bus between the processing resources and the memory array to execute instruction sets. Processing performance can be improved in processor-in-memory (PIM) devices, where the processor can be implemented internally and / or close to the memory (e.g., directly on the same chip as the memory array). PIM devices can save time and / or power by reducing and eliminating external communication. Summary of the Invention

[0008] One or more embodiments of this disclosure include a system. For example, the system may include a memory array comprising multiple memory cells at intersections of multiple word lines and multiple bit lines, wherein data written to the multiple memory cells corresponds to synaptic weight values. The system may include a driver configured to drive the multiple word lines. The system may also include a circuit system including a sense amplifier coupled to the multiple bit lines. The circuit system is configured to receive output signals from the multiple bit lines. The circuit system is further configured to generate a second signal having voltage, current, or timing characteristics or a combination thereof in response to a first signal driven on the word lines prior to the generation of a spike signal of a neuron, the second signal increasing the conductance of the first memory cell according to a spike timing-dependent plasticity (STDP) characteristic of the first memory cell among the multiple memory cells. The circuit system is further configured to generate a third signal having different voltage, current, or timing characteristics or a combination thereof in response to the first signal driven on the word lines after the generation of the spike signal of the neuron, the third signal decreasing the conductance of the first memory cell according to the STDP characteristic.

[0009] According to another embodiment, a method includes driving a first signal on a word line. The method further includes: in response to the first signal driven on the word line prior to generating a spike signal for a neuron, generating a second signal having voltage, current, or timing characteristics, or a combination thereof, the second signal increasing the conductance of a memory cell in a long-term enhancement (LTP) window of spike timing-dependent plasticity (STDP) characteristics; and transmitting the second signal to a bit line, wherein the memory cell is coupled to the word line and the bit line. The method further includes: in response to the first signal driven on the word line after generating the spike signal for the neuron, generating a third signal having different voltage, current, or timing characteristics, or a combination thereof, the third signal reducing the conductance of the memory cell in a long-term attenuation (LTD) window according to the STDP characteristics; and transmitting the third signal to the bit line.

[0010] In another embodiment, an electronic system includes at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The memory device includes a memory array comprising a plurality of memory cells at intersections of a plurality of word lines and a plurality of bit lines, wherein data written to the plurality of memory cells corresponds to synaptic weight values; and a circuit system including a sense amplifier coupled to the plurality of bit lines. The circuit system is configured to generate a second signal having voltage, current, or timing characteristics or a combination thereof, in response to a first signal driven on the word lines prior to the generation of a spike signal of a neuron, the second signal increasing the conductance of the memory cells among the plurality of memory cells; and to generate a third signal having different voltage, current, or timing characteristics or a combination thereof, in response to the first signal driven on the word lines after the generation of the spike signal of the neuron, the third signal decreasing the conductance of the memory cells.

[0011] According to other embodiments, an electronic system includes at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The at least one memory device includes: a memory cell array including a plurality of resistive elements configured to store synaptic weights; a driver configured to drive spike events on a plurality of word lines coupled to the plurality of resistive elements at each time quantum of a series of time quantumes in the SNN; and an integrator circuit configured to integrate the output voltage of the bit lines coupled to the resistive elements.

[0012] According to another embodiment, a system includes a memory array comprising a plurality of memory cells, wherein the conductance values ​​of the plurality of memory cells correspond to synaptic weight values. The system further includes a circuitry coupled to the memory array. The circuitry is configured to receive an output signal from the memory array and, in response to a first signal received at the memory array, generate a second signal to increase or decrease the conductance of the memory cells among the plurality of memory cells according to a spike timing-dependent plasticity (STDP) rule.

[0013] According to other embodiments, an electronic system includes at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The at least one memory device includes: a memory array comprising a plurality of memory elements; and a circuit system including one or more sense amplifiers coupled to the memory array. The circuit system is configured to generate a second signal to reduce the resistance of one or more of the plurality of memory elements in response to receiving an output signal from the memory array indicating a first signal arriving at the memory array before a spike signal generating a neuron. The circuit system is further configured to generate a third signal to increase the resistance of the one or more of the plurality of memory elements in response to receiving an output signal from the memory array indicating a first signal arriving at the memory array after a spike signal generating a neuron. Attached Figure Description

[0014] Figure 1 This is a block diagram of a system including a memory device according to several embodiments of the present disclosure.

[0015] Figure 2 A spike neural network according to various embodiments of the present disclosure is described.

[0016] Figure 3 This invention describes a memory system for processing spike events according to various embodiments of the present disclosure.

[0017] Figure 4 This describes filters configured to filter spike events according to various embodiments of the present disclosure.

[0018] Figure 5 A memory system for processing spike events according to various embodiments of the present disclosure is described, including a pointer table.

[0019] Figure 6 This invention describes a memory system for processing spike events according to various embodiments of the present disclosure.

[0020] Figure 7 A graph illustrating the spike temporal dependent plasticity (STDP) rule in a spike neural network (SNN) according to various embodiments of the present disclosure.

[0021] Figure 8 This is a flowchart of an example method for in-memory computing peak events according to various embodiments of the present disclosure.

[0022] Figure 9 This is a flowchart of another example method for in-memory computing peak events according to various embodiments of this disclosure.

[0023] Figure 10 This invention describes a memory system for processing spike events according to various embodiments of the present disclosure.

[0024] Figure 11 This describes the threshold delay effect according to various embodiments of the present disclosure.

[0025] Figure 12 This is a flowchart of another example method for in-memory computing peak events according to various embodiments of this disclosure.

[0026] Figure 13 This is a simplified block diagram of an instance memory system implemented according to one or more embodiments described herein.

[0027] Figure 14 It is a simplified block diagram of an example electronic system implemented according to one or more embodiments described herein. Detailed Implementation

[0028] Processing spike events in spike neural networks (SNNs) is used in many applications, such as machine learning, image processing, artificial intelligence, system modeling (e.g., electrical systems, mechanical systems, brain-computer interfaces, large-scale brain simulations, robotics, control systems, etc.), and many others. Operations that process spike events (e.g., presynaptic events, synaptic events) can be relatively simple (e.g., filtering, matching, and accumulation). However, conventional computer-based computation can involve processor- and memory-intensive operations, including transferring large amounts of data between computing cores and memory arrays.

[0029] Various embodiments of this disclosure relate to in-memory computing (PIM) operations, and more specifically to performing PIM operations to process spike events in a short-range neural network (SNN). In at least one embodiment, the memory system includes a memory block. The memory is configured to store data corresponding to a set of destination neurons. The memory may include a spike signal filter configured to allow data corresponding to a set of presynaptic spike events from a respective source neuron to pass through at each time interval (also referred to herein as a “temporal quantum”) of a series of time intervals in the SNN. The data corresponding to the set of presynaptic spike events can then be stored in the memory block. The memory block is also configured to store a pointer table. The pointer table is configured to store pointers to each set of the presynaptic spike events stored in the memory block, and to increment a label corresponding to each pointer at each time interval.

[0030] As used herein, a device with in-memory computing (PIM) capability refers to a memory device capable of performing arithmetic and logical operations on data stored in a memory cell array using the processing resources within the memory device (e.g., without transferring data to external processing resources such as a host processor). As an example, a PIM-capable device may include a memory array coupled to a sensing circuitry system including sensing components operable as a 1-bit processing element (e.g., performing parallel processing on a per-column basis) or a multi-bit processing element (e.g., performing parallel processing on a per-slice basis, where each slice (e.g., a slice of a row) comprises multiple columns). In addition to logical operations performed "in memory" (which may be referred to as "bit vector operations"), a PIM-capable device may also perform memory operations. As an example, a PIM-capable device may include a dynamic random access memory (DRAM) array configured for memory operations, including memory access operations such as read (e.g., load) and write (e.g., store), as well as other operations that do not involve manipulating data, and additional operations that do involve manipulating data. For example, a device with PIM capability can operate a DRAM array as a "normal" DRAM array and / or a PIM DRAM array, depending on the type of program being executed (e.g., by a host). This can include both memory operations and bit vector operations. For example, bit vector operations can include logical operations, such as Boolean operations (e.g., "AND", "OR", "XOR", etc.), and transfer operations, such as shifting data values ​​in an array and inverting data values.

[0031] As used herein, a PIM operation can refer to various operations associated with performing processing in memory using a device with PIM capabilities. An operation hierarchy can be used to define PIM operations. For example, the first (e.g., lowest) level in the operation hierarchy may contain bit vector operations (e.g., basic logical operations, which may be referred to as “primitive” operations). The next (e.g., middle) level in the hierarchy may contain compound operations, which include multiple bit vector operations. For example, compound operations may include mathematical operations such as addition, multiplication, etc., which may include multiple logical AND, OR, XOR, shift, etc. The third (e.g., highest) level in the hierarchy may contain control flow operations (e.g., loops, branches, filtering, matching, etc.) associated with executing a program that involves performing processing using a device with PIM capabilities.

[0032] As described in more detail herein, PIM operations can be performed by various components within a system that includes devices with PIM capabilities. For example, a first PIM control component (e.g., control logic, which may be referred to as a "scalar unit") located on a host may perform control flow operations and provide composite operations to a second PIM control component (e.g., a sequencer), which may also be located on a host or a device with PIM capabilities. In several embodiments, the second control component may provide low-level bit vector operations to a PIM control component located on a PIM-capable device (e.g., a bit vector timing circuit system), which may perform bit vector operations in memory and return the results to the host. As further described herein, an interface for transmitting PIM operations between a PIM-capable device and a host may include a channel that may include a bus separate from a typical memory interface (e.g., a DDR interface) used for transmitting commands, addresses, and / or data. Furthermore, in many embodiments, providing a PIM control component on the host can provide benefits, such as allowing PIM programs to use virtual addressing (e.g., by resolving virtual addresses on the host, since devices with PIM capabilities can operate only on physical addresses).

[0033] Figure 1 This is a block diagram of a system 100 including a memory device 120 according to several embodiments of the present disclosure. The memory device 120 (which may also be referred to herein as a "PIM-capable device" or "PIM-capable memory device") may include any suitable memory device. For example, the memory device 120 may include volatile memory (e.g., RAM, DRAM, etc.) and / or non-volatile memory (e.g., flash memory, cross-point memory devices, such as 3D cross-point memory devices, etc.). The memory device 120 may include a memory array 130 (i.e., containing memory cells) coupled to a sensing circuitry system, as described in more detail below. According to some embodiments, the memory device 120 may include multiple memory arrays 130 organized in the form of a storage bank, chipset, platform, plain text, block, segment, or some other form.

[0034] System 100 further includes a host 111 coupled to memory device 120. Host 111 may include a host system, such as a personal laptop computer, desktop computer, digital camera, smartphone, or memory card reader, and various other types of host systems. Host 111 may include a system motherboard and / or backplane and may include multiple processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry). System 100 may include a separate integrated circuit, or both host 111 and memory device 120 may be part of the same integrated circuit (e.g., on the same chip). System 100 may include, for example, a server system and / or a high-performance computing (HPC) system and / or a portion thereof.

[0035] The host 111 may include various components, including PIM control components (e.g., control logic 131, sequencer 132), channel controller 143, and memory management unit (MMU) controller 134. Control logic 131 may be configured to execute control flow commands associated with the executing PIM program and to provide composite commands to sequencer 132. Control logic 131 may be or may include a RISC-type controller configured to generate and issue a set of scalable composite PIM commands that include commands different from the DDR commands sent to sequencer 132. In some embodiments, control logic 131 may be configured to issue composite operation commands to cause bit vector operations to be performed on memory device 120. In some embodiments, composite operation commands may be transmitted from control logic 131 to memory device 120 (e.g., via sequencer 132 and channel 157).

[0036] In some embodiments, control logic 131 may decode microcode instructions into function calls, which may be microcode function calls associated with performing bit vector operations implemented by sequencer 132. The microcode function call may be an operation received and / or executed by sequencer 132 such that memory device 120 uses, for example, a sensing circuitry system 150 to perform a specific bit vector operation.

[0037] As in Figure 1As shown, control logic 131 and MMU controller 134 are located on host 111. This allows control logic 131 and / or MMU controller 134 to access virtual addresses stored on host 111 and perform virtual-to-physical address resolution (e.g., translating the virtual address of the address space associated with an application running on host 111 to the actual physical address of memory device 120) before transmitting instructions to memory device 120. The translation can be performed at the host by looking up an address translation table (e.g., a page table) stored in memory device 120 or by performing the same operation on memory device 120. In some embodiments, control logic 131 and / or sequencer 132 are located in memory device 120, for example in controller 140 or in line decoder 146. In other embodiments, control logic 131, sequencer 132, or MMU controller 134 may be distributed such that part of its functionality is located on host 111 and another part is located on memory device 120.

[0038] As used herein, a “bit vector” can refer to physically contiguous bits, whether physically contiguous in rows (e.g., horizontally oriented) or columns (e.g., vertically oriented). A device with PIM capability can be configured to perform bit vector operations, such as logical operations and / or transfer operations, on multiple contiguous portions (e.g., “blocks”) of a virtual address space. For example, a block of virtual address space may have a bit length of 256 bits. A block may be sequentially contiguous with other blocks in the virtual address space, or it may be discontiguous, however, it will be contiguous within the scope of a memory page. In the disclosed embodiments, a device with PIM capability can be configured to perform the operations in the virtual address space after translating the virtual address of a virtual page to the physical address of a physical page.

[0039] It can reside on host 111 (such as in Figure 1 The MMU controller 134 (shown in the diagram) is responsible for performing the translation of virtual memory addresses (e.g., addresses associated with host 111) to physical addresses (e.g., addresses associated with memory device 120). The MMU controller 134 can also perform memory protection operations, cache control, and / or bus arbitration operations.

[0040] The sequential circuit system 133 can provide timing to coordinate the execution of logic operations and can be responsible for providing access to arrays (e.g., Figure 1Conflict-free access to the memory array 130 in the memory. In various embodiments, the controller 140 and / or timing management circuitry 135 may generate status information, which may be transmitted to or from the host 111, for example, via channel 157. Channel 157 may be independent of (e.g., separate from) a Double Data Rate (DDR) memory interface (e.g., control bus 154), which can be used to transmit (e.g., transfer) DDR commands between the host 111 and the memory device 120. That is, in some embodiments, channel 157 can be used to transmit commands between the host 111 and the memory device 120, a memory access device, or another memory interface. Non-limiting examples of memory interfaces include, but are not limited to, Double Data Rate (DDR) memory interfaces, Fast Peripheral Component Interconnect (PCIe) memory interfaces, Coherent Accelerator Processor Interface (CAPI), Compute Fast Link (CXL), Cache Coherent Interconnect for Accelerators (CCIX), and combinations and sub-combinations of the foregoing.

[0041] As a non-limiting example, the DDR memory interface (e.g., control bus 154) can be used to transmit (e.g., transfer) DDR commands between host 111 and memory device 120. That is, in some embodiments, channel 157 can be used to transmit commands causing the execution of bit vector operations from host 111 to memory device 120, while control bus 154 can be used to transmit DRAM commands (or commands of another type of memory interface) from host 111 to memory device 120. In some embodiments, the DRAM commands (or other types of commands) transmitted via control bus 154 can be commands for controlling the operation of DRAM (or commands for controlling other types of memory, memory access devices, or memory interfaces), such as DDR1 SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4, DDR5, and other versions of the DDR type protocol, but are not limited thereto. In other embodiments, memory device 120 can send signals about operational readiness to the host via channel 157. In some embodiments, channel 157 is combined with control bus 154 and / or data bus 156. In addition, in some embodiments, host 111 may include multiple memory devices 120 having multiple channels and / or control buses.

[0042] In some embodiments, the sorter 132 may include a Very Large Instruction Word (VLIW) type controller configured to operate on logical operation commands, and control logic 131 may be configured to issue logical operation commands to the sorter 132 in response to signals from processing resources (not shown) from host 111. For example, the sorter 132 may be configured to sort multiple logical operations such that compound operation commands can be issued by the sorter 132. In some embodiments, control logic 131 may be configured to generate executable instructions, such as VLIW type instructions or SMID type instructions. In embodiments including a VLIW type instruction controller, control logic 131 may be configured to generate VLIWs as bit vector operation commands. VLIWs may include microcode instructions. The sorter 132 may be or may include a VLIW type controller configured to decode VLIWs into multiple individual microcode instructions. For example, the sorter 132 may decode VLIWs into instructions causing the execution of compound operations (e.g., addition, multiplication, dot product, but not limited thereto). In some embodiments, compound operation commands can provide an entry point into a VLIW instruction sequence to cause such compound operations to be performed. In embodiments that include an SMID type instruction controller, control logic 131 may be configured to generate data units, such as, but not limited to, data vectors, and sequencer 132 may cause a single instruction to be executed in parallel on multiple data points identified in the data units.

[0043] The sequencer 132 may be coupled to the memory device 120 and may pass commands for coordinating bit vector operations to the memory device 120 via channel 157. Microcode instructions may be executed sequentially and / or in parallel by the sequencer 132 itself and / or by other components in the memory device 120 (e.g., bit vector operation timing circuitry 139, timing circuitry 133, timing management circuitry 135, and / or sensing circuitry 150). For example, the memory array 130 may include a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array. The memory array 130 may include memory cells arranged in rows coupled by access lines, which may be referred to herein as word lines or select lines, and columns coupled by sensing lines, which may be referred to herein as data lines, digital lines, or bit lines. Although Figure 1 The example shown is a single memory array, but the embodiments are not limited thereto. For example, memory device 120 may include multiple memory arrays 130 (e.g., multiple memory banks of DRAM cells, NAND flash memory cells, etc.).

[0044] Memory device 120 includes an address circuitry 142 to latch address signals for data provided on bus 156 (e.g., a data / address bus) via I / O circuitry 144. Status and / or exception information can be provided from controller 140 on memory device 120 to channel controller 143 via an interface including channel 157 (e.g., a high-speed interface (HSI)). Address signals are received via address circuitry 142 and decoded by row decoder 146 and column decoder 152 to access memory array 130. Data can be read from memory array 130 by sensing the state of memory cells on digital lines using sensing circuitry 150. Depending on the memory cell technology, the state of memory cells can be sensed as, for example, voltage and / or current changes, magnetic state changes, resistivity, and quantum states. Sensing circuitry 150 can read and latch page (e.g., row) data from memory array 130. I / O circuitry 144 can be used for bidirectional data communication with host 111 via data bus 156. Write circuitry 148 can be used to write data to memory array 130. In some embodiments, write circuitry 148 is combined with sensing circuitry 150. In other embodiments, sensing circuitry 150 may be part of column decoder 152 and / or row decoder 146. In some embodiments, control bus 154 may be used as both a control and address bus for DRAM control and addressing (e.g., according to a DDR protocol in which control bus 154 operates as a unidirectional data bus). Although in Figure 1 While shown as a separate bus, in some embodiments, control bus 154 and data bus 156 may not be separate buses. Controller 140 (e.g., a memory controller) can decode signals provided from host 111 by control bus 154. These signals may include chip enable signals, write enable signals, and address latch signals for controlling DRAM operations (including data read, data write, and data erase operations) performed on memory array 130. In various embodiments, controller 140 may be responsible for executing instructions from host 111 and sequencing access to memory array 130. Controller 140 may include a state machine, a sequencer, or some other type of controller and includes hardware and / or firmware (e.g., microcode instructions) in the form of application-specific integrated circuits (ASICs). In several embodiments, controller 140 may include bit vector operation timing circuitry system 139. Controller 140 may control, for example, sensing circuitry system 150. For example, controller 140 may control the generation and application of clock signals to calculate components associated with performing bit vector operations.

[0045] As in Figure 1As shown, the bit vector operation timing circuit system 139 may include a timing circuit system 133 and a timing management circuit system 135. The timing circuit system 133 may include a FIFO buffer to provide timing coordination for the sensing circuit system 150 associated with the memory array 130 of the memory cells. In some embodiments, the timing circuit system 133 may include a state machine, such as an atomic state machine.

[0046] Timing management circuitry 135 can be configured to coordinate the timing of logical operations (e.g., sequences of logical operations) associated with bit vector operations, which are performed using a row address strobe (RAS) / column address strobe (CAS) component 136 associated with memory array 130. RAS component 136 can be configured to send and / or receive signals (e.g., RAS / CAS signals) to and / or from memory array 130 to identify and / or select row and / or column addresses of memory array 130. In some embodiments, memory device 120 can be configured to perform DRAM operations, such as memory array access requests, which can be issued by host 111 via bus 154. In some embodiments, timing management circuitry 135 can be configured to execute instructions to control the timing of bit vector operations.

[0047] In one or more embodiments, portions of controller 140 (e.g., bit vector operation timing circuitry 139, timing circuitry 133, and / or timing management circuitry 135) may include a Reduced Instruction Set Computer (RISC) type controller that operates on, for example, 32- or 64-bit long instructions. In various embodiments, timing management circuitry 135 may be responsible for executing instructions received from timing circuitry 133 to induce the execution of bit vector operations relating to data values ​​associated with sensing circuitry 150.

[0048] As further described below, in various embodiments, the sensing circuitry 150 may include a plurality of sensing components, each of which may include a sensing amplifier and a computing component. The computing component may serve as an accumulator, and the sensing circuitry 150 may be used to perform bit vector operations (e.g., on data associated with complementary digital lines). In various embodiments, the sensing circuitry 150 may be used to perform bit vector operations and / or store the results of the operations back into the memory array 130 using data stored in the memory array 130 as input without transferring data via digital line address access (e.g., without triggering column decoding signals). For example, various operations (e.g., bit vector operations) may be performed using and within the sensing circuitry 150, rather than through (or associated with) processing resources outside the sensing circuitry 150 (e.g., through processing resources associated with host 111 and / or other processing circuitry systems, such as an ALU circuitry system located on memory device 120 (e.g., on control circuitry 140 or elsewhere). In several embodiments, the sensing circuitry 150 (e.g., a plurality of sensing components) can be used to perform bit vector operations in a SIMD (Single Instruction Multiple Data) manner, wherein the sensing components act as 1-bit processing elements on a per-column basis. In embodiments where the sensing circuitry 150 performs bit vector operations, the sensing circuitry 150 may be used as and / or referred to as a “memory-embedded processor.” As described more fully below, in some embodiments, the sensing circuitry 150 may include a sorter (e.g., similar to sorter 132). In other embodiments, adjacent sensing components may exchange data bits with each other, thereby generating computations based on multiple data sources. In other embodiments, sensing components may generate different computations depending on their position within the sensing circuitry 150, thus providing computations in a VLIW or SIMD manner. In embodiments where the sensing circuitry 150 performs bit vector operations, the sensing circuitry 150 may be used as and / or referred to as a “memory-embedded processor.” As described more fully below, in some embodiments, the sensing circuitry 150 may include a sorter (e.g., similar to sorter 132).

[0049] In various methods, for example, data associated with operands may be read from memory via a sensing circuitry and provided to an external memory array ALU circuitry via I / O lines (e.g., via local I / O lines and / or global I / O lines). The external memory array ALU circuitry may include multiple registers and will perform bit vector operations using operands, and the results may be transferred back to the array via I / O lines. In other embodiments, the sensing circuitry 150 is configured to perform bit vector operations on data stored in the memory array 130 and store the results back to the memory array 130 without enabling I / O lines (e.g., local I / O lines) coupled to the sensing circuitry 150.

[0050] In several embodiments, it may not be necessary for circuitry outside the memory array 130 and sensing circuitry 150 to perform operations, because sensing circuitry 150 can perform appropriate bit vector operations without using external processing resources. Therefore, sensing circuitry 150 can be used to at least partially supplement and / or replace such external processing resources (or at least the bandwidth consumption of such external processing resources). However, in several embodiments, in addition to logical operations performed by external processing resources (e.g., host 111), sensing circuitry 150 can also be used to perform logical operations (e.g., execute instructions). For example, host 111 and / or sensing circuitry 150 may be limited to performing only certain logical operations and / or a specific number of logical operations.

[0051] Enabling an I / O line may include enabling (e.g., turning on) a transistor having a gate coupled to a decoded signal (e.g., a column decoded signal) and a source / drain coupled to the I / O line. However, embodiments are not limited to using a sensing circuitry system (e.g., sensing circuitry system 150) to perform logic operations without enabling the column decoded lines of the array. Regardless of whether the local I / O line is used in association with performing logic operations via sensing circuitry system 150, the local I / O line may be enabled to transfer the result to the appropriate location rather than back to the memory array 130 (e.g., to an external register).

[0052] Various embodiments of this disclosure relate to processing spike events in SNNs, and more specifically to performing PIM spike event operations. According to the various embodiments described herein, in an SNN, presynaptic spike signals from source neurons are routed to destination neurons by performing PIM operations. For example, an SNN is simulated at least in part by performing PIM operations on one or more resistive memory arrays. Furthermore, and more specifically, according to the various embodiments described herein, in an SNN, PIM operations are performed to, among other things, filter presynaptic events according to their appropriate destination, determine when a presynaptic spike event is triggered, determine when a presynaptic spike event becomes a spike event, maintain neuronal membrane potential, generate spike events, adjust synaptic weights, etc.

[0053] Figure 2 An embodiment of an SNN 200 comprising multiple layers of neurons is depicted. The SNN 200 includes first-layer neurons (e.g., source neurons 210, source neurons 210-1, 210-2, and 210-3) connected via synapses 230 (also referred to as synaptic connections) to second-layer neurons (e.g., destination neurons 220, including destination neurons 220-1, 220-2, and 220-3). For simplicity and clarity, only two layers of neurons are depicted in the SNN 200. However, the SNN 200 may contain any number of layers of neurons. Furthermore, each layer of neurons may contain any number of neurons. For example, the source neurons in any layer of the SNN 200 may each contain thousands of neurons, wherein each neuron in the first layer (e.g., source neuron 210) has a synapse 230 (or synaptic connection) with each neuron in the next layer (e.g., destination neuron 220). In this example, synapse 230-1 connects neuron 210-1 to neuron 220-1, synapse 230-2 connects neuron 210-2 to neuron 220-1, and synapse 230-3 connects neuron 210-3 to neuron 220-1. Similarly, neuron 210-2 has a synaptic connection with each destination neuron 220, and neuron 210-3 has a synaptic connection with each of the destination neurons 220.

[0054] Each of the source neurons 210 may receive input (e.g., spike event 205) generated by multiple neurons in a previous layer or layer (not shown) of the SNN 200. Thus, source neurons 210 can be considered destination neurons, and neurons in previous layers can be considered source neurons. The term "layer" is used herein for ease of representation. Layers have no fixed boundaries, and a layer can be any set of selected neurons selected according to certain criteria (e.g., neuronal function, locality, proximity, etc.), including random selection. Therefore, neurons can form connections within a layer. Thus, any neuron in any set of source neurons in any layer can also be a destination neuron in any set of destination neurons in any other layer. Similarly, any neuron in any set of destination neurons in any layer can also be a source neuron in any set of source neurons in any other layer. Spike event 205 may represent an input current to source neuron 210. This current can accumulate on the neuronal membrane of the neuron (e.g., neuron 210) to charge the membrane potential. When the membrane potential reaches the threshold, the neuron generates and triggers an output spike to be transmitted to the next level of neurons (e.g., destination neuron 220).

[0055] Spike transmission can be achieved from one level neuron (e.g., source neuron 210) to the next level neuron (e.g., destination neuron 220) via synapse 230 (or synaptic connection). Synapse 230 can receive the output signal (e.g., spike) from source neuron 210 and transmit the signal to destination neuron 220. For example, when neuron 210-1 receives one or more spike events 205 and reaches a threshold potential value, neuron 210-1 produces a “spike” and transmits the output spike via synapse 230-1 to (1) destination neuron 220-1, (2) destination neuron 220-2 via synapse, and (3) destination neuron 220-3 via synapse.

[0056] Furthermore, when the synapse 230 receives the output signal from the source neuron 210, it can scale the signal according to the adjustable synaptic weight. In this way, the synapse provides the combined scaled signal as an input signal to the destination neuron. For example, when neuron 210-1 receives one or more spike events 205 and reaches a threshold potential value, neuron 210-1 produces a "spike" and emits the output spike via synapse 230-1 to (1) destination neuron 220-1, (2) destination neuron 220-2 via synapse, and (3) destination neuron 220-3 via synapse. For example, the synaptic weight W_1 is scaled along the spike signal from neuron 210-1 to neuron 220-1 along synapse 230-1 (and the spike signals from neuron 210-1 to neurons 220-2 and 220-3 may be scaled with the same or other weights), the synaptic weight W_2 is scaled along the spike signal from neuron 210-2 to neuron 220-1 along synapse 230-2 (and the spike signals from neuron 210-2 to neurons 220-2 and 220-3 may be scaled with the same or other weights), and the synaptic weight W_3 is scaled along the spike signal from neuron 210-3 to neuron 220-1 along synapse 230-3 (and the spike signals from neuron 210-3 to neurons 220-2 and 220-3 may be scaled with the same or other weights). Therefore, the destination neuron 220 can generate an output spike (e.g., spike event 207) based on the corresponding combined input signals. Then another synaptic network in SNN 200 is used to fire the output spike (e.g., spike event 207) to neurons in another level or layer (not shown).

[0057] The bandwidth required to process spike events in a SNN can be quite large. The following description provides an example of the bandwidth required to process an SNN. Generally, in an SNN, 3-5% of neurons generate spikes every 1 millisecond (ms). In various embodiments, each spike event is represented by a small data structure: a source neuron ID and a spike timestamp (the spike timestamp is optional and can be inferred from the SNN time interval, as further shown). On average, each SNN neuron connects to approximately 1000 other neurons. Spikes generated by neurons are delivered to all connections after some delay. Upon delivery, these spike events become synaptic events. For example, when a source neuron ID matches a destination synapse ID, the spike event becomes a synaptic event, and the spike timestamp generated by the SNN system embodiment at the spike plus connection plus connection delay corresponds to the current SNN system timestamp.

[0058] Furthermore, the latency value for each connection varies and typically averages between 1 and 100 ms or 50 ms (floating-point or integer). The spike timestamp is unique for each spike event. Therefore, it may be desirable to deliver spikes promptly at specific synapses. For a small SNN with 1 million (M) neurons (0.001% of the human brain): 5% spikes × 1M neurons × 1000 connections per neuron × 64 bytes (b) per synaptic event = 400 MB / ms or 400 GB / s. That is, a computational system simulating an SNN requires the hardware and bandwidth to transmit at 400 MB / ms (or 400 GB / s). In some conventional computing systems, processing resources (e.g., processors and associated functional unit circuitry) may not be able to transmit data via the bus under such requirements. Therefore, a computing system is needed to handle SNN events requiring high data transfer bandwidth (e.g., presynaptic events, spike events, etc.). As will be described in more detail below, high bandwidth requirements can be adequately met through hierarchical routing and compact event storage on resistive memory arrays. For example, PIM operations implemented on resistive memory arrays can save time and / or power by reducing and eliminating external communication. As will be described in further detail herein, this can be achieved, at least in part, by using one or more resistive memory arrays (e.g., Figure 1 The memory array 130) performs PIM operations to simulate SNN (e.g., Figure 2 (SNN200).

[0059] Figure 3 This describes an embodiment of a system 300 for data partitioning and routing during peak events. System 300 includes multiple memory blocks, such as memory block 310, and a network 350. In various embodiments, memory block 310 includes a resistive memory array. Typically, a resistive memory array is a type of non-volatile random access computer memory comprising memory cells whose resistance (i.e., the amount of current flowing across the memory cells as a functional voltage applied across the memory cells) is variable. Such memory cells can be memory elements, PCM cells, 3D X-ray dots, diode-like cells, and even transistor-based cells with adjustable threshold voltages, and thus this adjustment provides the ability to modulate current across the memory cells (e.g., flash memory elements with floating gate transistors). In various embodiments, memory block 310 includes individual memory dies, memory data blocks, etc.

[0060] Memory block 310 contains a subgroup of neurons 330 in the SNN. Neuron 330 can be any subgroup of neurons in the SNN. It should be understood that memory block 310 contains both neurons and synapses between neurons (e.g., synapse 230). Thus, neuron 330 may also contain synapses associated with the neuron.

[0061] In this example, neuron 330 contains neurons in a specific layer or level of the SNN. In such an example, refer to... Figure 2 Neuron 330 contains destination neuron 220. Other subgroups of neurons in the SNN are stored in other memory blocks (not shown) that are also coupled to network 350. Thus, the neurons and synapses of the SNN (e.g., SNN 200) are divided into blocks, and these blocks are connected by network 350. In various embodiments, network 350 includes a ring or toroidal topology, which may be digital or analog. It should be understood that the partitioning of neurons may include hierarchical block organization. For example, a first large memory block is a collection of many smaller memory blocks.

[0062] At specific time intervals (e.g., every 1 ms), blocks of neurons generate spike events. For example, one or more neurons 330 (e.g., destination neuron 220) generate spike 316 (e.g., spike event 207), which is broadcast via network 350 to other neurons in other blocks (not shown). Simultaneously (e.g., within the same time interval or period), spikes 312 from other blocks generated simultaneously (e.g., within the same time interval or period) arrive at multiple blocks (e.g., each individual block in system 300). For example, spike 312 from other blocks (e.g., source neuron 210 stored in other blocks) is broadcast to neuron 330 in block 310. In some instances, the interval, period, or duration of time may be referred to as a time quantum, and intervals, time intervals, and series of time intervals may be referred to as series of time quantum.

[0063] In various embodiments, for a baseline of 1M neurons and 64b spike events, spike broadcasting on network 350 can be estimated as, for example: 5% neuron spikes × 1M neurons × 64b / synaptic event = 400KB / ms or 400MB / s. Additionally, in some embodiments, system 300 may require 40MB of storage to locally retain synaptic events (e.g., 400KB × 100ms maximum latency). Broadcasting spike events via network 350 can be implemented via shared memory (e.g., only 400KB per 1M neurons) or via a special bus or a combination of both.

[0064] In some embodiments, one or more blocks of memory in system 300 (e.g., each block) include filters. For example, block 310 includes filter 320. Filter 320 is configured to pass spikes with a destination in block 310. More specifically, for example, at each time quantum (e.g., every 1 ms), filter 320 filters spike 312 and allows filtered spike 314 with a destination in block 310 to pass through.

[0065] In various embodiments, filter 320 may filter spikes 312 at least in part based on neuron IDs. For example, spike 312 contains neuron IDs (e.g., the IDs of source neurons) and neurons 330 contain synapse IDs (i.e., the IDs of synapses that match the IDs of the source neurons to which these synapses are connected). Thus, filter 320 allows filtered spikes 314 to pass through, the filtered spikes having neuron IDs that match the synapse IDs of neurons 330. For 1M neurons and 32b neuron IDs, each local filter in each block (e.g., filter 320 in block 310) may perform partial address matching at each block at a rate of, for example, 200KB / ms or 200MB / s (i.e., 5% spikes × 1M neurons × 32b / neuron ID = 200KB / ms or 200MB / s).

[0066] In various embodiments, the matching or filtering function of the alternative filter 320 may include an address scheme with a predetermined algorithm for allocation. For example, a target neuron may be allocated such that the block ID matches a portion of the source neuron ID. This may not always be possible due to the unique topology. In some embodiments, a hybrid approach may be used, incorporating a combination of filters and address schemes. The same architecture (blocks organized on a bus, such as rings) can be used for other neural models: for example, deep neural networks (DNNs), artificial neural networks (ANNs), long short-term memory (LSTMs), where each block sequentially stores multiple sets of neural network layers, such that subsequent layers feed data to the next layer. Thus, the blocks operate in a daisy-chain manner. For example, each block receives data from a previous block and pushes data to the bus of the subsequent block. Additionally, it can be any data specific to the neural model used, rather than spikes. Recursion of the neural network is possible within the block because it will benefit from local communication with low latency.

[0067] Figure 4 An embodiment of filter 400 is depicted. In one embodiment, filter 400 is filter 320 (as in...). Figure 3 (As shown in the diagram). Filter 400 includes a resistive memory array 420 and is configured to retrieve neurons from other blocks (e.g., from neurons 210 stored in another block (see Figure 1)). Figure 2 )) Receive spike events (e.g., Figure 3 (Spirit 312 shown). For example, a spike event includes spike neuron identification 410, such as the identification of a source neuron in source neuron 210. In various embodiments, spike neuron identification 410 may include an N-bit number (e.g., an 8-bit number such as 00110011).

[0068] The resistive memory array 420 includes multiple word lines 422 and bit lines 424. At each intersection of the word lines and bit lines of the resistive memory array 420 is a resistive memory element (e.g., a memory element, a PCM element, an MTX, etc.). Each bit line in the resistive memory array 420 stores a bit for destination synapse identification. For example, as in... Figure 4 As described, the first bit line is associated with the storage destination synaptic identifier of the corresponding memory element (e.g., 01111111), the second bit line is associated with the storage destination synaptic identifier of the corresponding memory element (e.g., 111101111), and so on. (See reference...) Figure 3 The destination synapse recognition stored in the resistive memory array 420 may include the synapse recognition of neuron 330. Each synapse of a specific destination neuron may be stored on the same bit line (assuming a bit line ratio of 1:1). Figure 4 (The ones described above are much longer), or the synapses of specific destination neurons can be stored on several bit lines.

[0069] Spike neuron ID 410 is emitted on word line 422. For example, Bit0 (“0”) of spike neuron ID 410 is emitted on the first word line. Bit1 (“0”) of spike neuron ID 410 is emitted on the second word line. Bit2 (“1”) of spike neuron ID 410 is emitted on the third word line, and so on. In various embodiments, the spike neuron IDs input to word line 422 are grouped into positive polarity forward propagation phases and negative polarity forward propagation phases. As an example, the input of spike neuron ID 410 to word line 422 can be completed in two phases. For example, the bits of the first phase are emitted on the corresponding word line. While emitting the first phase, the bits of the second phase are then emitted on the corresponding word line.

[0070] When the spike neuron ID 410 is emitted along word line 422, the output of the corresponding sensing amplifier 426 indicates whether a match exists between the spike neuron ID 410 and the destination neuron ID stored along bit line 424. In one embodiment, a partial match is determined after the bits of the first stage are emitted on the corresponding word line. Alternatively, a complete match is determined after the bits of the first and second stages are emitted on word line 422. If the memory element is capable of storing multiple bits, such as a flash memory element comprising QLC, MLC, flash memory cells, etc., then more than two stages may be required.

[0071] In various embodiments, mismatch is determined based on the detection of a ripple event. Alternatively, matching is determined based on the absence of a detected ripple event. Ripple detection in the first stage can be used to abort the second stage. Under certain conditions, a ripple event can produce a sudden conductance. The occurrence of a ripple event tends to significantly affect the current-voltage behavior of the memory cell. Thus, for example, a sensing circuit can be provided in response to the occurrence of a ripple event in the memory cell. The sensing circuit can generate one or more feedback signals that initiate a change in the potential applied to the memory cell.

[0072] Table 1 describes how matching or mismatch is determined based on detecting sudden return events.

[0073] Table 1:

[0074]

[0075] Input state refers to the value of the bit in spike neuron ID 410. For example, the input state of Bit 0 is "0", the input state of Bit 1 is "1", and so on. Similarly, memory state refers to the value of the bit in the memory element along the bit line. For example, referring to the fifth bit line (from left to right), the destination neuron ID is 00110011. Thus, the memory state of the first bit is "0", the memory state of the second bit is "0", the memory state of the third bit is "1", and so on.

[0076] Note that both bit line and word line selection directions can be changed at each stage. Additionally, unselected bit lines and word lines remain at suppressed levels. Input mode affects both word line and bit line signals.

[0077] The matching indication is output 428, which is a "1" generated by the sense amplifier corresponding to the bit line (e.g., the fifth bit line from the left). Output 428 is a bitmask for the matching destination synapse ID of a destination neuron. Since the same source neuron targets multiple destination neurons, multiple synapses can have the same ID.

[0078] Figure 5 An embodiment of system 500 is depicted. In one embodiment, system 500 is similar to system 300. For example, system 500 includes block 310, filter 320, neuron 330, and network 350. Furthermore, filter 320 is configured to receive input spike 312 from network 350, and outgoing spike 316 (from neuron 330) is emitted to network 350. In various embodiments, data transmission within block 310 is via routing element 530 (e.g., data bus).

[0079] Spike event 520 may include spike events filtered by filter 320. In one embodiment, spike event 520 is filtered spike event 314 (such as at least regarding...). Figure 3 (As described). For example, spike event 520 is a subgroup of spikes 312 that have a destination in block 310 and pass through filter 320. Spike event 520 is stored in block 310 (when passing through filter 320). In various embodiments, each spike event in spike event 520 includes a memory address, spike neuron ID, and spike time.

[0080] Block 310 contains a pointer table 510 configured to store tags of spike events 520 that have passed through filter 320 and are subsequently stored in block 310. For example, pointer table 510 contains tags of pointers to various groups of spike events that have passed through filter 320. In various embodiments, every time quantum (e.g., every 1 ms), a group of spike events 520 passes through filter 320 and is stored in a designated memory array in block 310. The group is assigned a tag "0" in pointer table 510, indicating that it is the most recent spike event (in the most recent time quantum) that has passed through filter 320. Tags for other previously filtered groups are then incremented by 1. There are as many groups as time quantum in the maximum possible delay between a pair of neurons (e.g., between a source neuron and a destination neuron). For example, given a maximum delay of 100 ms and a time quantum of 1 ms, there are 100 groups and associated tags. Tags incremented to 100 become "0", and previously stored spike events are overwritten by the spike event (or simply spike) group that has just arrived (in the most recent time quantum).

[0081] The maximum delay can be greater than or less than 100 ms. For example, spike timing-dependent plasticity (STDP) may require only a greater number of sets than the maximum delay measured according to time quantum (e.g., 100 sets given a maximum delay of 100 ms and a single time interval of 1 ms), which will be described in more detail below. Typically, STDP is a biological process that modulates the strength of connections (i.e., synapses) between neurons in the brain. This process adjusts the connection strength based on the relative timing of the output and input action potentials (or spikes) of a particular neuron.

[0082] In one embodiment, the peak time of the spike events is optional data to reduce the need for time quantization of the SNN sub-parts requiring precise timing. The peak time is between 0 and 1 (precise values ​​within the time quantum) because the time interval / quantum and associated label imply coarse-grained timing. Thus, spike events 520 (and pointer table 510) are a compact representation of all presynaptic spike events bucketed by time quantum.

[0083] Figure 6An embodiment of system 600 is depicted, which is configured to convert presynaptic spike events into synaptic events. In particular, system 600 is configured to convert presynaptic spike events within a memory block (e.g., block 310).

[0084] System 600 includes spike events 620 stored in a memory array of memory blocks. In various embodiments, spike events 620 (e.g., filtered spikes 314, spike events 520) are, for example, presynaptic spike events from source neurons. For example, refer to... Figure 2 Spike event 620 is a presynaptic spike event originating from source neuron 210.

[0085] Synapses 630 (e.g., synapse 230) can receive output signals (e.g., spikes) from source neurons and transmit signals to destination neurons. Synapses 630 are stored in a memory array within a memory block, such that the synapses of each neuron are stored in predetermined, possibly contiguous regions. Synapses may also be stored in a separate and different (and different from) memory array 640 memory array from the memory array storing spike events 620.

[0086] Each neuron (e.g., the destination neuron) has a presynaptic (afferent) connection. In various embodiments, the connection (e.g., the synapse) contains the following information: the presynaptic neuron ID, the precise delay value (optional), and the connection weight.

[0087] Additionally, each connection has a delay, encompassing a range of delay values: for example, between 1 ms and 100 ms. The delay value can be quantized in increments of time quanta (e.g., 1 ms, 2 ms, 3 ms, etc.), or it can be precise (e.g., 1.23523 ms). The synaptic connections of each neuron (specifically, the presynaptic neuron ID, i.e., the source neuron ID) are stored or allocated in buckets in increments of 1 time quanta based on the quantized portion of the delay: for example, a bucket containing all connections with a 1 ms delay, a bucket containing all connections with a 2 ms delay, and so on. Precise delay values ​​can be used to reduce quantization, but are optional. A precise delay value is the addition of the quantized delay: for example, 2 ms (implied from the bucket number) + 0.34234 ms = 2.34234 ms, where 2.34234 ms is the precise value. Certain SNN segments requiring high accuracy may require precise delay values. Depending on the implementation, this can be floating-point or integer, or some other custom format.

[0088] Synapses 630 are grouped from multiple neurons, with each synaptic connection of a neuron further grouped into quantum storage buckets. For example, the synaptic connection of neuron 632 (e.g., the destination neuron) is divided into multiple time quantum units by the value of its delay, e.g., a 1ms time interval corresponds to a 1-2ms delay, a 2ms time interval corresponds to a 2-3ms delay, and so on. Similarly, the synaptic connection of neuron 634 (e.g., the destination neuron) is divided into multiple time intervals, e.g., a 1ms time interval corresponds to a 1-2ms delay, a 2ms time interval corresponds to a 2-3ms delay, and so on. Furthermore, groups of synapses corresponding to the same time intervals from different neurons can be stored or allocated along the same word lines in a segment of the memory array. It should be understood that synaptic connections can be divided into any number of time intervals (e.g., from 1ms to 50ms in 1ms intervals). Additionally, synapse 630 contains two neurons 632 and 634; however, it should be understood that synapse 630 can contain any number of neurons (e.g., the destination neuron).

[0089] At each time quantum, the pointer to spike event 620 increments as previously described (e.g., the 0ms bucket increments to the 1ms bucket, the 1ms bucket increments to the 2ms bucket, and so on).

[0090] Furthermore, at each time quantum, the spike neuron ID in each bucket of spike event 620 is matched with the presynaptic neuron ID in the corresponding synaptic bucket (e.g., the 1ms spike bucket matches the 1ms synaptic bucket, the 2ms synaptic bucket matches the 2ms synaptic bucket, and so on). Specifically, at each time quantum, it can be determined whether the spike neuron ID in a bucket (e.g., a 2ms bucket) of spike event 620 matches the presynaptic neuron ID in the corresponding bucket of synapse 630. For example, a matching function is implemented to determine whether the spike neuron ID in the 2ms bucket of spike event 620 matches the presynaptic neuron ID in the 2ms buckets of neurons 632 and 634. In various embodiments, the matching function is similar to filtering implemented by filter 320 and / or filter 400, as previously described. For example, a word line driver can be used with the presynaptic neuron ID (see...) Figure 4 The signal of the bit is used to drive the word line, and the sense amplifier can determine the mismatch or match on the bit line.

[0091] A match indicates that a spike event is scheduled to arrive at that specific time quantum and for that specific synaptic connection. For example, a spike event in a 2ms time quantum matches a presynaptic ID in a 2ms time quantum. Similarly, a spike event in a 1ms time quantum matches a presynaptic ID in a 1ms time quantum, and so on. In various embodiments, each time quantum of each neuron generates numerous synaptic events.

[0092] In various embodiments, the matching function is parallel. For example, each synaptic bucket may reside in a different memory array, and the matching function may determine matches in parallel. In various embodiments, neurons may be distributed across many subarrays, and so on. In various embodiments, presynaptic neuron IDs from many neurons may be assigned along word lines, such that IDs from many neurons belonging to the same delay bucket are tested for matches in parallel. This can result in parallel search operations. Alternatively, matching can be performed serially. For example, the matching function may be executed one bucket at a time in a single array, provided that the buckets are generated before the real-time quantum expires. Many pipelined and multiplexed variants of this method are possible.

[0093] In response to the matches generated by the matching function, a bitmask of the synaptic event is generated at each time quantum. For example, the implementation of the matching function is similar to... Figure 4 Filter 400. The matched output includes a bitmask. See again. Figure 6 The output of the matching function is the matching synapse ID (e.g., bitmask) corresponding to the destination synapse 614.

[0094] In some embodiments, bitmasks can be merged for different neurons. However, this can be done at the cost of space efficiency. For example, the more common connections in the neuron group used for merging, the smaller the shared bitmask becomes. In one instance (i.e., no shared presynaptic neurons in the time quantum), the number of neurons in the group significantly increases the shared bitmask. In another instance (i.e., all presynaptic neurons in the time quantum are shared), the shared bitmask is the same for all presynaptic neurons. In some embodiments, the bitmask is specific for each neuron. In some embodiments, an average of 5% of synaptic connections per time quantum generate synaptic events. For example, for 1000 incoming connections, the above scenario produces 50 synaptic events per time quantum. Therefore, the bitmask size is sparse (~50 set bits in 1000). The bitmask can also be compressed.

[0095] In some embodiments, matching functions can be avoided. For example, if network connectivity is patterned and can be described algorithmically in a compact manner (e.g., from 3-bit numbers to 8-bit 1-hot at the cost of array space), then matching functions can be avoided. Hybrid matching methods (e.g., hierarchical routing filters and matching functions, event addresses and matching functions, etc.) can also be implemented.

[0096] In various embodiments, memory array 640 facilitates the integration of presynaptic events according to a bitmask. In various embodiments, memory array 640 is separate and distinct from memory arrays used to store spike events 620 and synapses 630.

[0097] The memory array 640 includes multiple word lines (e.g., WL0 and WL1) and multiple bit lines (e.g., BL0 and BL1). Memory elements (or resistive devices) are located at the intersections of each word line and bit line. In various embodiments, the memory elements are used to store weights of synaptic connections. For example, the resistance or conductance of the memory elements is adjusted to correspond to the weights of the synaptic connections. The weights of the synaptic connections may be stored in one or more memory elements on a single bit line (or may be stored on multiple bit lines).

[0098] Driver 642 can drive signals (e.g., voltage or current signals) corresponding to matched synapses (e.g., bit masks) on one or more word lines. A sense amplifier (e.g., sense amplifiers 644 and 646) at each corresponding bit line can generate an output voltage based on the current output from the corresponding memory element. An integrator circuit system 650 (which includes sense amplifiers) can integrate the outputs of the sense amplifiers. A spike 616 can be generated when the threshold potential of the neuron is satisfied. Thus, memory array 640 at least partially simulates spike events in an SNN. For example, (1) the signal driven by driver 642 simulates presynaptic events, (2) the word lines, bit lines, and memory elements simulate synapses and corresponding weights, and (3) the sense amplifiers simulate neurons.

[0099] The integration of synaptic events can encompass various implementations depending on the data representation, such as (1) a digital representation of synaptic weights or (2) an analog or mixed-signal representation of synaptic weights. In one embodiment, if the synaptic weights are digital (floating-point or integer), then the computation is a dot product of the synaptic conductance equations at the “set” locations of the bitmask. For example, the computation (or integration) is based on a constant synaptic current multiplied by the synaptic weights. In various embodiments, the integration is performed by a sensing amplifier (e.g., sensing amplifiers 644 and 646) that includes a built-in multiply-accumulate (MAC) unit (e.g., MAC unit 645). In various embodiments, the sensing amplifier provides a function of the neuronal membrane equations.

[0100] Additionally, synaptic weights can be digitally stored in a segment of memory array 640 in a bit-serial or bit-parallel manner. In this embodiment, if time quantization effects are not desired, the sensing amplifier can use optional data (e.g., timestamps of each presynaptic spike event and precise delay supply) to calculate the integral at the precise time spike. This optional data can generate a synaptic event jump to the next bucket (but nothing more).

[0101] In analog or mixed-signal implementations, synaptic weights are stored in different (or the same) memory arrays. Each weight may be represented by one or more resistive memory cells. Bit masks are presented sequentially. For example, driver 642 drives the bit masks sequentially. For each cycle of this sequence, the relevant bit lines are enabled.

[0102] The size of the sequence depends on how many neurons share a common connection. For example, if every neuron shares a connection, then a sequence is presented for all bit lines (or data lines) in one cycle. In various embodiments, if optional data (e.g., synaptic current for each word line, precise synaptic event time, etc.) is provided, then each word line is driven according to the synaptic current intensity and at a specified precise time value.

[0103] In some embodiments, signals driven on the word lines can be encoded in various ways: pulses, frequencies, amplitudes (current and voltage), shapes (e.g., sawtooth, up-slope-down-slope), spikes, etc. As described above, the sensing amplifier represents neuronal function. For example, the sensing amplifier performs current integration on the bit lines and solves for and maintains membrane potential dynamics, and detects when a spike (e.g., spike 616) occurs in the target neuron. For better parallelism, neurons and associated bit lines can be split into multiple groups and multiplexed with a shared word line driver.

[0104] It should be understood that storing synaptic weights can also be done within the same array where matching occurs. For example, presynaptic neuron IDs are mixed with weights. In such instances, the memory array performs a dual function: in the first set of cycles, it generates a synaptic mask, and in the second set of cycles, it performs integration by feeding the synaptic mask back to itself (word lines) but targeting a different bit line (the bit line storing weight information). Time multiplexing and interleaving of those sets of cycles can achieve better efficiency.

[0105] Figure 7Example graphs depicting STDP results in synaptic weighting. The y-axis indicates synaptic weight (e.g., changes in conductance), and the x-axis indicates time. The vertical line (between LTD and LTP) indicates the timing of the postsynaptic spike (e.g., the spike generated by the destination neuron). For cases where the presynaptic spike arrives at its destination synapse before the postsynaptic neuron generates the spike, the corresponding synaptic weight increases, as illustrated in graph section 702. This weight increase can be referred to as long-term potentiation (LTP) of the synapse. As can be observed from graph section 702, the amount of LTP decreases approximately exponentially based on the difference between the presynaptic spike time and the postsynaptic spike time. Conversely, for cases where the presynaptic spike arrives at its destination synapse after the postsynaptic neuron generates the spike, the corresponding synaptic weight decreases, as illustrated in graph section 704. This weight decrease can be referred to as long-term potentiation (LTD). As can be observed from graph 704, the amount of LTD decreases approximately exponentially based on the difference between presynaptic spur time and postsynaptic spur time. For example, in Figure 7 As explained, the training curves for synaptic weights may be asymmetric. For short interpeak intervals, the LTP weight increments represented by the partial 702 may be larger, but may decay faster than the LTD weight intervals.

[0106] In various embodiments, the postsynaptic neuron spiking time is known for post-spiking postsynaptic events arriving within the LTD window. Therefore, adjustment of synaptic conductance can be readily determined based on the known postsynaptic neuron spiking time. In various embodiments, adjustment of synaptic conductance is challenging for pre-spiking presynaptic events within the LTP window because: (1) the postsynaptic neuron spiking time is unknown; (2) each time quantum can introduce a new presynaptic event, which can interfere with the membrane potential and affect the postsynaptic neuron spiking time (for excitatory synapses, the presynaptic event promotes the generation of the postsynaptic neuron spiking, while for inhibitory synapses, the presynaptic event delays the generation of the postsynaptic neuron spiking); and (3) the time quantum is approximately 1 ms, while the LTP window spans approximately 50 ms. Therefore, the postsynaptic spiking time is uncertain until the target neuron actually forms a spiking time in the current time quantum.

[0107] Biology addresses this problem at the intracellular level by opening a “qualification window” at each individual synapse using neuromodulators, “second messengers,” and receptors. This window decays over time in proportion to the STDP rule: that is, in the first few microseconds, if the target neuron’s spike and its potential wave propagate back to the synapse, the synapse is highly susceptible to alteration. However, in the absence of this back-propagating potential wave, the actual synaptic conductance remains unchanged. If another presynaptic event arrives before the postsynaptic neuron’s spike, it adds to the already opened “qualification window.”

[0108] In computer simulations or network simulations, in various embodiments, to address the aforementioned problem, all or the most recent presynaptic events (i.e., their timestamps) within the duration of the LTP window are stored, and then, once the postsynaptic neuron generates a spike, these events are replayed, and the synaptic conductance is adjusted accordingly. In another embodiment, the aforementioned problem is addressed by implementing a "qualified window" feature in the memory cells of a memory array.

[0109] Refer again Figure 6 The feedback path from the sensing amplifier is provided to the corresponding bit line. In one embodiment, the feedback path is attenuated according to the STDP rule to address the issue of presynaptic events arriving after a spike.

[0110] Figure 8 This is a flowchart of a method 800 for assigning a tag to a pointer to a presynaptic spike event according to various embodiments of the present disclosure. Method 800 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 800 may be provided by an apparatus or system (e.g., Figure 1 System 100 Figure 3 System 300 Figure 5 System 500 and / or Figure 6 The system 600, or another device or system, performs the operation. Although described as discrete blocks, depending on the intended implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated.

[0111] In block 810 of method 800, in the first time quantum of a series of time quantumes in the SNN, a first presynaptic spike event is received from the corresponding source neuron of the SNN. The first presynaptic spike event includes recognition of the corresponding source neuron. For example, at least referencing Figure 3 At the first time quantum (e.g., 1 ms), spike 312 is received from the source neurons of the SNN (e.g., source neuron 210). In one embodiment, the presynaptic spike from each neuron contains the source neuron ID, such as the ID of source neuron 210-1, the ID of source neuron 210-2, and so on.

[0112] In block 820, a set of first presynaptic spike events is filtered, the set of first presynaptic spike events having source neuron identifications that at least partially match the destination synapse identification of the destination neuron in the memory block. For example, filter 320 determines whether the source neuron ID in spike 312 at least partially matches the destination synapse ID of neuron 330 (e.g., the ID of destination neuron 220). Upon determining a match, filter 320 passes filtered spike 314 to block 310.

[0113] In block 830, the first presynaptic spike event of the group is stored in a memory block. When the filtered spike 314 is determined, the filtered spike 314 is stored in block 310, for example, in a resistive memory array of block 310. For example, refer to... Figure 5 Store spike event 520 (e.g., filtered spike 314) in block 310.

[0114] In box 840, tags are assigned to pointers in a pointer table within a memory block that point to the first presynaptic spike event of the group. The tags correspond to time quanta in a series of time quanta of the SNN. For example, still referring to... Figure 5 Pointer table 510 contains labels associated with pointers to spike events 520.

[0115] Modifications, additions, or omissions may be made to method 800 without departing from the scope of this disclosure. For example, the operations of method 800 may be performed in different orders. Furthermore, the operations and actions outlined are provided as examples only, and some operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without departing from the essence of the disclosed embodiments. For example, in various embodiments, at each successive time quantum, the label in pointer table 510 increments to the successive time quantum.

[0116] Figure 9 This is a flowchart of a method 900 for generating a bitmask of presynaptic spike events matching synaptic connections, according to various embodiments of the present disclosure. Method 900 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 900 may be provided by an apparatus or system (e.g., Figure 1 System 100 Figure 3 System 300 Figure 5 System 500 and / or Figure 6 The system 600, or another device or system, performs the operation. Although described as discrete blocks, depending on the intended implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated.

[0117] In block 910 of method 900, synaptic connections of the destination neuron (i.e., synapses and their associated variables or values) are stored in a first memory array, each of the presynaptic connections containing a delay value and an incoming neuron identification. Each of the synaptic connections is grouped together based on the delay value, and each of the delay values ​​corresponds to a time quantum in a series of time quantumes of the SNN. For example, synapse 630 is stored in the memory array. Synapses of neurons 632 and 634 are grouped in buckets of time quantumes (e.g., 1ms bucket, 2ms bucket, etc.). Each synapse of a neuron contains an identification.

[0118] In box 920, presynaptic spike events from the corresponding source neurons are stored in a second memory array. Each number of presynaptic spike events contains an incoming neuron identification, and the number of presynaptic spike events is grouped together according to the time quanta in a series of time quanta of the SNN. For example, refer to... Figure 6 The spike events 620 are stored in time quantum buckets (e.g., 0ms bucket, 1ms bucket, 2ms bucket, etc.). Each spike event 620 includes a time delay (e.g., the corresponding time quantum) and the incoming neuron ID (e.g., the source neuron ID).

[0119] In box 930, at a first-time quantum, the afferent neuron identification of the synaptic connection of the destination neuron is matched with the afferent neuron identification of the source neuron. For example, the spike event 620 of the source neuron (with the source neuron ID) matches the destination neuron ID of the synapse 630. This matching feature can be implemented using a filter similar to filter 320 (of filter 400).

[0120] In block 940, in response to a match, an output signal corresponding to a bitmask of the presynaptic spike event is generated at the second memory array. For example, in response to a match, a bitmask of the ID of the source neuron that matches the ID of the destination synapse 614 is generated. In such an instance, the destination synapse 614 is then sent to memory array 640 for driving on a word line via driver 642.

[0121] Modifications, additions, or omissions may be made to method 900 without departing from the scope of this disclosure. For example, the operations of method 900 may be performed in a different order. Furthermore, the operations and actions outlined are provided as examples only, and some operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions, without departing from the essence of the disclosed embodiments.

[0122] Figure 10 An embodiment of a system 1000 configured to generate synaptic events at least in part based on presynaptic spike events is shown. In particular, the system 1000 is configured to generate spike events within a memory (e.g., memory array 1010).

[0123] In at least one embodiment, system 1000 is based on, as per the following... Figure 7 The described STDP rule generates spike events. As described above, given the STDP rule, for a spike-postsynaptic event arriving within the LTD window, the postsynaptic neuron spike time is known. Therefore, the adjustment of synaptic conductance can be easily determined based on the known postsynaptic neuron spike time. However, for a spike-presynaptic event within the LTP window, the postsynaptic spike time is indeterminate until the target neuron actually forms a spike in the current time quantum.

[0124] In the various embodiments described herein, to address the aforementioned problems, presynaptic events received are stored in an LTP window, and then, once a postsynaptic neuron generates a spike, the presynaptic events are replayed, and the synaptic conductance is adjusted accordingly.

[0125] System 1000 includes a memory array 1010. In at least one embodiment, memory array 1010 is similar to memory array 610 as described above. Memory array 1010 includes a plurality of word lines (e.g., WL0, WL1, etc.) and a plurality of bit lines (e.g., BL0, BL1, BL2, etc.). Memory cells are disposed at the intersection of each word line and bit line. For example, memory array 1010 includes memory cells 1030, 1032, and 1034 along word line WL0 (at the intersections of BL0, BL1, and BL2, respectively), and memory cells 1040, 1042, and 1044 along word line WL1 (at the intersections of BL0, BL1, and BL2, respectively). In various embodiments, memory cells include memory elements. In various embodiments, memory cells are used to store weights of synaptic connections. For example, the resistance or conductance of the memory cell is adjusted to correspond to the weights of the synaptic connections. The weights of the synaptic connections may be stored in one or more memory cells on a single bit line (or may be stored on multiple bit lines).

[0126] Driver 1020 can drive signals (e.g., voltage or current signals) corresponding to matching neurons (e.g., bitmasks) on one or more word lines. One or more sense amplifiers (e.g., sense amplifier 1052) coupled to one or more bit lines can generate output voltages based on current output from corresponding memory cells.

[0127] An integrator circuit system 1050 (which includes one or more sense amplifiers) integrates the output of sense amplifier 1052. A spike 1060 is generated when the threshold potential value of the neuron is met. Thus, system 1000 at least partially simulates a spike event in an SNN. For example, (1) a signal driven by a driver simulates a presynaptic event, (2) a memory unit at least partially simulates a synapse and its corresponding synaptic weight, and (3) the integrator circuit system 1050 (which includes a sense amplifier) ​​simulates one or more neurons. For example, the integrator circuit system 1050 and / or sense amplifier 1052 can simulate a neuron in an SNN. Thus, sense amplifier 1052 and integrator circuit system 1050 may be described herein as a “neuron,” a “neuron circuit system,” or simply a “circuit system.”

[0128] The following description pertains to managing post-spiking presynaptic events. Post-spiking presynaptic events refer to presynaptic signals arriving at the destination synapse after a spike is generated in the destination neuron. Given the STDP rule, as described above, synaptic conductance (or synaptic weighting) is adjusted (e.g., attenuated) according to the LTD window.

[0129] The memory array 1010 includes a feedback path from the integrator system 1050 back to a bit line coupled to the integrator 1050. For example, the sense amplifier 1052 is coupled to feedback 1055 to bit line BL0, and to feedback 1057 to bit line BL1.

[0130] A feedback path is provided from the integrator circuit 1050 (or neuronal circuitry system) back to the corresponding bit line to address the problem of presynaptic events following spikes. According to the LTD window of the STDP rule, the synapses of those events should be attenuated. Thus, the feedback path provides a damped bias with the correct potential. In one embodiment, the damped bias is applied to each memory cell on the bit line (e.g., globally to each cell). For example, the damped bias signal is applied from feedback 1055 to BL0. Therefore, the damped bias is applied to cells 1030 and 1040 on BL0. Similarly, for example, the damped bias signal is applied from feedback 1057 to BL1. Therefore, the damped bias is applied to cells 1032 and 1042 on BL1. The damped bias can be differential to operate the sense amplifier 1052, which can also be differential.

[0131] In various embodiments, the feedback signal (or attenuated bias) is generated by the integrator 1050 (or neuronal circuitry system) in response to a presynaptic event driven on a bit line in the memory array. Furthermore, in various embodiments, the integrator 1050 (or neuronal circuitry system) receives an output signal from the memory array indicating a presynaptic signal received by the memory array.

[0132] If any presynaptic event arrives during this decaying bias period (within the LTD window), the cell conductance corresponding to the presynaptic event will be adjusted according to the decaying bias at the time of its arrival. The decaying bias applied to the bit line can be encoded by varying the bit line feedback potential or current in various ways, such as, but not limited to, pulses, frequencies, amplitudes (current and voltage), shapes (e.g., sawtooth, up-ramp-down-ramp), spikes, etc. The presynaptic signal driven on the word line by the driver 1020 (which simulates a presynaptic event) can also be encoded by varying the feedback potential or current. Due to the interaction between the encoded bias and the encoded presynaptic signal (driven by the driver 1020), the memory cell conductance is adjusted according to the LTD rules, and substantially simultaneously, the sense amplifier 1052 receives the synaptic current according to the adjusted conductance. The synaptic current can be integrated by an integrating circuit system 1050 (which includes one or more sense amplifiers) that integrates the output of the sense amplifier 1052. When the threshold potential of the neuron is met, an output spike of 1060 can be generated.

[0133] In various embodiments, the memory array 1010 is capable of integrating presynaptic currents in the subthreshold domain without memory cell backflow. As described above, backflow events can produce sudden conductance in memory cells. The occurrence of backflow events often significantly affects the current-voltage behavior of memory cells. Because the memory array 1010 is capable of operating in the subthreshold domain, the power consumed in integrating current on the bit lines can be very low.

[0134] In various embodiments, memory array 1010 enables a threshold delay effect. A threshold delay effect is a bias applied to a memory cell (e.g., a single pulse or multiple pulses) that alters the effective threshold (and current-voltage (IV) curve) of the memory cell without causing a hysteresis loop. Furthermore, the effect of the bias disappears after a certain time. Therefore, instead of applying a globally attenuated feedback bias to the bit line, a threshold-modulated bias pulse can be applied to the bit line immediately after the spike. Thus, the threshold of each cell on the bit line increases or decreases individually (depending on the embodiment). In other words, due to the uniqueness of each memory cell (i.e., each memory cell is slightly different from the others), the cell attenuation LTD window (in the form of a drift IV curve) of each memory cell is unique.

[0135] Figure 11 The possible distribution of the threshold delay effect is depicted. One or more thresholds are depicted by thick lines (e.g., threshold 1110). In response to a single pulse or multiple pulses, the threshold distribution shifts, as depicted by dashed lines (e.g., shifted threshold 1120). In various embodiments, if measured with a long selection time (pre-bias), the threshold distribution shifts towards the origin.

[0136] The threshold delay effect is a desirable feature in synaptic neurodynamics because synapses are unique to each other, yet they also follow the same STDP rule. According to the STDP rule, the bias drift of each synapse should be exponential and return to its original state within 50 time quanta. In various embodiments, each of the presynaptic events arriving on the word line after the spike will experience a unique (for its target cell) "snapshot" of the cell IV curve upon its arrival. For example, a presynaptic signal driven on word line WL0 can be received by memory cell 1030 (see [link to memory cell 1030]) upon signal arrival. Figure 10 The effect of a "snapshot" of the IV curve. Additionally, immediately upon arrival of the presynaptic event at the memory cell, actions can be taken on the memory cell conductance to permanently "fix" the IV curve "snapshot" of the memory cell. In various embodiments, the action to permanently "fix" the IV curve "snapshot" may be (1) sending a refresh pulse, and / or (2) having two memory cells per neuron: one cell (e.g., memory cell 1030) for drifting the conductance or IV curve as described, and another cell (e.g., memory cell 1032; see...). Figure 10 This is used to fix the permanent conductance (e.g., unlike using features different from the "threshold delay effect"). Additionally, in various embodiments, when a presynaptic event arrives at a memory cell, the analog value of the drifting memory cell is copied to another memory cell. For example, this can be accomplished using a successive approximation differential sensing converter (not shown). In some embodiments, the threshold delay effect can be avoided for presynaptic events arriving after a spike (LTD). However, the threshold delay effect is highly desirable for LTP.

[0137] The following description addresses the management of presynaptic events prior to the neuronal spike. Given the STDP rule, as described above, the synaptic conductance (or synaptic weight) is adjusted (e.g., attenuated) according to the LTP window. It should also be noted that a challenge in simulating LTP is the undefined postsynaptic spike timing, making the contribution of all presynaptic events to the postsynaptic spike unknown before the actual spike is emitted.

[0138] In at least one embodiment, the LTP window is modeled by storing timestamps of presynaptic events aligned with each synaptic pair. When a postsynaptic neuron spikes at a certain time, the timestamp is read on the word line. The time increment between the timestamp and the spike time is calculated, and weights are adjusted based on the time increment. For example, a presynaptic signal (based on the presynaptic event) is driven on word line WL1 at time T1. Time T1 is then stored, for example, in cell 1044 (see...). Figure 10On the memory cell of the simulated neuron. At time T2, the integrator circuit 1050 generates a spike (e.g., spike 1060). The increments of T2 and T1 are then determined. The conductance (e.g., synaptic weight) of the memory cell (e.g., cell 1042) is then adjusted based on the LTP window of the STPD rule. For example, refer to Figure 7 The increments of T2 and T1 are determined based on portion 702 of Figure 700, where portion 702 indicates the change in conductance based on the difference between the presynaptic spike time and the postsynaptic spike time.

[0139] Furthermore, in some embodiments, the threshold delay effect can be used to “dummy” or speculatively enhance conductance, as if a postsynaptic spike occurs in the time quantum of arrival of the presynaptic event at the time when the change in synaptic conductance is at its highest (the threshold decreases to a minimum or maximum value, depending on the implementation). Similar to the LTD condition (as described above), the IV curve will drift back to its original state after approximately 50 time quanta. However, if a postsynaptic neuronal spike occurs during this window, then action is immediately taken on the unit conductance to permanently fix the unit conductance at the time of the spike, and a “snapshot” of the IV curve at the exact time is considered.

[0140] In some embodiments, at least two cells per synapse (similar to the LTD condition described above) are used because the memory cell conductance deviates through “dummy” or speculative conductance enhancement. For example, a first memory cell (e.g., memory cell 1030) is used for the original conductance state of normal current integration, while a second memory cell (e.g., memory cell 1032) is used for threshold modulation. Both cells contain the same conductance at the origin. Therefore, any presynaptic event arriving within the LTP window can inject current into the first cell and participate in membrane potential interference, while simultaneously readjusting the IV threshold of the second cell through “dummy” or speculative conductance enhancement.

[0141] Additionally, in some embodiments, the two units have the same conductance at the postsynaptic spike. For example, the conductance from the threshold modulation unit (e.g., memory unit 1032) is “copied” to the first unit (e.g., memory unit 1030) to preserve the synaptic state. Immediately after the spike and after both units have acquired a “copy” of the same conductance, one unit (e.g., memory unit 1032) enters the LTD mode (threshold increase) as described above, and the other unit (e.g., memory unit 1030) performs current integration. In some embodiments, a single unit may be used for both LTD mode and current integration. In some embodiments, more than two units are used to implement both LTD mode and current integration.

[0142] As an alternative to natural threshold drift, a forced threshold adjustment is used for each time quantum (e.g., a 95% reduction per time quantum for a unit receiving a synaptic event). Forced threshold adjustment can be used if natural threshold drift does not meet one or more requirements of the simulated synaptic event. Forced thresholding allows for improved control over threshold adjustment as well as the direct use of a "permanent" threshold. Additionally, a pair of units can be equalized based on the spike signal from the neuron. Equalization can be accomplished using a differential amplifier.

[0143] refer to Figure 10 In one example, bit line BL0 is used for current integration, while bit line BL1 is used for modulating the neuron (simulated by sense amplifier 1052). A presynaptic event arrives at word line WL1. Memory cell 1040 allows input to WL1 via its conductance. For example, if the neuron spikes in the time quantum of the presynaptic event arrival, the bias voltage of memory cell 1042 is adjusted. Thus, according to the STDP rule, the threshold of memory cell 1042 is reduced (e.g., the bias voltage is adjusted to its maximum value). Additionally, the bias voltage of memory cell 1042 returns to its original state after 50 ms (LTP window). After several time quanta, the neuron (e.g., sense amplifier 1052) integrates sufficient charge on the bit line (e.g., BL0) and generates a spike (e.g., spike 1060). Therefore, spike 1060 is reflected back to both bit lines for threshold modulation. Therefore, the presynaptic event after the spike on word line WL0 participates in charge integration (on one of the bit lines) and weakens memory cells 1030 and 1040.

[0144] Figure 12 This is a flowchart of a method 1200 for adjusting synaptic weights according to various embodiments of the present disclosure. Method 1200 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 1200 may be provided by an apparatus or system (e.g., Figure 1 System 100 Figure 6 System 600 Figure 10 The system 1000 or other device or system) is executed. Although described as discrete blocks, depending on the implementation to be performed, the various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated.

[0145] At block 1210 of method 1200, a presynaptic spike signal is driven on the word line. For example, driver 1020 drives the signal on the word line of memory array 1010. The signal driven on the word line simulates the presynaptic signal received by the neuron.

[0146] In block 1220, in response to the presynaptic spike signal driven on the word line prior to the generation of the spike signal by the neuron: (1) a feedback signal is generated to increase the conductance of the memory cell in a long-term enhancement (LTP) window of the spike timing-dependent plasticity (STDP) rule, and (2) the feedback signal is emitted to the word line. For example, in response to the presynaptic spike signal being driven on word line WL1 by driver 1020 and prior to the generation of spike 1060 by sense amplifier 1052, a feedback signal (e.g., feedback 1055 and / or feedback 1057) is generated to increase the conductance of one or more memory cells coupled to word line WL1. In particular, the feedback signal is emitted to word line WL1.

[0147] In block 1230, in response to the presynaptic spike signal driven on the word line after the spike signal is generated by the neuron: (1) a feedback signal is generated to reduce the conductance of the memory cell in a long duration enhancement (LTP) window of the spike timing-dependent plasticity (STDP) rule, and (2) the feedback signal is emitted to the word line. For example, in response to the presynaptic spike signal being driven on word line WL1 by driver 1020 and after spike 1060 is generated by sense amplifier 1052, a feedback signal (e.g., feedback 1055 and / or feedback 1057) is generated to reduce the conductance of one or more memory cells coupled to word line WL1. In particular, the feedback signal is emitted to word line WL1.

[0148] Modifications, additions, or omissions may be made to method 1200 without departing from the scope of this disclosure. For example, the operations of method 1200 may be performed in a different order. Furthermore, the operations and actions outlined are provided as examples only, and some operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions, without departing from the essence of the disclosed embodiments.

[0149] Figure 13 This is a simplified block diagram of a memory system 1300 implemented according to one or more embodiments described herein. The memory system 1300 includes a memory module that includes a plurality of memory devices 1302 and control logic components 1304. For example, memory devices 1302 may include... Figure 1 The memory device 120 and / or memory array 130, and / or Figure 3 memory block 310 and / or Figure 6 The memory array 640, and / or Figure 10 The memory array 1010, and the control logic component 1304 may include Figure 1 The controller 140 and / or host 111. The control logic component 1304 is operatively coupled to the memory device 1302 to read, write, or refresh any or all memory cells within the memory device 1302.

[0150] An electronic system is also disclosed. The electronic system may include a memory system, which contains multiple memory devices. Figure 14 This is a simplified block diagram of an electronic system 1400 implemented according to one or more embodiments described herein. The electronic system 1400 includes at least one input device 1402. The input device 1402 may be a keyboard, mouse, or touchscreen. The electronic system 1400 further includes at least one output device 1404. The output device 1404 may be a monitor, touchscreen, or speaker. The input device 1402 and the output device 1404 need not be separate from each other. The electronic system 1400 further includes a storage device 1406. The input device 1402, output device 1404, and storage device 1406 are coupled to a processor 1408.

[0151] Electronic system 1400 further includes a memory device 1410 coupled to processor 1408. Memory device 1410 may include and / or may be a memory device (e.g., Figure 1 A part of the memory device 120) and / or may be a memory system (e.g., Figure 13 The electronic system 1400 may be or include a computing, processing, industrial, or consumer product. For example, but not limited to, the electronic system 1400 may include a personal computer or computer hardware component, a server or other network hardware component, a handheld device, a tablet computer, an e-notebook, a camera, a telephone, a music player, a wireless device, a display, a chipset, a game, a vehicle, or other known systems.

[0152] According to the various embodiments disclosed herein, and compared to some conventional apparatuses, systems, and methods, the data used in one or more PIM calculations can be used to perform SNN spike events. Therefore, the number of reads from and / or writes to one or more memory arrays can be reduced, which can improve the efficiency and / or speed of PIM operations and / or reduce the latency associated with PIM operations.

[0153] One or more embodiments of this disclosure include a system. For example, the system may include a memory array comprising multiple memory cells at intersections of multiple word lines and multiple bit lines, wherein data written to the multiple memory cells corresponds to synaptic weight values. The system may include a driver configured to drive the multiple word lines. The system may also include a circuit system including a sense amplifier coupled to the multiple bit lines. The circuit system is configured to receive output signals from the multiple bit lines. The circuit system is further configured to generate a second signal having voltage, current, or timing characteristics or a combination thereof in response to a first signal driven on the word lines prior to the generation of a spike signal of a neuron, the second signal increasing the conductance of the first memory cell according to a spike timing-dependent plasticity (STDP) characteristic of the first memory cell among the multiple memory cells. The circuit system is further configured to generate a third signal having different voltage, current, or timing characteristics or a combination thereof in response to the first signal driven on the word lines after the generation of the spike signal of the neuron, the third signal decreasing the conductance of the first memory cell according to the STDP characteristic.

[0154] According to another embodiment, a method includes driving a first signal on a word line. The method further includes: in response to the first signal driven on the word line prior to generating a spike signal for a neuron, generating a second signal having voltage, current, or timing characteristics, or a combination thereof, the second signal increasing the conductance of a memory cell in a long-term enhancement (LTP) window of spike timing-dependent plasticity (STDP) characteristics; and transmitting the second signal to a bit line, wherein the memory cell is coupled to the word line and the bit line. The method further includes: in response to the first signal driven on the word line after generating the spike signal for the neuron, generating a third signal having different voltage, current, or timing characteristics, or a combination thereof, the third signal reducing the conductance of the memory cell in a long-term attenuation (LTD) window according to the STDP characteristics; and transmitting the third signal to the bit line.

[0155] In another embodiment, an electronic system includes at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The memory device includes a memory array comprising a plurality of memory cells at intersections of a plurality of word lines and a plurality of bit lines, wherein data written to the plurality of memory cells corresponds to synaptic weight values; and a circuit system including a sense amplifier coupled to the plurality of bit lines. The circuit system is configured to generate a second signal having voltage, current, or timing characteristics or a combination thereof, in response to a first signal driven on the word lines prior to the generation of a spike signal of a neuron, the second signal increasing the conductance of the memory cells among the plurality of memory cells; and to generate a third signal having different voltage, current, or timing characteristics or a combination thereof, in response to the first signal driven on the word lines after the generation of the spike signal of the neuron, the third signal decreasing the conductance of the memory cells.

[0156] According to other embodiments, an electronic system includes at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The at least one memory device includes: a memory cell array including a plurality of resistive elements configured to store synaptic weights; a driver configured to drive spike events on a plurality of word lines coupled to the plurality of resistive elements at each time quantum of a series of time quantumes in the SNN; and an integrator circuit configured to integrate the output voltage of the bit lines coupled to the resistive elements.

[0157] According to another embodiment, a system includes a memory array comprising a plurality of memory cells, wherein the conductance values ​​of the plurality of memory cells correspond to synaptic weight values. The system further includes a circuitry coupled to the memory array. The circuitry is configured to receive an output signal from the memory array and, in response to a first signal received at the memory array, generate a second signal to increase or decrease the conductance of the memory cells among the plurality of memory cells according to a spike timing-dependent plasticity (STDP) rule.

[0158] According to other embodiments, an electronic system includes at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The at least one memory device includes: a memory array comprising a plurality of memory elements; and a circuit system including one or more sense amplifiers coupled to the memory array. The circuit system is configured to generate a second signal to reduce the resistance of one or more of the plurality of memory elements in response to receiving an output signal from the memory array indicating a first signal arriving at the memory array before a spike signal generating a neuron. The circuit system is further configured to generate a third signal to increase the resistance of the one or more of the plurality of memory elements in response to receiving an output signal from the memory array indicating a first signal arriving at the memory array after a spike signal generating a neuron.

[0159] As is customary, the various features illustrated in the drawings may not be drawn to scale. The descriptions presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations used to describe various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily expanded or reduced for clarity. Furthermore, some drawings may be simplified for clarity. Thus, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0160] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC).

[0161] The terms used herein and especially in the appended claims (e.g., the body of the appended claims) are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “include” should be interpreted as “including but not limited to”, etc.).

[0162] Furthermore, if it is intended that a specific number of claims be cited, then this intention will be explicitly stated in the claims, and where there is no such citation, then this intention does not exist. For example, as an aid to understanding, the appended claims may contain the use of descriptive phrases “at least one” and “one or more” to describe claim citations. However, the use of such phrases should not be construed as implying that a claim citation introduced by the indefinite article “a” or “an” limits any particular claim containing such a citation to containing only one embodiment of such a statement, even when the same claim contains the introductory phrase “one or more” or “at least one” and an indefinite article, such as “a” or “an” (e.g., “a” and / or “an” should be interpreted as “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim citations. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0163] Furthermore, even when a specific number of the introduced claims is explicitly cited, it should be understood that such citations should be interpreted as indicating at least the number cited (e.g., a simple citation of "two citations" without other modifiers implies at least two citations, or two or more citations). Additionally, in cases where conventions such as "at least one of A, B, and C," or "one or more of A, B, and C," are used, such constructions are generally intended to include a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0164] Furthermore, any transition words and / or phrases indicating two or more alternative terms (whether in the specification, claims, or drawings) should be understood to encompass the possibility of including one, any, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0165] Furthermore, the use of terms such as "first," "second," and "third" in this document does not necessarily indicate a specific order or number of elements. Generally, the terms "first," "second," and "third" are used as general identifiers to distinguish different elements. Unless otherwise stated, these terms should not be construed as indicating a specific order. Similarly, unless otherwise stated, these terms should not be construed as indicating a specific number of elements.

[0166] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is encompassed by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this invention. In fact, various modifications to this disclosure will become apparent to those skilled in the art from this description, in addition to those shown and set forth herein (e.g., alternative useful combinations of the described elements). These modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A memory system comprising: A memory array comprising a plurality of resistive memory cells located at the intersection of a plurality of word lines and a plurality of bit lines, wherein data written to the plurality of resistive memory cells corresponds to synaptic weight values; A driver configured to drive the plurality of word lines; and A circuit system comprising a sense amplifier coupled to the plurality of bit lines, the circuit system being configured to: Receive output signals from the plurality of bit lines; In response to a first signal driven on a word line among the plurality of word lines prior to the generation of a spike signal of a postsynaptic neuron, a second signal having voltage, current, or timing characteristics or a combination thereof is generated, and the second signal is emitted to a bit line coupled to a first resistive memory cell among the plurality of resistive memory cells to increase the conductance of the first resistive memory cell, the second signal increasing the conductance of the first resistive memory cell according to the spike timing-dependent plasticity (STDP) characteristic of the first resistive memory cell; and In response to the first signal driven on the word line after the generation of the spike signal of the postsynaptic neuron, a third signal with different voltage, current or timing characteristics or combinations thereof is generated and emitted to the bit line to reduce the conductance of the first resistive memory cell, the third signal reducing the conductance of the first resistive memory cell according to the STDP characteristic.

2. The memory system of claim 1, wherein the circuitry is further configured to emit a feedback signal to one of the plurality of bit lines in response to generating the spike signal of the postsynaptic neuron, wherein the feedback signal is an attenuated bias voltage.

3. The memory system of claim 2, wherein the second signal is applied to each of the plurality of resistive memory cells on the bit line.

4. The memory system of claim 2, wherein the circuitry is further configured to adjust the conductance of the first resistive memory cell in response to a fourth signal driven on the word line after the generation of the spike signal of the postsynaptic neuron and during the decaying bias, according to the decaying bias.

5. The memory system of claim 1, wherein the circuitry is further configured to apply a threshold modulation bias to one of the plurality of bit lines in response to generating the spike signal of the postsynaptic neuron.

6. The memory system of claim 5, wherein the threshold modulation bias is applied immediately after the spike signal is generated.

7. The memory system of claim 1, wherein the circuitry is further configured to apply a separate attenuated bias to each of the plurality of resistive memory cells on the bit lines in response to the first signal driven on the word line after the generation of the spike signal of the postsynaptic neuron.

8. The memory system of claim 1, wherein the circuitry is further configured to apply a decay feedback signal to each resistive memory cell on one of the plurality of bit lines in response to generating the spike signal of the postsynaptic neuron, wherein the decay feedback signal simulates a long-term attenuation (LTD) window of decay.

9. The memory system of claim 1, wherein the circuitry is further configured to apply another signal to one or more resistive memory cells of the plurality of resistive memory cells on the word line in response to the first signal driven on the word line prior to the generation of the spike signal of the postsynaptic neuron, wherein the conductance of the one or more resistive memory cells returns to its original conductance state after a predetermined duration.

10. The memory system of claim 1, wherein the timestamp of the first signal is stored in one or more of the plurality of resistive memory cells in the memory array.

11. The memory system of claim 1, wherein the circuitry is further configured to respond to the first signal driven on the word line: Integrate the current on the first bit line of the plurality of bit lines intersecting the word line; and Threshold modulation is enabled on the second bit line of the plurality of bit lines that intersect with the word line.

12. The memory system of claim 1, wherein the circuitry is further configured to respond to the first signal driven on the word line: Injecting current into the second resistive memory cell among the plurality of resistive memory cells on the first bit line of the plurality of bit lines intersecting the word line; and Adjust the threshold bias voltage on the third resistive memory cell among the plurality of resistive memory cells on the second bit line of the plurality of bit lines intersecting with the word line.

13. The memory system of claim 1, further comprising a memory controller configured to, during a long-term enhancement (LTP) window and in response to generating the spike signal of the postsynaptic neuron, copy the conductance on a second resistive memory cell on a second bit line of a plurality of bit lines intersecting the word line to a first resistive memory cell on a first bit line of a plurality of bit lines intersecting the word line.

14. The memory system of claim 1, wherein the circuitry is further configured to integrate the conductance of the resistive memory cell on the bit lines of the plurality of bit lines.

15. The memory system of claim 1, wherein the circuitry is further configured to generate the spike signal in response to the membrane potential of the postsynaptic neuron satisfying a predetermined threshold at least in part based on the output signal.

16. A method performed on a memory device, comprising: Drive the first signal on the word line; In response to the first signal driven on the word line prior to the generation of the spike signal of the postsynaptic neuron: A second signal with voltage, current, or timing characteristics, or a combination thereof, is generated, which increases the conductance of the resistive memory cell within a long-term enhancement (LTP) window of peak timing-dependent plasticity (STDP) characteristics. and In response to generating the spike signal of the postsynaptic neuron, the second signal is emitted to the bit line to increase the conductance of the resistive memory cell, wherein the resistive memory cell is coupled to the word line and the bit line; and In response to the first signal driven on the word line after the generation of the spike signal of the postsynaptic neuron: Generate a third signal with different voltage, current, or timing characteristics, or combinations thereof, wherein the third signal reduces the conductance of the resistive memory cell within a long-term attenuation (LTD) window according to the STDP characteristic; and The third signal is emitted to the bit line to reduce the conductance of the resistive memory cell.

17. The method of claim 16, further comprising: In response to the first signal driven on the word line prior to the generation of the spike signal of the postsynaptic neuron, an attenuation signal is generated to change the conductivity of the resistive memory cell in an attenuated manner.

18. The method of claim 17, further comprising: In response to the generation of the spike signal of the postsynaptic neuron and during the decay signal, the conductance of the resistive memory cell is adjusted according to the decay signal, the conductivity of the resistive memory cell, or both.

19. The method of claim 16, further comprising: In response to the first signal driven on the word line prior to the generation of the spike signal of the postsynaptic neuron: Applying current to a first resistive memory cell on the first bit line intersecting the word line; and Adjust the threshold bias voltage on the second resistive memory cell on the second bit line that intersects with the word line.

20. An electronic system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; and At least one memory device operatively coupled to the at least one processor device and comprising: A memory array comprising a plurality of resistive memory cells located at the intersection of a plurality of word lines and a plurality of bit lines, wherein data written to the plurality of resistive memory cells corresponds to synaptic weight values; A circuit system comprising a sense amplifier coupled to the plurality of bit lines, the circuit system being configured to: In response to a first signal driven on a word line among the plurality of word lines prior to the generation of a spike signal in the postsynaptic neuron, a second signal is generated having voltage, current, or timing characteristics, or a combination thereof, and increasing the conductance of the resistive memory cells among the plurality of resistive memory cells; and the second signal is emitted to a bit line coupled to the resistive memory cell to increase the conductance of the resistive memory cell; and In response to the first signal driven on the word line after the generation of the spike signal of the postsynaptic neuron, a third signal with different voltage, current or timing characteristics or a combination thereof is generated and reduces the conductance of the resistive memory cell, and the third signal is emitted to the bit line to reduce the conductance of the resistive memory cell.

21. The electronic system of claim 20, further comprising a memory controller configured to, during a long-term duration enhancement (LTP) window and in response to generating the spike signal of the postsynaptic neuron, copy the conductance on a second resistive memory cell of a plurality of resistive memory cells on a second bit line of a plurality of bit lines intersecting the word line to a first resistive memory cell of a plurality of resistive memory cells on a first bit line of a plurality of bit lines intersecting the word line.

22. The electronic system of claim 20, wherein the circuitry is further configured to integrate the conductance of the resistive memory cell on the bit line.

23. The electronic system of claim 20, wherein the circuitry is further configured to generate the spike signal in response to the membrane potential of the postsynaptic neuron satisfying a predetermined membrane potential threshold.

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