Vertical field effect transistor and method for manufacturing a vertical field effect transistor

Abstract

In various embodiments, a vertical field-effect transistor (100) is provided. The vertical field-effect transistor (100) has a trench structure (128) with a first side and a second side opposite to the first side. A field-effect transistor (100) (FET) channel is constructed on the first side and the second side does not have an FET channel. The FET channel has a gallium nitride (GaN) region and an aluminum gallium nitride (AlGaN) region (110) adjacent thereto. The GaN region (132) has a p-type conductive first region (106) and a second region (108) constructed thereon. The vertical field-effect transistor (100) also has a source electrode (130) electrically connected to the p-type conductive first region (106) of the GaN region (132) and the AlGaN region (110).

Description

Technical Field

[0001] The present invention relates to a vertical field-effect transistor and a method for manufacturing the same. Background Technology

[0002] Vertical gallium nitride (GaN) transistors can use a highly conductive intermediate layer (also known as a two-dimensional electron gas, 2DEG) at the aluminum gallium nitride (AlGaN) / GaN interface as the channel (vertical HEMT). This HEMT offers the possibility of achieving higher cutoff voltages while having lower on-resistance compared to any other semiconductor material currently available in mass-producible quantities.

[0003] To achieve high cutoff voltage in vertical GaN semiconductor devices, a p-type doped layer is buried beneath a channel. This p-type doped layer has narrow conductive openings through which current can flow from the source contact to the drain contact below in the on-state. This avoids high electric field strength within the gate region. For example, conventional concepts have been demonstrated for planar designs in Chowdhury et al. (IEEE, Vol. 33, No. 1, doi: 10.1109 / LED.2011.2173456) and for trench designs in Shibata et al. (IEEE IEDM16-248, doi: 10.1109 / IEDM.2016.7838385).

[0004] However, constructing a buried p-type doped layer beneath the gate region presents a significant technological challenge. The source electrode of a transistor contacts not only the n-type doped region but also the p-type doped region. The reverse operation of the transistor via a reverse diode (also known as a body diode) requires a low-ohmic p-type contact. Due to the large bandgap of GaN, constructing a low-ohmic p-type contact is more challenging than in the case of, for example, silicon.

[0005] Furthermore, in some applications, trenches with side angles of 30° to 60° are used in GaN. This allows for normally-off operation of the 2DEG by changing the polarization conditions. Due to substrate miscuts, two distinct crystal facets are generated during trench construction. Clearly, a trench thus has two sides with different side angles. These different crystal facets can lead to different gate characteristics (e.g., threshold voltage). Summary of the Invention

[0006] The objective of this invention is to provide a vertical field-effect transistor and a method for manufacturing it, wherein the vertical field-effect transistor / method solves one or more of the aforementioned problems.

[0007] According to one aspect of the invention, this task is accomplished by a vertical field-effect transistor (VFET) having a trench structure with a first side and a second side opposite to the first side, wherein a field-effect transistor (FET) channel is formed on the first side and the second side does not have an FET channel. The FET channel has a gallium nitride (GaN) region and an adjacent aluminum gallium nitride (AlGaN) region. The GaN region has a first p-type conductive region and a second region formed thereon. The source electrode is electrically connected to the p-type conductive first region of the GaN region and the AlGaN region.

[0008] In vertical field-effect transistors (VFETs) according to different implementations, it is evident that only one side of the trench structure is used as the FET channel. Therefore, the aforementioned problems of different facets can be avoided or reduced. Clearly, the single-sided FET channel provides a consistent threshold voltage across all cells of the VFET. The transition from the FET channel to the drift region arranged between the FET channel and the drain contact is shielded from the electric field by a buried p-type conductive first region.

[0009] According to another aspect of the invention, this task is accomplished by a method for fabricating a vertical field-effect transistor. The method comprises constructing a trench structure on or above a GaN substrate, wherein the trench structure has a first side and a second side opposite to the first side. A field-effect transistor (FET) channel is constructed on the first side, and the second side remains without an FET channel. The FET channel has a gallium nitride (GaN) region and an adjacent aluminum gallium nitride (AlGaN) region. The GaN region has a first p-type conductive region and a second region constructed thereon. The method further comprises constructing a source electrode electrically connected to the p-type conductive first region of the GaN region and the AlGaN region.

[0010] The specific shape and arrangement of the buried p-type conductive first region can be obtained in a simple manner from the process flow. The source n-type contact (the contact between the source electrode and the AlGaN region) and the source p-type contact (the contact between the source electrode and the p-type conductive first region of the GaN region) can be constructed in two (independent) process steps and then connected to a common potential. Thus, different materials can be used for the n-type and p-type contacts. For example, this allows for p-type implantation alone in the semiconductor device. This structure of the semiconductor device enables a simple construction of the buried p-type doped layer beneath the gate composite.

[0011] Due to the large bandgap of GaN, to construct the low-ohmic p-type conductive first region required for the transistor to operate in reverse via the body diode, source contacts with different material combinations may be needed in the first and second regions of the GaN region. The structure of the vertical transistor structure according to various embodiments achieves a separate, e.g., independent construction of the contacts in the first region of the GaN region and the contacts in the AlGaN region. This simplifies the manufacturing process of the semiconductor component, for example, by reducing the number of mask processes. Attached Figure Description

[0012] Extensions to the described aspects are explained in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and described in more detail below. The drawings show:

[0013] Figure 1 A cross-sectional view showing one embodiment of a vertical field-effect transistor;

[0014] Figure 2 Flowcharts illustrating methods for manufacturing vertical field-effect transistors according to different embodiments; and

[0015] Figures 3A to 3O Different processing stages of a method for manufacturing a vertical field-effect transistor according to one embodiment are shown. Detailed Implementation

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification and illustrate specific embodiments in which the invention can be practiced. It will be understood that other embodiments can be used and structural or logical changes can be made without departing from the scope of the invention. It will be understood that features of the different embodiments described herein can be combined with each other unless specifically stated otherwise. Therefore, the following detailed description should not be construed as limiting, and the scope of the invention is defined by the appended claims. In the drawings, the same or similar elements are given the same reference numerals, provided that this is for the purpose.

[0017] Within the scope of this specification, a p-type conductive region or p-type conductive layer can be a structure doped with p-type dopant by ion implantation or an epitaxial p-type conductive structure. In a p-type conductive structure, the free-moving majority carriers are holes. Similarly, an n-type conductive region or n-type conductive layer can be constructed, wherein the free-moving majority carriers in the n-type conductive structure are electrons. The intrinsic conductive region or intrinsic conductive layer possesses the conductivity of the material in the undoped or un-doped state.

[0018] Figure 1A cross-sectional view showing an embodiment of a vertical field-effect transistor 100 is presented. The vertical field-effect transistor 100 has a plurality of trench structures 128 on a substrate 102. In Figure 1 , two adjacent trench structures 128 are shown as an example. Each trench structure 128 can correspond to a cell of the transistor 100. Each trench structure 128 has a first side (in Figure 1 , the side on which the gate electrode 140 of the field-effect transistor 100 is constructed) and a second side opposite to the first side (in Figure 1 , the side on which the source electrode 130 of the field-effect transistor 100 is constructed). A field-effect transistor (FET) channel is constructed on the first side of the trench structure 128, and the second side of the trench structure 128 does not have an FET channel. The FET channel has a gallium nitride (GaN) region (106, 108) and an aluminum gallium nitride (AlGaN) region 110 adjacent thereto. The GaN region 108 and the adjacent AlGaN region 110 have physical and electrical contacts. The GaN region, for example, has a first region 106 with p-type conductivity (also referred to as the first layer 106 with p-type conductivity) and a second region 108 (also referred to as the second layer 108) constructed thereon. The second region 108 is, for example, intrinsic. The source electrode 130 is conductively connected to the first region 106 with p-type conductivity of the GaN region and the AlGaN region 110.

[0019] Obviously, the field-effect transistor 100 according to different embodiments has at least one trench structure 128. Each trench structure 128 has, for example, a V shape, and the V shape has side surfaces leading to a common point. In the trench structure 128, the FET channel is provided unidirectionally, for example, on only one leg, one facet, or one side surface of the V shape. The other leg, the other facet, or the other side surface of the trench structure 128 does not have an FET channel.

[0020] The FET channel can be set up such that it has a two-dimensional electron gas (2DEG). The FET channel can be formed, for example, by a structure composed of an aluminum gallium nitride region (Al x Ga 1-x N, where 0 < x < 1, hereinafter referred to as AlGaN) 110 and a gallium nitride (GaN) layer 108. This structure will be described in more detail below.

[0021] The contact between the source electrode 130 of transistor 100 and the FET channel is obviously located on the protrusion 120 between directly adjacent trench structures 128. The contact between the source electrode 130 of transistor 100 and the buried p-type conductive first region 106 of the GaN region is arranged in the bottom 122 of the adjacent trench structure 128. The contacts of the source electrode 130 are substantially at the same potential. This structure, consisting of the trench structure and the source electrode 130, causes the current (in the on state of transistor 100) to... Figure 1 (Indicated by arrow 124) Current is injected into the FET channel through the source contact 130 on the protrusion 120. Here, the current flows unilaterally through the FET channel along the sidewall of the trench structure 128 to the bottom 122 of the trench structure 128. At the bottom 122, the current is led downward to the drain electrode 150, which is located on the back side of the substrate 102. The p-type conductive first region 106, which is in electrical contact with the source electrode 130, acts as a diode in the cutoff direction with the drain electrode 150 in the on state, and causes the connection between the shielded FET channel and the drain electrode 150. With the help of the trench structure 128 with a unilateral FET channel, a consistent threshold voltage is achieved in each cell of the vertical field-effect transistor 100.

[0022] In the reverse operation of the vertical field-effect transistor 100 (in Figure 1 (Indicated by arrow 126), the p-type conductive first region 106 and the drain electrode 150 form a diode (also called a body diode) in the conduction direction, and the FET channel and the drain electrode 150 block current flow.

[0023] This transistor structure can be used, for example, in electric drive systems (e.g., in DC / DC converters or inverters) in electric vehicles or hybrid electric vehicles, in electric vehicle charging stations (also known as "car chargers"), in LiDAR systems (light detection and ranging), or in inverters for household appliances (e.g., washing machines).

[0024] In detail, Figure 1 The embodiment of the vertical field-effect transistor 100 shown has a substrate 102, such as an n-type GaN substrate, such as an n+ doped GaN substrate. The substrate 102 has a first side (front side) and a second side (back side) opposite the first side. A trench structure 128 is disposed on the first side of the GaN substrate. A drain electrode 150 is disposed on the second side of the GaN substrate 102. A second metal layer 134 is formed on or above the second side of the substrate 102. The second metal layer 134 may have or be configured with the drain electrode 150.

[0025] An n-type conductive GaN layer 104, such as an epitaxially grown n-type doped GaN layer, is disposed on or above the first side of the substrate 102.

[0026] A p-type conductive GaN layer 106 is disposed at least partially within the n-type doped GaN layer 104, for example, embedded or buried therein. The p-type conductive GaN layer 106 may be or have a first region 106 that is p-type conductive within the aforementioned GaN region.

[0027] An n-type conductive or intrinsically conductive GaN layer 108 is disposed at least partially in and on the p-type conductive GaN layer 106, for example, embedded or buried therein. The n-type conductive or intrinsically conductive GaN layer 108 can form or have a second region of the aforementioned GaN region.

[0028] An aluminum gallium nitride (AlGaN) layer 110 is disposed on the GaN layer 108. The AlGaN layer 110 can be an intrinsic layer. A gate dielectric 112 and an insulating layer 114 thereon are disposed on the GaN layers 106, 108 and the AlGaN layer 110. Openings are included in both the gate dielectric 112 and the insulating layer 114, through which the AlGaN layer 110 (on the protrusion between the two trench structures 128) and the buried p-type doped GaN layer 106 (on the bottom of the trench structure 128) are exposed. In the insulating layer 114, an opening is formed above the AlGaN layer 110, in which a gate metal portion 118, such as polysilicon, is formed. A structured first metal layer 116 is disposed on the insulating layer 114 and in its opening. The first metal layer 116 contacts the AlGaN layer 110 and the buried p-type conductive GaN layer 106 through the opening, thereby forming a source electrode 130. Another portion of the first metal layer 116 that is connected to the gate metal portion 118 forms the gate electrode 140.

[0029] With (first) trench structure 128 (e.g. with in Figure 1 The trench structure 128 on the right side of the first trench structure 128 is adjacent to the ground, which can be used to construct the second trench structure 128. The p-type conductive region 106 of the GaN region of the first trench structure 128 can extend below the bottom 122 of the second trench structure 128 and contact the source electrode 130 there, which forms the source contact for the FET channel of the (first) trench structure 128.

[0030] The first and second sides of each trench structure 128 can respectively form angles with the (GaN) substrate 102 in the range of greater than 0° and less than 90°, for example, in the range of about 30° to about 60°. Accordingly, the first and second sides can be referred to as ramps, facets, side surfaces, or lateral surfaces of the trench structure 128. A lateral surface angle of 30° to 60° is advantageous because it allows for normally-off operation of the 2DEG by changing the polarization conditions. The angle of the first side of the trench structure 128 can here be different from the angle of the second side of the trench structure 128.

[0031] The vertical field-effect transistor 100 is also capable of having a gate dielectric 112 constructed on an AlGaN region 110 and a gate electrode 140 constructed on the gate dielectric 112 in each trench structure 128.

[0032] Figure 2 Flowcharts illustrating methods for fabricating vertical field-effect transistors according to different embodiments are shown. Method 200 involves fabricating a transistor on a GaN substrate (e.g., ...). Figure 1 Construct a 202 trench structure on or above 102 (e.g.) Figure 1 (128 in the text). The trench structure has a first side and a second side opposite to the first side. A field-effect transistor (FET) channel is constructed on the first side and the second side remains without a FET channel. The FET channel has a gallium nitride (GaN) region (e.g., ...). Figure 1 The 106 / 108 region and the adjacent aluminum gallium nitride (AlGaN) region (e.g.) Figure 1 110 in the middle). The GaN region has a first region with p-type conductivity ( Figure 1 106 in the middle) and the second region constructed on it ( Figure 1 108 in the middle). Method 200 also has the function of constructing a 204 source electrode (e.g., 108 in the middle). Figure 1 (130) The source electrode is electrically connected to the p-type conductive first region of the GaN region and the AlGaN region.

[0033] The first and second sides of the trench structure can form angles with the GaN substrate ranging from greater than 0° to less than 90°. This method also allows for the fabrication of a gate dielectric (e.g., on the AlGaN region). Figure 1 (112) This method can also have the capability of constructing a gate electrode on the gate dielectric (e.g.) Figure 1 (140 in the text). This method is also capable of constructing a drain electrode on the side of the GaN substrate opposite to the side with the trench structure (e.g., 140 in the text). Figure 1 (150 in the middle).

[0034] Figures 3A to 3ODifferent processing stages of a method 300 for manufacturing a vertical field-effect transistor according to one embodiment are shown. (See also...) Figure 3A As shown, method 300 can include a substrate 102. Substrate 102 is, for example, an n+ doped GaN substrate.

[0035] As in Figure 3B As shown, method 300 can also have a layer 104 constructed on substrate 102, such as an epitaxially grown layer, such as an n-type conductive GaN layer 104.

[0036] As in Figure 3C As shown, method 300 can also have a shielded p-type conductive region 106a constructed in the GaN layer 104, for example, by means of ion implantation. The shielded region 106a can form part of a first region of the GaN region of the trench structure 128 (to be formed subsequently).

[0037] As in Figure 3D As shown, method 300 can also include an undoped (intrinsic) layer 108, for example, by epitaxially growing an undoped layer 108 on a layer 104 having a region 106a contained therein. The undoped layer 108 can form a second region of the GaN region of the trench structure 128 (to be formed subsequently). Alternatively, layer 108 can be n-type doped (n-type conductive).

[0038] As in Figure 3E As shown, method 300 can also have a p-type conductive region 106b buried in the undoped layer 108 by means of ion implantation 310. The p-type conductive region 106b can be formed below the gate electrode 140 (to be formed subsequently) and connected to the shielding region 106a, thereby forming a continuous p-type conductive region 106, which forms the first region of the aforementioned GaN region of the trench structure 128 (to be formed subsequently).

[0039] As in Figure 3F As shown, method 300 can also have at least one trench 330 constructed in the previously constructed layer structure, for example by means of an etching method. Figure 3BTwo trenches are illustrated in the diagram. These (or each) trenches 330 can be V-shaped, formed by the anisotropic etching of the materials of layers 106, 108. The V-shape has a surface forming an angle with the substrate 102, for example, in the range of about 30° and about 60°. On the protrusion 334 between two adjacent trenches 330, the intrinsically conductive or n-type conductive second region 108 of the GaN region can be exposed. In the bottom 332 of the trench 330, the p-type conductive first region 106 of the GaN region can be exposed. Furthermore, a portion of the n-type conductive layer 104 in the bottom 332 of the trench 330 can be exposed. Thus, the p-type conductive first regions 106 of the adjacent trenches 330 can be electrically insulated from each other.

[0040] As in Figure 3G As shown, method 300 can also have an undoped (intrinsically conductive) or n-type conductive GaN layer 336 constructed, for example, epitaxially grown, on or above the previously exposed surfaces of the protrusion 334, the bottom 332 of the trench 330, and the side surface 336. The GaN layer 336 can be the same as or different from layer 108. For example, the GaN layer 336 can have the same or different dopants as layer 108 at the same or different dopant concentrations.

[0041] As in Figure 3H As shown, method 300 can also remove or structure the previously applied layer 336 in the region of the trench. For example, layer 336 can be removed by etching the bottom region of the trench and one of the sidewalls of the trench (in Figure 3H The middle (right sidewall) is removed. Therefore, layer 336 can remain on the protrusion 334 and the other sidewall 338 of the trench. In a further step of method 300, the remaining portion of layer 336 can form part of the channel of a vertical field-effect transistor.

[0042] As in Figure 3I As shown, method 300 can also have an AlGaN layer 110 constructed, for example, by epitaxial growth. The AlGaN layer 110 can be constructed on the bottom of the trench, the protrusions, and the side surfaces (with and without layer 336).

[0043] As in Figure 3JAs shown, method 300 can also involve removing or structuring a portion of the previously constructed AlGaN layer 110. For example, the AlGaN layer 110 can be removed from the p-type conductive layer 106 and from the sidewalls of the trench by means of etching in the bottom region. Here, the AlGaN layer 110 can be removed from the sidewalls of the trench that do not have layer 336. The AlGaN layer 110 can form a portion of the channel of a vertical field-effect transistor on the sidewalls 338 of the trench together with the intrinsic or n-type conductive layer 108. The p-type conductive layer 106 on the bottom of the trench can be exposed. In other words, the p-type conductive layer 106 can not have direct conductive and / or physical contact with the AlGaN layer 110. In a further method, the AlGaN layer 110 can be used together with the intrinsically or n-type conductively constructed layer 108 to construct the FET channel of the vertical field-effect transistor.

[0044] As in Figure 3K As shown, method 300 can also have a gate dielectric 112 constructed, for example, by means of planar deposition. The gate dielectric 112 can be constructed as follows: Figure 3J The structure shown is a continuous layer above the exposed surface and is subsequently structured. Alternatively, the gate dielectric 112 can be applied to a portion of the exposed surface in a structured manner. The gate dielectric 112 is, for example, silicon nitride or silicon oxide or formed therefrom.

[0045] As in Figure 3L As shown, method 300 can also include the removal or structuring of the gate dielectric 112. For example, openings 340, 342 can be formed in the gate dielectric 112 in the areas of the trench bottom and the raised areas. Opening 340 can be formed in the gate dielectric 112 such that the p-type conductive layer 106 is exposed on the bottom of the trench. Opening 342 can be formed in the gate dielectric 112 such that the AlGaN layer 110 is exposed on the raised areas between the trench and adjacent trenches. Openings 340, 342 can be used to subsequently form contacts for the p-type conductive layer 106 and for the AlGaN layer 110.

[0046] As in Figure 3M As shown, method 300 can also have a gate metallization portion 118 constructed, for example, deposited and structured, such as polysilicon. The gate metallization portion 118 can be constructed on the gate dielectric 112 above the trench sidewall having the FET channel described above.

[0047] As in Figure 3NAs shown, method 300 can also have an insulating layer 114 structurally constructed on the exposed surface of the gate dielectric 112. The structural construction can have planar deposition of the insulating layer 114, such as a silicon nitride layer or a silicon oxide layer, and subsequently construction of openings in the insulating layer 114, so that the insulating layer 114 remains only on the exposed surface of the gate dielectric 112.

[0048] As in Figure 3O As shown, method 300 can also have metal layers structurally constructed on the exposed front and back sides. The structural construction can involve depositing a first metal layer onto the surface of the exposed layer on the front side of the substrate 102. Alternatively or additionally, a continuous second metal layer can be deposited on the exposed back side of the substrate 102. Openings can then be constructed in the first and / or second metal layers. Thus, a source electrode 130 and a gate electrode 140 can be constructed on the front side, and a drain electrode 150 of the vertical field-effect transistor 100 can be constructed on the back side.

[0049] The source electrode 130 is implemented, for example, by a first metal layer physically and electrically contacting the AlGaN layer 110 through an opening in the gate dielectric 112 and an opening in the insulating layer 114 on the trench protrusion. Furthermore, the first metal layer of the source electrode 130 physically and electrically contacts the p-type conductive layer 106 through openings in the gate dielectric 112 and in the insulating layer 114 at the bottom of the trench. Thus, the AlGaN layer 110 and the p-type conductive layer 106 are electrically connected to each other through the source electrode 130 and have substantially the same potential. Clearly, the AlGaN layer 110 and the p-type conductive layer 106 are electrically short-circuited through the source electrode 130.

[0050] The gate electrode 140 can be implemented by electrically and physically contacting the gate metallization portion 118 of the first metal layer. The portion of the first metal layer forming the gate electrode 140 is electrically insulated from the portion of the first metal layer forming the source electrode 130, for example, by means of an opening in the first metal layer.

[0051] The drain electrode 150 can be implemented by electrically and physically contacting the substrate 102 with the second metal layer.

[0052] The described and illustrated embodiments are selected only by way of example. Different embodiments can be implemented entirely or in combination with each other regarding various features. One embodiment can also be supplemented by features of another embodiment. Furthermore, the described method steps can be repeated and performed in a different order than described. In particular, the invention is not limited to the methods given. For example, a process flow for reducing process steps can be designed such that layers 104, 106, and 108 are first epitaxially grown and then doped or conductive is constructed. For example, implantation can be performed through an existing region. In another alternative embodiment, a p-type doped GaN region can be constructed below the gate metallization 118 instead of the gate dielectric 112. This p-type doped GaN region can ensure the latch-up operation of the vertical field-effect transistor by partially depleting the two-dimensional electron gas below the gate electrode 140.

Claims

1. A vertical field-effect transistor (100) having a trench structure (128) and a source electrode (130), in, The trench structure has a first side and a second side opposite to the first side. In this configuration, a field-effect transistor (FET) channel is constructed on the first side, while the second side does not have a field-effect transistor channel. The field-effect transistor channel has a gallium nitride (GaN) region and an adjacent aluminum gallium nitride (AlGaN) region (110). The gallium nitride region (132) has a first region (106) that is p-type conductive and a second region (108) formed thereon. The source electrode is electrically connected to the p-type conductive first region (106) of the gallium nitride region (132) and the aluminum gallium nitride region (110).

2. The vertical field-effect transistor (100) according to claim 1, in, The second region (108) of the gallium nitride region (132) is n-type conductive or intrinsically conductive.

3. The vertical field-effect transistor (100) according to any one of the preceding claims, the vertical field-effect transistor further comprising a GaN substrate (102), the GaN substrate having a first side and a second side opposite to the first side, wherein, The trench structure (128) is disposed on a first side of the GaN substrate (102), and the drain electrode (150) is disposed on a second side of the GaN substrate (102).

4. The vertical field-effect transistor (100) according to claim 3, wherein the vertical field-effect transistor structure further comprises a second trench structure adjacent to the trench structure (128), in, The first p-type conductive region (106) of the gallium nitride region (132) extends below the bottom of the second trench structure and contacts the source electrode (130) there.

5. The vertical field-effect transistor (100) according to claim 3, in, The first and second sides of the trench structure (128) form angles with the GaN substrate (102) in the range of greater than 0° and less than 90°.

6. The vertical field-effect transistor (100) according to claim 5, in, The angle of the first side of the groove structure (128) is different from the angle of the second side of the groove structure (128).

7. The vertical field-effect transistor (100) according to claim 1 or 2, wherein the vertical field-effect transistor further comprises: A gate dielectric (112) is constructed on the aluminum gallium nitride region (110) and a gate electrode (140) is constructed on the gate dielectric (112).

8. A method (200) for manufacturing a vertical field-effect transistor (100), the method (200) comprising: A trench structure (128) (202) is constructed on or above a GaN substrate. in, The trench structure (128) has a first side and a second side opposite to the first side. In this configuration, a field-effect transistor (100) channel is constructed on the first side, while the second side remains without a field-effect transistor channel. The field-effect transistor channel has a gallium nitride (GaN) region and an adjacent aluminum gallium nitride (AlGaN) region, and The gallium nitride region (132) has a first region (106) that is p-type conductive and a second region (108) formed thereon; and A source electrode (130) is constructed (204), which is electrically connected to the p-type conductive first region (106) of the gallium nitride region (132) and the aluminum gallium nitride region (110).

9. The method (200) for manufacturing a vertical field-effect transistor (100) according to claim 8, in, The first and second sides of the trench structure (128) form angles with the GaN substrate (102) in the range of greater than 0° and less than 90°.

10. The method (200) for manufacturing a vertical field-effect transistor (100) according to claim 8 or 9, the method further comprising: A gate dielectric (112) is formed on the aluminum gallium nitride region (110), and a gate electrode (140) is formed on the gate dielectric (112); and A drain electrode (150) is constructed on the side of the GaN substrate (102) opposite to the side having the trench structure (128).

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