Integrated circuit device with parallel power amplifier output paths

Abstract

An integrated circuit device (100) is provided. In some examples, the integrated circuit device includes a first amplifier path (112), a second amplifier path (114) coupled in parallel with the first amplifier path (112), a matching network (124) coupled to the first amplifier path (112) and the second amplifier path (114), and an antenna (104) coupled to the matching network (124). In some such examples, the first amplifier path (112) includes a first differential power amplifier (118) coupled to the matching network (124), and the second amplifier path (114) includes a second differential power amplifier (138) coupled to the matching network (124). The integrated circuit device (100) can also include a controller (110) coupled to selectively enable the first amplifier path (112) to provide transmitter output power in a first range and to selectively enable the second amplifier path (114) to provide transmitter output power in a second range different from the first range.

Description

Background Technology

[0001] The transmitter of a wireless communication device may include an amplifier circuit system that receives and amplifies a signal for transmission. In many such devices, the transmitter circuit system may consume a significant portion of the total power, and the amplifier circuit system within the transmitter may be one of the major contributors. Therefore, in battery-powered applications, the power consumption and efficiency of the amplifier circuit system can have a significant impact on battery life.

[0002] In some example devices utilizing power amplifier circuitry, the power amplifier circuitry operates most efficiently when the power amplifier is in saturation. However, to avoid harmful interference, the transmitter can be instructed to reduce its output power where possible. The reduced output power is still sufficient for communication with the receiver while minimizing interference to other devices. The transmitter's output power can be reduced by decreasing the bias current of the power amplifier, causing the power amplifier to operate in current saturation mode. However, in current saturation mode, the efficiency of the amplifier circuitry may decrease as the bias current decreases. This can be particularly noticeable when the output power is significantly reduced (e.g., back-off). In addition to inefficiency, the variation in the amplifier's output power may increase as the bias current decreases due to process variations within the active circuitry. Summary of the Invention

[0003] In some examples, an integrated circuit is provided that includes an amplifier circuit system for a wireless transmitter. The transmitter operates within a given transmitter output power range. The amplifier circuit system includes a first amplifier path and a second amplifier path, the first amplifier path being configured to transmit in a first (e.g., higher) portion of the output power range, and the second amplifier path being coupled in parallel and configured to transmit in a second (e.g., lower) portion of the power range. The first amplifier path is configured to operate most efficiently in the first portion of the power range, while the second amplifier path is configured to operate most efficiently in the second portion. Both paths may include differential power amplifiers and are both coupled to a matching network comprising a set of switches that reconfigure the matching network based on which amplifier path is enabled.

[0004] In some examples, an integrated circuit device includes: a first amplifier path, a second amplifier path coupled in parallel with the first amplifier path, a matching network coupled to the first and second amplifier paths, and an antenna coupled to the matching network. In some such examples, the first amplifier path includes a first differential power amplifier coupled to the matching network, and the second amplifier path includes a second differential power amplifier coupled to the matching network. In some such examples, the second amplifier path further includes a third differential power amplifier coupled to a differential input of the second differential power amplifier. In some such examples, the integrated circuit device also includes a controller coupled to control the first amplifier path, the second amplifier path, and the matching network. In some such examples, the controller is configured to selectively enable the first amplifier path to provide transmitter output power within a first range, and selectively enable the second amplifier path to provide transmitter output power within a second range less than the first range. In some such examples, the matching network includes a switch, and the controller is configured to set the state of the switch based on which of the first and second amplifier paths is selectively enabled. In some such examples, the integrated circuit device also includes a driver element coupled to provide an input signal to each of the first and second amplifier paths. In some such examples, the second amplifier path includes a first-stage power amplifier and a second-stage power amplifier. The first-stage power amplifier is coupled to receive an input signal from a driver element and generate a second signal in response to the input signal. The second-stage power amplifier is coupled to receive the second signal from the first-stage power amplifier and generate a third signal in response to the second signal. In some such examples, the matching network includes a balun coupled to the first amplifier path, a first capacitor coupled in parallel with the balun, and a second capacitor coupled in parallel with the first capacitor. The second-stage power amplifier includes a first differential output coupled to the balun and a second differential output coupled to the second capacitor. In some such examples, the matching network further includes a first switch coupled to the balun, a second switch coupled to the first capacitor, and a third switch coupled to the second capacitor.

[0005] In another example, an integrated circuit includes: a first power amplifier, a second power amplifier coupled in parallel with the first power amplifier, a matching network including a switch group coupled to the first and second power amplifiers, and a controller coupled to control the first power amplifier, the second power amplifier, and the switch group. The controller is configured to selectively enable one of the first and second power amplifiers based on a specified output power.

[0006] In yet another example, an integrated circuit includes a processing resource and a non-transitory computer-readable medium coupled to the processing resource. The computer-readable medium stores instructions that, when executed by the processing resource, cause the processing resource to determine a transmitter output power, selectively enable one of a first amplifier path and a second amplifier path based on the determined transmitter output power, and cause the selected amplifier path to transmit a signal according to the determined transmitter output power. Attached Figure Description

[0007] Figure 1 These are circuit diagrams based on some examples of integrated circuit devices.

[0008] Figure 2 It is a circuit diagram of a portion of an integrated circuit device in operation mode, based on some examples.

[0009] Figure 3 This is a flowchart illustrating methods for operating a wireless transmitter, based on some examples. Detailed Implementation

[0010] Specific examples are described in detail below with reference to the accompanying drawings. These examples are not limiting, and unless otherwise stated, no particular example requires any specific features. Furthermore, the first device, which is coupled or connected (electrically, physically, or otherwise) to the second device, may be directly coupled or connected without any intermediate device, or indirectly coupled or connected through one or more intermediate devices.

[0011] Many wireless communication standards require wireless transmitters to dynamically adjust their output power to reduce interference to other devices sharing the same or adjacent channels. This also reduces the power consumption of the transmitting device. As an example of such a standard, IEEE 802.11ax specifies that the transmitter output power is within a defined range and stipulates that the output power should be reduced where possible.

[0012] However, many power amplifier circuits have their highest efficiency at or near saturation, and their efficiency drops significantly as output power decreases. Therefore, some examples in this specification provide parallel power amplifier paths. A first path can be enabled when the specified transmitter output power is in the higher portion of the power range. The first path can be configured such that one or more power amplifiers in the first path are saturated at or near the maximum output power specified in the power range. When the specified transmitter output power is in the higher portion of the power range, the output power can be controlled by adjusting the bias current of one or more power amplifiers in the first path. However, dividing the power range into higher and lower portions avoids the inefficiencies involved in reducing the bias current sufficiently to satisfy the lower portion of the power range.

[0013] Conversely, a second path can be enabled when the specified transmitter output power is in the lower portion of the power range. The second path can be configured such that its power amplifier(s) saturate at or near the boundary (e.g., crossover) between the two portions of the power range. Using a second, lower power amplifier path can provide a significant improvement in efficiency compared to reducing the bias current of the power amplifier(s) of the first path(s) to reduce the transmitter output power to the lower portion of the power range. Furthermore, in some examples, the power amplifiers of the second path operate at a lower supply voltage than the power amplifiers of the first path to further improve efficiency. Therefore, in some such examples, if the second path is used to drive the lower portion of the power range, the efficiency of the second path is approximately 2 to approximately 2.5 times higher than that of the first path.

[0014] In some examples, because the power amplifiers in the first and second paths operate near saturation, process-dependent variation characteristics are reduced during lower power operation. This avoids process-dependent calibration of the transmitter.

[0015] The matching networks coupled to the first and second paths can be reconfigured via a switch depending on which path is enabled. In some examples, the regional impact is minimal because the second path uses smaller devices and the same matching network. In some examples, the matching network is configured to support a differential power amplifier in the second path, which provides greater saturation power than a comparable single-ended power amplifier. The use of a differential power amplifier can also reduce higher-order even harmonics, thereby improving the linearity of the transmitted signal.

[0016] Of course, these advantages are just examples, and no particular embodiment needs to have advantages.

[0017] An example of an amplifier integrated circuit device is described with reference to the following figures. In this respect, Figure 1 It is based on the circuit diagram of an integrated circuit device 100 in some examples.

[0018] Integrated circuit device 100 may be part of a wireless transmitter and receive input signal 102A for wireless transmission via antenna 104. In various such examples, signal 102A is received by driver element 106 of integrated circuit device 100. Driver element 106 may include one or more mixers, amplifiers, preamplifiers, filters, predistortion drivers, and / or other suitable signal processing components to condition signal 102A for transmission. After conditioning, driver element 106 may provide signal 102A as conditioned signal 102B. Signals 102A and 102B may be differential signals and / or single-ended signals, and driver element 106 may be a differential driver element and / or a single-ended driver element.

[0019] In the differential example, a variable capacitor 108 is coupled between the differential outputs of a driver element 106 that provides the regulated signal 102B. A controller 110 can adjust the capacitance of the variable capacitor 108 to tune the gain of the integrated circuit device 100 based on the carrier frequency of the regulated signal 102B. Specifically, the integrated circuit device 100 can be configured to transmit the regulated signal 102B within one or more frequency bands (e.g., 2.4 GHz embodiment, 5 GHz embodiment, etc.) designated for wireless communication. These frequency bands (one or more) can be further subdivided into one or more channels, and the capacitance of the variable capacitor 108 can be set based on the channel and frequency band on which the regulated signal 102B is to be transmitted.

[0020] Driver element 106 can provide the regulated signal 102B to one of two different and independent power amplifier paths. In some examples, integrated circuit device 100 includes a first power amplifier path 112 that is enabled and used when the desired transmitter output power is above a threshold (e.g., within the higher portion of the output power range). In some such examples, integrated circuit device 100 also includes a second power amplifier path 114 coupled in parallel with the first power amplifier path 112 that is enabled and used when the desired transmitter output power is below a threshold (e.g., within the lower portion of the output power range).

[0021] Turning to the first power amplifier path 112, the integrated circuit device 100 may include a transformer 116 or other coupling circuitry having inputs coupled to a differential output of the driver element 106. A variable capacitor 108 may be coupled between the inputs of the transformer 116. The transformer 116 may include a first set of coils coupled to an input receiving a regulated signal 102B and a second set of coils inductively coupled to the first set of coils in response to the generation of a third signal 102C in response to the regulated signal 102B.

[0022] A second set of coils in transformer 116 can be coupled to the inputs of main power amplifier 118 (e.g., a pair of differential inputs) to provide a third signal 102C to main power amplifier 118. Main power amplifier 118 amplifies the third signal 102C to generate a fourth signal 102D for transmission. Main power amplifier 118 can be a differential amplifier and / or a single-ended amplifier, and in a differential example, capacitor 120 and / or balun 122 (e.g., transformer) are coupled in parallel between the outputs of the main power amplifier that generates the fourth signal 102D.

[0023] The balun 122 couples the main power amplifier 118 to the matching network 124. Similar to the transformer 116, the balun 122 may include a first coil receiving a fourth signal 102D and a second coil inductively coupled to the first coil to generate a fifth signal 102E in response to the fourth signal 102D. The second coil of the balun 122 is coupled to one or more parallel capacitors (e.g., capacitors 132 and 134) of the matching network 124 and to the antenna 104 for wireless transmission of the fifth signal 102E.

[0024] As described above, the first power amplifier path 112 can be used when the transmitter output power is within a given range. More specifically, the controller 110 determines a specified transmitter output power and enters a first mode when the controller 110 determines that the transmitter output power falls within the higher portion of the power range. The controller 110 can make these determinations based on any suitable signal, either internal or external to the integrated circuit 100. In some examples, the controller 110 determines the specified transmitter output power based on a signal strength indication provided by the receiving device.

[0025] In a first mode where the transmitter output power falls within the higher portion of the power range, controller 110 enables main power amplifier 118 and closes a set of switches in matching network 124 by sending an enable signal on the corresponding control line 139. The switches may include a first switch 126 coupled between a second coil of balun 122 and a first terminal of antenna 104, a second switch 128 coupled between a first capacitor 132 of matching network 124 and a first terminal of antenna 104, and a third switch 130 coupled between a second capacitor 134 of matching network 124 and a first terminal of antenna 104. The exact subset of closed switches 126-130 may vary based on the channel frequency. For example, for a first channel frequency, switches 126-130 may all be closed, while for a second channel frequency, switches 126 and 128 may be closed and switch 130 may be open. In some examples, when operating in the first mode, at least switches 126 and 128 may be closed. Therefore, in the first mode, the main power amplifier 118 sees the second coil of the balun 122 connected in parallel with the first capacitor 132 and, in some examples, with the second capacitor 134.

[0026] In the first mode, the controller can also use the set of control lines 139 to disable power amplifiers 136 and 138 of the second power amplifier path 114, which will be described in more detail below. The first terminal of antenna 104 can be further coupled to ground, and in the example where switches 126 and 128 are closed in the first mode, this can be used to ground the output of the final amplifier of the second power amplifier path 114.

[0027] The controller 110 can select a first mode based on the transmitter output power of the integrated circuit device 100 being in the higher part of the power range (e.g., between about 5 dBm and about 20 dBm). Therefore, the matching network 124 and the main power amplifier 118 enabled in the first mode can be optimized for efficiency in this part of the range.

[0028] However, it has been determined that in some examples, the main power amplifier 118 may become significantly inefficient as the controller 110 reduces the transmitter output power generated by the main power amplifier 118. For example, the controller 110 may reduce the bias current of the main power amplifier 118 to reduce the transmitter output power. However, the reduced bias current pushes the main power amplifier 118 further away from its most efficient saturation operating mode.

[0029] Furthermore, reducing the transmitter output power by decreasing the bias current may cause the main power amplifier 118 to operate in a linear mode, which can be both inefficient and overly sensitive to the conditions of the integrated circuit device 100. Small variations in process conditions can cause the performance of the components of the integrated circuit device 100 (such as the drive strength of the transistors constituting the power amplifier 118) to vary across the entire integrated circuit device 100. In turn, these drive strength and other process variations significantly affect the amplifier gain, which in turn causes variations in the transmitter output power across the device 100. When the specified transmitter output power is in the lower part of the power range, these design and other issues can be mitigated by using a second power amplifier path 114, allowing the main power amplifier 118 to avoid significant excursion into linear mode.

[0030] Turning now to the second power amplifier path 114, this path may include one or more power amplifier stages based on desired voltage gain and other design considerations. Thus, in the two-stage example, the second power amplifier path 114 includes a first-stage power amplifier 136, which is coupled in parallel with a variable capacitor 108 to the differential output of driver element 106. The first-stage power amplifier 136 receives a regulated signal 102B from the driver element and generates a sixth signal 102F in response to the regulated signal 102B. The first-stage power amplifier 136 may be configured to provide most of the voltage gain and isolate driver element 106 from subsequent stages. Although two are shown, other examples include a different number of power amplifier stages.

[0031] In the two-stage example, the second power amplifier path 114 includes a second-stage power amplifier 138 coupled to the first-stage power amplifier 136. The second-stage power amplifier 138 receives a sixth signal 102F from the first-stage power amplifier 136 and, when enabled, provides a fifth signal 102E to the matching network 124 in response to the sixth signal 102F.

[0032] The first-stage power amplifier 136 and the second-stage power amplifier 138 can be differential or single-ended. In some examples, the differential-mode first-stage power amplifier 136 and the differential-mode second-stage power amplifier 138 provide higher efficiency and increased saturation power than comparable single-ended amplifiers. In some examples, the differential-mode first-stage power amplifier 136 and the differential-mode second-stage power amplifier 138 exhibit reduced harmonics (e.g., second-order and larger even-order harmonics) in their outputs compared to single-ended amplifiers.

[0033] In the differential example, the first differential output of the second-stage power amplifier 138 is coupled to the first terminal of the antenna 104 via the first switch 126, and further coupled to the second coil of the balun 122, and thus coupled to the second terminal of the antenna 104. The second differential output of the second-stage power amplifier 138 is coupled to the first terminal of the antenna 104 via the second switch 128, and coupled to a capacitor (e.g., capacitor 132), which in turn is coupled to the second terminal of the antenna 104.

[0034] The second power amplifier path 114 can be used in a second operating mode, where the transmitter output power will be in the lower portion of the output power range (e.g., between approximately -10 dBm and approximately 5 dBm). The controller 110 can determine that the output power will fall within this lower range based on any suitable signal, either internal or external to the integrated circuit 100. In the second mode, the controller 110 enables power amplifiers 136 and 138 of the second power amplifier path 114 by providing an enable signal on the corresponding control line 139, and also disconnects some or all of the switch groups 126-130 in the matching network 124. In some examples, at least switches 126 and 128 are open when operating in the second mode. The controller can also disable the main power amplifier 118 using control line 139.

[0035] The second power amplifier path 114 can be configured to provide a lower output power than the first power amplifier path 112, and therefore, the power amplifiers 136 and 138 of the second power amplifier path 114 can be configured differently from the main power amplifier 118. Specifically, the power amplifiers 136 and 138 of the second power amplifier path 114 can be optimized for efficiency within this range. In some such examples, the power amplifiers 136 and 138 of the second power amplifier path 114 operate at a lower supply voltage than the main power amplifier 118 (e.g., about 1.2V compared to about 3V). In some such examples, the components (including transistors) of the power amplifiers 136 and 138 of the second power amplifier path 114 are smaller than their counterparts in the main power amplifier 118. In this and other ways, the power amplifiers 136 and 138 of the second power amplifier path 114 can be biased to operate more efficiently in the lower portion of the transmitter output power range. In some such examples, power amplifiers 136 and 138 of the second power amplifier path 114 are biased to operate in saturation mode at or near the upper limit of the lower output power range. For example, if the threshold is about 5 dBm, such that controller 110 enables the first power amplifier path 112 for transmitter output power above 5 dBm and enables the second power amplifier path 114 for output power below about 5 dBm, amplifiers 136 and 138 of the second power amplifier path 114 can be biased to operate in saturation mode at or near 5 dBm.

[0036] refer to Figure 2 The operation of the second power amplifier path 114 in the second mode is further described. Figure 2 This is a circuit diagram of a portion of an integrated circuit device 100 in a second operating mode, based on some examples. Specifically, Figure 2 The diagram illustrates the second-stage power amplifier 136 of the matching network 124, the balun 122, the antenna 104, and the first capacitor 132.

[0037] As mentioned above, some or all of switches 126-130 can be disconnected in the second mode. Therefore, in some examples, the matching network 124 in this mode can be modeled as the second coil of the balun 122 coupled between the first differential output of the second-stage power amplifier 138 and node 202. Capacitor 132 is effectively coupled between the second differential output of the second-stage power amplifier 138 and node 202, and antenna 104 is coupled between node 202 and ground. In this model, the voltage at node 202 can be determined by the following equation:

[0038]

[0039] Where v0 represents the voltage at node 202, v represents the single-ended voltage output by the second-stage power amplifier 138, Y1 represents the reciprocal (1 / X) of the impedance of the second coil of the balun 122, Y2 represents the reciprocal of the impedance of the capacitor 132, and G L This represents the reciprocal of the impedance of antenna 104.

[0040] In some examples, the maximum power transfer occurs when Y1 = –Y2, which happens at the resonant frequency of the matching network 124. However, in some examples, because the matching network is a low-Q network, the power and efficiency of the second power amplifier path 114 are not adversely affected even if there is some deviation between the resonant frequency of the matching network 124 and the carrier frequency of the regulated signal 102B.

[0041] exist Figure 1 and Figure 3 The operation of controller 110 is further described in the context of this description. Figure 3 This is a flowchart of method 300 for operating a wireless transmitter according to some examples. Some procedures of method 300 may be performed in a different order than described, and many procedures may be performed in parallel simultaneously. Furthermore, in some examples of this specification, procedures of method 300 may be omitted or substituted. Method 300 is suitable for execution by controller 110 or some other integrated circuit device.

[0042] The controller 110 or other integrated circuit device may perform the process of method 300 using any combination of dedicated hardware and instructions stored in a non-transitory medium. Therefore, the controller 110 may include a processing resource 140 coupled to the non-transitory computer-readable medium 142. The processing resource 140 may include one or more microcontrollers, ASICs, CPUs, GPUs, and / or other processing resources configured to execute instructions stored on the medium 142. Examples of suitable non-transitory computer-readable media 142 include one or more flash memory devices, battery-powered RAM, SSDs, HDDs, optical media, and / or other memory devices suitable for storing instructions for processing resource 140.

[0043] Referring to block 302, controller 110 determines a specified transmitter output power. The transmitter output power can be determined based on a wireless communication protocol or specification and / or any suitable signal, either internal or external to integrated circuit 100. In some examples, controller 110 determines the specified transmitter output power based on a signal strength indication provided by a receiving device and selects the transmitter output power to allow communication with minimal interference.

[0044] Referring to block 304, controller 110 determines whether a specified transmitter output power falls within the higher or lower portion of the power range. This may include determining whether the specified transmitter output power meets or exceeds a power threshold.

[0045] Reference block 306, when controller 110 determines that a specified output power falls within the higher portion of the power range, controller enables components of the first power amplifier path 112, such as the main power amplifier 118. This may include disabling components of the second power amplifier path 114 that are coupled in parallel with the first power amplifier path 112. Reference block 308, controller 110 sets the state of switches 126-130 of matching network 124 (e.g., closing switches 126-130) based on operating parameters of the main power amplifier 118, the carrier frequency of the signal to be transmitted, and / or other suitable considerations to optimize the frequency response of matching network 124.

[0046] Reference box 310, first power amplifier path 112 is used to transmit signals via antenna 104 at specified transmitter output power.

[0047] Conversely, when controller 110 determines in block 304 that the specified output power falls within the lower portion of the power range, method 300 proceeds to block 312, where the controller enables components of the second power amplifier path 114, such as the first-stage power amplifier 136 and the second-stage power amplifier 138. This may include disabling components of the first power amplifier path 112. Referring to block 314, controller 110 sets the state of switches 126-130 of matching network 124 (e.g., disconnects switches 126-130) based on operating parameters of the first-stage power amplifier 136, parameters of the second-stage power amplifier 138, the carrier frequency of the signal to be transmitted, and / or other suitable considerations to optimize the frequency response of matching network 124.

[0048] Reference box 316, first power amplifier path 112 is used to transmit signals via antenna 104 at specified transmitter output power.

[0049] This specification provides several exemplary embodiments, and modifications may be made to these embodiments. Such modifications are explicitly within the scope of this disclosure. Furthermore, applying these teachings to other environments, applications, and / or purposes consistent with and contemplated by this specification is also permitted.

Claims

1. An integrated circuit device, comprising: First amplifier path; A second amplifier path is coupled in parallel with the first amplifier path and has a first output and a second output; A balun includes a first coil and a second coil, the first coil being coupled to a first amplifier path, and the second coil being coupled to a first output and a second output of the second amplifier path; as well as A matching network, coupled to the balun, comprising: First capacitor and second capacitor; A first switch has a first terminal and a second terminal, the first terminal of the first switch being coupled to a first terminal of a second coil of the balun and a first output of the second amplifier path, and the second terminal of the first switch being coupled to a common node; A second switch having a first terminal and a second terminal, the first terminal of the second switch being coupled via the first capacitor to the second terminal of the second coil of the balun, and coupled to the second output of the second amplifier path; the second terminal of the second switch being coupled to the common node; and A third switch has a first terminal and a second terminal. The first terminal of the third switch is coupled to the second terminal of the second coil of the balun via the second capacitor, and is coupled to the first terminal of the second switch via the first capacitor and the second capacitor. The second terminal of the third switch is coupled to the common node.

2. The integrated circuit device according to claim 1, wherein: The first amplifier path includes a first differential power amplifier coupled to the first coil of the balun; and The second amplifier path includes a second differential power amplifier having a first output and a second output, which are coupled to the second coil of the balun and the matching network, respectively.

3. The integrated circuit device of claim 2, wherein the second amplifier path further includes a third differential power amplifier coupled to the differential input terminal of the second differential power amplifier.

4. The integrated circuit device of claim 3, further comprising a controller coupled to control the first amplifier path, the second amplifier path, and the matching network.

5. The integrated circuit device of claim 4, wherein the controller is configured to: Selectively enable the first amplifier path to provide transmitter output power within a first range; and The second amplifier path is selectively enabled to provide transmitter output power in a second range that is less than the first range.

6. The integrated circuit device according to claim 4, wherein: The controller is configured to set the state of the first switch, the second switch, and the third switch based on which of the first amplifier path and the second amplifier path is selectively enabled.

7. The integrated circuit device of claim 1, further comprising a driver element coupled to provide an input signal to each of the first amplifier path and the second amplifier path.

8. The integrated circuit device of claim 7, wherein the second amplifier path comprises: A first-stage power amplifier is coupled to receive the input signal from the driver element and generate a second signal in response to the input signal; and A second-stage power amplifier is coupled to receive the second signal from the first-stage power amplifier and generate a third signal in response to the second signal.

9. The integrated circuit device according to claim 7, further comprising: A variable capacitor coupled between the first and second outputs of the driver element.

10. The integrated circuit device according to claim 9, wherein: The controller is configured to adjust the variable capacitor to tune the gain of the integrated circuit.

11. The integrated circuit device according to claim 3, wherein: The second differential power amplifier generates the first voltage gain of the differential signal; The third differential power amplifier generates a second voltage gain for the differential signal; and The first voltage gain is greater than the second voltage gain.

12. The integrated circuit device according to claim 1, wherein: The first capacitor and the second capacitor are coupled in parallel.

13. The integrated circuit device according to claim 1, wherein: The matching network is a low-Q network.

14. The integrated circuit device according to claim 1, further comprising: The antenna is coupled to the matching network.

15. An integrated circuit, comprising: Processing resources; First amplifier path; The second amplifier path has a first output and a second output; A balun includes a first coil and a second coil, the first coil being coupled to a first amplifier path and the second coil being coupled to a second amplifier path; as well as A matching network, configured for use with the first amplifier path and the second amplifier path, comprises: A capacitor having a first end and a second end, the first end being coupled to a second terminal of a second coil of the balun; A first switch is configured to couple a first terminal of the second coil of the balun and a first output of the second amplifier path to a common node when the first switch is closed. A second switch is configured to couple a second terminal of the capacitor to the common node when the second switch is closed; and A third switch is configured to couple the second terminal of the second coil of the balun to the common node when the third switch is closed; and A non-transitory computer-readable medium coupled to the processing resource and storing instructions that, when executed by the processing resource, cause the processing resource to: Determine the transmitter output power; Based on a determined transmitter output power, selectively enable one of the first amplifier path and the second amplifier path; and The amplifier path selected from the first amplifier path and the second amplifier path transmits the signal according to the determined transmitter output power.

16. The integrated circuit according to claim 15, wherein: The instructions include additional instructions that cause the processing resources to control the state of the first switch, the second switch, and the third switch based on the transmitter output power.

17. The integrated circuit according to claim 15, wherein: The first amplifier path includes a first differential power amplifier; and The second amplifier path includes a second differential power amplifier.

18. The integrated circuit according to claim 17, wherein: The first coil of the balun is coupled to the first differential power amplifier; The second coil of the balun is coupled to the second differential power amplifier; and The matching network is configured to be coupled to the antenna.

19. The integrated circuit according to claim 17, wherein, The first amplifier path also includes a variable capacitor coupled to the input of the first differential power amplifier.

20. The integrated circuit according to claim 19, wherein: The instructions also include additional instructions for controlling the variable capacitor to tune the gain of the integrated circuit.

21. The integrated circuit according to claim 15, wherein: The capacitor is a first capacitor; and The matching network also includes a second capacitor coupled between a second terminal of the second coil of the balun and the third switch.

22. The integrated circuit according to claim 15, wherein: The matching network also includes an output coupled to a first terminal of the capacitor and a second terminal of a second coil of the balun, the output of which is configured to be coupled to an antenna.

23. The integrated circuit according to claim 15, further comprising: The driver circuit is configured to output a differential signal; as well as A variable capacitor is coupled between the first and second outputs of the driver circuit.

24. The integrated circuit according to claim 23, wherein: The instructions also include additional instructions that cause the processing resources to control the variable capacitor to tune the gain of the integrated circuit based on the carrier frequency of the differential signal.

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