Memory device, storage apparatus including the memory device, and method of operating the storage apparatus

Abstract

A method of operating a controller for controlling a memory device including a plurality of blocks of memory cells is provided. The method includes outputting block address information based on reliability information of each of the blocks of memory cells, providing a scrub read command to the memory device, and controlling the memory device to perform a scrub read operation in response to the scrub read command, wherein the block address information includes an order of the scrub read operation for the blocks of memory cells based on the reliability information.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0132979, filed with the Korean Intellectual Property Office on October 14, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to storage devices, and more particularly to storage devices, storage devices including storage devices, and methods of operating storage devices. Background Technology

[0004] As a non-volatile memory, flash memory retains stored data even when power is off. Recently, storage devices, including those using flash memory such as embedded multimedia cards (eMMC), universal flash memory (UFS), solid-state drives (SSDs), and memory cards, have become widely used and are extremely useful for storing or transferring large amounts of data. Therefore, the demand for methods and devices to improve the reliability of storage devices continues to grow. Summary of the Invention

[0005] The present invention provides a storage device that can improve the reliability of a storage device including the storage device, a storage device including the storage device, and a method for operating the storage device.

[0006] According to one aspect of the present invention, a method for operating a controller for controlling a storage device including a plurality of memory cell blocks may include: outputting block address information based on reliability information of each of the memory cell blocks; providing a patrol read command to the storage device; and controlling the storage device to perform a patrol read operation in response to the patrol read command, wherein the block address information includes the order of patrol read operations for the memory cell blocks based on the reliability information.

[0007] According to another aspect of the present invention, a method of operating a storage device including a storage device configured to perform a patrol read operation may include: controlling the storage device by providing block address information to the storage device based on patrol read commands and reliability information of each of a plurality of storage cell blocks; and generating information relating to a target block for reclamation in the storage cell block for which a reclamation operation is to be performed, wherein the block address information includes the order of patrol read operations for the storage cell block based on the reliability information.

[0008] According to another aspect of the present invention, a controller for a storage device may include: at least one processor configured to: generate a patrol read command in response to a patrol read instruction; generate block address information based on reliability information of each of a plurality of storage cell blocks included in the storage device; and provide the patrol read command and the block address information to the storage device, wherein the block address information includes the order of patrol read operations for the storage cell blocks based on the reliability information.

[0009] According to another aspect of the present invention, a storage device may include: a storage device comprising a plurality of storage cell blocks and configured to generate information relating to a target block for which a reclamation operation is to be performed based on a traverse read operation for each storage cell block; and a controller configured to provide block address information to the storage device based on traverse read commands and reliability information for each of the storage cell blocks, wherein the block address information includes the order of the traverse read operations for the storage cell blocks based on the reliability information. Attached Figure Description

[0010] Example embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating an exemplary embodiment of a storage system according to a concept of the present invention;

[0012] Figure 2 This is a block diagram showing in more detail the controller included in the storage device according to an example embodiment;

[0013] Figure 3 This is a block diagram showing in more detail the storage devices included in the storage device according to an example embodiment;

[0014] Figure 4 This is an equivalent circuit diagram of a memory cell block of a memory cell array included in a memory device according to an example embodiment;

[0015] Figure 5 It is a graph showing the threshold voltage distribution of a degraded memory cell according to an example embodiment;

[0016] Figure 6 This is a flowchart of a method for operating a controller according to an exemplary embodiment of the present invention;

[0017] Figure 7 This is a table showing reliability information about storage cell blocks according to an example embodiment;

[0018] Figure 8A and Figure 8BThis is a table illustrating the priority of performing patrol read operations based on reliability information in some example embodiments of the present invention;

[0019] Figure 9 This is a block diagram representing a storage device that receives block address information according to priority;

[0020] Figure 10 This is a flowchart of a method for updating reliability information each time the idle mode is entered according to an example embodiment;

[0021] Figure 11 This is a timing diagram of the method for updating reliability information each time the system enters idle mode;

[0022] Figure 12 This is a flowchart of a method for determining which of the retention time and the program-erase count will be used as information for updating reliability information each time the idle mode is entered.

[0023] Figure 13 This is a flowchart illustrating an operational method of a storage system for generating block address information according to an example embodiment; and

[0024] Figure 14 This is a flowchart of an operation method for a storage system that generates block address information according to an example embodiment. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating an example embodiment of a storage system according to a concept of the present invention.

[0026] Storage system 10 can be implemented as, for example, a personal computer (PC), a data server, a network attached storage device (NAS), an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices can be laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio equipment, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game consoles, e-book devices, wearable devices, etc.

[0027] Storage system 10 may include storage device 200 and host 100. Host 100 may control the operation of storage device 200, and host 100 may include host controller 110 and host memory 120. Host memory 120 may be used as a buffer memory for temporarily storing data to be sent to or from storage device 200. In an example embodiment, storage device 200 may include one or more solid-state drives (SSDs). When storage device 200 includes SSDs, storage device 200 may include multiple flash memory chips (e.g., NAND flash memory devices) for storing data.

[0028] Storage device 200 may correspond to a flash memory device including one or more flash memory devices. In an example embodiment, storage device 200 may be an embedded memory included in storage system 10. For example, storage device 200 may be an embedded multimedia card (eMMC) or an embedded universal flash memory (UFS) storage device. In an example embodiment, storage device 200 may be an external memory detachably attached to storage system 10. For example, storage device 200 may be a UFS memory card, a compact flash (CF) card, a secure digital card (SD) card, a micro secure digital card (SD) card, a mini secure digital card (SD) card, an ultra-fast digital card (XD) card, or a memory stick.

[0029] refer to Figure 1 Storage device 200 may include storage controller 210 and storage device 220. Host 100 can communicate with storage device 200 through various interfaces and can send requests such as read requests and programming requests to storage device 200. In example embodiments, host 100 may be implemented as an application processor (AP) or a system-on-a-chip (SoC).

[0030] Storage controller 210 can control the operation of storage device 220 through at least one channel. Storage controller 210 can control storage device 220 to read data DATA stored in storage device 220 in response to a read request from host 100, or to program data DATA into storage device 220 in response to a programming request from host 100.

[0031] When a patrol read event occurs, the storage controller 210 can perform a patrol read operation by controlling the storage device 220. A patrol read event may include receiving a patrol read instruction from the host 100. However, exemplary embodiments of the inventive concept are not limited thereto, and patrol read events may include background events executed when entering an idle mode. A patrol read operation is an example of defensive code operations performed to find a target block to be reclaimed from a plurality of storage cell blocks, and may include, for example, determining whether a corresponding cell block is a target storage cell to be reclaimed based on the read level read from each storage cell. In this case, the reclamation operation refers to the operation of reusing the source storage area by moving data in the source storage area to another destination storage area and erasing the data in the source storage area. For example, valid data stored in the source storage area can be read, and the read valid data can be programmed into another destination storage area. Therefore, the address corresponding to the valid data in the mapping table can be changed from the address in the source storage area to the address in the destination storage area.

[0032] Reference Figure 1 The storage controller 210 may include a host interface 211, a memory interface 212, a command generator 213, and an address generator 214. The storage controller 210 can receive operation command signals from the host 100 through the host interface 211, and generate command and address information based on the operation command signals using the command generator 213 and the address generator 214. The memory interface 212 of the storage controller 210 can provide the generated command and address information to the storage device 220.

[0033] According to an example embodiment, when a patrol read instruction is received from the host 100, the command generator 213 of the storage controller 210 can generate a patrol read command in response to the patrol read instruction and provide it to the storage device 220. Furthermore, the address generator 214 can determine the priority of the block for performing the patrol read operation based on the reliability information of the storage cell blocks, and provide the block address information of the storage cell blocks to the storage device 220 according to the priority order. For example, the address generator 214 can determine the priority for performing the patrol read operation by following the ascending order of the reliability of the determined storage cell blocks to output the block address information. Since the address generator 214 provides the block address information corresponding to the storage cell blocks to the storage device 220 according to the priority, the storage device 220 can perform the patrol read operation according to the priority order and provide the recycling target block information for performing the recycling operation to the storage controller 210 based on the same order (e.g., priority order). Therefore, in response to an instruction from the host 100 to perform a recycling operation, the storage controller 210 can perform a recycling operation on the storage cell block corresponding to the recycling target block information.

[0034] The non-volatile memory of storage device 200 may include flash memory, which may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. In another example, storage device 200 may include a variety of other types of non-volatile memory. For example, storage device 200 may include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, and a variety of other types of memory.

[0035] Compared to a comparative example where random inspection read operations are performed on storage cell blocks, the storage device 200 according to the present invention can more effectively mitigate or prevent performance degradation by performing inspection read operations primarily on storage cell blocks corresponding to factors with poor reliability.

[0036] Figure 2 This is a block diagram showing in more detail a storage controller included in a storage device according to an example embodiment.

[0037] Reference Figure 1 and Figure 2 The storage controller 210 may include a host interface 211, a memory interface 212, and a central processing unit (CPU) 215. Furthermore, the storage controller 210 may also include a flash translation layer (FTL) 216, a packet manager 217, a buffer memory 218, an error correction code (ECC) engine 219a, and an Advanced Encryption Standard (AES) engine 219b. The storage controller 210 may also include working memory (not shown) that loads the FTL 216, and when the CPU 215 executes the FTL 216, it can control the operations of programming data to and reading data from the non-volatile memory.

[0038] Host interface 211 can send and receive data packets to host 100. Data packets sent from host 100 to host interface 211 may include commands or data to be programmed into storage device 220, and data packets sent from host interface 211 to host 100 may include responses to commands or data read from storage device 220. Memory interface 212 can send data to be programmed into storage device 220 or receive data to be read from storage device 220. Memory interface 212 may be implemented to conform to standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0039] Command generator 213 can generate a patrol read command in response to a patrol read command, and can generate a read command in response to a read command or a programming command in response to a read command or a programming command in response to a read command or a programming command in response to a program command from the host 100. However, the command generator 213 of the present invention is not limited thereto, and the command generator 213 can also generate commands including erase commands and reclaim commands.

[0040] Address generator 214 can generate block address information corresponding to each memory cell block of storage device 220, and according to an example embodiment of the present invention, the block address information can be generated based on reliability information in the order in which the inspection read operations are performed. Reliability information is information related to the expected value of the degradation of the memory cell block, and can be information determined based on lifespan variables related to product degradation over time, environmental variables due to poor environments, and performance-related characteristic variables. For example, reliability information can be information determined based on retention information and durability information; retention information can be determined based on retention time, and durability information can be determined based on program-erase counts. In other words, reliability information can be determined based on retention time and program-erase counts. According to an example embodiment, retention information can be information about how long electrons can remain at the level of information in the floating gate (FG) to be used as each memory cell. Durability information can be information related to the number of repetitions of programming and erasing operations. For example, when electrons are stored in the FG for a long time and programming and erasing are repeated many times, the reliability of the corresponding memory cell can be determined to be low.

[0041] FTL 216 can perform various functions, such as address mapping, wear leveling, and garbage collection. Address mapping is used to translate logical addresses received from the host into physical addresses for actually storing data in storage device 220. Wear leveling is a technique that prevents excessive degradation of specific blocks by allowing blocks in storage device 220 to be used evenly, and can be implemented, for example, through firmware techniques used to balance the erase counts of physical blocks. Garbage collection is a technique that ensures available capacity in storage device 220 by copying valid data from blocks to new blocks and then erasing the old blocks. Packet manager 217 can generate packets according to an interface protocol consistent with host 100, or can parse various information from packets received from host 100.

[0042] Furthermore, buffer memory 218 can temporarily store data to be programmed into storage device 220 or data to be read from storage device 220. Buffer memory 218 can be a component disposed in storage controller 210, but it can also be disposed outside storage controller 210. According to an exemplary embodiment of the present invention, buffer memory 218 can store at least one of retention time or program-erase count corresponding to each memory cell block, and can provide information corresponding to each memory cell block to address generator 214 upon request.

[0043] ECC engine 219a can detect and correct errors in read data from storage device 220. For example, ECC engine 219a can generate parity bits associated with programming data to be programmed into storage device 220, and such parity bits can be stored in storage device 220 along with the programming data. When reading data from storage device 220, ECC engine 219a can use the parity bits read from storage device 220 along with the read data to correct errors in the read data and output the error-corrected read data. AES engine 219b can use a symmetric key algorithm to perform at least one of encryption or decryption operations on data input to storage controller 210.

[0044] Various elements of the storage controller 210 (e.g., CPU 125, command generator 213, FTL 216, packet manager 217, address generator 214, ECC engine 219a, and AES 219b) can be implemented as processing circuitry (e.g., at least one processor), such as hardware or hardware / software combinations including logic circuitry (e.g., a processor executing software). For example, the processing circuitry or processor may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Therefore, the various elements of the storage controller 210 can be functional representations related to the various functions performed by the storage controller 210.

[0045] Figure 3 This is a block diagram showing in more detail the storage devices included in the storage device according to an example embodiment.

[0046] refer to Figure 1 and Figure 3 The storage device 220 may include a memory cell array 222, an address decoder 223, a control logic block 224, a page buffer 225, an input / output circuit 226, and a voltage generator 227. Although not shown, the storage device 220 may also include an input / output interface.

[0047] The memory cell array 222 can be connected to the word line WL, the serial select line SSL, the ground select line GSL, and the bit line BL. The memory cell array 222 can be connected to the address decoder 223 via the word line WL, the serial select line SSL, and the ground select line GSL, and can also be connected to the page buffer 225 via the bit line BL. The memory cell array 222 can include multiple memory blocks BLK1 to BLKn.

[0048] Each of the memory blocks BLK1 to BLKn may include multiple memory cells and multiple select transistors. The memory cells may be connected to the word line WL, and the select transistors may be connected to the serial select line SSL or the ground select line GSL. Each memory cell in memory blocks BLK1 to BLKn may be a single-level cell (SLC) storing 1 bit of data or a multi-level cell (MLC) storing 2 or more bits of data. However, the inventive concept is not limited thereto; the memory cells may also be three-level cells (TLC) and four-level cells (QLC).

[0049] Storage blocks BLK1 to BLKn may each include multiple pages PG1 to PGm. Each of pages PG1 to PGm may correspond to a unit in a storage block used for programming or reading data. In an example embodiment, the storage cells included in each of pages PG1 to PGm may be connected to the same word line.

[0050] Address decoder 223 can select one of the multiple storage blocks BLK1 to BLKn of storage cell array 222, select one of the word lines WL of the selected storage block, and select one of the serial selection lines SSL.

[0051] Control logic block 224 (or control logic circuit) can output various control signals for performing programming, reading, and erasing operations on memory cell array 222 based on command CMD, address ADDR, and control signal CTRL. Control logic block 224 can provide row address X-ADDR to address decoder 223, column address Y-ADDR to page buffer 225, and voltage control signal CTRL_Vol to voltage generator 227.

[0052] Control logic block 224 can perform erase operations on each of the storage blocks BLK1 to BLKn. Control logic block 224 can perform read and program operations on each of the pages PG1 to PGm.

[0053] In the example embodiment, control logic block 224 can perform a patrol read operation on each of the storage blocks BLK1 to BLKn. For example, control logic block 224 can receive a series of block address information corresponding to each storage unit block, and perform patrol read operations on the corresponding storage unit blocks in the order in which the block address information is received. For example, when control logic block 224 sequentially receives block address information corresponding to the first, second, and third storage unit blocks, it can perform patrol read operations in the order of the first, second, and third storage unit blocks.

[0054] Depending on the operating mode, page buffer 225 can operate as a programming driver or a sense amplifier. During a read operation, page buffer 225 can sense the bit line BL of the selected memory cell under the control of control logic block 224. The sensed data can be stored in a latch provided in page buffer 225. Page buffer 225 can also dump the data stored in the latch to input / output circuit 226 under the control of control logic block 224.

[0055] The input / output circuit 226 can temporarily store commands CMD, addresses ADDR, control signals CTRL, and data DATA provided from the external storage device 220 via input / output lines I / O. The input / output circuit 226 can also temporarily store read data from the storage device 220 and output the read data to the external storage device via input / output lines I / O at specified times.

[0056] Voltage generator 227 can generate various types of voltages for performing programming, reading, and erasing operations on memory cell array 222 based on the voltage control signal CTRL_vol. For example, voltage generator 227 can generate word line voltages VWL, such as programming voltage, read voltage, pass voltage, erase verification voltage, or programming verification voltage. Furthermore, voltage generator 227 can generate serial select line voltage and ground select line voltage based on the voltage control signal CTRL_Vol. Additionally, voltage generator 227 can generate the erase voltage to be supplied to memory cell array 222.

[0057] Figure 4 This is an equivalent circuit diagram of a memory cell block of a memory cell array included in a memory device according to an example embodiment.

[0058] Figure 4 This is an equivalent circuit diagram of a vertical NAND flash memory device with a vertical channel structure formed on a substrate. (Refer to...) Figure 4The memory block BLK included in the memory cell array can include multiple memory cell strings MS. The memory block BLK can include: multiple bit lines BL, BL1 to BLk; multiple word lines WL, WL1 to WLm; multiple string select lines SSL, SSL1 to SSLk; at least one ground select line GSL; and a common source line CSL. Multiple memory cell strings MS can be formed between the bit lines BL (BL1 to BLk) and the common source line CSL.

[0059] Each memory cell string MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cells MC1 to MCm. The drain region of the string select transistor SST may be connected to the bit line BL, and the source region of the ground select transistor GST may be connected to the common source line CSL. The common source line CSL may be the region to which the source regions of multiple ground select transistors GST are commonly connected.

[0060] To be controlled independently, the string select transistors (SSTs) included in the memory cell string (MS) can be connected to different string select lines. For example, the string select transistors (SSTs) can be connected to one of the string select lines (e.g., one of SSL1, SSL2, and SSL3).

[0061] The ground select transistor GST can be connected to the ground select line GSL. In the example embodiment, the different ground select transistors GST included in the memory cell string MS of the memory block BLK can be connected to the same ground select line GSL. However, the inventive concept is not limited to this, and different ground select transistors GST can be connected to different ground select lines GSL respectively.

[0062] The memory cells MC1 to MCm constituting the memory cell string MS in the memory block BLK can have a structure in which they are connected in series in the Z-axis direction perpendicular to the main surface of the substrate. In the memory block BLK, the word line WL can extend in the X-axis direction, and the bit line BL can extend in the Y-axis direction.

[0063] Storage cells MC1 to MCm can be connected to word lines WL, respectively. Each of storage cells MC1 to MCm can store one bit of data or two or more bits of data. In an example embodiment, some of the storage cells MC1 to MCm can be SLCs, while others can be MLCs. For example, in storage cells MC1 to MCm, the first storage cell MC1, formed at the bottom layer and connected to the first word line WL1, can be an SLC. Furthermore, for example, in storage cells MC1 to MCm, the m-th storage cell MCm, formed at the top layer and connected to the m-th word line WLm, can be an SLC. The top and bottom layer storage cells (e.g., the first storage cell MC1 and the m-th storage cell MCm) in storage cells MC1 to MCm can be formed as SLCs, thereby improving data reliability.

[0064] Within the memory cell string MS, programming and reading operations can be performed page by page. A page can be a row of memory cells connected to a word line. Memory cells MC1 to MCm can be selected page by page by each word line WL.

[0065] Figure 5 It is a graph showing the threshold voltage distribution of a degraded memory cell according to an example embodiment.

[0066] Reference Figure 5 The distribution shape of the multiple memory cells connected to the word line can be changed from the initial distribution 50 to a modified distribution 51 due to variations. In both the initial distribution 50 and the modified distribution 51, the horizontal axis can represent the threshold voltage Vth, and the vertical axis can represent the number of memory cells MC. In other words, the initial distribution 50 and the modified distribution 51 can respectively represent the distribution of memory cells according to the threshold voltage Vth.

[0067] The initial distribution 50 can be a distribution of memory cells immediately following a programming operation on a memory cell or within a desired (or alternatively, predetermined) time period after the programming operation is completed. According to an example embodiment, the control logic can determine multiple default read voltage levels RL1 to RL7 for each programming state P1 to P7 based on each valley between two adjacent programming states. For example, the control logic can determine a first default read voltage level RL1 based on the valley between the erase state E and the first programming state P1. Furthermore, the control logic can determine a seventh default read voltage level RL7 based on the valley between the sixth programming state P6 and the seventh programming state P7.

[0068] The modified distribution 51 can be the distribution of the memory cells after a desired (or alternatively, predetermined) time following a programming operation of the memory cell. Memory cells programmed to erase state E and first programming states P1 through seventh programming states P7, respectively, can have the modified distribution 51, wherein the threshold voltage changes due to external stimuli or wear compared to the initial distribution 50. For example, as time passes after a programming operation, i.e., as the retention time increases, charge stored in the charge trapping layer of the memory cell may leak to the substrate, thus potentially decreasing the threshold voltage of the memory cell. In another example, the threshold voltage of the memory cell may increase due to a read interruption caused by a read operation of an adjacent memory cell. In yet another example, the threshold voltage of the memory cell may change due to the temperature difference between the programming and read operations.

[0069] Retention time is the time elapsed at high or room temperature after a programming operation is performed on a memory cell, and it can also be referred to as data retention time. As retention time increases, charge loss within the memory cell increases, and the charge loss rate may vary from one word line to another. Specifically, due to various phenomena such as time-varying rearrangements, channel region loss, and electron transfer through the charge trapping layer, the number of electrons trapped in the charge trapping layer by the programming operation may decrease. Therefore, the threshold voltage of the memory cell decreases, and as a result, the distribution may droop and expand depending on the threshold voltage of the memory cell. The amount of threshold voltage reduction may vary from one word line to another.

[0070] A read interruption refers to the phenomenon where the distribution of memory cells connected to adjacent word lines changes as a result of a read operation on a memory cell connected to the selected word line. For example, when a programming state corresponding to a high threshold voltage is programmed to a memory cell connected to the selected word line, the threshold voltage of the memory cells connected to adjacent word lines may increase, where the amount of the increase in threshold voltage varies from one word line to another depending on the distance from the selected word line.

[0071] For example, the threshold voltage of memory cells programmed into erase state E and first programming state P1 can be reduced, so the valley between erase state E and first programming state P1 can be shifted in the negative direction. Therefore, when a read operation is performed using the first default read voltage level RL1, read errors may occur for some memory cells programmed into first programming state P1. Here, a read error can correspond to the following situation: the number of invalid bits in the read data is equal to or greater than the ECC-correctable reference number. In this case, the read error can be eliminated by changing the optimal read voltage of first programming state P1 to a first corrected read voltage level corresponding to the valley of the offset between erase state E and first programming state P1.

[0072] The above describes read errors occurring on the same word line according to the initial distribution 50 and the modified distribution 51 due to increased retention time or temperature differences during programming / reading of adjacent memory cells. However, although data in memory cells needs to be read at different actual read voltage levels for word lines connected to different chips or blocks due to process differences, read errors can still occur even when reading memory cells of different chips or blocks at a preset default read voltage level.

[0073] Therefore, according to an exemplary embodiment of the present invention, a patrol read operation is performed on each memory cell block to determine whether the read voltage level of the corresponding memory cell block has shifted, wherein the patrol read operation can be performed according to a priority determined based on reliability information.

[0074] Figure 6 This is a flowchart of a method for operating the storage controller 210 according to an exemplary embodiment of the present invention.

[0075] Reference Figure 6 The storage controller 210 can receive target block information for reclamation by providing a patrol read command and block address information of the storage cell block to perform a patrol read operation on the storage device 220. In operation S10, when a request to perform a patrol read operation is received from the host 100 or when the storage device 200 is detected to have entered an idle mode, the storage controller 210 can output a patrol read command. For example, in response to the storage device 200 entering an idle mode, the storage controller 210 can provide a patrol read command to the storage device 220. The idle mode can be a mode corresponding to the standby mode of the storage device 200, in which the storage device 200 is available but not actually operated. By performing a patrol read operation in response to the storage device 200 entering an idle mode, optimized storage cell reclamation operations can be performed even when operations for programming, reading, or erasing data are not being performed.

[0076] In operation S20, the storage controller 210 can output block address information for performing a patrol read operation in an order determined based on reliability information. The reliability information relates to the reliability of the data stored in the storage cell, and the reliability of the data can be related to whether the logic level of the data programmed when the threshold voltage level of the corresponding storage cell deviates. Therefore, for example, since the threshold voltage value of a storage cell that was programmed with data a long time ago is likely to deviate, the storage device 200 can determine that the reliability of the storage cell block, including that corresponding storage cell, is low.

[0077] According to an exemplary embodiment of the present invention, the storage controller 210 can set the priority of storage cell blocks by performing patrol read operations in ascending order of reliability based on reliability information. Therefore, the storage controller 210 can set the priority of performing patrol read operations on storage cell blocks based on reliability information, thus performing patrol read operations more efficiently compared to a comparative example of randomly performing patrol read operations on storage cell blocks.

[0078] In operation S30, as a result of performing the inspection read operation, the storage controller 210 can receive reclaimable target block information related to whether the corresponding storage cell block is a reclaimable target block to be reclaimed. The storage controller 210 can receive the reclaimable target block information and store it in the page buffer, and in response to a request to perform a reclaim operation, the storage controller 210 can load the reclaimable target block information from the page buffer and perform the reclaim operation.

[0079] Figure 7 This is a table showing reliability information related to storage cell blocks according to an example embodiment.

[0080] Reference Figure 7 Storage device 200 may store at least one of the program-erase count (PE#) or retention time for each storage cell block as reliability information related to the corresponding storage cell block. According to an example embodiment, storage device 220 may manage a portion of the area used for storing data as a user area for storing user data, and manage at least a portion of the remaining area used for storing data, excluding the user area, as a meta-area for storing information related to the storage cell block, wherein storage device 220 may store reliability information in the meta-area. However, the inventive concept is not limited thereto; the reliability information may be stored in the page buffer of storage controller 210.

[0081] Reference Figure 7 Storage device 200 can store the retention times of nine memory blocks in the most recently programmed order PG. The most recently programmed order PG can be the order in which data has been programmed into the corresponding memory block most recently, and the earliest most recently programmed order PG can indicate the longest time elapsed since the data was written. Storage device 200 can determine the most recently programmed order PG of each memory block by counting the number of programming cycles after the latest data has been programmed.

[0082] For example, according to Figure 7Because the most recently programmed (PG) order of the first memory cell block BLK1 is the earliest and the most recently programmed (PG) order of the eighth memory cell block BLK8 is the latest, the reliability information indicates that among the nine memory cell blocks, the longest time has elapsed since the latest data was programmed to the first memory cell block BLK1, and the shortest time has elapsed since the latest data was programmed to the eighth memory cell block BLK8. In other words, since the retention time of the first memory cell block BLK1 is the longest and the retention time of the eighth memory cell block BLK8 is the shortest, the reliability of the first memory cell block BLK1 may be lower than that of the eighth memory cell block BLK8.

[0083] Furthermore, storage device 200 can store a program-erase count PE# for each storage cell block. Storage device 200 can generate a program-erase count PE# based on the number of times the program-erase cycle has been repeated, by counting the programming and erasure of data in the storage cell block as a single count after the data is initially programmed into the corresponding storage cell block.

[0084] Because the charge carriers in the floating gate have the characteristic of returning to a stable state when they are in an unstable state, when the memory device 220 is in a programming state for a long time, such as Figure 5 As shown, the distribution of erased states is shifted to the right and the distribution of programmed states is shifted to the left, therefore the retention time in the reliability information can be highly correlated with the reliability of the data. Furthermore, with the increase in the number of programming and erasing operations, the tunnel oxide of the memory cells deteriorates, and the performance of programming and erasing may also deteriorate. Therefore, even when performing programming or erasing operations, memory cell blocks that have been programmed and erased multiple times may have low reliability due to low electron mobility.

[0085] In an exemplary embodiment of the present invention, retention time and program-erase count (PE#) are used as examples of reliability information factors affecting the reliability of memory cell blocks. However, the present invention is not limited thereto, and the storage device 200 may utilize information relating to at least some of lifetime variables, environmental variables, and performance-related characteristic variables as factors of reliability information.

[0086] Figure 8A and Figure 8B This is a table illustrating the priority of performing patrol read operations based on reliability information in some example embodiments of the present invention.

[0087] Reference Figure 8AThe storage device 200 can determine the priority for outputting block address information based on the program-erase count PE#. For example, the seventh storage cell block BLK7 has a program-erase count PE# of 210, and it has been programmed and erased the most times among the nine storage cell blocks. On the other hand, the ninth storage cell block BLK9 has a program-erase count PE# of 10, and it has been programmed and erased the fewest times among the nine storage cell blocks. Therefore, since the reliability of the seventh storage cell block BLK7 is likely the lowest, and the reliability of the ninth storage cell block BLK9 is likely the highest, the storage device 200 can set the highest priority for the seventh storage cell block BLK7 and the lowest priority for the ninth storage cell block BLK9 when performing a patrol read operation. In other words, the storage controller 210 can output the block address information related to the seventh storage cell block BLK7 first along with the patrol read command, and can output the block address information related to the ninth storage cell block BLK9 last.

[0088] Reference Figure 8B The storage device 200 can determine the priority for outputting block address information based on the most recently programmed order (PG). For example, the most recently programmed order (PG) of the first storage cell block BLK1 can be first. In other words, among the nine storage cell blocks, the first storage cell block BLK1 may have the longest retention time since the latest data was programmed. Conversely, the eighth storage cell block BLK8 may have the shortest retention time since the latest data was programmed. Therefore, since the reliability of the first storage cell block BLK1 may be the lowest, and the reliability of the eighth storage cell block BLK8 may be the highest, the storage device 200 can set the highest priority for the first storage cell block BLK1 and the lowest priority for the eighth storage cell block BLK8 when performing a traversal read operation. In other words, the storage controller 210 can first output the block address information related to the first storage cell block BLK1 along with the inspection read command, and can finally output the block address information related to the eighth storage cell block BLK8.

[0089] Figure 9 This is a block diagram showing a storage device 220 that receives block address information according to priority.

[0090] Reference Figure 9The storage device 220 can receive a patrol read command CMD and a series of block address information ADDR_Q corresponding to a memory cell block, and can perform patrol read operations on the memory cell blocks corresponding to the series of block address information ADDR_Q respectively. The series of block address information ADDR_Q can be based on... Figure 8A and Figure 8B The block address information is arranged in priority order based on any one of the tables in the table. When the storage device 220 is based on... Figure 8A When receiving a series of block address information ADDR_Q according to the priority determined by the table, the storage device 220 can receive the block address information corresponding to blocks 7, 4, 5, 8, 6, 3, 2, 1 and 9 in the described order.

[0091] The control logic block 224 of storage device 220 can select a memory cell block for a round-robin read operation based on the received block address information, and provide the row address X_ADDR of the selected memory cell block to the address decoder 223 and the column address Y_ADDR to the page buffer 225. The address decoder 223, upon receiving the row address X_ADDR, can apply a voltage for performing the round-robin read operation to the serial select line SSL, word line WL, and ground select line GSL included in the selected memory cell block. Furthermore, the page buffer 225, upon receiving the column address Y_ADDR, can apply a voltage for performing the round-robin read operation to the bit lines included in the selected memory cell block. Storage device 220 can determine whether the selected memory cell block is one that needs to be reclaimed by performing a round-robin read operation on it, and can provide the determination result to the storage controller 210 or the host 100.

[0092] Figure 10 and Figure 11 This is a diagram illustrating a method for updating reliability information according to an example embodiment. Figure 10 This is a flowchart of the method for updating reliability information. Figure 11 This is a timing diagram of the method for updating reliability information. Please note that the timing diagram provided here is not necessarily drawn to scale.

[0093] Reference Figure 10 Storage device 200 can determine, based on information used when generating previous reliability information, which of the retention time and program-erase count to use to generate the reliability information. In other words, as in Figure 11 In an example embodiment, the storage device 200 of the present invention may alternately use retention time and program-erase count to generate reliability information.

[0094] In operation S210, storage device 200 can determine whether the previous reliability information was generated based on the retention time. In operation S220, when it is determined that the previous reliability information was generated based on the retention time, storage device 200 can generate reliability information based on the program-erase count. Otherwise, in operation S230, when it is determined that the previous reliability information was not generated based on the retention time, and for example, based on the program-erase count, storage device 200 can update the reliability information based on the retention time. In other words, according to... Figure 10 In an example embodiment, when periodically performing a patrol read operation, the storage device 200 can generate reliability information based on the program-erase count in the 2nth round (n is a natural number) and generate reliability information based on the retention time in the 2n+1th round.

[0095] In operation S240, storage device 200 can determine the priority of patrol read operations for storage cell blocks based on reliability information. For example, when storage device 200 generates reliability information based on retention time, the priority of patrol read operations can be determined in descending order of retention time for storage cell blocks. When storage device 200 generates reliability information based on program-erase counts, the priority of patrol read operations can be determined in descending order of program-erase counts for storage cell blocks. (The above has been referenced.) Figure 8A and Figure 8B An example embodiment of the storage device 200 for determining priority is described, and therefore its detailed description will be omitted.

[0096] In operation S250, storage device 200 can generate block address information according to a determined priority and output the block address information to storage device 220. After receiving the block address information and the patrol read command, storage device 220 can perform a patrol read operation on the storage cell block corresponding to the block address information, and in operation S30, storage device 200 can determine whether the storage cell block to which the patrol read operation is performed is a target block for reclamation.

[0097] according to Figure 10 In this embodiment, because the storage device 200 can generate reliability information based on information other than the information used to generate previous reliability information, the storage device 200 can effectively perform a patrol read operation.

[0098] Reference Figure 11 When storage device 200 according to Figure 10 When performing a patrol read operation, the embodiment can receive information related to retention time or program-erase count to update reliability information. Figure 11The time points T1 to T4 can indicate the time when the storage device 200 enters the idle mode. The storage device 200 can receive reliability information based on the program-erase count at time point T1, and can receive reliability information based on the retention time at time point T2. In other words, the storage device 200 can update the reliability information based on information different from the information used to enter the previous idle mode.

[0099] Figure 12 This is a flowchart illustrating a method for determining which of the retention time and the program-erase count will be used as information for updating reliability information each time the system enters idle mode.

[0100] Reference Figure 12 When storage device 200 determines the priority of performing patrol read operations on storage cell blocks, it can determine which of the retention time and program-erase count will be given higher weight based on the remaining lifetime and the ratio of cold cell blocks. The weight can indicate the frequency of use of retention time and program-erase count in multiple reliability information updates when storage device 200 is operating and performing multiple patrol read operations. However, the inventive concept is not limited to this; the weight can also indicate the degree to which retention time and program-erase count are reflected in a single reliability information generation.

[0101] In operation S211, storage device 200 can determine whether its remaining lifetime is less than a threshold. The remaining lifetime of storage device 200 can be obtained by subtracting the operating time from the expected lifetime of storage device 200. The shorter the remaining lifetime, the longer storage device 200 may have been operating. Therefore, the shorter the remaining lifetime, the higher the proportion of storage cell blocks that have undergone intensive program-erase operations among all storage cell blocks. Therefore, in operation S233, when storage device 200 determines that its remaining lifetime is less than the threshold, a higher weight can be applied to the program-erase count.

[0102] In operation S221, when storage device 200 determines that its remaining lifetime is equal to or greater than a threshold, it can determine whether the proportion of cold cell blocks is equal to or greater than the threshold proportion. Cold cell blocks are storage cell blocks that have been accessed less frequently. The fewer the accesses, the more likely the retention time is to increase. Therefore, in operation S232, when storage device 200 determines that the proportion of cold cell blocks in the storage cell blocks of storage device 220 is high, storage device 200 can assign a higher weight to retention time. In operation S231, when the proportion of cold cell blocks is less than the threshold proportion and the remaining lifetime of storage device 200 is equal to or greater than the threshold (e.g., storage cell blocks are accessed evenly), the variation in retention time may be small, so storage device 200 can assign the same weight to program-erase count and retention time.

[0103] In operation S241, storage device 200 may output block address information based on at least one of retention time or program-erase count. Storage device 220 can perform a patrol read operation by receiving the output block address information.

[0104] According to the example embodiment, the higher the priority of the inspection read operation, the earlier the storage device 200 can perform the inspection read operation. However, the inventive concept is not limited to this. For example, the higher the priority of the inspection read operation, the more inspection read operations the storage device 200 can perform. For example, the storage device 200 can perform multiple inspection read operations on some high-priority storage cell blocks. Because as a result of performing multiple inspection read operations, it can be determined whether the corresponding storage cell block is a storage cell block that needs to be reclaimed, so the target storage cell block for reclamation can be detected more accurately.

[0105] Figure 13 This is a flowchart of an operation method for a storage system in which the storage controller 210 generates block address information according to an example embodiment. Figure 14 This is a flowchart of an operation method for a storage system that generates block address information according to an example embodiment of the storage device 220.

[0106] Reference Figure 13The storage controller 210 can determine the priority of performing a patrol read operation on a storage cell block by generating reliability information. In operation S100, the storage controller 210 can receive an instruction to perform a patrol read operation from the host 100. For example, the instruction to perform a patrol read operation could refer to a signal instructing the storage device 200 to enter an idle mode. In operation S200, the storage controller 210 can generate a patrol read command in response to the instruction to perform a patrol read operation from the host 100. In operation S300, the storage controller 210 can generate reliability information based on at least one of retention time or program-erase count, and in operation S400, the storage controller 210 can generate block address information based on the reliability information.

[0107] In operation S500, the storage controller 210 can provide a patrol read command and block address information to the storage device 220. The block address information may be information corresponding to the address information of the storage cell block to which the patrol read operation is performed, and the storage controller 210 can provide the block address information to the storage device 220 in an order of priority determined based on reliability information. In operation S600, the storage device 220 can sequentially perform patrol read operations on the corresponding storage cell blocks in response to the patrol read command and block address information.

[0108] Reference Figure 14 When a patrol read command is received from the storage controller 210 in operation S200a in response to a patrol read command from the host 100 in operation S300a, the storage device 220 can generate reliability information based on at least one of retention time or program-erase count associated with each memory cell block stored in the page buffer in operation S300a. In operation S400a, block address information for performing the patrol read operation is generated based on the reliability information, and the patrol read operation is performed in operation S500a. Figure 13 Compared to the example embodiments, in Figure 14 In the example embodiment, because the storage device 220 generates reliability information and block address information in operations S300a and 400a, the patrol read operation can be performed with less signal exchange with the storage controller 210 of the storage device 200.

[0109] Although the inventive concept has been shown and described in detail with reference to some exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the claims.

Claims

1. A method of operating a controller, the controller being used to control a storage device including a plurality of memory cell blocks, the method comprising: The inspection and read command is provided to the storage device; The priority of the storage cell block used to perform the inspection read operation is determined based on the reliability information of the storage cell block; Output block address information in the order of the determined priority; as well as The control device responds to the patrol read command and the block address information, and executes the patrol read operation in a determined priority order. The process of determining the priority of the storage cell blocks used to perform the inspection read operation includes: determining the retention time and program-erase count of each of the storage cell blocks. The determination of the retention time and the program-erase count for each of the storage cell blocks includes: In response to the remaining lifetime of the storage device being less than a threshold, the program-erase count is given a higher weight than the retention time.

2. The method according to claim 1, further comprising: Receive information related to the target block for reclamation operation within the storage cell block for which the inspection read operation is performed.

3. The method according to claim 1, further comprising: The reliability information is updated in response to the storage device entering an idle mode.

4. The method according to claim 1, wherein, Determining the retention time or program-erase count for each of the memory cell blocks includes: when the remaining lifetime of the memory device is greater than or equal to the threshold, in response to the proportion of cold cell blocks in the memory cell block that have been accessed less than a set number of times being equal to or greater than the threshold proportion, giving the retention time a higher weight than the program-erase count.

5. The method according to claim 1, wherein, The output includes: determining the number of times to output the block address information for each of the storage unit blocks based on the corresponding priority in the priority.

6. A method of operating a storage device, the storage device including a storage device configured to perform a traverse read operation, the storage device including a plurality of storage cell blocks, the method comprising: The inspection and read command is provided to the storage device; The priority of the storage cell block used to perform the inspection read operation is determined based on the reliability information of the storage cell block; Output block address information in the order of the determined priority; The storage device is controlled to respond to the patrol read command and the block address information, and to perform the patrol read operation in a determined priority order; as well as Information is generated regarding the target block to be reclaimed within the memory cell block from which the inspection read operation is performed. The process of determining the priority of the storage cell blocks used to perform the inspection read operation includes: determining the retention time and program-erase count of each of the storage cell blocks. The determination of the retention time and the program-erase count for each of the storage cell blocks includes: In response to the remaining lifetime of the storage device being less than a threshold, the program-erase count is given a higher weight than the retention time.

7. The method according to claim 6, further comprising: The reliability information is updated in response to the storage device entering an idle mode.

8. A controller for a storage device, the controller comprising: At least one processor is configured as follows: In response to the patrol read command, a patrol read command is generated. The priority of the storage cell block used to perform the inspection read operation is determined based on the reliability information of the storage cell block of the storage device in the storage device. Output block address information in the order of the determined priority; and The storage device is controlled to respond to the patrol read command and the block address information, and to perform the patrol read operation in a determined priority order; as well as The memory interface is configured to provide the patrol read command and the block address information to the memory device. The at least one processor is configured to determine the priority of the memory cell block by determining the retention time and program-erase count of each of the memory cell blocks. The at least one processor is configured to determine the retention time and the program-erase count for each of the memory cell blocks by assigning a higher weight to the program-erase count compared to the retention time in response to the remaining lifetime of the memory device being less than a threshold.

9. The controller according to claim 8, wherein, The at least one processor is configured to update the reliability information in response to the storage device entering an idle mode.

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