A method and circuit for detecting the performance of a DRAM memory

Abstract

The application relates to a performance detection method and detection circuit of a DRAM memory. The performance detection method of the DRAM memory comprises the following steps: connecting one end of a word line and / or one end of a bit line of a storage unit to a measurement pad respectively, the storage unit being located at the edge of the DRAM memory; applying a measurement voltage or a measurement current to the one end of the word line and / or the one end of the bit line connected to the measurement pad; and outputting a measurement result through the measurement pad. By connecting the one end of the word line and / or the one end of the bit line of the storage unit located at the edge of the DRAM memory to the measurement pad respectively, applying the measurement voltage or the measurement current, and outputting the measurement result, the performance of the memory can be detected without affecting the storage unit, and the product yield and the cost of the product are not affected.

Description

Technical Field

[0001] This application relates to the field of DRAM memory technology, and specifically to a DRAM memory performance testing method and testing circuit. Background Technology

[0002] As the size of DRAM memory cells shrinks and the operating voltage decreases, the distribution of memory cells has a significant impact on product performance. It is necessary to adjust the substrate's body bias to minimize the influence of cell distribution. Cell characteristics are measured via scribe lanes, and the DRAM memory's product characteristics are adjusted based on the measurements. However, measurements performed in the scribe lanes cannot fully reflect the product's characteristics. Furthermore, with the miniaturization of semiconductor processes, various unforeseen factors can cause inconsistencies between the characteristics measured in the scribe lanes and those of surrounding products, or even the distribution of cells within the scribe lanes.

[0003] Measuring the characteristics of memory cells within a product is difficult. To directly measure the performance of DRAM memory cells within the product, it is necessary to modify or add peripheral circuitry, but such modifications or additions are very difficult to implement and cannot be achieved.

[0004] Existing technologies can measure the characteristics of storage cells inside a product, but this testing method has a high probability of damaging the storage cell being measured, affecting the product yield. Therefore, it is necessary to repair the storage cell being measured to make it a redundant memory cell, which increases costs.

[0005] Therefore, there is a need for a DRAM memory performance testing method and testing circuit that can measure DRAM memory cells without affecting product yield and product cost. Summary of the Invention

[0006] To address the aforementioned problems, this application provides a performance testing method for a DRAM memory, comprising the following steps: connecting one end of the word line and / or one end of the bit line of a memory cell to a measurement pad, wherein the memory cell is located at the edge of the DRAM memory; applying a measurement voltage or measurement current to one end of the word line and / or one end of the bit line connected to the measurement pad; and outputting the measurement result through the measurement pad.

[0007] To address the aforementioned problems, this application also provides a DRAM memory performance testing circuit for detecting memory cells in the memory using the DRAM memory performance testing method described above. The DRAM memory performance testing circuit includes one or more measurement pads, which are connected to one end of the word line and / or one end of the bit line of the memory cell to be tested.

[0008] The advantage of this application is that by connecting one end of the word line and / or one end of the bit line of the memory cell located at the edge of the DRAM memory to the measurement pad, applying the measurement voltage or measurement current, and outputting the measurement result, the performance of the memory can be tested without affecting the memory cell, and without affecting the product yield and product cost. Attached Figure Description

[0009] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0010] Figure 1 A schematic diagram of an existing DRAM memory is shown;

[0011] Figure 2 A schematic diagram of another existing DRAM memory is shown;

[0012] Figure 3 A schematic diagram of a performance detection circuit for a DRAM memory according to an embodiment of this application is shown;

[0013] Figure 4 A schematic diagram of another DRAM memory performance detection circuit according to an embodiment of this application is shown;

[0014] Figure 5 A schematic diagram illustrating the steps of a DRAM memory performance testing method according to an embodiment of this application is shown. Detailed Implementation

[0015] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0016] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0017] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0018] Figure 1 and Figure 2 This illustrates the circuitry of a storage cell in an existing DRAM memory. (Example:) Figure 1 As shown, the word line DWL connected to the dummy cell 101 in the edge cell of the DRAM memory block 100 is grounded. Figure 2 As shown, the bit line DBL and word line DWL connected to the pseudo cell 101 in the DRAM memory are both grounded. The bit line BL, which connects to memory cells other than the pseudo cell, is connected to the S / A pad 104 for connecting the sense amplifier S / A. The edge cell 102 includes at least one column or row of memory cells at the edge of the memory 100. The word line is connected to the gate of the memory cell, and the bit line is connected to the P-well of the memory cell. The edge cell 102 includes the pseudo cell 101. The pseudo cell 101 includes one column or row of memory cells at the outermost edge of the memory.

[0019] To fine-tune the characteristics of memory products, it is necessary to accurately measure the characteristic values ​​of memory cells. Because fine-tuning processes can cause variations in distribution due to process characteristics, measurements taken around the memory may not reflect the true characteristics of the product (memory). Therefore, it is essential to accurately measure the characteristics of the memory cells within the product itself. Based on these measurements, fine-tuning of the product's electrical properties can be performed.

[0020] Figure 3 and Figure 4This diagram illustrates a performance testing circuit for a DRAM memory according to an embodiment of this application. The circuit is used to test memory cells using a DRAM memory performance testing method. The DRAM memory performance testing circuit includes one or more measuring pads 103. The measuring pads 103 are connected to one end of the word line WL and / or one end of the bit line BL of the memory cell to be tested in the memory 100. The memory cell is located at the edge of the DRAM memory. Figure 3 As shown, the measurement pad 103 is connected to one end of the word line DWL of the memory cell located at the edge of the memory. Figure 4 As shown, the measurement pad 103 is connected to one end of the word line DWL and one end of the bit line DBL of the memory cell located at the edge of the memory. The word line is connected to the gate of the memory cell, and the bit line is connected to the P-well of the memory cell.

[0021] Figure 5 A performance testing method for a DRAM memory is illustrated. The example method begins with operation 501, connecting one end of the word line and / or one end of the bit line of a memory cell to a measurement pad, respectively. The memory cell is located at the edge of the DRAM memory 100. The memory cell is at least one row or column of memory cells located at the edge of the memory 100. Figure 3 and Figure 4 As shown, a measurement pad 103 is connected to one end of the pseudo-cell word line DWL and / or one end of the pseudo-cell bit line DBL located at the edge of memory 100. Embodiments of this application can be used before or after packaging memory 100.

[0022] Continue operation 502, applying a measurement voltage or current to one end of the word line WL and / or one end of the bit line BL connected to the measurement pad 103. Continue operation 503, outputting measurement results through the measurement pad 103. These measurement results include: the characteristics and thickness of the gate oxide film of the memory cell, the capacitance of the memory cell, the characteristics of the transmission transistor of the memory cell, the thickness of the insulating film of the memory cell, and / or the resistance value of the word line. Based on the measurement results output from the measurement pad 103, the manufacturing process, performance parameters, and testing methods of the DRAM memory can be adjusted; the manufacturing process of the DRAM memory can also be managed based on the measurement results.

[0023] Measuring edge cell 102 can improve the characteristics of the memory cell. To prevent signal interference with edge cell 102, the bit line BL and word line WL are biased towards the 0 (Ground) state. In pseudo cell 101, measuring items that can indirectly predict the characteristics of the cell's transmission transistors is more effective than measuring the cell transmission transistors of the repair memory block in the cut-out track or the capacitance of the capacitors in the cell. Therefore, the bit line BL and word line WL, biased towards the 0 state, are connected to pads that can be measured externally or to biasable pads. Measurements are performed using external pads, and the characteristics of the cell's transmission transistors and capacitors are inferred from the measurement results. After the measurement is completed, grounding is performed during the package stage without affecting the cell.

[0024] The method in this application connects one end of the word line and / or one end of the bit line of the memory cell located at the edge of the DRAM memory to the measurement pad, applies a measurement voltage or measurement current, and outputs the measurement result. It connects unmeasurable dummy cells to the measurement pad, making them measurable. This allows for memory performance testing without affecting the memory cells, thus not impacting product yield or cost. The measurement result is an internal value of the product, accurately reflecting its characteristics. Because the dummy cells are located on the periphery of the memory cells, the distribution of the actually used memory cells is improved. Furthermore, by electrically connecting the gate or P-well of the dummy cells to ground, the measurement of the dummy cells does not electrically affect the memory cells.

[0025] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0026] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for testing the performance of a DRAM memory, characterized in that, Includes the following steps: Connect one end of the word line and / or one end of the bit line of the memory cell to the measurement pad respectively. The memory cell is located at the edge of the DRAM memory. A measurement voltage or measurement current is applied to one end of a word line and / or one end of a bit line connected to the measurement pad; The measurement results are output through the measurement pads; After outputting the measurement results through the measurement pads, the following steps are also included: Based on the measurement results, the manufacturing process, performance parameters, and testing methods of the DRAM memory are adjusted. After outputting the measurement results through the measurement pads, the following steps are also included: Based on the measurement results, manage the manufacturing process of the DRAM memory; The measurement results include: the characteristics of the gate oxide film of the memory cell, the capacitance of the memory cell, the characteristics of the transmission transistor of the memory cell, the thickness of the insulating film of the memory cell, and / or the resistance value of the word line; The storage unit is at least one row or one column of storage units located at the edge of the memory; The storage unit includes: a pseudo-unit; One end of the word line and / or one end of the bit line of the memory cell includes: one end of the pseudo-cell word line and / or one end of the pseudo-cell bit line.

2. A performance testing circuit for a DRAM memory, characterized in that, For detecting memory cells in a DRAM memory using a performance testing method according to claim 1, the performance testing circuit of the DRAM memory includes one or more measurement pads, the measurement pads being connected to one end of the word line and / or one end of the bit line of the memory cell to be tested.

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