Memory device and method of testing the same, memory built-in self-test circuit

Abstract

A method of testing a memory device for improved reliability and reduced test time, a memory built-in self-test (MBIST) circuit, and a memory device. The memory device includes a plurality of memory banks and an MBIST circuit. The MBIST circuit is configured to generate a double data rate (DDR) test pattern and a parallel bit test (PBT) test pattern to test the memory banks. When a defective cell is detected as a result of a PBT test or a DDR test, the MBIST circuit is configured to perform a repair operation to replace the defective cell with a redundant cell, and perform a retest to verify the repair operation. The MBIST circuit can be configured to perform a DDR test on one or more memory cells including the defective cell during the retest.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0131968, filed on October 13, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a semiconductor memory device, and more specifically, to a method for testing a memory device to improve reliability and reduce test time, a memory-built-in self-test (MBIST) circuit, and a memory device. Background Technology

[0004] Semiconductor chips are manufactured using semiconductor manufacturing processes and tested by test equipment while they are in the form of wafers, dies, or packages. Testing selects defective or faulty chips, and if some memory cells fail, repair operations are performed to salvage the semiconductor chip. As semiconductor chips, such as dynamic random-access memory (DRAM), continue to miniaturize, they are more prone to errors during the manufacturing process. Furthermore, even if errors are not detected during initial testing, they can still occur during chip operation.

[0005] Systems using semiconductor chips (e.g., data centers) are hosted by numerous companies and their computer systems. Data centers distribute the hosted applications and / or transactions and include networked computing resources, often referred to as the cloud (e.g., servers, disks, virtual machines, etc.). In this configuration, the company is the customer of the data center. Data centers offer numerous advantages to clients, including reduced costs, ease of scalability, and reduced administrative workload. Data centers widely use DRAM as the system's operating memory or main memory and utilize storage devices, including non-volatile memory, as storage media to store data or instructions used by hosts in the data center and / or to perform computational operations.

[0006] Data centers require large-capacity DRAM for stable and rapid real-time processing of massive amounts of data. However, the performance quality of DRAM can change over time. For example, page faults can occur due to faulty memory when applications and / or transactions are allocated and use a certain amount of space in memory. When such page faults occur frequently, the normal flow of instruction execution may be interrupted, and therefore, data center availability constraints may exist, such as the abortion and restart of already started operations.

[0007] Therefore, testing DRAM with it installed and operating normally in the system is becoming increasingly important. Furthermore, since system-level testing allows for the repair of faulty DRAM cells in case of failure, it can contribute to improved DRAM performance and reliability. Additionally, testing time for high-capacity DRAM can be reduced to prevent interference with system performance. Summary of the Invention

[0008] One or more embodiments of this disclosure provide a method for testing a memory device to improve reliability and reduce test time, a memory-embedded self-test (MBIST) circuit, and a memory device.

[0009] According to an embodiment, a method for testing a memory device is provided, the memory device including a plurality of memory banks and a memory-in-memory self-test (MBIST) circuit, wherein the plurality of memory banks include a plurality of memory cells, and the memory-in-memory self-test circuit performs a double data rate (DDR) test or a parallel bit test (PBT) test. The method includes: setting an MBIST option, the MBIST option including a DDR test mode and a PBT test mode; performing a PBT test on the plurality of memory banks based on setting the PBT test mode to the MBIST option; performing a DDR test on one memory bank selected from the plurality of memory banks based on setting the DDR test mode to the MBIST option; and performing a repair operation via the MBIST circuit to repair the defective cell with redundant cells based on the detection of a defective cell as a result of the DDR test or the PBT test; and

[0010] The MBIST circuitry performs a retest to verify the repair operation, wherein the retest is performed on one or more memory cells, including the defective cell, among the plurality of memory cells.

[0011] The method further includes generating an internal clock signal having the highest frequency used in operation for testing the memory device, wherein the MBIST circuit is configured to perform the PBT test or the DDR test by using the internal clock signal.

[0012] The method further includes providing information about the defective cell to a memory controller connected to the memory device via the MBIST circuit, wherein the defective cell is detected by comparing the logic state output from each of the plurality of memory cells in response to the same write data input to each of the plurality of memory cells.

[0013] The MBIST options also include an MBIST repair option for repairing the defective unit and an MBIST auto-repair option for automatically repairing the defective unit.

[0014] During the setting of the MBIST option, the MBIST option is set in the mode register or test mode register of the memory device.

[0015] When setting the MBIST options, the test interface standard is used to set the MBIST options.

[0016] Performing the PBT test includes: generating a plurality of PBT test patterns through the test pattern generation (TPG) circuit of the MBIST circuit; performing the PBT test on the plurality of memory banks by using an enabled pattern among the plurality of PBT test patterns; and not performing the PBT test on the plurality of memory banks by using a disabled pattern among the plurality of PBT test patterns.

[0017] Performing the DDR test includes: generating a plurality of DDR test patterns through the test pattern generation (TPG) circuit of the MBIST circuit; performing the DDR test on a selected memory bank by using an enabled pattern from the plurality of DDR test patterns; and not performing the DDR test on the selected memory bank by using a disabled pattern from the plurality of DDR test patterns.

[0018] The step of performing the repair operation via the MBIST circuit for repairing the defective unit with the redundant units includes: outputting a fault marker signal indicating that the defective unit has been detected; outputting the fault unit address of the defective unit; in response to the fault marker signal, repairing the fault row address and fault column address included in the fault unit address with redundant row addresses and redundant column addresses; and storing the fault row address, the fault column address, the redundant row address corresponding to the fault row address, and the redundant column address corresponding to the fault column address in an address storage table (AST).

[0019] The method further includes providing information about the AST to a memory controller connected to the memory device.

[0020] During the retest performed by the MBIST circuit to verify the repair operation, the DDR test is performed on the defective unit.

[0021] During the retest performed by the MBIST circuit to verify the repair operation, the DDR test is performed on the one or more memory cells including the defective cell.

[0022] During the retest performed by the MBIST circuit to verify the repair operation, the PBT test is performed on all of the plurality of memory cells of the plurality of memory banks.

[0023] The method also includes using the MBIST circuit to test the architectural requirements of the memory physical layer (PHY) included in the memory controller connected to the memory device by using the results of the DDR test.

[0024] The architecture requirements of the memory PHY include DC parameters and AC parameters. The DC parameters include the voltage level, rise time, and fall time of the input / output signals provided to the signal lines connected to the memory PHY. The AC parameters include the memory access time, setup time, and hold time for the input / output signals.

[0025] According to an embodiment, a Memory Built-in Self-Test (MBIST) circuit for testing a memory device comprising multiple memory banks is provided. The MBIST circuit includes: a Test Pattern Generation (TPG) circuit configured to generate multiple test patterns, including a Double Data Rate (DDR) test pattern and a Parallel Bit Test (PBT) test pattern; a Built-in Redundancy Analysis (BIRA) circuit configured to perform a repair operation to replace a defective cell detected in a PBT or DDR test of the memory device with a redundant cell, and to store information about the address of the faulty cell and the address of the redundant cell in an Address Storage Table (AST); and a Built-in Self-Repair (BISR) control circuit configured to output a BISR signal in response to a fault marker signal indicating that the defective cell has been detected to perform the repair operation, wherein the TPG circuit is further configured to perform a retest on one or more memory cells, including the defective cell, among the multiple memory cells to verify the repair operation performed by the BIRA circuit.

[0026] The MBIST circuit is also configured to receive an internal clock signal having the highest frequency for testing the operation of the memory device, and to perform the PBT test or the DDR test by using the internal clock signal.

[0027] The MBIST circuit is also configured to provide information about the defective cell to a memory controller connected to the memory device, wherein the defective cell is detected by comparing the logic state output from each of the plurality of memory cells in response to the same write data input to each of the plurality of memory cells.

[0028] The BIRA circuit is also configured to output information about the AST to a memory controller external to the memory device.

[0029] The TPG circuit is also configured to perform the DDR test on one or more memory cells, including the defective cell, among the plurality of memory cells during the retest.

[0030] The TPG circuit is also configured to perform the PBT test on all of the plurality of memory cells of the plurality of memory banks during the retest.

[0031] The MBIST circuit further includes an input / output path test circuit configured to test the architectural requirements of a memory physical layer (PHY) included in a memory controller connected to the memory device using the results of the DDR test, wherein the architectural requirements of the memory PHY include DC parameters and AC parameters, the DC parameters including voltage levels and rise and fall times of input / output signals provided to signal lines connected to the memory PHY, and the AC parameters including memory access times, setup times, and hold times for the input / output signals.

[0032] According to an embodiment, a memory device is provided, comprising: a plurality of memory banks including a plurality of memory cells; control circuitry configured to control the operation of the memory device, wherein the control circuitry includes a mode register and a test mode register, the mode register providing operation options for the memory device, and the test mode register providing test mode options including a parallel bit test (PBT) test mode and a double data rate (DDR) test mode; and a memory built-in self-test (MBIST) circuitry configured to test the plurality of memory banks in the DDR test mode or the PBT test mode, wherein the MBIST circuitry is further configured to perform a repair operation for replacing defective cells detected in the PBT test or DDR test with redundant cells, and to perform a retest on one or more memory cells among the plurality of memory cells including the defective cells to verify the repair operation.

[0033] The memory device further includes a clock generator configured to generate an internal clock signal having the highest frequency used in testing the operation of the memory device, wherein the clock frequency of the internal clock signal is higher than the clock frequency of an external clock signal applied to the memory device in normal DDR mode, and the internal clock signal is used in either the PBT test mode or the DDR test mode.

[0034] The MBIST circuit also includes a test pattern generation (TPG) circuit configured to generate multiple test patterns, including DDR test patterns and PBT test patterns.

[0035] The TPG circuit is also configured to perform the DDR test on one or more memory cells, including the defective cell, among the plurality of memory cells during the retest by using the DDR test pattern.

[0036] The TPG circuit is also configured to perform the PBT test on all of the plurality of memory cells of the plurality of memory banks during the retest by using the PBT test pattern.

[0037] The memory device further includes a built-in self-repair (BISR) control circuit configured to output a BISR signal in response to a fault marker signal indicating that the defective cell has been detected in order to perform the repair operation, wherein the defective cell is detected by comparing the logic state output from each of the plurality of memory cells in response to the same write data input to each of the plurality of memory cells.

[0038] The memory device also includes a built-in redundancy analysis (BIRA) circuit, which is configured to: perform the repair operation and store information about the fault cell address and the redundant cell address in an address storage table (AST); and output information about the AST to a memory controller outside the memory device.

[0039] The memory device further includes an input / output path test circuit configured to test the architectural requirements of the memory physical layer (PHY) included in the memory controller connected to the memory device using the results of the DDR test. The architectural requirements of the memory PHY include DC parameters and AC parameters. The DC parameters include the voltage level and rise and fall times of the input / output signals provided to the signal lines connected to the memory PHY. The AC parameters include the memory access time, setup time, and hold time for the input / output signals. Attached Figure Description

[0040] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0041] Figure 1 This is a block diagram illustrating a system according to an embodiment;

[0042] Figure 2 This illustrates an embodiment. Figure 1 A block diagram of a memory device in a memory system;

[0043] Figure 3 This is a flowchart describing a method for testing a memory device according to an embodiment;

[0044] Figure 4A and Figure 4B This is a diagram illustrating a method for testing a memory device according to an embodiment;

[0045] Figure 5A and Figure 5B This is a flowchart describing a method for testing a memory device according to an embodiment;

[0046] Figure 6 This is a flowchart describing a method for testing a memory device according to an embodiment;

[0047] Figure 7 and Figure 8 It is used to describe the embodiments. Figure 2 A diagram of the address storage table of the built-in redundancy analysis (BIRA) circuitry;

[0048] Figure 9A and Figure 9B This is a diagram illustrating a repair operation in which a faulty cell in a memory cell array is replaced with a redundant cell according to an embodiment.

[0049] Figure 10 This is a flowchart describing a method for testing a memory device according to an embodiment;

[0050] Figure 11This illustrates an embodiment. Figure 1 A block diagram of a memory device in a memory system;

[0051] Figure 12 This is a block diagram illustrating a memory device according to an embodiment; and

[0052] Figure 13 This is a block diagram illustrating a system including a memory device according to an embodiment. Detailed Implementation

[0053] Figure 1 This is a block diagram illustrating a system according to an embodiment.

[0054] Reference Figure 1 System 10 may be a data center comprising dozens of host machines or servers for running hundreds of virtual machines. According to some embodiments, system 10 may be, for example, a computing device such as a laptop computer, desktop computer, server computer, workstation, portable communication terminal, personal digital assistant (PDA), portable multimedia player (PMP), smartphone, or any other suitable computer, VM, or virtual computing device thereof. Additionally, system 10 may be a component included in a computing system (e.g., a graphics card).

[0055] although Figure 1 Various hardware components of the system 10 described below are shown, but the inventive concept is not limited thereto and may include other components. System 10 may include a host device 20 and a memory system 30. The host device 20 and memory system 30 may be interconnected according to various standard interfaces (e.g., Peripheral Component Interconnect Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS)). Furthermore, various other interface protocols (such as Universal Serial Bus (USB), Universal Flash Storage (UFS), Multimedia Card (MMC), Enhanced Small Digital Disk Interface (ESDI), or Integrated Drive Electronics (IDE)) may be applied to the protocol between the host device 20 and the memory system 30.

[0056] The host device 20 may include a processor 22, which may be configured to execute an operating system (OS) and / or various applications. The processor 22 may be communicatively connected to a memory system 30. The memory system 30 connected to the processor 22 may be referred to as system memory. Examples can be described using the expressions “connected” and / or “coupled” and their derivatives. These terms are not necessarily intended to be synonyms. For example, a description using the terms “connected” and / or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. Alternatively, the terms “connected” and / or “coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0057] Processor 22 can be configured to perform computer operations in system 10 and can be any type of processor, such as a central processing unit (CPU), digital signal processor (DSP), network processor, application processor (AP), or any other means for executing code. Processor 22 can be configured to execute instructions, software, firmware, or combinations thereof that can be executed by one or more machines. Processor 22 can include any number of processor cores. For example, processor 22 can include a single core or multi-core processors such as dual-core, quad-core, and hexa-core. Although... Figure 1 A system 10 including a processor 22 is shown, but according to an embodiment, system 10 may include multiple processors.

[0058] Processor 22 can execute software in a virtualized environment. In host device 20, virtual machines can include applications (APPs) and an operating system (OS). Since the application APP uses a virtual address space, it uses virtual addresses (i.e., addresses that can be used by the software). The OS in each virtual machine can control the timing of a specific application APP's access to a given memory device 120, and can at least partially control the addresses accessed by the application APP. The OS in the virtual machine can perform and manage the mapping between virtual addresses (VAs) and physical addresses (PAs). The physical address PA generated by the OS is the system physical address PA (i.e., the address of the entire physical address space of the actual memory system 30, 120, that can be used by the memory controller 110). The OS can perform address translation (e.g., address mapping) between virtual addresses VAs and system physical addresses PAs.

[0059] The memory system 30 may include a memory controller 110, a memory device 120, and a memory interface 130. The memory controller 110 may control memory access operations (e.g., write or read operations) for the memory device 120 in response to requests from a host device 20 connected to the memory system 30. The memory device 120 may be used as working memory for recording or loading data for operations of the processor 22. Although Figure 1 A memory system 30 is shown that includes a memory device 120, but according to an embodiment, the memory system 30 may include multiple memory devices.

[0060] For simplicity, memory interface 130 is shown as a single signal line connecting memory controller 110 and memory device 120; however, memory interface 130 may include multiple signal lines for connecting memory controller 110 and memory device 120. Memory interface 130 includes connectors for connecting memory controller 110 and memory device 120. The connectors may be implemented as pins, balls, signal lines, or other hardware components. For example, clock signals CLK, command / address signals CMD / ADDR, data DQ, etc., can be sent and received between memory controller 110 and memory device 120 via memory interface 130. Memory interface 130 may be implemented as a channel including multiple signal lines, or it may be implemented as multiple channels. Memory interface 130 may be referred to as a channel; however, the terms memory interface and channel are used interchangeably in this disclosure.

[0061] The memory controller 110 can access the memory device 120 according to a memory request from the processor 22, and can provide a system physical address to access the memory device 120. The memory controller 110 may include a memory physical layer interface (i.e., a memory PHY 112 for memory interaction (e.g., selecting rows and columns corresponding to memory cells, writing data to memory cells, or reading written data).

[0062] The actual physical implementation of the memory PHY 112 of the memory controller 110, which performs the functions described above, can take various forms. For example, the memory controller 110 may include physical components for exchanging data with the memory device 120, and may include at least one transmitter and at least one receiver. The memory controller 110 may be implemented by one or more hardware components (e.g., analog circuitry, logic circuitry) and program code in software and / or firmware. The memory controller 110 may be commonly integrated into one or more processors 22, such that the memory device 120 can be consistently accessed by one or more processors 22.

[0063] Memory device 120 may be a DRAM device. In this disclosure, the terms memory device and DRAM are used interchangeably. However, the inventive concept is not limited thereto, and memory device 120 may be any of a volatile memory device (e.g., synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, wide I / O DRAM, high bandwidth memory (HBM), and hybrid memory cube (HMC)). According to another embodiment, memory device 120 may be any of a plurality of memory devices mounted on a memory module. The memory module may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a reduced load DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc.

[0064] Terms such as “unit” or “module” used in one or more embodiments of this disclosure refer to a unit for performing at least one function or operation, and may be implemented in hardware, software, or a combination of hardware and software.

[0065] The term "unit" or "module" can be implemented by a program stored in an addressable storage medium and executable by a processor.

[0066] For example, the term "unit" or "module" can include software components, object-oriented software components, class components and task components, processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuit systems, data, databases, data structures, tables, arrays, and / or variables.

[0067] Memory device 120 may include a memory cell array (MCA) 122, control circuitry 124, and memory built-in self-test (MBIST) circuitry 126. MCA 122 may include multiple word lines, multiple bit lines, and multiple memory cells formed at the intersections of word lines and bit lines. Each memory cell may include a DRAM cell, which includes an access transistor and a storage capacitor. MCA 122 may include multiple memory banks, and each memory bank may include a normal cell array and a redundant cell array.

[0068] Control circuit 124 can control access to MCA 122 based on commands and addresses received from memory device 120. Control circuit 124 can control testing of MCA 122 connected to MBIST circuit 126.

[0069] MBIST circuit 126 can perform test and repair operations on MCA 122. MBIST circuit 126 may include test pattern generation (TPG) circuit 127 and built-in self-healing (BISR) control circuit 128.

[0070] TPG circuit 127 can provide a test pattern for detecting cell faults in MCA 122. The test pattern can include various test vectors for detecting specific faults and structural defects, and has high fault coverage. For example, the test pattern can include a random test pattern, a pseudo-random test pattern (similar to a random test pattern except that its test vector sequence is repeated), or a parallel bit test (PBT) test pattern including the same data (e.g., "0" or "1").

[0071] The BISR control circuit 128 can control the MCA 122 to repair defective cells in the MCA 122 using redundant cells. The TPG circuit 127 can perform a retest on the MCA 122 to verify the repair operation. During the retest, the TPG circuit 127 can selectively test the entire MCA 122 or a portion of the MCA 122 including the defective cells.

[0072] Figure 2 This illustrates an embodiment. Figure 1 A block diagram of a memory device in a memory system. Figure 2 The diagram illustrates multiple hardware components included in the memory device 120. However, the inventive concept is not limited thereto, and other components may be provided. In the following, letters attached to the reference numerals (e.g., 122a, 260a, 270a, etc.) are used to identify multiple circuits having the same function.

[0073] Reference Figure 1 and Figure 2 The memory device 120 may include a memory core 200, a control circuit 124, an MBIST circuit 126, a built-in redundancy analysis (BIRA) circuit 220, and a clock generator 230.

[0074] The memory core 200 may include a first memory array to a fourth memory array 122a, 122b, 122c, and 122d. The first memory array to the fourth memory array 122a, 122b, 122c, and 122d may correspond to... Figure 1The memory cell array 122. First-bank row decoders to fourth-bank row decoders 260a, 260b, 260c, and 260d, and first-bank column decoders to fourth-bank column decoders 270a, 270b, 270c, and 270d, can be connected to the first-bank array to fourth-bank array 122a, 122b, 122c, and 122d, respectively. The memory core 200 may include first-bank sense amplifiers to fourth-bank sense amplifiers connected to the first-bank array to fourth-bank array 122a, 122b, 122c, and 122d, respectively. The first to fourth memory arrays 122a, 122b, 122c and 122d, the first to fourth memory row decoders 260a, 260b, 260c and 260d, the first to fourth memory column decoders 270a, 270b, 270c and 270d, and the first to fourth memory sense amplifiers can constitute the first to fourth memory banks BANK1 to BANK4. Although Figure 2 An example of a memory device 120 including four memory banks is shown, but one or more embodiments are not limited thereto, and the memory device 120 may include any number of memory banks.

[0075] Control circuit 124 can be accessed via Figure 1 The memory interface 130 shown receives commands CMD and addresses ADDR from the memory controller 110. Control circuitry 124 can control normal operation, test operation, or refresh operation for the first memory bank BANK1 through the fourth memory bank BANK4 based on commands CMD and addresses ADDR. Control circuitry 124 can control the first memory bank row decoders through the fourth memory bank row decoders 260a, 260b, 260c, and 260d, the first memory bank column decoders through the fourth memory bank column decoders 270a, 270b, 270c, and 270d, the MBIST circuitry 126, and the BIRA circuitry 220 based on commands CMD and addresses ADDR.

[0076] The BIRA circuit 220 is associated with the BISR control circuit 128 of the MBIST circuit 126. During testing of the first memory bank BANK1 through the fourth memory bank BANK4, when a fault is detected in one of the memory banks, the BIRA circuit 220 can perform a redundancy repair process to repair the detected fault using redundant rows or columns.

[0077] Control circuit 124 can control the normal mode (i.e., read operation or write operation) of memory device 120. The normal mode is based on the command CMD and address ADDR received from memory controller 110 via memory interface 130 to input data DQ into first memory banks BANK1 to fourth memory banks BANK4 and output data DQ from first memory banks BANK1 to fourth memory banks BANK4. Furthermore, control circuit 124 can control memory core 200 to perform automatic refresh operations for first memory banks BANK1 to fourth memory banks BANK4 in response to refresh commands received via memory interface 130, or to perform self-refresh operations for first memory banks BANK1 to fourth memory banks BANK4 in response to self-refresh enter commands. For ease of explanation and simplified illustration, the command CMD, address ADDR, and data DQ received via memory interface 130 are indicated as the normal DDR signal N_DDRS.

[0078] Control circuitry 124 may include a mode register (MRS) providing multiple operating options for memory device 120 and a test mode register (TMRS) providing test operation options. MRS / TMRS 212 can be programmed with various functions, characteristics, and modes of memory device 120. Test mode options (e.g., DDR test mode or PBT test mode) to be performed by MBIST circuitry 126 can be selectively set by MRS / TMRS 212.

[0079] Control circuit 124 may include comparator 210, which outputs a fault flag signal FS and a fault cell address F / A when a defective cell is detected during a DDR test or PBT test performed by MBIST circuit 126. Comparator 210 may be implemented as an XOR logic circuit or an XNOR logic circuit. The fault flag signal FS may be provided to BISR control circuit 128 of MBIST circuit 126, and the fault cell address F / A may be stored in address storage table (AST) 222 of BIRA circuit 220. Address storage table AST 222 may store the fault row address FRA and / or fault column address FCA representing the fault cell address F / A.

[0080] Clock generator 230 generates an internal clock signal iCLK with an optimal frequency for test operations on memory device 120. The internal clock signal iCLK can be provided to a first selector 241. The first selector 241 can be implemented as a multiplexer that receives clock signal CLK from memory interface 130 as a first input I1 and internal clock signal iCLK from clock generator 230 as a second input I2, and outputs output O based on the first input I1 and the second input I2. Clock signal CLK may be referred to as "external clock signal CLK" to distinguish it from internal clock signal iCLK. In this disclosure, the terms clock signal CLK and external clock signal CLK are used interchangeably.

[0081] When the memory device 120 is in normal mode (e.g., DDR mode), the external clock signal CLK has an operating frequency. The internal clock signal iCLK may have a higher clock frequency than the external clock signal CLK. When the memory device 120 is in normal mode, the first selector 241 can select the external clock signal CLK of the first input I1 and output it to output O. At this time, the MBIST circuit 126 is disabled. When the memory device 120 is in test mode, the first selector 241 can select the internal clock signal iCLK of the second input I2 and output it to output O. The output O of the first selector 241 can be provided to the MBIST circuit 126 as the MBIST clock signal MBIST_CLK. Since the MBIST circuit 126 uses the MBIST clock signal MBIST_CLK with a high clock frequency to test the memory device 120, the test time can be reduced.

[0082] In the MBIST circuit 126, when the memory device 120 is in test mode, the TPG circuit 127 can provide various test patterns. The TPG circuit 127 can output a DDR test signal T_DDRS including a test pattern suitable for DDR testing. Furthermore, the TPG circuit 127 can output a PBT signal PBTS including a test pattern suitable for PBT testing.

[0083] In MBIST circuit 126, BISR control circuit 128 may receive a fault marker signal FS output from comparator 210 of control circuit 124. In response to the fault marker signal FS indicating that a defective cell has been detected, BISR control circuit 128 may output a BISR signal BISRS, which instructs BIRA circuit 220 to perform a redundancy repair process for repairing the defective cell using redundant rows or columns.

[0084] The BIRA circuit 220 can perform a repair operation based on the BISR signal BISRS, and replace the faulty row address FRA and / or faulty column address FCA stored in AST 222 with redundant row addresses RRA and / or redundant column addresses RCA, respectively. During the repair operation, the BIRA circuit 220 can store information about the source address S_ADDR and the destination address D_ADDR, where the source address S_ADDR indicates the faulty row address FRA and / or faulty column address FCA of one or more memory banks that need to be repaired, and the destination address D_ADDR indicates the redundant row address RRA and / or redundant column address RCA in AST 222.

[0085] In this embodiment, the BIRA circuit 220 and the MBIST circuit 126 are shown to be implemented separately. However, the embodiment is not limited to this, and the BIRA circuit 220 may be included in the MBIST circuit 126.

[0086] BIRA circuit 220 can provide information about AST 222 to memory controller 110. Memory controller 110 can store the information about AST 222 as memory management information for consistent access to memory device 120 by one or more processors 22. The information about AST 222 can be shared with one or more processors 22. When one or more processors 22 perform memory allocation operations during application execution, they can perform memory allocation operations based on the information about AST 222. Therefore, one or more processors 22 can perform functions commonly referred to as memory manager functions, namely, managing the address space of the OS in memory device 120 and evenly distributing memory regions to other virtual machines using memory device 120 by using memory management information.

[0087] Furthermore, the BIRA circuit 220 can provide information about AST 222 to the TPG circuit 127. The TPG circuit 127 can perform retesting on the first memory bank BANK1 through the fourth memory bank BANK4 to verify the repair operations performed by the BIRA circuit 220 based on the information about AST 222. During the retesting, the TPG circuit 127 can selectively test all or some areas of the first memory bank BANK1 through the fourth memory bank BANK4, including defective cells.

[0088] MBIST circuit 126 may include second to fifth selectors 242, 243, 244, and 245 that control the test modes and test sequences of memory device 120. Second to fifth selectors 242, 243, 244, and 245 may be implemented as multiplexers. Second selector 242 may receive an external clock signal CLK as a first input I1 and an MBIST clock signal MBIST_CLK as a second input I2, and output output O. When memory device 120 is in normal mode, second selector 242 can select the external clock signal CLK of the first input I1 and output it to output O. When memory device 120 is in test mode via MBIST circuit 126, second selector 242 can select the MBIST clock signal MBIST_CLK of the second input I2 and output it to output O. Output O of second selector 242 may be provided to control circuit 124. The control circuit 124 can control the normal mode operation of the memory device 120 based on the external clock signal CLK, and can control the testing of the memory device 120 based on the MBIST clock signal MBIST_CLK.

[0089] The third selector 243 can receive a normal DDR signal N_DDRS as a first input I1 and a DDR test signal T_DDRS as a second input I2, and outputs output O based on the first input I1 and the second input I2. When the memory device 120 is in normal mode, the third selector 243 can select the normal DDR signal N_DDRS of the first input I1 and output it to output O. When the memory device 120 is in DDR test mode via the MBIST circuit 126, the third selector 243 can select the DDR test signal T_DDRS of the second input I2 and output it to output O. The output O of the third selector 243 can be provided to the control circuit 124. The control circuit 124 can control the normal mode operation of the memory device 120 based on the normal DDR signal N_DDRS, and can control the DDR test of the memory device 120 based on the DDR test signal T_DDRS.

[0090] The fourth selector 244 can receive the normal DDR signal N_DDRS as the first input I1 and the PBT signal PBTS as the second input I2, and output output O. When the memory device 120 is in normal mode, the fourth selector 244 can select the normal DDR signal N_DDRS from the first input I1 and output it to output O. When the memory device 120 is in PBT test mode via the MBIST circuit 126, the fourth selector 244 can select the PBT signal PBTS from the second input I2 and output it to output O. The output O of the fourth selector 244 can be provided to the control circuit 124. The control circuit 124 can control the normal mode operation of the memory device 120 based on the normal DDR signal N_DDRS, and can control the PBT test of the memory device 120 based on the PBT signal PBTS.

[0091] MBIST circuit 126 can be configured such that only one of the third selector 243 and the fourth selector 244 is activated according to either DDR test mode or PBT test mode. In DDR test mode, the third selector 243 can be activated and the fourth selector 244 can be deactivated. In PBT test mode, the fourth selector 244 can be activated and the third selector 243 can be deactivated.

[0092] The fifth selector 245 can receive a normal DDR signal N_DDRS as a first input I1 and a BISR signal BISRS as a second input I2, and output output O based on the first input I1 and the second input I2. When the memory device 120 is in normal mode, the fifth selector 245 can select the normal DDR signal N_DDRS of the first input I1 and output it to output O. When the memory device 120 is in DDR test mode or PBT test mode via the MBIST circuit 126, the fifth selector 245 can select the BISR signal BISRS of the second input I2 and output it to output O. The output O of the fifth selector 245 can be provided to the BIRA circuit 220. The BIRA circuit 220 can perform a repair operation in the normal mode of the memory device 120 based on the normal DDR signal N_DDRS, and can perform a repair operation in the DDR test mode or PBT test mode based on the BISR signal BISRS.

[0093] Although this embodiment shows the implementation of the second selector 242 to the fifth selector 245 in the MBIST circuit 126, the embodiment is not limited thereto, and at least one of the second selector 242 to the fifth selector 245 may be implemented separately from the MBIST circuit 126.

[0094] MBIST circuit 126 can provide DDR test results and / or PBT test results for memory device 120 to memory controller 110. Memory controller 110 can perform memory allocation operations by referring to the test results output from MBIST circuit 126.

[0095] Figure 3 This is a flowchart describing a method for testing a memory device according to an embodiment, and Figure 4A and Figure 4B This is a diagram illustrating a method for testing a memory device according to an embodiment.

[0096] Reference Figure 2 and Figure 3 In operation S310, the MBIST option can be set, and depending on the set MBIST option, in operation S320, a PBT test can be performed through the MBIST circuit 126, or in operation S330, a DDR test can be performed through the MBIST circuit 126.

[0097] In operation S310, the test mode option (e.g., PBT test mode or DDR test mode) for the tests performed by the MBIST circuitry 126 can be set by the MRS / TMRS 212 of the memory device 120. According to an embodiment, the test mode option (e.g., DDR test mode or PBT test mode) for the tests performed by the MBIST circuitry 126 using a test interface (e.g., IEEE 1500 standard or IEEE 1149.1 standard (or JTAG)) can be set to the memory device 120.

[0098] Furthermore, during operation S310, an MBIST repair option can be set for repairing one or more defective cells obtained as a result of testing the memory device 120 via the MBIST circuit 126. Moreover, during repair, an MBIST automatic repair option can be set for automatic repair via the BISR control circuit 128 and the BIRA circuit 220.

[0099] In the PBT test performed via MBIST circuit 126 in operation S320, such as Figure 4AAs shown, a PBT test can be performed on memory cells MC, each MC being connected to a selected word line WLi and a selected bit line BLi. Here, the number of multiple selected bit lines BLi can correspond to the number of first memory banks BANK1 to fourth memory banks BANK4, where the number of first memory banks BANK1 to fourth memory banks BANK4 is 4. However, one or more embodiments are not limited to this, and the number of selected bit lines BLi can vary depending on the number of memory banks. In the PBT test, after the PBT test pattern (i.e., the same data (e.g., "0" or "1")) is written to the memory cells MC of the first memory banks BANK1 to fourth memory banks BANK4, the data read from the first memory banks BANK1 to fourth memory banks BANK4 can be compared with each other in bit pairs.

[0100] During the PBT test, when data read from memory cells MC of the first memory bank BANK1 to the fourth memory bank BANK4 is read in the same logic state, comparator 210 can output a comparison signal, for example, a logic low level. During the PBT test, when a different logic state is detected in even one of the data read from memory cells MC of the first memory bank BANK1 to the fourth memory bank BANK4, comparator 210 can output a comparison signal, for example, a logic high level. Control circuit 124 can output a fault marker signal FS indicating that a defective cell has been detected during the PBT test based on the logic high level comparison signal output from comparator 210, and output the fault cell address F / A of the corresponding defective cell.

[0101] In the DDR test of operating S330, such as Figure 4B As shown, a DDR test can be performed on a memory cell MC from one of the selected memory banks (e.g., the first memory bank BANK1) connected to a selected word line WLi and multiple selected bit lines BLi. In the DDR test, after a random test pattern provided by the TPG circuit 127 of the MBIST circuit 126 is written to the memory cell MC of the first memory bank BANK1, data read from the first memory bank BANK1 can be compared with the random test pattern of the TPG circuit 127.

[0102] During DDR testing, when data read from memory cell MC of the first memory bank BANK1 is read in the same logic state as the random test pattern of TPG circuit 127, comparator 210 can output a comparison signal, for example, a logic low level. During DDR testing, when a different logic state is detected in even one of the data read from memory cell MC of the first memory bank BANK1, comparator 210 can output a comparison signal, for example, a logic high level. Control circuit 124 can output a fault marker signal FS indicating that a defective cell has been detected during DDR testing based on the logic high level comparison signal output from comparator 210, and output the corresponding fault cell address F / A.

[0103] Figure 5A and Figure 5B This is a diagram illustrating a method for testing a memory device according to an embodiment.

[0104] Reference Figure 2 , Figure 3 , Figure 4A and Figure 5A When the test mode option for the test to be performed in the MBIST circuit 126 is set to PBT test mode, a PBT test on the memory device 120 can be performed (operation S320).

[0105] During the PBT test in operation S320, operation S521 can be performed, in which the TPG circuit 127 of the MBIST circuit 126 generates and sets a PBT signal PBTS including multiple PBT test patterns suitable for PBT testing.

[0106] In operation S522, when the operation state of the first test pattern TP1 in the PBT test pattern is enabled, PBT tests on the first memory bank BANK1 to the fourth memory bank BANK4 are performed using the first test pattern TP1 (operation S523). When the operation state of the first test pattern TP1 in the PBT test pattern is disabled, no test is performed, and PBT tests for the next test pattern can be performed. Similarly, depending on the state of each of the second to (n-1)th (n is a natural number) test patterns, PBT tests on each of the first memory bank BANK1 to the fourth memory bank BANK4 can be performed or not.

[0107] In operation S524, when the operation state of the nth test pattern TPn, which is the last of the PBT test patterns, is enabled, the PBT test on the first memory bank BANK1 to the fourth memory bank BANK4 is performed using the nth test pattern TPn (operation S525). When the operation state of the nth test pattern TPn is disabled, no test is performed.

[0108] Reference Figure 2 , Figure 3 , Figure 4B and Figure 5B When the test mode option for the test to be performed in the MBIST circuit 126 is set to DDR test mode, a DDR test on the memory device 120 can be performed (operation S330).

[0109] During the DDR test in operation S330, operation S531 can be performed, in which the TPG circuit 127 of the MBIST circuit 126 generates and sets a DDR test signal T_DDRS that includes multiple DDR test patterns suitable for DDR testing.

[0110] In operation S532, when the operation state of the first test pattern TP1 in the DDR test pattern is enabled, a DDR test on the first memory bank BANK1 is performed using the first test pattern TP1 (operation S533). When the operation state of the first test pattern TP1 is disabled, no test is performed, and a DDR test for the next test pattern can be performed. Similarly, depending on the state of each of the second to (m-1)th test patterns (m is a natural number), a DDR test on the first memory bank BANK1 may or may not be performed.

[0111] In operation S534, when the operation state of the m-th test pattern TPm, which is the last DDR test pattern, is enabled, the DDR test on the first memory bank BANK1 is performed using the m-th test pattern TPm (operation S535). When the operation state of the m-th test pattern TPm is disabled, no test is performed. After performing the DDR test on the first memory bank BANK1, DDR testing can continue on each of the remaining second memory banks BANK2 to fourth memory banks BANK4.

[0112] Figure 6 This is a diagram illustrating a method for testing a memory device according to an embodiment.

[0113] Reference Figure 2 , Figure 3 and Figure 6 According to the MBIST option in operation S310, a PBT test is performed on the first memory bank BANK1 to the fourth memory bank BANK4 (operation S320), or a DDR test is performed on each memory bank selected sequentially from the first memory bank BANK1 to the fourth memory bank BANK4 (operation S330), and a fault can be detected as a result of the test (operation S610).

[0114] In operation S610, when a defective cell is detected during a DDR test or PBT test performed by the MBIST circuit 126, the control circuit 124 can output a fault marker signal FS and a fault cell address F / A. The fault marker signal FS can be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fault cell address F / A can be stored in the address storage table 222 of the BIRA circuit 220. In operation S610, when no faulty cell is detected, MBIST can be terminated.

[0115] In operation S620, if the MBIST repair option of operation S310 is set, the method proceeds to operation S630. Otherwise, the method proceeds to operation S640. In operation S630, if the MBIST automatic repair option of operation S310 is set, the BISR operation (operation S650) can be performed, and MBIST can be terminated thereafter. In operation S630, if the MBIST automatic repair option of operation S310 is not set, the test results can be output in operation S640.

[0116] In operation S640, the MBIST circuit 126 can output the DDR test results and / or PBT test results of the memory device 120 to the memory controller 110 and terminate MBIST. The memory controller 110 can perform memory allocation operations by referring to the test results output from the MBIST circuit 126. Here, the test results may only include information about the fault cell address F / A.

[0117] In operation S650, the BISR control circuit 128 of the MBIST circuit 126 can output a BISR signal BISRS in response to the fault marker signal FS output from the control circuit 124. The BISR signal BISRS instructs the BIRA circuit 220 to perform a redundant repair process for repairing detected defective cells using redundant rows or redundant columns. The BIRA circuit 220 can perform the repair operation based on the BISR signal BISRS, and replace the faulty row address FRA and / or faulty column address FCA stored in AST222 with the redundant row address RRA and / or redundant column address RCA, respectively.

[0118] Figure 7 and Figure 8 It is used to describe Figure 2 A diagram of the address storage table for the BIRA circuit.

[0119] Reference Figure 2 , Figure 6 and Figure 7The BIRA circuit 220 replaces the information about the fault cell address F / A provided by the control circuit 124 with redundant row addresses RRA and / or redundant column addresses RCA, respectively; that is, the fault row address FRA and / or fault column address FCA stored in AST 222. During BISR operation, the BIRA circuit 220 may store information about the source address S_ADDR (e.g., fault row address FRA and / or fault column address FCA) and the destination address D_ADDR including the redundant row address RRA and / or redundant column address RCA of one or more memory cells (MCs) that need to be repaired in AST 222.

[0120] Reference Figure 8 AST 222 may include an antifuse array comprising one or more antifuses 822 and a sensing unit 810. The antifuse 822 is a resistive fuse element having electrical characteristics opposite to those of a fuse element, exhibiting high resistance in a non-programmed state and low resistance in a programmed state. AST 222 can selectively program one or more antifuses 822 to store a source address S_ADDR in a first memory cell 821 and a destination address D_ADDR in a second memory cell 823. The sensing unit 810 may include a first sub-sensing unit 811 and a second sub-sensing unit 813 connected to the first memory cell 821 and the second memory cell 823, respectively. The first sub-sensing unit 811 and the second sub-sensing unit 813 may include NMOS transistors. The sensing unit 810 may output information about the source address S_ADDR and the destination address D_ADDR in response to a fault flag signal FS.

[0121] Figure 9A and Figure 9B This is a diagram used to describe the repair operation of replacing defective cells in a memory cell array with redundant cells.

[0122] exist Figure 9A In this example, it is assumed that a redundant row address (RRA) is used to repair a faulty row address (FRA). The memory cell array 122a may include a normal cell array (NMCA) and a redundant cell array (RMCA). The normal cell array (NMCA) may include memory cells connected to word lines and bit lines, and the redundant cell array (RMCA) may include memory cells connected to redundant word lines and redundant bit lines. The BISR control circuitry 128 may include a row repair unit 1281, which determines the redundant row addresses (RRA) such that the redundant resources used to repair the faulty row address (FRA) do not overlap.

[0123] The row repair unit 1281 can perform a repair operation that selects a redundant row address RRA instead of a faulty row address FRA. The row repair unit 1281 deactivates the word line corresponding to the faulty row address FRA and instead activates the redundant word line corresponding to the redundant row address RRA. Therefore, a redundant memory cell corresponding to the redundant row address RRA is selected instead of the memory cell corresponding to the faulty row address FRA.

[0124] exist Figure 9B In this example, it is assumed that a faulty column address FCA is repaired using a redundant column address RCA. The memory cell array 122b may include a normal cell array NMCA and a redundant cell array RMCA. The normal cell array NMCA may include memory cells connected to word lines and bit lines, and the redundant cell array RMCA may include memory cells connected to redundant word lines and redundant bit lines. The BISR control circuit 128 may include a column repair unit 1282, which determines the redundant column address RCA such that the redundant resources used to repair the faulty column address FCA do not overlap.

[0125] The column repair unit 1282 can perform a repair operation that selects a redundant column address RCA instead of a faulty column address FCA. The column repair unit 1282 prevents the selection of the bit line corresponding to the faulty column address FCA and instead selects a redundant bit line corresponding to the redundant column address RCA. Therefore, a redundant cell corresponding to the redundant column address RCA is selected instead of the memory cell corresponding to the faulty column address FCA.

[0126] Figure 10 This is a diagram illustrating a method for testing a memory device according to an embodiment.

[0127] Reference Figure 2 , Figure 3 , Figure 6 and Figure 10 The BISR control circuit 128 and BIRA circuit 220 performed the following: Figure 6 After the BISR operation in S650, operation S1010 for verifying the repair operation can be performed.

[0128] Reference Figure 10 In operation S1020, if the MBIST section retest option of operation S310 is set, the method proceeds to operation S1030. Otherwise, the method proceeds to operation S1040.

[0129] In operation S1030, the MBIST circuit 126 can perform partial cell inspection to test defective cells or areas containing defective cells in each of the first memory bank BANK1 to the fourth memory bank BANK4. The MBIST circuit 126 can perform the partial cell inspection of operation S1030 in DDR test mode.

[0130] In operation S1040, the MBIST circuit 126 can perform a full cell check to test all memory cells from the first memory bank BANK1 to the fourth memory bank BANK4. The MBIST circuit 126 can perform the full cell check of operation S1040 in PBT test mode.

[0131] Figure 11 This illustrates an embodiment according to another embodiment. Figure 1 A block diagram of a memory device in a memory system. Figure 11 The memory device 120a and Figure 2 The difference between memory device 120 and MBIST circuit 126 is that MBIST circuit 126 also includes input / output path test circuit 129. In addition to the following... Figure 11 Within the scope of the conflicting descriptions, the above regarding Figure 2 The description of the memory device 120 is also applicable to Figure 11 Memory device 120a. (The following is omitted: The pair with the above pair...) Figure 2 The memory device 120 is described in the same way. Figure 11 Description of memory device 120a.

[0132] Reference Figure 1 and Figure 11 The MBIST circuit 126 can test memory interactions at the physical layer interconnecting the memory device 120a and the memory controller 110. The MBIST circuit 126 may include an input / output path test circuit 129, which tests input / output paths including signal lines connected between pins of the memory interface 130. DDR input / output signals I / O_DDRS for transmitting unidirectional single-signal information or bidirectional data transmission can be sent and received via the signal lines.

[0133] The input / output path test circuit 129 can provide DDR test results for the memory device 120a as the DDR input / output signal I / O_DDRS. The input / output path test circuit 129 can use the DDR input / output signal I / O_DDRS to test the architectural requirements of the memory PHY 112. The architectural requirements of the memory PHY 112 may include DC parameters (such as the voltage levels of the input / output signals and their rise and fall times) and AC parameters (such as the memory access time, setup time, and hold time for the input / output signals).

[0134] Figure 12 This is a block diagram illustrating an example of a memory device according to an embodiment.

[0135] Reference Figure 12 The memory device 120b may include a first set of dies 1210 and a second set of dies 1220, which use MBIST circuitry 126 in a stacked chip structure to provide fault analysis and repair capabilities. The memory device 120b may be implemented as an HBM structure.

[0136] The first set of dies 1210 may include at least one buffer die 1211. The second set of dies 1220 is stacked on top of the first set of dies 1210 and may include multiple memory dies 1220-1, 1220-2, ..., and 1220-p that exchange control signals and / or data with the first set of dies 1210 via multiple through-silicon via (TSV) lines 1232. The TSV lines 1232 may be electrically connected to microbumps (MCBs) formed between the memory dies 1220-1, 1220-2, ..., and 1220-p. At least one of the memory dies 1220-1, 1220-2, ..., and 1220-p may include multiple memory banks, and each memory bank may include DRAM cells, each DRAM cell including an access transistor and a storage capacitor.

[0137] The buffer die 1211 may include the above reference. Figures 1 to 12The MBIST circuit 126 is described. The MBIST circuit 126 may include a TPG circuit 127, which generates a DDR test pattern or a PBT test pattern and performs PBT tests on memory dies 1220-1, 1220-2, ..., and 1220-p using the PBT test pattern, or performs DDR tests on memory dies 1220-1, 1220-2, ..., and 1220-p using the DDR test pattern. The MBIST circuit 126 may include a BISR control circuit 128, which outputs a BISR signal indicating that a faulty cell has been detected as a result of a PBT test or DDR test, in response to a fault marker signal indicating that a faulty cell has been detected. This BISR control circuit 128 is responsible for performing a repair operation to replace the defective cell with a redundant cell.

[0138] Memory dies 1220-1, 1220-2, ..., and 1220-p may each include a BIRA circuit 220, which performs a repair operation to replace defective cells detected in PBT or DDR tests on multiple memory banks with redundant cells, and stores information about the addresses of the faulty cells and the redundant cells in the AST. The TPG circuit 127 can perform a retest to verify the repair operation performed by the BIRA circuit 220, and can perform DDR tests on some memory cells, including the faulty cells, during the retest.

[0139] Figure 13 This is a block diagram illustrating a system 1000 including a memory device according to an embodiment.

[0140] Reference Figure 13 System 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAM 1500a and 1500b, flash memory devices 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor (AP) 1800. System 1000 may be implemented as a laptop computer, mobile phone, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, system 1000 may be implemented as a server or desktop PC.

[0141] Camera 1100 can capture still images or videos under user control and can store the captured image / video data or send the captured image / video data to display 1200. Audio processor 1300 can process audio data or network content included in flash memory devices 1600a and 1600b. Modem 1400 can modulate and transmit signals for wired / wireless data transmission / reception, and the modulated signals can be demodulated by a receiver to recover the original signals. I / O devices 1700a and 1700b may include devices that provide digital input and / or digital output functions, such as Universal Serial Bus (USB), memory, digital camera, Secure Digital (SD) card, Digital Universal Optical Disc (DVD), network adapter, touch screen, etc.

[0142] AP 1800 can control the overall operation of system 1000. AP 1800 can control display 1200, displaying portions of the contents stored in flash memory devices 1600a and 1600b on display 1200. When user input is received through I / O devices 1700a and 1700b, AP 1800 can perform control operations corresponding to the user input. AP 1800 may include an accelerator block, which is circuitry dedicated to computing artificial intelligence (AI) data, or may include an accelerator chip 1820 separate from AP 1800. DRAM 1500b may be additionally disposed in the accelerator block or accelerator chip (i.e., accelerator) 1820. An accelerator is a functional block dedicated to performing specific functions of AP 1800 and may include a GPU, a neural processing unit (NPU), and a data processing unit (DPU). The GPU is a functional block dedicated to processing graphics data, the NPU is a block dedicated to AI computation and inference, and the DPU is a block dedicated to data transmission.

[0143] System 1000 may include multiple DRAMs 1500a and 1500b. AP 1800 can establish a DRAM interface protocol and communicate with DRAMs 1500a and 1500b to control them via commands compliant with Joint Electronic Devices Engineering Committee (JEDEC) standards and Mode Register (MRS) settings, or to use company-specific functions (e.g., low-voltage / high-speed / reliability and Cyclic Redundancy Check (CRC) / Error Correction Code (ECC) functions). For example, AP 1800 can communicate with DRAM 1500a via a JEDEC-compliant interface (e.g., LPDDR4 and LPDDR5), and accelerator block or accelerator chip 1820 can be configured and use a new DRAM interface protocol to control DRAM 1500b for the accelerator, which has a larger bandwidth than DRAM 1500a.

[0144] although Figure 13 Only DRAMs 1500a and 1500b are shown, but the inventive concept is not limited thereto. Any memory such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM can be used, provided that the bandwidth, response speed, and voltage conditions of AP 1800 or accelerator chip 1820 are met. DRAMs 1500a and 1500b have relatively lower latency and bandwidth than I / O devices 1700a and 1700b or flash memory devices 1600a and 1600b. When system 1000 is powered on and OS and application data are loaded into system 1000, DRAMs 1500a and 1500b are initialized, and therefore DRAMs 1500a and 1500b can be used as temporary storage for OS and application data or as execution space for various software codes.

[0145] In DRAMs 1500a and 1500b, arithmetic operations (e.g., addition, subtraction, multiplication, and division), vector calculations, address calculations, or Fast Fourier Transform (FFT) calculations can be performed. Furthermore, in DRAMs 1500a and 1500b, functions for inference operations can be performed. Here, inference can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm can include training operations for learning a model from various data and inference operations for recognizing data using the trained model. According to an embodiment, an image captured by a user via camera 1100 is signal processed and stored in DRAM 1500b, and the accelerator block or accelerator chip 1820 can use the data stored in DRAM 1500b and the inference functions to perform AI data computation for recognizing data.

[0146] DRAM 1500a and 1500b can each include the components mentioned above. Figures 1 to 12 The description includes multiple memory banks and MBIST circuitry. The MBIST circuitry can generate DDR test patterns or PBT test patterns, perform PBT tests on the memory banks using the PBT test patterns, or perform DDR tests on the memory banks using the DDR test patterns. When a defective cell is detected as a result of the PBT or DDR test, a repair operation is performed to replace the faulty cell with a redundant cell. A retest is then performed to verify the repair operation, and during the retest, DDR tests are performed on some of the memory cells, including the defective cell. Furthermore, the MBIST circuitry can use the results of the DDR tests to test the architectural requirements of the memory physical layer (PHY) included in the memory controllers connected to DRAM 1500a and 1500b.

[0147] System 1000 may include multiple memory devices or multiple flash memory devices 1600a and 1600b with a capacity greater than that of DRAM 1500a and 1500b. Accelerator block or accelerator chip 1820 may use flash memory devices 1600a and 1600b to perform training operations and AI data computations. In embodiments, flash memory devices 1600a and 1600b can more efficiently perform training and inference operations for AI data computations, which are performed by AP 1800 and / or accelerator chip 1820 using computing power provided in memory controller 1610. Flash memory devices 1600a and 1600b may store images captured by camera 1100 or data transmitted via a data network. For example, flash memory devices 1600a and 1600b may store augmented reality / virtual reality content, high-definition (HD) content, or ultra-high-definition (UHD) content.

[0148] Although the inventive concept has been specifically shown and described with reference to one or more embodiments and accompanying drawings, the present disclosure is not limited thereto, and it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A method of testing a memory device, the memory device comprising a plurality of memory banks and a memory built-in self-test circuit, wherein, The plurality of storage banks include a plurality of memory cells, and the memory has a built-in self-test circuit to perform a double data rate test or a parallel bit test, the method comprising: Configure built-in self-test options for the memory, including a double data rate test mode and a parallel bit test mode; Based on setting the parallel bit test mode to the memory's built-in self-test option, the parallel bit test is performed on the multiple memory banks; Based on setting the double data rate test mode to the built-in self-test option of the memory, the double data rate test is performed on one memory selected from the plurality of memory banks; Based on the detection of a defective cell as a result of the double data rate test or the parallel bit test, a repair operation for repairing the defective cell with redundant cells is performed via the memory's built-in self-test circuit; and A retest for verifying the repair operation is performed via the memory's built-in self-test circuitry, wherein the retest is performed on one or more memory cells, including the defective cell, among the plurality of memory cells.

2. The method of claim 1, further comprising generating an internal clock signal having the highest frequency used in testing the operation of the memory device. wherein The memory's built-in self-test circuit is configured to perform the parallel bit test or the double data rate test using the internal clock signal.

3. The method of claim 1, further comprising providing information about the defective cell to a memory controller connected to the memory device via the memory-built-in self-test circuit. wherein The defective unit is detected by comparing the logic state output from each of the plurality of memory units in response to the same write data input to each of the plurality of memory units.

4. The method of claim 1, wherein, The built-in memory self-test options also include a built-in memory self-test repair option for repairing the defective unit and a built-in memory self-test automatic repair option for automatically repairing the defective unit.

5. The method of claim 1, wherein, Performing the parallel bit test includes: Multiple parallel bit test patterns are generated by the test pattern generation circuit of the built-in self-test circuit of the memory. The parallel bit test is performed on the plurality of memory banks by using the enabled pattern among the plurality of parallel bit test test patterns; and The parallel bit test is not performed on the multiple memory banks by using the disabled pattern in the multiple parallel bit test test pattern.

6. The method of claim 1, wherein, Performing the double data rate test includes: Multiple double data rate test patterns are generated by the test pattern generation circuit of the built-in self-test circuit of the memory. The double data rate test is performed on a selected memory bank by using the enabled pattern among the plurality of double data rate test patterns; and The double data rate test is not performed on the selected memory bank by using a disabled pattern among the plurality of double data rate test patterns.

7. The method of claim 1, wherein, The repair operation performed via the built-in self-test circuit of the memory for repairing the defective unit with the redundant unit includes: The output indicates that a fault marker signal has been detected for the defective unit; Output the fault cell address of the defective cell; In response to the fault marking signal, the fault row address and fault column address included in the fault cell address are repaired using redundant row addresses and redundant column addresses; and The fault row address, the fault column address, the redundant row address corresponding to the fault row address, and the redundant column address corresponding to the fault column address are stored in an address storage table.

8. The method of claim 1, wherein, During the retest performed by the memory's built-in self-test circuit to verify the repair operation, the double data rate test is performed on the one or more memory cells including the defective cell.

9. The method of claim 1, wherein, During the retest performed by the memory-built-in self-test circuit to verify the repair operation, the parallel bit test is performed on all of the plurality of memory cells of the plurality of memory banks.

10. The method of claim 1, further comprising testing the architectural requirements of the memory physical layer included in the memory controller connected to the memory device by using the results of the double data rate test through the memory-built-in self-test circuit.

11. The method of claim 10, wherein, The architecture requirements of the memory physical layer include DC parameters and AC parameters. The DC parameters include the voltage level, rise time, and fall time of the input / output signals provided to the signal lines connected to the memory physical layer. The AC parameters include the memory access time, setup time, and hold time for the input / output signals.

12. A memory-in-memory self-test circuit for testing a memory device comprising multiple memory banks, the memory-in-memory self-test circuit comprising: A test pattern generating circuit is configured to generate multiple test patterns, including a double data rate test pattern and a parallel bit test pattern. The built-in redundancy analysis circuit is configured to perform a repair operation to replace defective cells detected in a parallel bit test or double data rate test of the memory device with redundant cells, and to store information about the address of the faulty cell and the address of the redundant cell in an address storage table. as well as The built-in self-healing control circuit is configured to output a built-in self-healing signal in response to a fault marker signal indicating that the defective unit has been detected, in order to perform the repair operation. The test pattern generation circuit is further configured to perform a retest on one or more memory cells, including the defective cell, among a plurality of memory cells to verify the repair operation performed by the built-in redundancy analysis circuit.

13. A memory device, comprising: Multiple storage banks, which include multiple memory units; A control circuit configured to control the operation of the memory device, wherein the control circuit includes a mode register and a test mode register, the mode register providing operating options for the memory device, and the test mode register providing test mode options including a parallel bit test mode and a double data rate test mode; and The memory has a built-in self-test circuit configured to test the plurality of memory banks in either the double data rate test mode or the parallel bit test mode. The built-in self-test circuitry of the memory is further configured to perform a repair operation to replace a defective cell detected in a parallel bit test or a double data rate test with a redundant cell, and to perform a retest on one or more memory cells, including the defective cell, among the plurality of memory cells to verify the repair operation.

14. The memory device of claim 13, further comprising a clock generator configured to generate an internal clock signal having the highest frequency used in testing the operation of the memory device. wherein The clock frequency of the internal clock signal is higher than the clock frequency of the external clock signal applied to the memory device. The external clock signal is used in the normal double data rate mode of the memory device, and The internal clock signal is used in the parallel bit test mode or the double data rate test mode.

15. The memory device of claim 13, further comprising a test pattern generating circuit configured to generate a plurality of test patterns. wherein The multiple test patterns include a double data rate test pattern and a parallel bit test pattern.

16. The memory device of claim 15, wherein, The test pattern generation circuit is also configured to perform the double data rate test on one or more memory cells, including the defective cell, among the plurality of memory cells during the retest by using the double data rate test pattern.

17. The memory device of claim 15, wherein, The test pattern generation circuit is also configured to perform the parallel bit test on all of the plurality of memory cells of the plurality of memory banks during the retest by using the parallel bit test test pattern.

18. The memory device of claim 13, further comprising a built-in self-repair control circuit configured to output a built-in self-repair signal in response to a fault marker signal indicating that the defective cell has been detected, to perform the repair operation. wherein The defective unit is detected by comparing the logic state output from each of the plurality of memory units in response to the same write data input to each of the plurality of memory units.

19. The memory device of claim 13, further comprising a built-in redundancy analysis circuit, the built-in redundancy analysis circuit being configured to: Perform the repair operation and store information about the faulty unit address and redundant unit address in the address storage table; and Information about the address storage table is output to a memory controller external to the memory device.

20. The memory device of claim 13, further comprising an input / output path test circuit configured to test the architectural requirements of a memory physical layer included in a memory controller connected to the memory device using the results of the double data rate test. wherein, The architecture requirements of the memory physical layer include DC parameters and AC parameters. The DC parameters include the voltage level, rise time, and fall time of the input / output signals provided to the signal lines connected to the memory physical layer. The AC parameters include the memory access time, setup time, and hold time for the input / output signals.

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