Semiconductor structure, method of manufacturing the same and memory device

Abstract

This invention relates to a method for fabricating a semiconductor structure, comprising: providing a substrate; forming an initial structure on the substrate, the initial structure including a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, the first gate layer having a first thickness; and oxidizing the initial structure to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer, the second thickness being less than the first thickness. The above-described method for fabricating a semiconductor structure, by oxidizing the first gate layer in the initial structure, grows a high-quality second gate dielectric layer on the surface of the first gate layer, eliminating dangling bonds at the interface between the first gate layer and the first gate dielectric layer, thereby improving the film quality at the interface.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a semiconductor, its fabrication method, and a semiconductor device. Background Technology

[0002] When a gate layer is fabricated on the surface of a gate dielectric layer, the periodicity of the gate layer lattice is suddenly interrupted due to the interface characteristics of the gate layer and the gate dielectric layer. This results in dangling bonds at the interface between the gate layer and the gate dielectric layer, which allows for electron energy levels in the bandgap. This has an adverse effect on the performance improvement and stability of semiconductor devices. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor structure, its fabrication method, and a storage device to address the above-mentioned problems.

[0004] This application discloses a method for fabricating a semiconductor structure, comprising: providing a substrate; forming an initial structure on the substrate, the initial structure including a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, the first gate layer having a first thickness; performing an oxidation treatment on the initial structure to form a second gate dielectric layer with a second thickness between the first gate dielectric layer and the first gate layer, the second thickness being less than the first thickness.

[0005] The above-described semiconductor structure fabrication method, by oxidizing the first gate layer in the initial structure, grows a high-quality second gate dielectric layer on the surface of the first gate layer. This eliminates dangling bonds at the interface between the first gate layer and the first gate dielectric layer, improves the film quality at the interface, and reduces gate leakage current and parasitic capacitance. Furthermore, the second thickness is limited to be less than the first thickness to ensure that the first gate layer is not completely oxidized after the oxidation process.

[0006] In one embodiment, the first gate dielectric layer is formed using an in-situ water vapor growth process.

[0007] In one embodiment, oxidizing the initial structure to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer includes oxidizing the surface of the first gate layer facing the first gate dielectric layer to form the second gate dielectric layer.

[0008] In one embodiment, the initial structure is oxidized to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer, including:

[0009] In one embodiment, the first gate layer is oxidized, a second gate dielectric layer with a second thickness is formed on the interface of the first gate layer facing the first gate dielectric layer, and an oxide layer with a third thickness is formed on the interface of the first gate layer away from the first gate dielectric layer, the third thickness being greater than the second thickness, and the sum of the third thickness and the second thickness being less than the first thickness; the oxide layer is then removed.

[0010] By controlling the sum of the third thickness and the second thickness to be less than the first thickness, it can be ensured that the unoxidized portion is retained in the first gate layer. This allows for the continued deposition of gate material on the first gate surface after the oxide layer is removed, resulting in a gate of the target thickness.

[0011] In one embodiment, after removing the oxide layer, the method further includes forming a second gate layer on the upper surface of the first gate layer.

[0012] In one embodiment, the step of forming the second gate layer includes: forming a second gate material layer on the upper surface of the first gate layer; annealing the second gate material layer; and etching the second gate material layer to obtain the second gate layer.

[0013] In one embodiment, the first gate layer and the second gate layer include a polysilicon layer, and the first gate dielectric layer, the second gate dielectric layer and the oxide layer include a silicon oxide layer.

[0014] In one embodiment, the first thickness includes 5 nm to 100 nm, and the second thickness includes 0.1 nm to 10 nm.

[0015] In one embodiment, the oxidation treatment step includes: providing a reaction chamber and placing the initial structure inside the reaction chamber; introducing a reaction gas into the reaction chamber, the reaction gas including hydrogen and oxygen, wherein the volume percentage of hydrogen in the reaction gas is 2% to 3% and the volume percentage of oxygen is 97% to 98%; setting the temperature of the reaction chamber to a reaction temperature of 900°C to 1100°C, and reacting at the reaction temperature for 40 to 50 seconds.

[0016] In one embodiment, the oxidation process includes a cyclic oxidation process, which includes: performing a first oxidation process on an initial structure to form a second gate dielectric layer with a second thickness on the interface of the first gate layer facing the first gate dielectric layer, and forming a first oxide layer with a third thickness on the interface of the first gate layer away from the first gate dielectric layer, wherein the sum of the third thickness and the second thickness is less than the first thickness; removing the first oxide layer to obtain an intermediate structure; performing a second oxidation process on the intermediate structure to form a third gate dielectric layer with a fourth thickness on the interface of the first gate layer facing the first gate dielectric layer, and forming a second oxide layer with a fifth thickness on the interface of the first gate layer away from the first gate dielectric layer, wherein the sum of the second thickness, third thickness, fourth thickness, and fifth thickness is less than the first thickness; removing the second oxide layer; and repeating the above oxidation process until the dielectric layer thickness between the first gate dielectric layer and the first gate layer reaches the target thickness.

[0017] In one embodiment, the single oxidation process in the cyclic oxidation process includes: providing a reaction chamber and placing the initial structure or intermediate structure inside the reaction chamber; introducing a reaction gas into the reaction chamber, the reaction gas including hydrogen and oxygen, wherein the volume percentage of hydrogen in the reaction gas is 2% to 3% and the volume percentage of oxygen is 97% to 98%; setting the temperature of the reaction chamber to a reaction temperature of 900°C to 1100°C, and reacting at the reaction temperature for 8 to 10 seconds.

[0018] The above-mentioned semiconductor structure fabrication method can better control the thickness of the newly generated gate dielectric layer at the interface by reducing the time of a single oxidation process and increasing the number of oxidation processes, thus preventing over-oxidation and ensuring that the unoxidized portion is retained in the first gate layer.

[0019] In one embodiment, after forming the initial structure on the substrate, the method further includes annealing the first gate layer.

[0020] In one embodiment, after forming the second gate dielectric layer, the process further includes annealing the second gate dielectric layer.

[0021] This application also discloses a semiconductor structure prepared by the semiconductor structure preparation method of any of the above embodiments.

[0022] The aforementioned semiconductor structure, using the aforementioned semiconductor structure fabrication method, eliminates dangling bonds and grain boundary defects at the gate and gate dielectric layer interface, improves film quality, and reduces gate leakage current and parasitic capacitance.

[0023] This application also discloses a storage device including the semiconductor structure described in the above embodiments. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.

[0025] Figure 2 This is a schematic diagram of the cross-sectional structure of a substrate provided in one embodiment of this application.

[0026] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure obtained after forming an initial structure on a substrate in one embodiment of this application.

[0027] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming an oxide layer and a second gate dielectric layer in one embodiment of this application.

[0028] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure obtained after removing the oxide layer in one embodiment of this application.

[0029] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming the second gate layer in one embodiment of this application.

[0030] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure obtained after the first gate layer undergoes a second oxidation treatment in one embodiment of this application.

[0031] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure obtained after removing the second oxide layer in one embodiment of this application.

[0032] Explanation of icon numbers:

[0033] 10. Substrate; 11. Doped substrate; 12. Well region; 21. First gate dielectric layer; 22. First gate layer; 23. Second gate dielectric layer; 24. First oxide layer; 25. Second gate layer; 26. Third gate dielectric layer; 27. Second oxide layer. Detailed Implementation

[0034] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0037] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0038] One embodiment of this application discloses a method for fabricating a semiconductor structure, such as... Figure 1 As shown, it includes:

[0039] S10: Provides a substrate;

[0040] S20: An initial structure is formed on a substrate, the initial structure including a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, the first gate layer having a first thickness;

[0041] S30: The initial structure is oxidized to form a second gate dielectric layer with a second thickness between the first gate dielectric layer and the first gate layer. The second thickness is less than the first thickness.

[0042] A transistor structure includes a gate dielectric layer and a gate conductive layer located on top of the gate dielectric layer. The interface properties between the gate dielectric layer and the gate conductive layer are important factors affecting transistor performance. For example, silicon dioxide thin film, as a natural oxide of silicon, is an important gate dielectric layer material for silicon-based MOSFETs (metal-oxide-semiconductor field-effect transistors). However, due to the different interface characteristics between SiO2 and Si, dangling bonds exist at the interface between the gate and the gate dielectric layer, resulting in permitted electronic energy levels in the bandgap, which adversely affects the improvement and stability of semiconductor device performance. The method in the embodiments of this application can effectively solve the above problems.

[0043] In step S10, the substrate may include, but is not limited to, a silicon-based substrate. For example, such as... Figure 2 As shown, the substrate 10 includes a doped substrate 11 and a well region 12. As an example, the doped substrate 11 is a P-type doped substrate, and the well region 12 is a P-type well region. In other embodiments, the doped substrate 11 may also be an N-type doped substrate, and the well region 12 may be an N-type well region. This application does not limit the doping type of the well region 12 and the doped substrate 11 in the substrate 10.

[0044] In step S20, the initial structure formed on the substrate 10 is as follows: Figure 3 As shown. Specifically, the step of forming the initial structure on the substrate 10 includes:

[0045] S21: A first gate dielectric layer 21 is formed on the upper surface of the substrate 10.

[0046] For example, the first gate dielectric layer 21 may include, but is not limited to, a silicon oxide layer. Methods for forming the first gate dielectric layer 21 include chemical vapor deposition, physical vapor deposition, and atomic layer deposition. In other embodiments, the first gate dielectric layer 21 may also be prepared using in-situ steam generation (ISSG).

[0047] S22: A first gate layer 22 is formed on the upper surface of the first gate dielectric layer 21.

[0048] The first gate layer 22 may include, but is not limited to, a polysilicon layer. For example, a polysilicon layer of a first thickness may be deposited on the upper surface of the first gate dielectric layer 21. The first thickness may be 5 nm to 100 nm, such as 5 nm, 10 nm, 30 nm, 50 nm, or 100 nm. In one embodiment, after forming the first gate layer 22 of the first thickness, the first gate layer 22 is annealed to improve the gate dopant activation rate and gate quality.

[0049] In step S30, by oxidizing the initial structure, a second gate dielectric layer of a second thickness can be formed between the first gate dielectric layer 21 and the first gate layer 22. The second thickness is less than the first thickness.

[0050] Specifically, in some embodiments, the step of forming the second gate dielectric layer includes:

[0051] S31: The first gate layer 22 is oxidized, and a second gate dielectric layer 23 with a second thickness is formed on the interface of the first gate layer 22 facing the first gate dielectric layer 21. A first oxide layer 24 with a third thickness is formed on the interface of the first gate layer 22 away from the first gate dielectric layer 21. The third thickness is greater than the second thickness, and the sum of the third thickness and the second thickness is less than the first thickness. Figure 4As shown.

[0052] For example, the method for oxidizing the first gate layer 22 may include, but is not limited to, the ISSG process. Specifically, during the oxidation process of the initial structure using the ISSG process, a first oxide layer 24 is formed on both the upper surface and the side surface of the first gate layer 22, and a second gate dielectric layer 23 is formed at the interface between the first gate layer 22 and the first gate dielectric layer 21, such as... Figure 4 As shown. For example, the first gate layer 22 is a polysilicon layer, the second gate dielectric layer 23 and the first oxide layer 24 are silicon oxide layers. Since the second gate dielectric layer 23 is obtained by silicon oxidation on the surface of the polysilicon layer, there are no interface defects and dangling bonds between the second gate dielectric layer 23 and the first gate layer 22, thus eliminating the interface defects and dangling bonds between the first gate dielectric layer 21 and the first gate layer 22 in the initial structure.

[0053] Furthermore, in this embodiment, the sum of the third thickness and the second thickness is less than the first thickness. This is to prevent the first gate layer 22 from being completely oxidized. If the first gate layer 22 is completely oxidized, then when the gate thickness needs to be increased in subsequent steps, a polysilicon material layer can only be deposited on the surface of the silicon oxide layer. This would form a new Si-SiO2 interface, generating new interface defects and dangling bonds. Therefore, by controlling the sum of the third thickness and the second thickness to be less than the first thickness, it can be ensured that the initial structure retains a certain thickness of unoxidized polysilicon layer after oxidation treatment, avoiding the generation of new interface defects and dangling bonds when increasing the gate layer thickness in subsequent steps.

[0054] For example, the second thickness can be 0.1 nm to 10 nm. Specifically, the thickness of the second gate dielectric layer 23 is related to the region where the semiconductor structure is located. When the semiconductor structure is located in the active region, the thickness of the second gate dielectric layer 23 is smaller, for example, 0.1 nm to 5 nm, such as 0.1 nm, 1 nm, 3 nm, or 5 nm. When the semiconductor structure is located in the peripheral region, the thickness of the second gate dielectric layer 23 is larger, for example, 6 nm to 10 nm, such as 6 nm, 8 nm, or 10 nm. For example, the third thickness can be 5 nm to 50 nm, such as 5 nm, 10 nm, 20 nm, 30 nm, or 50 nm.

[0055] S32: Remove the first oxide layer 24.

[0056] For example, an etching process can be used to remove the first oxide layer 24 on the upper surface and side surfaces of the first gate layer 22, to obtain, as shown below. Figure 5 The semiconductor structure shown.

[0057] In some embodiments, the surface of the first gate layer 22 facing the first gate dielectric layer 21 is oxidized to form the second gate dielectric layer 23, such as... Figure 5 As shown.

[0058] For example, the oxidation process includes, but is not limited to, the ISSG process. When the first gate layer 22 is a polysilicon layer, the formed second gate dielectric layer 23 is a silicon oxide layer. Since the second gate dielectric layer 23 is obtained by silicon oxidation on the surface of the polysilicon layer, there are no interface defects or dangling bonds between the second gate dielectric layer 23 and the first gate layer 22. In one embodiment, after forming the second gate dielectric layer 23, an annealing process is further included.

[0059] In one embodiment, after removing the first oxide layer 24, the method further includes:

[0060] S40: A second gate layer 25 is formed on the upper surface of the first gate layer 22, such as... Figure 6 As shown.

[0061] The thickness of the first gate layer 22 in the initial structure is reduced after oxidation. In order to obtain the gate of the required thickness, the gate thickness needs to be increased based on the first gate layer 22. For example, a second gate layer 25 can be formed on the upper surface of the first gate layer 22 to form the final semiconductor structure.

[0062] As an example, the final semiconductor structure can be the MOS structure in a MOSFET (metal-oxide-semiconductor field-effect transistor).

[0063] For example, the step of forming the second gate layer 25 includes:

[0064] S41: A second gate material layer is formed on the upper surface of the first gate layer 22.

[0065] For example, both the second gate material layer and the first gate layer 22 are polysilicon layers.

[0066] S42: Anneal the second gate material layer.

[0067] Annealing can improve the activation rate of gate dopants and gate quality.

[0068] S43: Etch the second gate material layer to obtain the second gate layer 25.

[0069] For example, an etching process is used to remove a polysilicon layer exceeding the required thickness to obtain a second gate layer 25. In other embodiments, a planarization process may also be performed on the upper surface of the second gate layer 25.

[0070] In one embodiment, the step of oxidizing the initial structure includes: providing a reaction chamber and placing the initial structure inside the reaction chamber; introducing a reaction gas into the reaction chamber, the reaction gas comprising hydrogen and oxygen, wherein the volume percentage of hydrogen in the reaction gas is 2% to 3%, for example 2%, 2.5% or 3%; and the volume percentage of oxygen is 97% to 98%, for example 97%, 97.5% or 98%; setting the temperature of the reaction chamber to a reaction temperature of 900°C to 1100°C, for example 900°C, 1000°C or 1100°C, and reacting at the reaction temperature for 40s to 50s, for example 40s, 45s or 50s.

[0071] As an example, the specific parameters for oxidizing the initial structure can be: 2.5% hydrogen by volume, 97.5% oxygen by volume, 1000℃ reaction temperature, and 45s reaction time.

[0072] The above-described semiconductor structure fabrication method, by oxidizing the first gate layer in the initial structure, grows a high-quality second gate dielectric layer on the surface of the first gate layer. This eliminates dangling bonds at the interface between the first gate layer and the first gate dielectric layer, improves the film quality at the interface, and reduces gate leakage current and parasitic capacitance. Furthermore, the second thickness is limited to be less than the first thickness to ensure that the first gate layer is not completely oxidized after the oxidation process.

[0073] In the aforementioned embodiments, the initial structure undergoes a single oxidation treatment. In one embodiment, the oxidation treatment may further include a cyclic oxidation process. A cyclic oxidation process involves performing multiple oxidation treatments on the initial structure while keeping other parameters constant, thus shortening the time of each single oxidation treatment.

[0074] For example, the time for a single oxidation process can be 1 / 3, 1 / 5, or 1 / 10 of the time for a single oxidation process in the aforementioned embodiments. For instance, in the aforementioned embodiments, the initial structure is oxidized only once, with a processing time of 40-50 seconds. Then, in the cyclic oxidation process, the time for each oxidation process can be, for example, 12-16 seconds, 8-10 seconds, or 4-5 seconds. In other embodiments, the total time of the cyclic oxidation process remains constant, or is flexibly adjusted according to the thickness of the dielectric layer formed between the first gate layer 22 and the first gate dielectric layer 21.

[0075] In one embodiment, as an example, the time for each oxidation treatment is set to 8 seconds, and the steps of the cyclic oxidation process on the initial structure are as follows:

[0076] S311: The initial structure undergoes a first oxidation treatment. A second gate dielectric layer 23 with a second thickness is formed on the interface of the first gate layer 22 facing the first gate dielectric layer 21. A first oxide layer 24 with a third thickness is formed on the interface of the first gate layer 22 away from the first gate dielectric layer 21. The sum of the third thickness and the second thickness is less than the first thickness. Figure 4 As shown;

[0077] S312: Remove the first oxide layer 24 to obtain the intermediate structure, such as Figure 5 As shown;

[0078] S313: A second oxidation process is performed on the intermediate structure. A third gate dielectric layer 26 with a fourth thickness is formed on the interface of the first gate layer 22 facing the first gate dielectric layer 21, and a second oxide layer 27 with a fifth thickness is formed on the interface of the first gate layer 22 away from the first gate dielectric layer 21; the sum of the second, third, fourth, and fifth thicknesses is less than the first thickness, such as... Figure 7 As shown;

[0079] S314: Remove the second oxide layer 27, such as Figure 8 As shown;

[0080] S315: Repeat the above oxidation process until the thickness of the dielectric layer between the first gate dielectric layer 21 and the first gate layer 22 reaches the target thickness.

[0081] The target thickness can be 1nm-10nm, for example, 1nm, 3nm, 5nm, 6nm, 8nm, or 10nm. For example, the target thickness is also related to the region where the semiconductor structure is located. When the semiconductor structure is located in the active region, the target thickness is smaller, for example, 1nm, 3nm, or 5nm. When the semiconductor structure is located in the peripheral region, the target thickness is larger, for example, 6nm, 8nm, or 10nm. In other embodiments, the target thickness is also related to the thickness of the first gate dielectric layer 21 in the initial structure. When the thickness of the first gate dielectric layer 21 is larger, the target thickness can be reduced accordingly.

[0082] Because the single oxidation process is short, the second and third thicknesses in this embodiment are both smaller than those in the previous embodiments. Furthermore, after the first oxidation process, although the thickness of the first oxide layer 24 (the third thickness) is still greater than the thickness of the second gate dielectric layer 23 (the second thickness), the difference between the third and second thicknesses is reduced. Similarly, after removing the first oxide layer 24 and performing a second oxidation process on the intermediate structure, a third gate dielectric layer 26 with a fourth thickness and a second oxide layer 27 with a fifth thickness are formed, wherein the fourth thickness is the same as or close to the second thickness, and the fifth thickness is the same as or close to the third thickness. The dielectric layer thickness between the first gate dielectric layer 21 and the first gate electrode layer 22 is the sum of the fourth and second thicknesses.

[0083] In the cyclic oxidation process, by reducing the time of each oxidation treatment, the thickness of the newly formed oxide layer and the newly formed gate dielectric layer can be reduced, as can the thickness difference between them. This allows for better control of the oxidation degree of the first gate layer 22 in each oxidation treatment, preventing over-oxidation. Furthermore, by controlling the sum of the thicknesses of the oxide layer and the gate dielectric layer formed after each oxidation treatment to be less than a first thickness, it can be ensured that unoxidized gate layers are retained in the first gate layer 22.

[0084] As an example, the steps of a single oxidation treatment in a cyclic oxidation process are as follows: providing a reaction chamber, placing the initial structure or intermediate structure inside the reaction chamber; introducing a reaction gas into the reaction chamber, the reaction gas comprising hydrogen and oxygen, wherein the volume percentage of hydrogen in the reaction gas is 2% to 3%, for example 2%, 2.5%, or 3%; and the volume percentage of oxygen is 97% to 98%, for example 97%, 97.5%, or 98%; setting the temperature of the reaction chamber to a reaction temperature of 900°C to 1100°C, for example 900°C, 1000°C, or 1100°C, and reacting at the reaction temperature for 8 to 10 seconds, for example 8 seconds, 9 seconds, or 10 seconds. In other embodiments, the reaction time may also include 12 seconds to 16 seconds or 4 seconds to 5 seconds.

[0085] One embodiment of this application also discloses a semiconductor structure, which is prepared using the semiconductor structure preparation method described in any of the foregoing embodiments. By employing the semiconductor structure preparation method described in the foregoing embodiments, dangling bonds and grain boundary defects at the gate and gate dielectric layer interface can be eliminated, improving film quality and reducing gate leakage current and parasitic capacitance.

[0086] One embodiment of this application also discloses a storage device including the semiconductor structure described in the above embodiments. By employing the above semiconductor structure, the performance of the storage device can be improved.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; An initial structure is formed on the substrate, the initial structure including a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, the first gate layer having a first thickness; The initial structure is oxidized to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer, the second thickness being less than the first thickness. The oxidation treatment of the initial structure to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer includes: The surface of the first gate layer facing the first gate dielectric layer is oxidized to form the second gate dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first gate dielectric layer is formed using an in-situ water vapor growth process.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The oxidation treatment of the initial structure further includes: forming an oxide layer with a third thickness on the interface of the first gate layer away from the first gate dielectric layer, the third thickness being greater than the second thickness, and the sum of the third thickness and the second thickness being less than the first thickness; Remove the oxide layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, After removing the oxide layer, the process further includes: A second gate layer is formed on the upper surface of the first gate layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The step of forming the second gate layer includes: A second gate material layer is formed on the upper surface of the first gate layer; The second gate material layer is annealed. The second gate material layer is etched to obtain the second gate layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The first gate layer and the second gate layer include a polysilicon layer, and the first gate dielectric layer, the second gate dielectric layer and the oxide layer include a silicon oxide layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first thickness includes 5nm to 100nm, and the second thickness includes 0.1nm to 10nm.

8. The method for preparing a semiconductor structure according to any one of claims 1-7, characterized in that, The oxidation treatment steps include: A reaction chamber is provided, and the initial structure is placed inside the reaction chamber; A reaction gas, comprising hydrogen and oxygen, is introduced into the reaction chamber, wherein the volume percentage of hydrogen in the reaction gas is 2% to 3% and the volume percentage of oxygen is 97% to 98%. The temperature of the reaction chamber is set to the reaction temperature, which is 900℃~1100℃, and the reaction is carried out at the reaction temperature for 40s~50s.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The oxidation treatment includes a cyclic oxidation process, which includes: The initial structure is subjected to a first oxidation treatment, and a second gate dielectric layer with a second thickness is formed on the interface of the first gate layer facing the first gate dielectric layer, and a first oxide layer with a third thickness is formed on the interface of the first gate layer away from the first gate dielectric layer, wherein the sum of the third thickness and the second thickness is less than the first thickness. Remove the first oxide layer to obtain the intermediate structure; The intermediate structure undergoes a second oxidation process, forming a third gate dielectric layer with a fourth thickness at the interface of the first gate layer facing the first gate dielectric layer, and forming a second oxide layer with a fifth thickness at the interface of the first gate layer away from the first gate dielectric layer; the sum of the second thickness, the third thickness, the fourth thickness, and the fifth thickness is less than the first thickness; Remove the second oxide layer; Repeat the above oxidation process until the thickness of the dielectric layer between the first gate dielectric layer and the first gate electrode layer reaches the target thickness.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The steps of a single oxidation treatment in the cyclic oxidation process include: A reaction chamber is provided, and the initial structure or the intermediate structure is placed inside the reaction chamber; A reaction gas, comprising hydrogen and oxygen, is introduced into the reaction chamber, wherein the volume percentage of hydrogen in the reaction gas is 2% to 3% and the volume percentage of oxygen is 97% to 98%. The temperature of the reaction chamber is set to the reaction temperature, which is 900℃~1100℃, and the reaction is carried out at the reaction temperature for 8s~10s.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the initial structure on the substrate, the method further includes annealing the first gate layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, After forming the second gate dielectric layer, the process further includes annealing the second gate dielectric layer.

13. A semiconductor structure, characterized in that, The semiconductor structure was prepared using the method described in any one of claims 1-12.

14. A storage device, characterized in that, Including the semiconductor structure described in claim 13.

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