Semiconductor structure, method of forming the same and ozone cleaning apparatus

Abstract

This application discloses a semiconductor structure, its formation method, and an ozone cleaning device. The semiconductor structure formation method includes: dry etching a silicon wafer in the semiconductor structure to form a trench; cleaning the trench; forming an oxide layer on the surface of the trench; etching away the oxide layer, and forming a smooth curved surface between the bottom and sidewalls of the trench. After etching the trench, this application cleans away some of the residual silicon particles in the trench; then, it oxidizes the trench surface, forming a silicon dioxide layer on the upper half of the trench surface and the silicon particles remaining at the bottom of the trench; subsequently, by etching away this silicon dioxide layer, it is equivalent to removing part of the silicon wafer in the upper half of the trench and the silicon particles at the bottom, making the trench opening larger, thereby forming a curved surface between the sidewalls and the bottom of the trench; in this way, the oxide dielectric can be fully filled in the trench in subsequent processes without gaps, thus preventing leakage current.

Description

Technical Field

[0001] This application relates to the field of chip manufacturing technology, and in particular to a semiconductor structure, a method for forming the same, and an ozone cleaning device. Background Technology

[0002] Etching is a common process in semiconductor device manufacturing. In the manufacturing of semiconductor integrated circuits, etching is the selective removal of unwanted material from the surface of a silicon wafer using chemical or physical methods. From a process perspective, etching can be divided into wet etching and dry etching. Wet etching is characterized by isotropic etching, while dry etching uses plasma for anisotropic etching, allowing for strict control of both longitudinal and lateral etching.

[0003] There are currently three methods for trenching in semiconductor device manufacturing: wet etching, dry etching, and wet etching + dry etching. For semiconductor devices with photolithography precision below 0.18µm, dry etching is generally used for trenching. However, dry etching is anisotropic, which causes the bottom of the trench to form a 90° angle with the sidewall. This can lead to incomplete filling of the trench with oxide dielectric in subsequent processes, resulting in gaps and increased leakage current. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor structure, a method for forming the same, and an ozone cleaning device, which enables the bottom and sidewalls of the trench in the semiconductor structure to form smooth curved surfaces, allowing the oxide dielectric to be fully filled in the trench in subsequent processes without creating gaps.

[0005] This application discloses a method for forming a semiconductor structure, including:

[0006] Dry etching is performed on the silicon wafer to form trenches;

[0007] Clean the trench;

[0008] An oxide layer is formed on the surface of the trench; and

[0009] The oxide layer is etched away, and a smooth curved surface is formed between the bottom and sidewalls of the trench.

[0010] Optionally, the step of cleaning the trench includes: immersing the silicon wafer in a diluted hydrofluoric acid solution to clean the trench.

[0011] Optionally, the concentration of hydrofluoric acid in the diluted hydrofluoric acid solution is 1-2%, the silicon wafer is immersed in the diluted hydrofluoric acid solution for 20-60 seconds, and the temperature of the diluted hydrofluoric acid solution is 25±5℃.

[0012] Optionally, the step of forming an oxide layer on the surface of the trench includes:

[0013] Ozone is introduced into deionized water; and

[0014] The silicon wafer is placed in deionized water containing ozone, and an oxide layer is formed on the surface of the trench.

[0015] Optionally, the concentration of ozone in the deionized water is 1-20%.

[0016] Optionally, in the step of introducing ozone into the deionized water, the flow rate of ozone into the deionized water is 50-150 ml / min, and the introduction time is 20-60 seconds.

[0017] Optionally, the thickness of the oxide layer is 7-9 nm.

[0018] Optionally, in the step of etching away the oxide layer and forming a smooth curved surface between the bottom and sidewalls of the trench, if a smooth curved surface is not formed between the bottom and sidewalls of the trench after etching away the oxide layer, the steps of forming an oxide layer on the surface of the trench and etching the oxide layer are repeated until a smooth curved surface is formed between the bottom and sidewalls of the trench; if a smooth curved surface is formed between the bottom and sidewalls of the trench, the next process is performed.

[0019] This application also discloses a semiconductor structure, which is fabricated by the semiconductor structure formation method described above.

[0020] This application also discloses an ozone cleaning device for cleaning the aforementioned semiconductor. The ozone cleaning device includes an ozone tank, four rapid high-purity water rinsing tanks, two diluted hydrofluoric acid solution tanks, and an exhaust port. On one side of the ozone tank, two rapid high-purity water rinsing tanks and one hydrofluoric acid solution tank are provided, with the hydrofluoric acid solution tanks positioned between the two rapid high-purity water rinsing tanks. On the other side of the ozone tank, similarly, two rapid high-purity water rinsing tanks and one hydrofluoric acid solution tank are provided, with the hydrofluoric acid solution tanks positioned between the two rapid high-purity water rinsing tanks. The exhaust port is connected to each of the ozone tank, the rapid high-purity water rinsing tanks, and the diluted hydrofluoric acid solution tank.

[0021] Dry etching achieves its effect through chemical and physical processes, or the combined effect of both. The chemical process involves a chemical reaction between the silicon surface material and plasma, generating gaseous byproducts that are then removed by exhaust. The physical process involves plasma bombardment of the silicon surface, causing collisions between particles to achieve etching. This physical process is anisotropic and highly selective, etching only the silicon perpendicular to the plasma and not the protective layer. Therefore, the resulting trenches have 90° sidewalls and retain many small silicon particles. In this application, after etching the trenches, some of the residual silicon particles are cleaned away, but some adsorbed at the bottom of the trenches and... Silicon particles at corners are difficult to clean off. Next, the trench surface is oxidized, forming a silicon dioxide layer on the upper surface of the trench and on the remaining silicon particles at the bottom. Subsequently, etching away this silicon dioxide layer effectively removes part of the silicon wafer in the upper half of the trench and the silicon particles at the bottom, increasing the trench opening and creating a curved surface between the trench's sidewalls and bottom. Removing the silicon dioxide layer also performs a fine chemical polishing of the trench surface, creating a smooth curved surface between the bottom and sidewalls. This allows the oxide dielectric to fully fill the trench in subsequent processes, preventing gaps and leakage current. Attached Figure Description

[0022] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0023] Figure 1 This is a schematic diagram of an exemplary semiconductor structure;

[0024] Figure 2 This is a flowchart of a semiconductor structure formation method provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0026] Figure 4 This is a flowchart of a semiconductor structure formation method provided in another embodiment of this application;

[0027] Figure 5 This is a schematic diagram of an ozone cleaning device provided in another embodiment of this application.

[0028] Among them, 100 is a semiconductor structure; 110 is a silicon wafer; 120 is a trench; 121 is the bottom of the trench; 122 is the sidewall of the trench; 130 is an oxide dielectric layer; 200 is an ozone cleaning device; 210 is a QDR flushing tank; 220 is a DHF solution tank; 230 is an ozone tank; and 240 is an exhaust port. Detailed Implementation

[0029] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0030] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0031] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0032] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] In the fabrication of semiconductor structures, many processes require etching trenches on the silicon wafer first. For example, trenches are first etched on the silicon wafer, and then epitaxial thin film is grown on the silicon wafer and in the trenches. In this case, the role of the trenches is to reduce the generation of dislocation defects, improve the quality of epitaxial crystals, and improve the transmission characteristics of light at the dielectric interface. In addition, the shallow trench isolation (STI) process also requires trenches to be first etched on the silicon wafer, and oxide is deposited in the trenches to define the active region of the transistor.

[0034] like Figure 1 The diagram illustrates a silicon wafer in an exemplary semiconductor structure 100. The semiconductor structure 100 includes a silicon wafer 110 with trenches 120. The angle between the bottom 121 and the sidewall 122 of the trench is 90°. An oxide dielectric layer 130 is disposed on the trench 120, and voids exist between the oxide dielectric layer 130 and the trench 120. In shallow trench etching processes, dry etching is commonly used to create trenches on silicon wafers. However, dry etching is anisotropic, causing the bottom and sidewall of the trench to form a 90° angle. When oxide is subsequently deposited into the trench, the oxide dielectric cannot be completely filled because voids and air pockets remain at the junction of the sidewall and bottom of the trench. When the reverse voltage increases, the built-in electric field also increases, and the electric field concentrates in areas with voids. When the built-in electric field reaches a certain level, the air in the void areas expands and will be the first to break down the oxide dielectric layer, causing device failure. If the built-in electric field does not reach the breakdown threshold, the air in the void areas will ionize and participate in conductivity, increasing leakage current. To solve the above problems, this application provides the following technical solutions, which will be described in detail below with reference to the accompanying drawings and optional embodiments.

[0035] like Figure 2 The diagram shows a flowchart of a method for forming a semiconductor structure. As an embodiment of this application, this application discloses a method for forming a semiconductor structure, including the following steps:

[0036] S1: Dry etching is performed on the silicon wafer to form trenches;

[0037] S2: Clean the trench;

[0038] S3: An oxide layer is formed on the surface of the trench;

[0039] S4: Etch away the oxide layer and create a smooth curved surface between the bottom and sidewalls of the trench.

[0040] Dry etching is achieved through chemical and physical processes, or the combined effect of both. The chemical process involves a chemical reaction between the silicon surface material and plasma to generate gaseous byproducts that are then removed by exhaust air. The physical process involves plasma bombarding the silicon surface, causing collisions between particles to achieve etching. The physical process is anisotropic and has a high selectivity, etching only the silicon perpendicular to the plasma and not the protective layer. Therefore, the trenches after dry etching form 90° sidewalls, while leaving many small silicon particles.

[0041] After etching the trench, this application cleans away some of the residual silicon particles in the trench. However, the silicon particles adsorbed at the bottom and corners of the trench are difficult to clean. Next, the surface of the trench is oxidized to form an oxide layer, namely a silicon dioxide layer, on the upper half of the trench surface and the silicon particles remaining at the bottom of the trench. Subsequently, by etching away this part of the silicon dioxide layer, it is equivalent to removing part of the silicon wafer in the upper half of the trench and the silicon particles at the bottom, which makes the opening of the trench larger, thereby forming a curved surface between the sidewalls and the bottom of the trench. At the same time, removing the silicon dioxide layer is equivalent to performing a fine chemical polishing on the surface of the trench, so that a smooth curved surface is formed between the bottom and the sidewalls of the trench. In this way, the oxide dielectric can be fully filled in the trench in subsequent processes without gaps, thus preventing leakage current.

[0042] The semiconductor structure obtained by the above method is as follows: Figure 3 As shown, Figure 3 This illustration only depicts the silicon wafer 110, the trench 120 within the silicon wafer 110, and the oxide dielectric layer 130 within the trench 120 of the semiconductor structure 100. The semiconductor structure 100 is a part of a semiconductor device; other structures within the semiconductor device can be referenced from common MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and are not shown here. In this application, the trench sidewalls 122 and the trench bottom 121 form smooth curved surfaces. The oxide dielectric layer 130 is in full contact with the trench 120, without creating gaps or voids between them, and without any air remaining between the oxide dielectric layer 130 and the trench 120. Thus, when the reverse voltage increases, no air will expand due to the built-in electric field, preventing breakdown of the oxide dielectric layer 130 and device failure. Similarly, even if the built-in electric field does not reach the breakdown limit, no air will ionize and will not participate in conduction, thus preventing increased leakage current.

[0043] for Figure 2 The method for forming the semiconductor structure shown in the application provides two specific implementation methods.

[0044] The first embodiment is an exemplary implementation. Step S2 involves immersing the silicon wafer in a diluted hydrofluoric acid (DHF) solution to remove the natural oxide layer and a small amount of silicon particles. The wafer is then cleaned with an alkaline hydrogen peroxide cleaning solution (SC-1, RCA-1, or APM) to remove metal ions, particles, and organic matter, ensuring the trench is free of contamination. Step S3 involves introducing oxygen at high temperature to react with the trench surface, forming an oxide layer. Step S4 involves immersing the silicon wafer in a diluted hydrofluoric acid solution to etch away the oxide layer, then transferring the wafer to an alkaline hydrogen peroxide cleaning solution for further cleaning, and finally rinsing it quickly in a rapid high-purity water rinsing tank (QDR) to obtain a silicon wafer with a smooth curved surface between the bottom and sidewalls of the trench. If step S4 does not form a smooth curved surface between the bottom and sidewalls of the trench in one attempt, steps S3 and S4 are repeated until a smooth curved surface is formed between the bottom and sidewalls of the trench.

[0045] Specifically, in step S2, after dry etching the silicon wafer (or a steel wafer), the silicon wafer is immersed in a 1%-2% DHF solution bath for about 1 minute, and then transferred to a QDR rinsing tank for a rapid rinsing for 10 minutes. Next, the silicon wafer is transferred to an SC-1 (NH4OH:H2O2:H2O=1:1:5) cleaning solution for 10 minutes, then transferred to a QDR rinsing tank for a rapid rinsing for 10 minutes, then transferred to a 1%-2% DHF solution bath for about 30 seconds, and finally transferred to a QDR rinsing tank for a rapid rinsing for 10 minutes. After the rinsing conductivity reaches 9 MΩ, the wafer is transferred to a centrifugal spin dryer for 7-8 minutes to clean the trench. In step S3, a robotic arm pushes the silicon wafer into a diffusion furnace for oxidation. The oxidation conditions are: temperature 900-1000℃, oxygen is introduced at a flow rate of 10-15L / min, and the reaction time depends on the film thickness, generally 30-60min, thereby forming an oxide layer on the surface of the trench.

[0046] In step S4, after the oxide layer in the trenches of the silicon wafer is formed, the silicon wafer is immersed in a 1%-2% DHF solution bath for about 5-10 minutes. According to the oxide layer growth principle, growing a 1µm oxide layer on silicon requires 0.44µm of silicon. The reaction principle is SiO2 + 4HF = SiF4↑ + 2H2O. While removing the oxide layer, some Si is also removed, thereby removing contaminants attached to the silicon surface in the trenches, making the bottom and sidewalls of the trenches smooth. Next, the silicon wafer is transferred to the SC-1 cleaning bath and immersed for 10 minutes, then transferred to the QDR rinsing tank for a quick rinse for 10 minutes, then transferred to a 1%-2% DHF solution bath for about 30 seconds, and finally transferred to the QDR rinsing tank for a quick rinse for 10 minutes. After the rinsing water conductivity reaches 9 MΩ, it is transferred to a centrifugal spin dryer for 7-8 minutes. Steps S3 and S4 can be repeated to form a smooth curved surface between the bottom and sidewalls of the trench. Since the thickness of the oxide layer varies, the process time can be adjusted accordingly.

[0047] In the second embodiment, step S2 involves immersing the silicon wafer in a diluted hydrofluoric acid solution (DHF) to remove the natural oxide layer and a small amount of silicon particles; step S3 involves immersing the silicon wafer in deionized water containing ozone to form an oxide layer on the surface of the trench; step S4 involves immersing the silicon wafer in a diluted hydrofluoric acid solution (DHF) to etch away the oxide layer, then transferring the silicon wafer to an alkaline hydrogen peroxide cleaning solution for cleaning, and finally rinsing it quickly in a QDR rinsing tank to obtain a silicon wafer with a smooth curved surface between the bottom and sidewalls of the trench. Similarly, if step S4 does not form a smooth curved surface between the bottom and sidewalls of the trench in one attempt, steps S3 and S4 are repeated until a smooth curved surface is formed between the bottom and sidewalls of the trench.

[0048] Specifically, in step S2, after dry etching of the semiconductor structure trenches, the silicon wafer is immersed in a diluted hydrofluoric acid solution to clean the trenches. The purpose of this process is to remove the natural oxide layer on the silicon wafer and any remaining small amount of silicon particles in the trenches. Compared to other cleaning methods, using a diluted hydrofluoric acid solution to clean the trenches can both etch away the natural oxide layer on the silicon wafer surface and remove silicon particles, achieving two goals at once. Furthermore, the cost of the diluted hydrofluoric acid solution is relatively low. Through multiple experiments, the inventors have determined that setting the concentration of hydrofluoric acid in the diluted hydrofluoric acid solution to 1-2%, immersing the silicon wafer in the diluted hydrofluoric acid solution for 20-60 seconds, and maintaining the temperature of the diluted hydrofluoric acid solution at 25±5℃ results in a shorter time required to complete step S2.

[0049] In addition, after immersing the silicon wafer in a diluted hydrofluoric acid solution, it can also be moved into a QDR rinsing tank and rinsed quickly for 10 minutes. After the water conductivity reaches 9 megohms, it can be moved into a centrifugal spin dryer and spun for 7 to 8 minutes to clean the groove.

[0050] In step S3, ozone is first introduced into the deionized water at a flow rate of 50-150 ml / min, the specific flow rate depending on the volume of the water tank. A mass flow meter (MFC) can be installed in the ozone inlet pipe to control the ozone flow rate. The ozone introduction time is 20-60 seconds, resulting in ozone deionized water with an ozone concentration of 1-20%. The ozone concentration in the ozone deionized water needs to be defined according to the temperature of the deionized water. At room temperature, the ozone concentration is 1-3%, and at 60℃, the ozone concentration can reach 20%. Generally, a concentration of 4-6% is used. This application strictly controls the ozone concentration in ozone-deionized water to prevent harm to the human body due to excessive ozone concentration. At the same time, since the ozone concentration in ozone-deionized water and the film thickness of the oxide layer in the trench are not linearly related, the oxide film grown by the reaction of ozone and silicon cannot grow after reaching a certain point. When the ozone concentration is too high, it will lead to ozone waste and increase costs. Therefore, the inventors selected an ozone concentration range that takes into account both safety and process considerations.

[0051] When the ozone concentration in the ozone-deionized water reaches 1-20%, the silicon wafer is placed in the ozone-containing deionized water, forming an oxide layer on the surface of the trench. The oxidation reaction between ozone and the bare silicon in the trench is: Si + 4O3 = SiO2 + 5O2. After the reaction, a silicon dioxide layer with a thickness of 7-9 nm is generated in the trench, ensuring that all silicon particles at the bottom of the trench can react with silicon dioxide and that more silicon material participates in the reaction at the top of the trench, resulting in a larger opening in the trench and a greater inclination to the bottom of the trench. This facilitates the subsequent filling of the oxide dielectric layer and makes it easier for the oxide dielectric layer to fill the trench.

[0052] Furthermore, when ozone deionized water is used to react with the trench, ozone can also react with residual metal ions in the silicon wafer to achieve a further cleaning effect on the silicon wafer. The reaction formula is 5O3+6Fe=3Fe2O3+3O2.

[0053] In step S4, the reacted semiconductor structure is immersed in DHF solution to peel off the silicon dioxide layer in the trench. The silicon wafer is then transferred to a deionized water fast-drainage tank for rinsing, removing residual acid and reaction particles. This smooths the sidewalls and bottom of the trench, effectively removing metal ions and cleaning the silicon wafer. The reaction between DHF solution and silicon dioxide is: SiO2 + 4HF = SiF4↑ + 2H2O. After the reaction, silicon tetrafluoride gas is generated and removed by exhaust, thus smoothing the bottom and sidewalls of the trench. The reaction between DHF solution and metal ions is: 2Fe + 6HF = 2FeF3 + 3H2. The resulting reaction particles are easily washed away by the deionized water fast-drainage tank.

[0054] Furthermore, the DHF solution concentration is 1-2%, the immersion time is 20-60 seconds, and the temperature is 25±5℃. At this concentration and temperature, the etching rate is 7-12 nm / min, which effectively removes the oxide layer from the trench. Moreover, the DHF solution concentration and temperature, as well as the immersion time of the silicon wafer in the DHF solution, are the same parameters used in the trench cleaning process in step S2. This allows the DHF solution in step S2 to be reused without requiring repeated parameter settings on the machine, thus saving costs and improving production efficiency.

[0055] The first method for obtaining ideal trench morphology requires six steps (immersion in DHF, SC-1 cleaning, growth of an oxide layer in the trench, removal of the oxide layer with DHF, SC-1 cleaning, and DHF cleaning), making the process relatively complex. The second method requires only three steps (immersion in DHF, ozone-deionized water immersion, and immersion in DHF). This invention dissolves a certain proportion of ozone in deionized water, where it reacts with silicon to generate silicon dioxide. This silicon dioxide is then reacted with diluted hydrofluoric acid to remove the ozone-generated silica, thereby removing contaminants from the silicon surface of the trench and repairing the trench sidewalls. This method reduces the number of steps involved in SC-1 cleaning, sacrificial layer growth, and oxidation, significantly simplifying the manufacturing process, shortening the process flow, saving chemical reagents, improving process efficiency, and reducing the environmental impact of acid discharge.

[0056] like Figure 4 The diagram shown is a flowchart of another specific semiconductor structure formation method; as another embodiment of this application, this application also discloses another method for forming a semiconductor structure, including the following steps:

[0057] S1: Dry etching is performed on the silicon wafer to form trenches;

[0058] S21: Immerse the silicon wafer in a diluted hydrofluoric acid solution to clean the trench;

[0059] S31: Ozone is introduced into deionized water to form ozone deionized water with an ozone concentration of 1-20%;

[0060] S32: Immerse the silicon wafer in the ozone-deionized water to form an oxide layer on the surface of the trench;

[0061] S41: Immerse the silicon wafer in a diluted hydrofluoric acid solution to etch away the oxide layer;

[0062] S5: The silicon wafer is transferred into a deionized water fast drain tank for rinsing to remove residual acid and reaction particles, so that a smooth curved surface is formed between the bottom and sidewalls of the trench.

[0063] Dry etching achieves its effect through chemical and physical processes, or the combined effect of both. The chemical process involves the reaction between the silicon surface material and plasma to generate gaseous byproducts that are then removed by exhaust. The physical process involves plasma bombardment of the silicon surface, causing collisions between particles to achieve etching. Physical etching is anisotropic and highly selective, etching only the silicon perpendicular to the plasma and not the protective layer. Therefore, the resulting trenches have 90° sidewalls and retain many small silicon particles. While DHF immersion can remove some particles, it cannot completely remove silicon particles adsorbed at the bottom and corners of the trenches. Immersing the silicon wafer in deionized water with a certain proportion of ozone causes an oxidation reaction between the ozone and silicon and its particles, generating silicon dioxide. This silicon dioxide then reacts chemically with DHF. Since the formation of silicon dioxide from silicon and oxygen consumes 44% of the silicon, removing the silicon dioxide is equivalent to a fine chemical polishing of the silicon, resulting in a trench morphology with an arc-shaped bottom and sidewalls.

[0064] like Figure 5The diagram shown is a schematic of an ozone cleaning device. As another embodiment of this application, an ozone cleaning device 200 is also disclosed. The ozone cleaning device 200 includes an ozone tank 230, four rapid high-purity water rinsing tanks (QDR) 210, and two DHF solution tanks 220. The ozone cleaning device 200 has a symmetrical structure, and its internal structure is arranged sequentially as follows: QDR rinsing tank 210, DHF solution tank 220, QDR rinsing tank 210, ozone tank 230, QDR rinsing tank 210, DHF solution tank 220, and QDR rinsing tank 210. In the above-mentioned method for forming the semiconductor structure 100, the processes corresponding to each step correspond to the structure in the ozone cleaning device 200, and these processes can be designed with automated operating equipment, circulating left and right. The number of cycles and process time can be set according to process requirements. Furthermore, the ozone cleaning equipment 200 also includes an exhaust port 240, which is connected to each of the ozone tank 230, the rapid high-purity water rinsing tank 210 and the diluted hydrofluoric acid solution tank 220, so that the generated gas can be discharged at any time to prevent these gases from participating in the reaction or causing harm to the human body.

[0065] Existing technologies employ a rotational + spraying method for ozone treatment, and can only perform single-wafer operations. Furthermore, the equipment is imported, and this design cannot achieve the morphological restoration effect described in this case, while also incurring relatively high maintenance costs. The ozone cleaning equipment designed in this application can be manufactured by any domestic wet processing equipment manufacturer and can be used in conjunction with the semiconductor structure formation method described in this application to produce the desired trench morphology.

[0066] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0067] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Dry etching is performed on the silicon wafer to form trenches; Clean the trench; An oxide layer is formed on the surface of the trench; as well as The oxide layer is etched away, and a smooth curved surface is formed between the bottom and sidewalls of the trench; The step of forming an oxide layer on the surface of the trench includes: Ozone is introduced into deionized water; and The silicon wafer is placed in deionized water containing ozone to form an oxide layer on the surface of the trench; The thickness of the oxide layer is 7-9 nm; in the step of forming the oxide layer on the surface of the trench, the upper half of the surface of the trench and the silicon particles remaining at the bottom of the trench are formed with oxide layers. The trenches formed after dry etching have 90° sidewalls; In this process, while etching away the oxide layer and forming a smooth curved surface between the bottom and sidewalls of the trench, the opening of the trench is enlarged, the sidewalls of the trench are made arc-shaped, and the opening of the trench gradually increases in the direction away from the bottom of the trench. The step of cleaning the trench includes: immersing the silicon wafer in a diluted hydrofluoric acid solution to clean the trench; The concentration of hydrofluoric acid in the diluted hydrofluoric acid solution is 1-2%, the silicon wafer is immersed in the diluted hydrofluoric acid solution for 20-60 seconds, and the temperature of the diluted hydrofluoric acid solution is 25±5℃, in order to wash away some silicon particles except those adsorbed at the bottom and corners of the trench.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of introducing ozone into deionized water, the flow rate of ozone into the deionized water is 50-150 ml / min, and the introduction time is 20-60 seconds.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of etching away the oxide layer and forming a smooth curved surface between the bottom and sidewalls of the trench, if a smooth curved surface is not formed between the bottom and sidewalls of the trench after the oxide layer is etched away, the steps of forming an oxide layer on the surface of the trench and etching the oxide layer are repeated until a smooth curved surface is formed between the bottom and sidewalls of the trench. If a smooth curved surface is formed between the bottom and sidewall of the groove, the next process is carried out.

4. A semiconductor structure, characterized in that, The semiconductor structure is fabricated by the method for forming a semiconductor structure according to any one of claims 1-3.

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