Method of fabricating a semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of bit line structures adjacent to each other and forming a contact hole; forming an initial contact layer in the contact hole, the initial contact layer comprising a gap; etching the initial contact layer to remove part of the initial contact layer to form a first contact layer; etching the first contact layer to remove part of the gap, the remaining first contact layer forming a second contact layer; etching the second contact layer, the etching rate of the recessed sidewall being greater than the etching rate of the recessed bottom to remove the remaining gap and form a third contact layer. The present disclosure forms a contact layer with a flat topography by etching the initial contact layer multiple times and controlling the etching speed of the edge position of the second contact layer to be greater than the etching speed at the middle position of the second contact layer, thereby improving the yield and conductivity of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for fabricating a semiconductor structure. Background Technology

[0002] With the continuous development of Dynamic Random Access Memory (DRAM) manufacturing technology, the spacing between adjacent bit line structures is becoming smaller and smaller. As the spacing between adjacent bit line structures decreases, the manufacturing difficulty of the contact holes formed between the bit line structures becomes increasingly difficult, especially when forming contact holes with high aspect ratios. Gaps may exist in the material used to form the contact layer within the contact hole, and the top morphology of the contact layer within the contact hole is difficult to control, thereby reducing the conductivity and yield of the semiconductor structure. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure.

[0005] This disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] A substrate is provided, wherein a plurality of mutually discrete bit line structures are provided on the substrate, and contact holes are formed between adjacent bit line structures;

[0007] An initial contact layer is formed within the contact hole, the initial contact layer fills the contact hole and extends outside the contact hole, the top surface of the initial contact layer is higher than the top surface of the bit line structure, wherein the initial contact layer includes a gap, and the top surface of the gap is lower than the top surface of the bit line structure;

[0008] The initial contact layer is etched to remove a portion of the initial contact layer, exposing the top surface of the bit line structure. The remaining initial contact layer forms the first contact layer.

[0009] The first contact layer is etched to remove part of the gap, and the remaining first contact layer forms a second contact layer, the top of the second contact layer being recessed.

[0010] The second contact layer is etched, and the etching rate of the recessed sidewalls is greater than the etching rate of the recessed bottom, in order to remove the remaining gaps and form a third contact layer.

[0011] According to some embodiments of this disclosure, etching the first contact layer to remove a portion of the gap includes:

[0012] The first contact layer is subjected to a first over-etching process for a first duration to remove part of the gaps.

[0013] According to some embodiments of this disclosure, the first over-etching process of the first contact layer for a first duration includes:

[0014] Under the conditions of source power of 300-500W, bias power of 50-80W, and pressure of 5-20mTorr, the first contact layer is etched using a first etching gas with a high selectivity.

[0015] According to some embodiments of this disclosure, etching the second contact layer at a rate greater than the etching rate at the bottom of the recess to remove the remaining gaps and form a third contact layer includes:

[0016] A second over-etching process of a second duration is performed on the top of the second contact layer, wherein the etching rate of the recessed sidewalls is greater than the etching rate of the recessed bottom in the second over-etching process to remove part of the second contact layer, and the remaining second contact layer forms the third contact layer.

[0017] According to some embodiments of this disclosure, the second duration includes a first time period; the second over-etching process on the top of the second contact layer for a second duration includes:

[0018] A second over-etching process is performed on the top of the second contact layer for a first time period to remove a portion of the second contact layer and form a first depression with a first morphology on the top of the remaining second contact layer.

[0019] According to some embodiments of this disclosure, the second duration includes a second time period, wherein the duration of the second time period is greater than the duration of the first time period;

[0020] The second over-etching process on the top of the second contact layer for a second duration includes:

[0021] A second over-etching process with a second time period is performed on the top of the second contact layer to remove part of the second contact layer and form a second depression with a second morphology on the top of the remaining second contact layer.

[0022] Wherein, along the first direction, the difference between the top and bottom of the second depression is less than the difference between the top and bottom of the first depression.

[0023] According to some embodiments of this disclosure, the second over-etching process on the top of the second contact layer for a second duration includes:

[0024] Determine the second duration;

[0025] During the second time period, the second contact layer is etched using the second over-etching process.

[0026] According to some embodiments of this disclosure, determining the second duration includes:

[0027] The second duration is determined based on the ratio between the first duration and the second duration.

[0028] According to some embodiments of this disclosure, determining the second duration based on the proportional range between the first duration and the second duration includes:

[0029] The ratio of the first duration to the second duration is determined to be within the range of 1:(0~0.33);

[0030] Determine the morphology of the first depression or the second depression;

[0031] The second duration is determined based on the stated ratio range and the morphology of the first or second depression.

[0032] According to some embodiments of this disclosure, the etching of the second contact layer using the second over-etching process during the second time period includes:

[0033] Under the conditions of source power of 400-600W, bias power of 50-80W, and pressure of 5-10mTorr, the second contact layer is etched using the second etching gas.

[0034] According to some embodiments of this disclosure, etching the initial contact layer to remove a portion of the initial contact layer, exposing the top surface of the bit line structure, with the remaining initial contact layer forming a first contact layer, includes:

[0035] Under the conditions of source power of 300-500W, bias power of 50-80W, and pressure of 5-20mTorr, the initial contact layer is etched using a first etching gas.

[0036] According to some embodiments of this disclosure, etching the initial contact layer using a first etching gas includes:

[0037] The initial contact layer is etched using a first etching gas with a high selectivity, with the top surface of the bit line structure as the etching endpoint.

[0038] According to some embodiments of this disclosure, the provided substrate includes a plurality of mutually discrete bit line structures, with contact holes formed between adjacent bit line structures, including:

[0039] A plurality of spaced bit lines are formed on the substrate, and a first trench is formed between adjacent bit lines;

[0040] An insulating layer is formed in the first trench, the insulating layer extending outside the first trench and covering the top surface of the bit line;

[0041] The insulating layer located at the bottom of the first trench is removed, and the insulating layer remaining in the first trench forms the contact hole;

[0042] The bit line and the insulating layer formed on the sidewall and top surface of the bit line constitute the bit line structure.

[0043] According to some embodiments of this disclosure, forming a plurality of spaced bit lines on the substrate, with adjacent bit lines forming a first trench, includes:

[0044] A bit line contact layer, a first dielectric layer, a conductive layer, and a second dielectric layer are sequentially formed on the substrate.

[0045] A mask layer with a mask pattern is formed on the second dielectric layer. A portion of the second dielectric layer, a portion of the conductive layer, a portion of the first dielectric layer, and a portion of the bit line contact layer are removed according to the mask pattern. The remaining bit line contact layer, the first dielectric layer, the conductive layer, and the second dielectric layer form a plurality of bit lines.

[0046] Along the second direction, the multiple bit lines form multiple spaced-apart first trenches.

[0047] According to some embodiments of this disclosure, forming an insulating layer within the first trench, the insulating layer extending outside the first trench and covering the top surface of the bit line structure, includes:

[0048] The insulating layer is formed in the first trench using an atomic layer deposition process.

[0049] In the semiconductor structure fabrication method provided in this disclosure, the initial contact layer within the contact hole is etched multiple times to remove gaps in multiple stages. Simultaneously, the etching rate at the edges of the second contact layer is controlled to be greater than the etching rate at the center of the second contact layer, thereby forming contact layers with different top morphologies. When the top morphology of the formed contact layer is U-shaped, the resistance of the subsequently formed contact structure can be reduced, thereby improving the conductivity of the semiconductor structure. When the top morphology of the formed contact layer is planarized, the aspect ratio of the contact hole is effectively reduced, thereby preventing the formation of gaps when other structures are formed subsequently, thus improving the yield and conductivity of the semiconductor structure.

[0050] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0052] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0053] Figure 2 This is a schematic diagram illustrating the formation of bit lines in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0054] Figure 3 This is a schematic diagram illustrating the formation of a bit line structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0055] Figure 4 This is a schematic diagram illustrating the formation of an initial contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0056] Figure 5 This is a schematic diagram illustrating the formation of a first contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0057] Figure 6 This is a schematic diagram illustrating the formation of a second contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0058] Figure 7 This is a schematic diagram illustrating the formation of a third contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0059] Figure 8 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, showing the formation of a third contact layer having a first recessed morphology.

[0060] Figure 9 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, showing the formation of a third contact layer having a second recessed morphology.

[0061] Figure label:

[0062] 10. Substrate; 20. Bitline structure;

[0063] 30. Contact hole; 40. Bit line;

[0064] 50. First trench; 60. Insulation layer;

[0065] 70. Initial insulation layer; 80. Gap;

[0066] 90. First contact layer; 100. Second contact layer;

[0067] 110. Depression-like; 120. Third contact layer;

[0068] 130. First depression; 140. Second depression;

[0069] 410. Bit line contact layer; 420. First dielectric layer;

[0070] 430, Conductive layer; 440, Second dielectric layer;

[0071] 710, First groove; 910, Second groove.

[0072] X, the first direction; Y, the second direction. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0074] With the continuous development of Dynamic Random Access Memory (DRAM) manufacturing technology, the spacing between adjacent bit line structures is becoming smaller and smaller. As the spacing between adjacent bit line structures decreases, the manufacturing difficulty of the contact holes formed between the bit line structures becomes increasingly difficult, especially when forming contact holes with high aspect ratios. Gaps may exist in the material used to form the contact layer within the contact hole, and the top morphology of the contact layer within the contact hole is difficult to control, thereby reducing the conductivity and yield of the semiconductor structure.

[0075] In the semiconductor structure fabrication method provided in this embodiment, the initial contact layer within the contact hole is etched multiple times to remove gaps in multiple stages. Simultaneously, the etching rate at the edges of the second contact layer is controlled to be greater than the etching rate at the center of the second contact layer, thereby forming contact layers with different top morphologies. When the top morphology of the formed contact layer is U-shaped, the resistance of the subsequently formed contact structure can be reduced, thereby improving the conductivity of the semiconductor structure. When the top morphology of the formed contact layer is planarized, the aspect ratio of the contact hole is effectively reduced, thereby preventing the formation of gaps when other structures are formed subsequently, thus improving the yield and conductivity of the semiconductor structure.

[0076] like Figure 1 As shown, a flowchart of a method for fabricating a semiconductor structure is provided in an exemplary embodiment of this disclosure. The following is in conjunction with... Figures 1-9 The methods for fabricating semiconductor structures are introduced.

[0077] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0078] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0079] Step S100: Provide a substrate, on which a plurality of mutually independent bit line structures are provided, and contact holes are formed between adjacent bit line structures.

[0080] Step S200: An initial contact layer is formed inside the contact hole. The initial contact layer fills the contact hole and extends outside the contact hole. The top surface of the initial contact layer is higher than the top surface of the bit line structure. The initial contact layer includes a gap, and the top surface of the gap is lower than the top surface of the bit line structure.

[0081] Step S300: Etch the initial contact layer to remove part of the initial contact layer and expose the top surface of the bit line structure. The remaining initial contact layer forms the first contact layer.

[0082] Step S400: The first contact layer is etched to remove part of the gaps, and the remaining first contact layer forms the second contact layer, with the top of the second contact layer being recessed.

[0083] Step S500: The second contact layer is etched, and the etching rate of the recessed sidewall is greater than the etching rate of the recessed bottom, in order to remove the remaining gaps and form the third contact layer.

[0084] For example, such as Figures 1 to 3 As shown, in step S100, a substrate 10 is provided. The substrate 10 may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. It should be noted that in some embodiments, the substrate 10 may also include structures such as buried word lines, shallow trench isolation structures, and active regions.

[0085] The substrate 10 includes a plurality of mutually independent bit line structures 20, and contact holes 30 are formed between adjacent bit line structures 20.

[0086] In some embodiments, multiple discrete bit line structures 20 are formed on the substrate 10, which can be achieved by the following methods:

[0087] A plurality of spaced bit lines 40 are formed on the substrate 10, wherein adjacent bit lines 40 form a first trench 50.

[0088] In some embodiments, firstly, a bit line contact layer 410, a first dielectric layer 420, a conductive layer 430, and a second dielectric layer 440 are sequentially formed on a substrate 10 using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Then, a mask layer with a mask pattern is formed on the second dielectric layer 440. Taking the direction from the top surface of the substrate 10 to the bottom surface of the substrate 10 as the extending direction, portions of the second dielectric layer 440, the conductive layer 430, the first dielectric layer 420, and the bit line contact layer 410 are sequentially removed along the extending direction according to the mask pattern. The remaining bit line contact layer 410, the first dielectric layer 420, the conductive layer 430, and the second dielectric layer 440 form a plurality of bit lines 40. At this time, a plurality of spaced first trenches 50 are formed in the plurality of bit lines 40 along the second direction Y, wherein, with reference to... Figure 2 As shown, the second direction Y is the direction that extends along the length of the base 10.

[0089] It should be noted that the material of the bit line contact layer 410 includes tungsten or polycrystalline silicon. The materials of the first dielectric layer 420 and the second dielectric layer 440 can be the same or different, and the materials of the first dielectric layer 420 and the second dielectric layer 440 include silicon nitride, silicon dioxide, or silicon oxynitride, etc. The conductive layer 430 can be composed of one or more conductive materials, such as compounds doped with polycrystalline silicon, titanium, titanium nitride, and tungsten, etc.

[0090] After the first trench 50 is formed, an insulating layer 60 can be formed within the first trench 50 using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). In one example, the insulating layer 60 can be formed using ALD, which is characterized by a slow deposition rate, high film density, and good step coverage. Forming the insulating layer 60 using ALD can effectively isolate and protect the position lines 40 even with a relatively thin layer, avoiding occupying a large space in the first trench 50 and facilitating the subsequent filling or formation of other structural layers.

[0091] The insulating layer 60 extends beyond the first trench 50 and covers the top surface of the bit line 40. The insulating layer 60 is used to protect and isolate adjacent bit lines 40. The material of the insulating layer 60 includes silicon nitride or silicon oxynitride.

[0092] After the insulating layer 60 is formed, the insulating layer 60 at the bottom of the first trench 50 can be removed by etching. At this time, the adjacent insulating layers 60 remaining in the first trench 50 and located on the sidewall of the bit line 40 form a contact hole 30. The bit line 40 and the insulating layers 60 formed on the sidewall and top surface of the bit line 40 constitute the bit line structure 20, that is, a contact hole 30 is formed between two adjacent bit line structures 20.

[0093] The bit line formation method in this embodiment is simple and easy to operate. The bit line can be connected to the drain of a subsequently formed transistor, the gate of the transistor is connected to a word line, and the source is connected to a capacitor structure. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor structure through the bit line, or writing data information into the capacitor structure for storage through the bit line.

[0094] For example, such as Figure 4As shown, in step S200, an initial contact layer 70 can be formed within the contact hole 30 using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The initial contact layer 70 can be a silicon material layer doped with elements such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon, and the doping elements include boron or phosphorus. In some embodiments, the initial contact layer 70 can also be a highly concentrated doped layer, which is used to reduce the contact resistance between the doped layer and the substrate 10.

[0095] The initial contact layer 70 fills the contact hole 30 and extends beyond it, with its top surface higher than the top surface of the bit line structure 20. Due to continuous miniaturization of the manufacturing process, in the direction perpendicular to the top surface of the substrate 10, with the height of the bit line structure 20 remaining constant, the distance between adjacent bit line structures 20 tends to decrease, leading to an increase in the aspect ratio of the contact hole 30. For example, when the aspect ratio of the contact hole 30 is greater than 6:1, when the initial contact layer 70 is deposited within the contact hole 30, the initial contact layer 70 is pre-sealed at the top, resulting in a gap 80 within the formed initial contact layer 70, with the top surface of the gap 80 lower than the top surface of the bit line structure 20. Simultaneously, a first groove 710 is formed on the top of the initial contact layer 70 at the position aligned with each contact hole 30. In the semiconductor structure manufacturing process, when the contact hole 30 has a gap 80 and the top of the initial contact layer 70 has a first groove 710, it will be detrimental to improving the conductivity of the semiconductor structure. Therefore, the gap 80 and the first groove 710 can be removed in subsequent processes.

[0096] It should be noted that, since the top of the formed initial contact layer 70 is higher than the top of the bit line structure 20, the thickness of the initial contact layer 70 is relatively large along the first direction X, that is, along the direction perpendicular to the top surface of the substrate 10. Therefore, using a chemical vapor deposition process with a faster deposition rate to form the initial contact layer 70 is beneficial to shorten the process cycle of the semiconductor structure.

[0097] For example, such as Figure 4 and Figure 5 As shown, in step S300, the initial contact layer 70 is etched to remove part of the initial contact layer 70 and the first groove 710, and to expose the top surface of the bit line structure 20. At this time, the retained initial contact layer 70 forms the first contact layer 90.

[0098] The initial contact layer 70 can be removed using the following method:

[0099] Under conditions of source power of 300–500W, bias power of 50–80W, and pressure of 5–20 mTorr, the initial contact layer 70 is etched using a first etching gas. In some embodiments, the first etching gas may include high-selectivity gases such as chlorine or hydrobromic acid. Using a high-selectivity first etching gas can quickly remove a portion of the initial contact layer 70, which helps save on semiconductor fabrication cycle time, improve etching accuracy, and increase the yield of subsequent processes. In this embodiment, the etching of a portion of the initial contact layer 70 is the main etching step. In this step, etching endpoint detection technology can be used to ensure that the etching endpoint of the initial contact layer 70 stops at the top surface of the bit line structure 20. It should be noted that in this main etching step, as the etching endpoint stops at the top surface of the bit line structure 20, the retained initial contact layer 70 located within the contact hole 30 forms the first contact layer 90, and a second groove 910 may be formed on the top surface of the first contact layer 90. The bottom of the second groove 910 is close to the top of the gap 80, and the two sides of the second groove 910 are flush with the top surface of the adjacent insulating layer 60. In some embodiments, the longitudinal cross-sectional shape of the second groove 910 may include a semi-circle or a semi-ellipse to facilitate selective etching of the first contact layer 90 and improve the etching rate.

[0100] For example, such as Figure 6 As shown, in step S400, the first contact layer 90 is etched to remove a portion of the gap 80, and the remaining first contact layer 90 forms the second contact layer 100. In this step, since a portion of the gap 80 is removed, the remaining portion of the gap 80 causes the top of the second contact layer 100 to form a recessed shape 110. It should be noted that in some steps, the entire gap 80 within the contact hole 30 can also be removed by etching the first contact layer 90.

[0101] It should be noted that, referring to Figure 6 As shown, by removing part of the gap 80, the top of the gap 80 is opened, exposing the lower half of the gap 80. In one process, contact material can be directly filled into the lower half of the gap 80 to form a filler layer, etc. However, in this process, since only the upper half of the gap 80 is removed during etching, the lower half of the gap 80 still has a high aspect ratio. Therefore, other gaps may be formed again inside the filler layer formed in the gap 80, resulting in a decrease in the performance of the semiconductor structure.

[0102] Therefore, in this embodiment, the entire gap 80 can be removed in multiple steps in subsequent process steps, thereby improving the performance and yield of the semiconductor structure.

[0103] In some embodiments, the first removal of the gap 80 can be performed using the following method:

[0104] By performing a first over-etching process on the first contact layer 90 for a first duration, part of the gaps 80 are removed. The etching process for the first over-etching process is as follows: under the conditions of source power of 300-500W, bias power of 50-80W, and pressure of 5-20mTorr, the first contact layer 90 is etched using a first etching gas with a high selectivity.

[0105] In some embodiments, the first etching gas can be an isotropic gas such as hydrobromic acid (HBr) or chlorine (Cl2). Under etching conditions of source power of 300-500W, bias power of 50-80W, and pressure of 5-20mTorr, the first contact layer 90 is etched for a first duration to quickly and uniformly consume the filling material in the first contact layer, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon, and eliminate the remaining gaps 80, thereby effectively improving the conductivity of the subsequent semiconductor structure and increasing the yield of the semiconductor structure.

[0106] For example, such as Figures 7 to 9 As shown, in step S500, the second contact layer 100 is etched. In this etching step, a second over-etching process of a second duration can be performed on the top of the second contact layer 100. In this second over-etching process, along the first direction X, i.e., along the direction perpendicular to the top surface of the substrate 10, the etching rate on the two sidewalls of the recessed shape 110 is greater than the etching rate on the bottom of the recessed shape 110, to remove part of the second contact layer 100 and the remaining gap 80. The remaining second contact layer 100 forms the third contact layer 120. By using different etching rates at different locations of the recessed shape 110, the etching rate of the second contact layer 100 is increased, so that the top of the third contact layer 120 can form a top morphology with different shapes, such as a deep V-shaped top morphology, a U-shaped top morphology, or a planar top morphology, facilitating the subsequent formation of other structures. In some embodiments, since the top of the second contact layer 100 is recessed 110 and some gaps 80 still exist in the second contact layer 100, if the etching rate at the bottom of the recessed 110 is greater than the etching rate at the sidewall, then the gaps 80 will still exist in the second contact layer 100. That is to say, when etching the second contact layer 100, only some gaps 80 can be removed, and the gaps 80 cannot be completely removed.

[0107] Therefore, in the above embodiments, by controlling the etching time of different durations, the entire gap 80 is removed in multiple stages, and different etching processes are used to obtain a third contact layer 120 with a relatively flat top morphology, which effectively reduces the depth-to-width ratio of the contact hole, thereby preventing the formation of gaps when other structures are formed subsequently.

[0108] In some embodiments, the etching process of the second over-etching treatment is as follows: under the conditions of source power of 400-600W, bias power of 50-80W, and pressure of 5-10mTorr, the second contact layer 100 is etched using a second etching gas. The second etching gas includes inert gas argon (Ar) and anisotropic gas sulfur hexafluoride (SF6), etc. In this embodiment, the inert gas argon (Ar) is introduced at a rate of 100-160 sccm, and the sulfur hexafluoride (SF6) is introduced at a rate of 15-30 sccm. By setting the etching conditions of the second over-etching treatment, the second contact layer 100 is etched within a second time period, which can improve the etching rate, ensure etching accuracy, and thus improve the yield of subsequent processes.

[0109] It should be noted that, referring to Figure 7 As shown, in some embodiments, after the second contact layer 100 undergoes a second over-etching process for a predetermined time, the top morphology of the second contact layer 100 will form as shown. Figure 7 The deep V-shaped top morphology shown is followed by a second over-etching process on the second contact layer 100, which can change the top morphology of the second contact layer 100 from a deep V-shape to a U-shape or a flat top morphology. The following explanation uses over-etching processes of different time periods as examples.

[0110] Reference Figure 7 As shown, in some embodiments, the second duration includes the first time period. Specifically, in the second over-etching process of the second duration on the top of the second contact layer 100, the etching process of the second over-etching process described above is used to etch the second contact layer 100 for the first time period, thereby removing a portion of the second contact layer 100. At this time, the top of the remaining second contact layer 100 forms a first recess 130 with a first morphology. It should be noted that, along the first direction X, the longitudinal cross-sectional shape of the first recess 130 includes a deep V-shape.

[0111] In other embodiments, reference is made to Figure 8 and Figure 9As shown, the second duration includes a second time period, wherein the duration of the second time period is longer than the duration of the first time period. In the second over-etching process of the second duration on the top of the second contact layer 100, the second contact layer 100 is etched for the second time period using the etching process described above, thereby further removing a portion of the second contact layer 100. At this time, the top of the remaining second contact layer 100 forms a second recess 140 with a second morphology along the first direction X. The difference between the top and bottom of the second recess 140 is less than the difference between the top and bottom of the first recess 130. Wherein, taking a plane perpendicular to the first direction X as the cross-section, the cross-sectional shape of the top surface of the second recess 140 can include a U-shape or a planar shape.

[0112] It should be noted that after the second over-etching process of the second contact layer 100 during the second time period, the etched second contact layer 100 changes from a deep V-shaped top morphology to a U-shaped top morphology. Then, the second contact layer 100 continues to be etched, at which point the U-shaped top morphology further changes to a planar top morphology. Therefore, by controlling the duration of the second time period, the top morphology of the third contact layer 120 can be made to form a more flattened morphology, thus facilitating the subsequent formation of other structures in the semiconductor structure.

[0113] In this embodiment, by performing a second over-etching process for a first time period or a second over-etching process for a second time period on the second contact layer 100, the duration of the second time period is limited to be longer than the duration of the first time period. Based on the setting of the etching rate in the second over-etching process, the top morphology of the third contact layer 120 is precisely controlled, thereby effectively improving the yield of subsequent semiconductor structures.

[0114] Reference Figure 8 and Figure 9 As shown, in some embodiments, in the second over-etching process of the second contact layer 100 for a second duration, the second duration can be determined first, so that the second contact layer 100 can be etched by the second over-etching process within the second duration.

[0115] The second duration can be determined using the following method:

[0116] The ratio of the first duration to the second duration is determined to be 1:(0~0.33).

[0117] Determine the morphology of the first depression 130 or the second depression 140.

[0118] The second duration is determined based on the proportional range and the morphology of the first or second depression.

[0119] For example, in one embodiment, a third contact layer 120 with a U-shaped cross-sectional top is to be formed within the contact hole 30 on the substrate 10. Based on the proportional relationship, when the ratio of the second duration to the first duration is 1:9, a third contact layer 120 with a U-shaped longitudinal cross-sectional top can be obtained, thus determining the second duration based on the first duration. Therefore, within the second duration, a second over-etching process is performed on the second contact layer 100, thereby removing a portion of the second contact layer 100. At this time, a first recess 130 with a first morphology is formed on the top of the retained second contact layer 100. The retained second contact layer 100 forms the third contact layer 120. In this embodiment, the second duration includes the first time period.

[0120] In another embodiment, a third contact layer 120 with a planar cross-sectional shape at its top needs to be formed within the contact hole 30 on the substrate 10. Based on the proportional relationship, when the ratio of the second duration to the first duration is 1:3, a third contact layer 120 with a planar cross-sectional shape at its top can be obtained, thus determining the second duration based on the first duration. Therefore, during the second duration, a second over-etching process is performed on the second contact layer 100, thereby removing a portion of the second contact layer 100. At this time, a second recess 140 with a second morphology is formed on the top of the retained second contact layer 100. The retained second contact layer 100 forms the third contact layer 120. In this embodiment, the second duration includes a second time period.

[0121] In another embodiment, when the ratio between the first duration and the second duration is 1:0, the processing of the second duration is not required, and only the processing of the first duration is required.

[0122] In the above embodiments, by performing a two-step over-etching process on the first contact layer 90, the top morphology of the third contact layer 120 within the contact hole 30 is precisely controlled, thereby improving the yield of subsequent semiconductor structures and enhancing the conductivity of the semiconductor structures.

[0123] In the first over-etching process, isotropic gases such as hydrobromic acid (HBr) and chlorine (Cl2) are used to quickly remove part of the first contact layer 90. The remaining first contact layer 90 forms the second contact layer 100. At this time, the longitudinal cross-sectional shape of the top morphology of the second contact layer 100 can be V-shaped.

[0124] Then, under the etching conditions of the second over-etching process, the second contact layer is etched using a second etching gas, such as the inert gas argon (Ar) and the anisotropic gas sulfur hexafluoride (SF6), to rapidly remove a portion of the second contact layer 100. The remaining second contact layer 100 forms the third contact layer 120. (Refer to...) Figures 7 to 9 As shown, the longitudinal cross-sectional shape of the top morphology of the third contact layer 120 can be changed from a V-shaped morphology to a U-shaped morphology, and eventually to a flattened planar morphology, depending on the increase of the second time duration. It should be noted that with the increase of the second time duration, various bottom morphologies of the contact hole 30 can be obtained, i.e., the top morphology of the third contact layer 120 within the contact hole 30. This not only improves the conductivity of the semiconductor structure by removing the gap 80, but also effectively improves the yield of the semiconductor structure. It should also be noted that when the top of the third contact layer 120 is a U-shaped or V-shaped morphology, the contact area between the third contact layer 120 and the subsequent memory node structure can be reduced, thereby reducing contact resistance. Furthermore, forming the third contact layer by repeatedly etching the initial contact layer can prevent the etching process from affecting the bit line structure.

[0125] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0126] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0127] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0128] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0129] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0130] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A substrate is provided, wherein a plurality of mutually discrete bit line structures are provided on the substrate, and contact holes are formed between adjacent bit line structures; An initial contact layer is formed within the contact hole, the initial contact layer fills the contact hole and extends outside the contact hole, the top surface of the initial contact layer is higher than the top surface of the bit line structure, wherein the initial contact layer includes a gap, and the top surface of the gap is lower than the top surface of the bit line structure; The initial contact layer is etched to remove a portion of the initial contact layer, exposing the top surface of the bit line structure. The remaining initial contact layer forms the first contact layer. The first contact layer is etched to remove part of the gap, and the remaining first contact layer forms a second contact layer, the top of the second contact layer being recessed. The second contact layer is etched, and the etching rate of the recessed sidewalls is greater than the etching rate of the recessed bottom, in order to remove the remaining gaps and form a third contact layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The etching of the first contact layer to remove part of the gap includes: The first contact layer is subjected to a first over-etching process for a first duration to remove part of the gaps.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The first over-etching process for the first contact layer for a first duration includes: Under the conditions of source power of 300-500W, bias power of 50-80W, and pressure of 5-20mTorr, the first contact layer is etched using a first etching gas with a high selectivity.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The etching of the second contact layer, wherein the etching rate of the recessed sidewalls is greater than the etching rate of the recessed bottom, to remove the remaining gaps and form the third contact layer, includes: A second over-etching process of a second duration is performed on the top of the second contact layer, wherein the etching rate of the recessed sidewalls is greater than the etching rate of the recessed bottom in the second over-etching process to remove part of the second contact layer, and the remaining second contact layer forms the third contact layer.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The second duration includes the first time period; The second over-etching process on the top of the second contact layer for a second duration includes: A second over-etching process is performed on the top of the second contact layer for a first time period to remove a portion of the second contact layer and form a first depression with a first morphology on the top of the remaining second contact layer.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The second duration includes a second time period, wherein the duration of the second time period is greater than the duration of the first time period; The second over-etching process on the top of the second contact layer for a second duration includes: A second over-etching process with a second time period is performed on the top of the second contact layer to remove part of the second contact layer and form a second depression with a second morphology on the top of the remaining second contact layer. Wherein, along the first direction, the difference between the top and bottom of the second depression is less than the difference between the top and bottom of the first depression.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The second over-etching process on the top of the second contact layer for a second duration includes: Determine the second duration; During the second time period, the second contact layer is etched using the second over-etching process.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, Determining the second duration includes: The second duration is determined based on the ratio between the first duration and the second duration.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Determining the second duration based on the proportional range between the first duration and the second duration includes: The ratio of the first duration to the second duration is determined to be within the range of 1:(0~0.33); Determine the morphology of the first depression or the second depression; The second duration is determined based on the stated ratio range and the morphology of the first or second depression.

10. The method for fabricating a semiconductor structure according to claim 7, characterized in that, During the second time period, the second contact layer is etched using the second over-etching process, including: Under the conditions of source power of 400-600W, bias power of 50-80W, and pressure of 5-10mTorr, the second contact layer is etched using a second etching gas.

11. The method for fabricating a semiconductor structure according to any one of claims 1-10, characterized in that, The etching of the initial contact layer to remove a portion of the initial contact layer and expose the top surface of the bit line structure, with the remaining initial contact layer forming the first contact layer, includes: Under the conditions of source power of 300-500W, bias power of 50-80W, and pressure of 5-20mTorr, the initial contact layer is etched using a first etching gas.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The etching of the initial contact layer using a first etching gas includes: The initial contact layer is etched using a first etching gas with a high selectivity, with the top surface of the bit line structure as the etching endpoint.

13. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The provided substrate includes a plurality of mutually discrete bit line structures, with contact holes formed between adjacent bit line structures, including: A plurality of spaced bit lines are formed on the substrate, and a first trench is formed between adjacent bit lines; An insulating layer is formed in the first trench, the insulating layer extending outside the first trench and covering the top surface of the bit line; The insulating layer located at the bottom of the first trench is removed, and the insulating layer remaining in the first trench forms the contact hole; The bit line and the insulating layer formed on the sidewall and top surface of the bit line constitute the bit line structure.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The method of forming a plurality of spaced bit lines on the substrate, wherein adjacent bit lines form a first trench, includes: A bit line contact layer, a first dielectric layer, a conductive layer, and a second dielectric layer are sequentially formed on the substrate. A mask layer with a mask pattern is formed on the second dielectric layer. A portion of the second dielectric layer, a portion of the conductive layer, a portion of the first dielectric layer, and a portion of the bit line contact layer are removed according to the mask pattern. The remaining bit line contact layer, the first dielectric layer, the conductive layer, and the second dielectric layer form a plurality of bit lines. Along the second direction, the multiple bit lines form multiple spaced-apart first trenches.

15. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The step of forming an insulating layer within the first trench, the insulating layer extending outside the first trench and covering the top surface of the bit line structure, includes: The insulating layer is formed in the first trench using an atomic layer deposition process.

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