Ultra-low leakage electrostatic discharge device with controllable trigger voltage

Abstract

The present invention relates to ultra-low leakage electrostatic discharge devices with controllable trigger voltage. Embodiments of the present disclosure provide an electrostatic discharge (ESD) device comprising: an input pad; an underlap field effect transistor (UL-FET) having a trigger voltage Vt, comprising: an underlap drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a barrier layer separating the underlap drain region and the gate structure of the UL-FET by an underlap distance.

Description

Technical Field

[0001] This disclosure relates to integrated circuits, and more specifically to electrostatic discharge (ESD) devices having ultra-low leakage and controllable trigger voltage. Background Technology

[0002] Integrated circuits (ICs) can be affected by random ESD events, which can drive potentially large and damaging ESD currents to the sensitive electronic components of an IC. For example, ESD events can occur during post-manufacturing chip handling or after the chip has been mounted on a circuit board or other carrier. During an ESD event, electrostatic charge can rapidly transfer between two objects at different potentials when they come into direct contact.

[0003] To prevent ESD events, an IC can be equipped with one or more ESD devices. These ESD devices are typically designed to remain quiescent during normal IC operation and turn on in response to an ESD event. When implementing these devices on an IC, designers must consider the operating voltage, leakage current, breakdown constraints, and footprint of the ESD devices.

[0004] A typical ESD device may have a trigger voltage (Vt) higher than the IC's operating voltage, whereby the ESD device remains in a silent state until the voltage applied due to an ESD event reaches or exceeds Vt. When an ESD event occurs, the ESD device enters a low-impedance state, which conducts the ESD current to ground and away from the IC's sensitive electronic components. The ESD device may remain (e.g., clamped) in its low-impedance state until the ESD current is drained and the ESD voltage is discharged to an acceptable level.

[0005] Designers are often tasked with reducing the power consumption of ICs (e.g., by reducing leakage current from ESD devices and other components). Current leakage from ESD devices is a significant factor in power consumption for circuit applications. This is especially true for mobile electronic devices such as smartphones, tablets, wearables, or medical devices, as leakage in the off state can affect battery life and thus operating time. While ultra-low leakage (ULL) ESD devices have been developed, such ULL ESD devices typically require trigger voltages much higher than the operating voltages of other circuits / devices on the IC. Although the trigger voltage can be adjusted (e.g., using additional injection), this usually results in higher cost and higher leakage current.

[0006] Examples of ESD devices with reduced leakage current include gated silicon controlled rectifiers (SCRs), diode strings, and SCRs with feedback loops. However, such ESD devices have a larger footprint and increased cost. Furthermore, such ESD devices cannot provide low leakage current and controllable trigger voltage. Summary of the Invention

[0007] A first aspect of this disclosure relates to an electrostatic discharge (ESD) device comprising: an input pad; an underlapped field-effect transistor (UL-FET) having a trigger voltage Vt, comprising: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a barrier layer separating the underlapped drain region of the UL-FET from the gate structure by an underlapped distance.

[0008] A second aspect of this disclosure relates to a method for electrostatic discharge (ESD) protection, comprising: coupling an ESD device to a circuit to be protected, the ESD device including an under-overlapping field-effect transistor (UL-FET) having an under-overlapping drain region; and controlling a trigger voltage of the UL-FET by at least one of: adjusting a gate voltage Vg applied to a gate structure of the UL-FET; adjusting the capacitance of a capacitor C coupled between the gate structure of the UL-FET and an input pad; and adjusting an under-overlapping distance between the under-overlapping drain region of the UL-FET and the gate structure of the FET.

[0009] A third aspect of this disclosure relates to an electrostatic discharge (ESD) device comprising: an input pad; an under-overlapping n-type field-effect transistor (UL-NFET) having a trigger voltage Vt, comprising: an under-overlapping n+-doped drain region formed in a p-well and coupled to the input pad; an n+-doped source region formed in the p-well and coupled to ground; and a gate structure coupled to the input pad; and a silicide barrier layer separating the under-overlapping n+-doped drain region of the UL-NFET from the gate structure by an under-overlapping distance.

[0010] The above and other features of this disclosure will become apparent from the following more detailed description of embodiments thereof. Attached Figure Description

[0011] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein similar reference numerals denote similar elements:

[0012] Figure 1 An ultra-low leakage (ULL) electrostatic discharge (ESD) device with a controllable trigger voltage is shown according to an embodiment.

[0013] Figure 2 An example is shown. Figure 1 The equivalent circuit of the ULL ESD device.

[0014] Figure 3 An embodiment is shown with different gate voltages Vg and under-overlap distance X1 = 0. Figure 1 The relationship between the snapback current Id (logarithmic scale) and the drain voltage Vd of an ESD device.

[0015] Figure 4 Examples are shown with different gate voltages Vg and under-overlap distance X1 = 50 nm. Figure 1 The relationship between the foldback current Id (logarithmic scale) and the drain voltage Vd of an ESD device.

[0016] Figure 5 Examples are shown with different gate voltages Vg and under-overlap distance X1 = 100 nm. Figure 1 The relationship between the foldback current Id (logarithmic scale) and the drain voltage Vd of an ESD device.

[0017] Figure 6 An embodiment is shown with different gate voltages Vg and under-overlap distance X1 = 0. Figure 1 The relationship between the foldback current Id (linear scale) and the drain voltage Vd of the ESD device.

[0018] Figure 7 Examples are shown with different gate voltages Vg and under-overlap distance X1 = 50 nm. Figure 1 The relationship between the foldback current Id (linear scale) and the drain voltage Vd of the ESD device.

[0019] Figure 8 Examples are shown with different gate voltages Vg and under-overlap distance X1 = 100 nm. Figure 1 The relationship between the foldback current Id (linear scale) and the drain voltage Vd of the ESD device.

[0020] Figure 9 The illustration shows embodiments with different gate voltages Vg and under-overlap distances X1. Figure 1 The table shows the trigger voltage Vt of the ESD device.

[0021] Figure 10 An ESD device and an npn device for providing a discharge path are shown according to an embodiment.

[0022] Figure 11 An ESD device and a silicon controlled rectifier (SCR) device for providing a discharge path are shown according to an embodiment.

[0023] Note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0024] In the following description, reference is made to the accompanying drawings, which form part of this specification, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0025] This document describes an electrostatic discharge (ESD) device with ultra-low leakage (ULL) current and a controllable trigger voltage according to embodiments. The ULL ESD device according to embodiments may include an under-overlapping field-effect transistor (UL-FET). The gate voltage of the ULL ESD device can be dynamically controlled by the voltage applied to the gate of the UL-FET. The ULL ESD device can be modulated by adjusting the capacitance coupled to the gate of the UL-FET or by changing the degree of under-overlap of the UL-FET. The ULL ESD device is compatible with existing masks and processes and can be provided without significant cost increases or area penalties.

[0026] Figure 1 An ultra-low leakage (ULL) electrostatic discharge (ESD) device 100 with a controllable trigger voltage is shown according to an embodiment (hereinafter referred to as ESD device 100). Figure 2 An example is shown. Figure 1 The equivalent circuit of the ESD device 100. For example... Figure 1 and Figure 2 As shown, the ESD device 100 may include an under-overlapping n-type field-effect transistor (UL-NFET) 102, a capacitor 104 (e.g., a back-end process (BEOL) capacitor), and an n-type switching FET (NFET) 106.

[0027] The UL-NFET 102 can be formed in a p-type doped region 108 (e.g., p-well 108 hereinafter) and can include an n+ doped source region 110, a sub-overlapping n+ doped drain region 112, and a gate structure 114. A "sub-overlapping region" refers to a diffusion region in which no portion is directly below the gate structure 114. For example, as... Figure 1As shown, the under-overlapping n+ doped drain region 112 is separated from the edge of the gate structure 114 and the underlying gate channel region 116 by an under-overlapping distance X1. The various doped regions described herein can be formed in any known manner (e.g., via ion implantation of dopant). The various gate structures described herein can also be formed in any known manner.

[0028] A silicide barrier layer, including a source-side silicide barrier (SOP) region 118 and a drain-side silicide barrier (DOP) region 120, can be formed over portions of the p-well 108, the n+-doped source region 110, and the under-overlapping n+-doped drain region 112, such as... Figure 1 As shown. The formation of the silicide barrier layer may include, for example, depositing an insulating layer and selectively etching the insulating layer. The silicide barrier layer may be formed, for example, from silicon oxide or silicon nitride.

[0029] According to an embodiment, the under-overlapping n+ doped drain region 112 can be coupled to an input terminal or an input pad 122 (hereinafter referred to as input pad 122). The gate structure 114 of the UL-NFET 102 can also be coupled to the input pad 122 via a capacitor 104. The gate structure 114 of the UL-NFET 102 can be further latched to ground by switching the NFET 106. Figure 2 In the equivalent circuit of the ESD device 100 shown, the intrinsic gate-source capacitance of the UL-NFET 102 is represented by capacitor Cgs. Therefore, the gate voltage Vg applied to the gate structure 114 of the UL-NFET 102 can be set by a voltage divider formed by capacitor 104 and capacitor Cgs connected in series. According to other embodiments, capacitor 104 can be replaced by the intrinsic gate-to-drain capacitance Cgd of the UL-NFET 102. According to a further embodiment, an additional capacitor can be coupled in parallel with the intrinsic gate-source capacitance Cgs of the UL-NFET 102 for better control of the gate voltage Vg.

[0030] The switching NFET 106 can also be formed in the p-well 108. The switching NFET 106 may include an n+-doped drain region 124, an n+-doped source region 110, and a gate structure 126. According to an embodiment, the n+-doped drain region 110 may be shared by the switching NFET 106 and the UL-NFET 102. The gate structure 124 of the switching NFET 106 may be coupled to a power supply voltage Vdd.

[0031] Switching NFET 106 can be used to control the operation of UL-NFET 102. When Vdd is high, the gate voltage Vg at the gate structure 114 of UL-NFET 102 is latched to ground, thereby disabling UL-NFET 102. When Vdd is low, switching NFET 106 is in a floating state and the gate voltage Vg depends on the voltage at input pad 122 and the capacitance values ​​of capacitor 104 and the intrinsic gate-source capacitance Cgs of UL-NFET 102.

[0032] Refer again Figure 1 as well as Figure 2 During ESD event 130 (represented by the lightning ball at input pad 122), a gate voltage Vg is applied to the gate structure 114 of the UL-NFET 102 of the ESD device 100. As described above, the gate voltage Vg depends on the voltage at input pad 122 and the capacitance values ​​of capacitor 104 and the intrinsic gate-source capacitance Cgs of the UL-NFET 102. The ESD device 100 is activated when the voltage between the n+-doped drain region 110 and the under-overlapping n+-doped drain region 112 is greater than the trigger voltage Vt of the UL-NFET 102. The trigger voltage Vt is modulated by the gate voltage Vg.

[0033] Many ESD devices are voltage clamping devices, which have a high resistance up to the trigger (e.g., breakdown) voltage, and their resistance drops sharply once the trigger voltage is exceeded. At this point, the ESD device turns on and begins to conduct current. For this type of ESD device, the trigger voltage (turn-on) is higher than the normal operating voltage of the protected circuit, but low enough that the clamping voltage is below the voltage that could damage the protected circuit. Voltage clamping devices are ideally turned off during normal operation (allowing negligible current to pass), but begin to conduct current once their threshold voltage is reached.

[0034] Considering the internal structure of solid-state ESD devices, free electrons (holes) become mobile in the presence of an electric field. If the electric field is low, the electrons move freely without incident. On the other hand, the strong electric field generated by the high voltage associated with an ESD event excites the moving electrons to collide with and release the bound electrons. The free electrons propagate the same effect, leading to electron avalanche (breakdown).

[0035] ESD devices such as the snapback ESD device 100 according to the embodiment exhibit different behavior. A typical MOSFET has a parasitic bipolar junction transistor, which has a source as its emitter and a drain as its collector. When an avalanche current flows to the base of the parasitic bipolar junction transistor, the base current can trigger the ESD device to allow current to flow between the collector and emitter. Once triggered, the strong electric field that caused the avalanche current is no longer needed to sustain it. Large current conduction continues even at lower voltages.

[0036] At low voltages, the foldback ESD device also exhibits high resistance until it turns on at a trigger voltage Vt greater than the normal operating condition of the protected circuit. After the foldback ESD device begins to conduct (now with low resistance), the voltage drops towards the normal operating voltage of the protected circuit, falling below the trigger voltage Vt. In other words, the device remains on and conducts current even after the ESD event has ended.

[0037] ESD protection devices should be selected such that their trigger voltage is not high enough to damage sensitive components of the circuit being protected. Similarly, the holding voltage should be low enough not to fall below the circuit's normal operating voltage so as not to cause the device to shut down after an ESD event.

[0038] Figure 3 The relationship between the foldback current Id (logarithmic scale) and the drain voltage Vd of the ESD device is shown in embodiments with different gate voltages Vg and under-overlap distance X1 = 0. Figure 4 The relationship between the foldback current Id (logarithmic scale) and the drain voltage Vd of ESD devices with different gate voltages Vg and under-overlap distances X1 = 50 nm is shown. Figure 5 The relationship between the foldback current Id (logarithmic scale) and the drain voltage Vd of ESD devices with different gate voltages Vg and under-overlap distances X1 = 100 nm is shown.

[0039] exist Figures 3 to 5 In the diagram, the foldback current Id at gate voltage Vg = 0V represents the leakage current of ESD device 100. For example, comparing... Figure 3 and Figure 4 It can be seen that the overlap distance X1 = 50nm ( Figure 4 The leakage current at Vg = 0V (i.e., the foldback current) is significantly smaller than the overlap distance X1 = 0. Figure 3 The leakage current at which the drain voltage Vd is 5V and the under-overlap distance X1 = 0 is actually the leakage current. Figure 3 At this point, the leakage current is approximately 100 nA, while the drain voltage Vd is 5 V and the under-overlap distance X1 = 50 nm. Figure 4At this point, the leakage current is approximately 0.01 nA. In this respect, compared to when the under-overlap distance X1 = 0, setting the under-overlap distance X1 = 50 nm reduces the leakage current by approximately three orders of magnitude (e.g., 1000 times). A similar reduction in leakage current is provided when the under-overlap distance X1 = 100 nm is used compared to when the under-overlap distance X1 = 0. Based on this data and other data presented herein, it can be inferred that the leakage current decreases when the under-overlap distance X1 > 0.

[0040] Figures 6 to 8 They respectively showed the same as Figures 3 to 5 The data shown is the same, but different scales were used for the foldback current Id (i.e., linear scale vs. logarithmic scale). Specifically, Figure 6 An embodiment is shown with different gate voltages Vg and under-overlap distance X1 = 0. Figure 1 The relationship between the foldback current Id (linear scale) and the drain voltage Vd of the ESD device. Figure 7 Examples are shown with different gate voltages Vg and under-overlap distance X1 = 50 nm. Figure 1 The relationship between the foldback current Id (linear scale) and the drain voltage Vd of the ESD device. Figure 8 Examples are shown with different gate voltages Vg and under-overlap distance X1 = 100 nm. Figure 1 The relationship between the foldback current Id (linear scale) and the drain voltage Vd of the ESD device.

[0041] Compare Figures 6 to 8 As can be seen, the trigger voltage Vt required to turn on the ESD device 100 can be dynamically controlled in a variety of ways. For example, the trigger voltage Vt can be controlled based on the overlap distance X1 of the ESD device 100 and / or the gate voltage Vg applied to the gate structure 114 of the UL-NFET 102 of the ESD device 100. Figure 9 It shows the basis Figures 6 to 8 The data provided shows Figure 1 The table shows the relationship between the trigger voltage Vt, under-overlap distance X1, and gate voltage Vg of the ESD device 100 (Table 1).

[0042] As shown in Table 1, in the absence of under-overlap (under-overlap distance X1 = 0), a gate voltage of approximately 0.2 Vg results in a trigger voltage of approximately 6 V, while a gate voltage of approximately 0.4 Vg results in a trigger voltage of approximately 4.2 V. For an under-overlap distance X1 = 50 nm, the trigger voltage Vt can have a wider range. For example, again from Table 1, in the case of an under-overlap distance X1 = 50 nm, a gate voltage of approximately 0.2 Vg results in a trigger voltage of approximately 10.5 V, while a gate voltage of approximately 0.8 Vg results in a trigger voltage of approximately 3.5 V. The gate voltage Vg set by the voltage divider formed by the series connection of capacitor 104 and intrinsic gate-source capacitance Cgs can also be adjusted by changing the capacitance of capacitor 104 coupled to the gate structure 114 of UL-NFET 102. In summary, the trigger voltage Vt can be dynamically adjusted over a wide range by changing at least one of the following:

[0043] 1) Gate voltage Vg;

[0044] 2) The capacitance of capacitor 104; and

[0045] 3) Under-overlap distance X1.

[0046] ESD device 100 provides a trigger path (TP) for current in response to an ESD event 130 at input pad 122. See below for details. Figure 10 and Figure 11 As described in detail, in response to an ESD event 130, the current actuate flowing along the trigger path passes through the discharge path (DP) of the discharge path device, which safely dissipates the ESD current to ground.

[0047] Figure 10 An ESD device 200 according to an embodiment is shown, comprising a sub-overlapping n-type field-effect transistor (UL-NFET) 202 and an npn device 250 for providing a discharge path. The UL-NFET 202 may be formed in a p-type doped region 208 (e.g., p-well 208 hereinafter) and may include an n+ doped source region 210, a sub-overlapping n+ doped drain region 212, and a gate structure 214. The p-well 208 may be separated from the substrate 252 by an n-type doped region 254 (e.g., an n-well). Again, as described above, a "sub-overlapping region" refers to a diffusion region in which no portion of it is located directly below the gate structure 214. For example, as... Figure 10 As shown, the under-overlapping n+ doped drain region 212 is separated from the edge of the gate structure 214 and the underlying gate channel region 216 by an under-overlapping distance X1. The various doped regions described herein can be formed in any known manner (e.g., via ion implantation). The various gate structures described herein can also be formed in any known manner.

[0048] A silicide barrier layer, including a source-side silicide barrier (SOP) region 218 and a drain-side silicide barrier (DOP) region 220, can be formed over the p-well 208 and the under-overlapping n+-doped drain region 212. The formation of the silicide barrier layer may include, for example, depositing an insulating layer and selectively etching the insulating layer. The silicide barrier layer may be formed, for example, from silicon oxide or silicon nitride.

[0049] According to an embodiment, the under-overlapping n+ doped drain region 212 can be coupled to an input terminal or pad 222 (hereinafter referred to as input pad 222). The gate structure 214 of the UL-NFET 202 can also be coupled to the input pad 222 via a capacitor 204. The gate structure 214 and the n+ doped source region 210 of the UL-NFET 202 can be coupled to ground via resistors R1 and R2, respectively. The n+ doped source region 210 can also be coupled to a p+ doped region 256 formed in the p-well 208 and can be isolated from the n+ doped source region 210 by an isolation region 258 (e.g., a shallow trench isolation region or a silicon barrier region). The isolation region described herein can be formed in any known manner, such as by etching a trench pattern in the p-well 208, depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trench, and removing excess dielectric material using techniques such as chemical mechanical planarization. Similar to Figure 1 The gate voltage Vg applied to the gate structure 214 of the UL-NFET 202 of the ESD device 100 shown can be set by a voltage divider formed by the series connection of capacitor 204 and the intrinsic gate-source capacitance of the UL-NFET 202.

[0050] The npn device 250 can be formed from an under-overlapping n+ doped drain region 212 (shared by the UL-NFET 202), an n+ doped region 260 formed in the p-well 208, and the p-well 208 itself. Figure 10 As shown, the under-overlapping n+ doped drain region 212 is isolated from the n+ doped region 260 by the isolation region 258.

[0051] The UL-NFET 202 can be activated in response to an ESD event 230 at the input pad 222. For example, the UL-NFET 202 can be activated when the voltage between the n+ doped source region 210 and the under-overlapping n+ doped drain region 212 is greater than the trigger voltage Vt of the UL-NFET 202. In this case, current flows along the trigger path (TP) from the under-overlapping n+ doped drain region 212 to the n+ doped source region 210, and then through resistor R2 to ground. The bias of the p-well 208 is increased via the p+ doped region 256, thereby activating the npn device 250. When the npn device 250 is activated, current flows along the discharge path (DP) from the under-overlapping n+ doped drain region 212 through the n+ doped region 260 to ground.

[0052] Figure 11 An ESD device 300 according to an embodiment is shown, comprising an n-type field-effect transistor (UL-NFET) 302 and a silicon controlled rectifier (SCR) device 350 for providing a discharge path. The UL-NFET 302 may be formed in a p-type doped substrate 308 and may include an n+ doped source region 310, a sub-overlapping n+ doped drain region 312, and a gate structure 314. Again, as described above, a "sub-overlapping region" refers to a diffusion region in which no portion of it is located directly below the gate structure 314. For example, as... Figure 11 As shown, the under-overlapping n+ doped drain region 312 is separated from the edge of the gate structure 314 and the underlying gate channel region 316 by an under-overlapping distance X1. The various doped regions described herein can be formed in any known manner (e.g., via ion implantation). The various gate structures described herein can also be formed in any known manner.

[0053] A silicide barrier layer, including a source-side silicide barrier (SOP) region 318 and a drain-side silicide barrier (DOP) region 320, can be formed over a p-type doped substrate 308 and an under-overlapping n+ doped drain region 312. The formation of the silicide barrier layer may include, for example, depositing an insulating layer and selectively etching the insulating layer. The silicide barrier layer may be formed, for example, from silicon oxide or silicon nitride.

[0054] According to an embodiment, the gate structure 314 of the UL-NFET 302 can be coupled to an input terminal or a pad 322 (hereinafter referred to as input pad 322) via a capacitor 304. The gate structure 314 of the UL-NFET 302 can also be coupled to ground via a resistor R. The n+ doped source region 310 of the UL-NFET 302 can also be coupled to ground. A p+ doped substrate contact 356 can be formed in a p-type doped substrate 308 and can be isolated from the n+ doped source region 310 via an isolation region 358 (e.g., a shallow trench isolation region or a silicon barrier region). According to an embodiment, the gate voltage Vg applied to the gate structure 314 of the UL-NFET 302 can be set by a voltage divider formed by the series connection of the capacitor 304 and the intrinsic gate-source capacitance Cgs of the UL-NFET 302.

[0055] The SCR device 350 according to an embodiment may include an n-type doped region (hereinafter referred to as n-well 360) and a p-type doped region (hereinafter referred to as p-well 362). Furthermore, the SCR device 350 may include a partially overlapping n+ doped drain region 312 (which partially extends over the p-type doped substrate 308 and n-well 360), a p+ doped region 364 isolated from the partially overlapping n+ doped drain region 312 and coupled to an input pad 322 via an isolation region 358, an n+ doped region 366 formed in the p-well 362 and coupled to ground, and a p+ doped region 368 formed in the p-well 362 and coupled to ground. The isolation region 358 may be formed between the p+ doped region 364 and the n+ doped region 366, and between the n+ doped region 366 and the p+ doped region 368.

[0056] The UL-NFET 302 can be activated in response to an ESD event 330 at the input pad 322. When a positive ESD current is applied to the input pad 322, the diode formed by the p+ doped region 364 and the n-well 360 is forward biased, and current flows into the n-well 360 connected to the under-overlapping n+ doped drain region 312 of the UL-NFET 302. The UL-NFET 302 is then activated when the voltage between the n+ doped source region 310 and the under-overlapping n+ doped drain region 312 is greater than the trigger voltage Vt of the UL-NFET 302. In this case, current flows along the trigger path (TP) from the p+ doped region 364 to the n+ doped source region 310. This current path injects holes into the n-well 360 of the SCR, which can trigger the SCR 350 and provide a discharge path to ground.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0058] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximately,” and “substantially” are not limited to specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. An “approximate” term applied to a specific value within a range applies to both values ​​and may indicate + / - 10% of said value unless otherwise dependent on the precision of the instrument used to measure the value.

[0059] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. An electrostatic discharge (ESD) device, comprising: Input pad; An under-overlapping field-effect transistor (UL-FET) with a trigger voltage Vt, comprising: Coupled to the under-overlapping drain region of the input pad; The source region coupled to ground; and A gate structure coupled to the input pad; A barrier layer that separates the under-overlapping drain region of the UL-FET from the gate structure by an under-overlapping distance; and A silicon controlled rectifier (SCR) device, laterally adjacent to the UL-FET, the SCR device comprising: p+ doped region, which is coupled to the input pad and located above the n-well; An n+ doped region is coupled to ground and located above a p-well adjacent to the n-well; A first isolation region is located between the p+ doped region and the n+ doped region; and The under-overlapping drain region extends partially above the n-well and is separated from the p+ doped region by a second isolation region.

2. The ESD device of claim 1 further includes a switching FET for selectively activating the UL-FET.

3. The ESD device of claim 1 further includes a voltage divider for setting the gate voltage Vg applied to the gate structure of the UL-FET.

4. The ESD device of claim 3, wherein the voltage divider further comprises a capacitor coupled to the gate structure and the input pad, the capacitor being connected in series with the intrinsic gate-to-source capacitance of the UL-FET.

5. The ESD device of claim 1, wherein the UL-FET further comprises a trigger path TP formed between the under-overlapping drain region and the source region.

6. The ESD device of claim 1, wherein the SCR device is coupled to the UL-FET for discharging ESD current along a discharge path DP from the input pad to ground in response to an ESD event.

7. The ESD device of claim 1, wherein the trigger voltage Vt of the UL-FET is controlled by at least one of the following: The gate voltage Vg applied to the gate structure; The capacitance of the capacitor coupled to the gate structure and the input pad; and The under-overlap distance between the under-overlapping drain region and the gate structure.

8. A method for electrostatic discharge (ESD) protection, comprising: An ESD device is coupled to the circuit to be protected, the ESD device comprising: An under-overlapping field-effect transistor (UL-FET) includes: an under-overlapping drain region coupled to an input pad; a source region coupled to ground; and a gate structure coupled to the input pad. A barrier layer that separates the under-overlapping drain region of the UL-FET from the gate structure by an under-overlapping distance; and A silicon controlled rectifier (SCR) device laterally adjacent to the UL-FET, the SCR device comprising: a p+ doped region coupled to an input pad and located above an n-well; an n+ doped region coupled to ground and located above a p-well adjacent to the n-well; a first isolation region located between the p+ doped region and the n+ doped region; and an under-overlapping drain region extending partially above the n-well and separated from the p+ doped region by a second isolation region; and Use at least one of the following to control the trigger voltage of the UL-FET: The gate voltage Vg applied to the gate structure of the UL-FET; The capacitance of the capacitor coupled between the gate structure and the input pad of the UL-FET; and The under-overlap distance between the under-overlapping drain region of the UL-FET and the gate structure of the FET.

9. The method of claim 8, further comprising selectively activating the UL-FET using a switching FET.

10. The method of claim 8, further comprising using a voltage divider to set the gate voltage Vg applied to the gate structure of the UL-FET, the voltage divider being formed by a series connection of the capacitor coupled to the gate structure and the input pad and the intrinsic gate-to-source capacitance of the UL-FET.

11. The method of claim 8, further comprising coupling the SCR device to the UL-FET to release ESD current along a discharge path DP from the input pad to ground in response to an ESD event.

12. An electrostatic discharge (ESD) device, comprising: Input pad; A sub-overlapping n-type field-effect transistor UL-NFET with a trigger voltage Vt, comprising: An under-overlapping n+ doped drain region is formed in the p-well and coupled to the input pad; An n+ doped source region is formed in the p-well and coupled to ground; and A gate structure coupled to the input pad; A silicide barrier layer that separates the under-overlapping n+ doped drain region of the UL-NFET from the gate structure by an under-overlapping distance; and A silicon controlled rectifier (SCR) device, laterally adjacent to the UL-NFET, the SCR device comprising: p+ doped region, which is coupled to the input pad and located above the n-well; An n+ doped region is coupled to ground and located above a p-well adjacent to the n-well; A first isolation region is located between the p+ doped region and the n+ doped region; and The under-overlapping n+ drain region extends partially above the n-well and is separated from the p+ doped region by a second isolation region.

13. The ESD device of claim 12, further comprising a switching FET for selectively activating the UL-NFET.

14. The ESD device of claim 12, further comprising a voltage divider for setting the gate voltage Vg applied to the gate structure of the UL-NFET.

15. The ESD device of claim 14, wherein the voltage divider further comprises a capacitor coupled to the gate structure and the input pad, the capacitor being connected in series with the intrinsic gate-to-source capacitance of the UL-NFET.

16. The ESD device of claim 12, wherein the UL-NFET further comprises a trigger path TP, the trigger path TP being formed through the p-well between the under-overlapping n+ doped drain region and the n+ doped source region.

17. The ESD device of claim 12, wherein the SCR device is coupled to the UL-NFET for discharging ESD current along a discharge path DP from the input pad to ground in response to an ESD event.

18. The ESD device of claim 12, wherein the trigger voltage Vt of the UL-NFET is controlled by at least one of the following: The gate voltage Vg applied to the gate structure; The capacitance of the capacitor coupled to the gate structure and the input pad; and The under-overlap distance between the under-overlapping n+ doped drain region and the gate structure.

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