Semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of improving performance and reliability of an element. The semiconductor device includes a substrate including a first region and a second region; a first silicon germanium film conformally formed inside the substrate of the first region and defining a first gate trench; a first gate insulating film extending along an outline of the first gate trench on the first silicon germanium film and in contact with the first silicon germanium film; a first metal gate electrode on the first gate insulating film; a source / drain region formed inside the substrate and disposed on both sides of the first metal gate electrode; a second gate insulating film disposed in the second region; and a second metal gate electrode on the second gate insulating film.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2020-0130911, filed on October 12, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0003] As the feature size of MOS transistors decreases, the gate length and the length of the channel formed under the gate also decrease. Therefore, various studies are underway to increase the capacitance between the gate and the channel and improve the operating characteristics of MOS transistors.

[0004] Silicon oxide films, primarily used as gate insulating films, reach their physical limits in terms of electrical properties as their thickness decreases. Therefore, research is actively underway on high-dielectric films with high dielectric constants to replace conventional silicon oxide films. High-dielectric films can reduce leakage current between the gate electrode and the channel region while maintaining an equivalent oxide film thickness. Summary of the Invention

[0005] This disclosure provides semiconductor devices capable of improving the performance and reliability of components.

[0006] This disclosure also provides methods for manufacturing semiconductor devices that can improve the performance and reliability of components.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0008] According to an aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate including a first region and a second region; a first silicon-germanium film conformally formed within the substrate in the first region and defining a first gate trench; a first gate insulating film extending along the contour of the first gate trench on the first silicon-germanium film and contacting the first silicon-germanium film; a first metal gate electrode located on the first gate insulating film; source / drain regions formed within the substrate and disposed on both sides of the first metal gate electrode; a second gate insulating film disposed in the second region; and a second metal gate electrode located on the second gate insulating film.

[0009] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a silicon-germanium film formed inside a substrate and defining a gate trench; a gate insulating film extending on the silicon-germanium film along the contour of the gate trench; a gate electrode stack filling the gate trench on the gate insulating film; and source / drain regions formed inside the substrate and disposed on both sides of the gate electrode stack, wherein the germanium fraction of the silicon-germanium film decreases as the silicon-germanium film moves away from the gate insulating film, the silicon-germanium film extends along an upper side of the substrate, and portions of the source / drain regions are disposed within the silicon-germanium film.

[0010] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate including a cell region and a peripheral region defined around the cell region; a bit line structure including a cell conductor on the substrate of the cell region and a cell line capping film located on the cell conductor; a cell gate electrode disposed inside the substrate of the cell region and intersecting the cell conductor; a silicon-germanium film conformally formed inside the substrate of the peripheral region and defining a gate trench; a gate insulating film extending along the contour of the gate trench on the silicon-germanium film; and a gate electrode stack filling the gate trench on the gate insulating film, wherein the gate electrode stack includes a lower metal gate electrode and an upper gate electrode located on the lower metal gate electrode, and the upper gate electrode has the same stacking structure as the stacking structure of the cell conductor.

[0011] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a germanium supply film comprising germanium on a silicon substrate; forming a barrier film on the germanium supply film; after forming the barrier film, diffusing germanium in the germanium supply film into the silicon substrate by a first heat treatment process to form a pre-silicon germanium film; recrystallizing the pre-silicon germanium film by a second heat treatment process to form a silicon germanium film; and forming a gate insulating film on the silicon germanium film. Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0013] Figure 1 These are diagrams illustrating a semiconductor device according to some embodiments;

[0014] Figure 2A and Figure 2B These are schematic representations along... Figure 1 A graph showing the fraction of germanium (Ge) along the scan line;

[0015] Figure 3 These are diagrams illustrating a semiconductor device according to some embodiments;

[0016] Figure 4These are diagrams illustrating a semiconductor device according to some embodiments;

[0017] Figure 5 These are diagrams illustrating a semiconductor device according to some embodiments;

[0018] Figure 6 These are diagrams illustrating a semiconductor device according to some embodiments;

[0019] Figure 7 This is a schematic layout diagram of a semiconductor device according to some embodiments;

[0020] Figure 8 It is shown Figure 7 A schematic layout diagram of an enlarged portion of R3;

[0021] Figure 9 It is along Figure 8 A sectional view taken by line AA;

[0022] Figure 10 It is along Figure 8 A sectional view taken by line BB;

[0023] Figure 11 This is a layout diagram used to illustrate a semiconductor device according to some embodiments;

[0024] Figure 12 This is a perspective view used to illustrate a semiconductor device according to some embodiments;

[0025] Figure 13 It is along Figure 11 A cross-sectional view taken from lines CC and DD;

[0026] Figure 14 This is a layout diagram used to illustrate a semiconductor device according to some embodiments;

[0027] Figure 15 This is a perspective view used to illustrate a semiconductor device according to some embodiments;

[0028] Figure 16 and Figure 17 These are diagrams illustrating a semiconductor device according to some embodiments;

[0029] Figure 18 These are diagrams illustrating a semiconductor device according to some embodiments;

[0030] Figures 19 to 24 These are intermediate stage diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments; and

[0031] Figures 25 to 27This is an intermediate stage diagram illustrating a method of manufacturing a semiconductor device according to each of some embodiments. Detailed Implementation

[0032] Figure 1 These are diagrams used to illustrate a semiconductor device according to some embodiments. Figure 2A and Figure 2B These are schematic representations along... Figure 1 A graph showing the fraction of germanium (Ge) along the scan line.

[0033] Reference Figures 1 to 2B A semiconductor device according to some embodiments may include a substrate 100, a first silicon-germanium film 110, a first gate electrode stack 120, a first gate insulating film 130, and a first source / drain region 150.

[0034] The substrate 100 may be a silicon substrate or SOI (silicon-on-insulator). Alternatively, the substrate 100 may include (but is not limited to) silicon germanium, SGOI (silicon-on-insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0035] In a semiconductor device according to some embodiments, substrate 100 may be a silicon substrate. Alternatively, substrate 100 may have a shape in which the silicon substrate and a base substrate made of another material are bonded to each other. The base substrate may be (but is not limited to) a substrate composed of compound semiconductors described above. When substrate 100 is in the form of a combination of silicon substrate and base substrate, a first silicon-germanium film 110, which will be described later, may be formed inside the silicon substrate.

[0036] The first element isolation film 105 may be disposed inside the substrate 100. The first element isolation film 105 may define an active region. The first element isolation film 105 may be formed as a shallow trench isolation (STI) structure. The first element isolation film 105 may be disposed in the thickness direction of the substrate 100 (e.g., Figure 12 The first element isolation film 105 extends from the upper side 100US of the substrate (D4). The thickness direction of the substrate 100 may be perpendicular to the upper side 100US of the substrate. The first element isolation film 105 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0037] The first silicon-germanium film 110 can be formed inside the substrate 100. The first silicon-germanium film 110 can be formed conformally inside the substrate 100.

[0038] For example, the first silicon-germanium film 110 may include a first portion disposed on the upper side 100US of the substrate and a second portion disposed at a position below the upper side 100US of the substrate. Here, the upper side 100US of the substrate 100 is the boundary line between the substrate 100 and the first portion of the first silicon-germanium film 110.

[0039] The first silicon-germanium film 110 may define a first gate trench 110t. The first gate trench 110t may be defined by the first silicon-germanium film 110 disposed at a position 100 μs above the substrate. That is, the first gate trench 110t may be defined by a second portion of the first silicon-germanium film 110.

[0040] The first gate trench 110t can extend from the upper side 100US of the substrate into the substrate 100. The first gate trench 110t can extend from the upper side 100US of the substrate in the thickness direction of the substrate 100.

[0041] In a semiconductor device according to some embodiments, the expression "conformally formed film" can mean forming a film with a uniform thickness. A first silicon-germanium film 110 can be formed within the substrate 100 with a uniform thickness. For example, in the portion of the first silicon-germanium film 110 defining the first gate trench 110t, the ratio of the minimum thickness to the maximum thickness of the first silicon-germanium film 110 can be 90% or greater.

[0042] The first silicon-germanium film 110 may be formed from a silicon-germanium film. For example, the first silicon-germanium film 110 may comprise a single-crystal silicon-germanium film. As an example, the first silicon-germanium film 110 may comprise doped p-type impurities and / or n-type impurities. As another example, the first silicon-germanium film 110 may be formed from an undoped silicon-germanium film. Here, the term "undoped" does not mean excluding impurities, but rather excluding intentionally doped impurities. That is, an undoped silicon-germanium film may or may not contain impurities.

[0043] The first gate insulating film 130 may be disposed on the first silicon-germanium film 110. The first gate insulating film 130 may be in contact with the first silicon-germanium film 110.

[0044] The first gate insulating film 130 may extend along the contour of the first gate trench 110t. The first gate insulating film 130 may extend along the contour of the first silicon-germanium film 110.

[0045] As an example, the first gate insulating film 130 may include a portion extending along the upper side 100µs of the substrate. As another example, unlike the example shown, the first gate insulating film 130 does not include a portion extending along the upper side 100µs of the substrate.

[0046] The first gate insulating film 130 includes a first interface film 131 and a first high-dielectric-constant insulating film 132 sequentially disposed on the first silicon-germanium film 110. The first interface film 131 may be disposed between the first silicon-germanium film 110 and the first high-dielectric-constant insulating film 132. The first interface film 131 may be in direct contact with the first silicon-germanium film 110. The first interface film 131 may include, for example, a silicon oxide film.

[0047] The first high-dielectric-constant insulating film 132 may include, for example, a high-dielectric-constant material having a higher dielectric constant than silicon oxide. The high-dielectric-constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0048] exist Figure 2A and Figure 2B In this process, the germanium fraction of the first silicon-germanium film 110 can change as the first silicon-germanium film 110 moves away from the first gate insulating film 130. For example, the germanium fraction of the first silicon-germanium film 110 decreases as the first silicon-germanium film 110 moves away from the first gate insulating film 130.

[0049] Although the germanium fraction in the first interface film 131 and the germanium fraction in the substrate 100 are shown as 0, this is for illustrative purposes only, and the embodiments are not limited thereto. That is, the first interface film 131 and / or the substrate 100 may include germanium diffused from the first silicon-germanium film 110.

[0050] As an example, at the boundary between the first silicon-germanium film 110 and the substrate 100, the germanium fraction of the first silicon-germanium film 110 is greater than zero. As another example, unlike the example shown, at the boundary between the first silicon-germanium film 110 and the substrate 100, the germanium fraction of the first silicon-germanium film 110 can be 0.

[0051] exist Figure 2A In this process, the germanium fraction of the first silicon-germanium film 110 can decrease continuously as the first silicon-germanium film 110 moves away from the first interface film 131. Although the germanium fraction of the first silicon-germanium film 110 decreases linearly, this is only for illustrative purposes, and the embodiments are not limited thereto.

[0052] exist Figure 2BIn this process, the first silicon-germanium film 110 may include a first portion RA and a second portion RB. Within the first portion RA of the first silicon-germanium film 110, the germanium fraction can be constant. The germanium fraction can continuously decrease within the second portion RB of the first silicon-germanium film 110. The first portion RA of the first silicon-germanium film 110 may be closer to the first interface film 131 than the second portion RB of the first silicon-germanium film 110. For example, the first interface film 131 can be formed by oxidizing the silicon-germanium film. At this time, while the first interface film 131 is being formed, the germanium in the first silicon-germanium film 110 can move in the direction of the substrate 100. That is, while the first interface film 131 is being formed, a germanium concentration appears in the first silicon-germanium film 110 that forms a boundary with the first interface film 131. Therefore, within the first portion RA of the first silicon-germanium film 110, the germanium fraction can be constant.

[0053] The semiconductor device according to some embodiments may include an NC (negative capacitance) FET using a negative capacitor. For example, the first high dielectric constant insulating film 132 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0054] Ferroelectric films can have negative capacitance, and paraelectric films can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is reduced more than the capacitance of each individual capacitor. On the other hand, if at least one of the capacitors connected in series has a negative capacitance, the total capacitance can be greater than the absolute value of each individual capacitor while also being positive. When a ferroelectric film with negative capacitance and a paraelectric film with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric films can be increased. Taking advantage of the increased total capacitance, transistors incorporating ferroelectric films can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0055] Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films can include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide can be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide can also be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0056] Ferroelectric material films may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The types of dopants included in the ferroelectric material film can vary depending on the type of ferroelectric material included in the film.

[0057] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0058] When the dopant is aluminum (Al), the ferroelectric film can include 3 at% to 8 at% (atomic percentage) aluminum. Here, the dopant ratio can be the ratio of aluminum to the sum of hafnium and aluminum.

[0059] When the dopant is silicon (Si), the ferroelectric film may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric film may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric film may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric film may include 50 at% to 80 at% zirconium.

[0060] The paraelectric material film may possess paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide.

[0061] Ferroelectric and paraelectric material films can comprise the same material. Although ferroelectric material films possess ferroelectric properties, paraelectric material films may not. For example, when ferroelectric and paraelectric material films include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film differs from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0062] The ferroelectric material film can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film can be, for example (but not limited to), 0.5 nm to 10 nm. Since the critical thickness exhibiting ferroelectric properties can vary for each ferroelectric material, the thickness of the ferroelectric material film can vary depending on the ferroelectric material. As an example, the first gate insulating film 130 may include a single ferroelectric material film. As another example, the first gate insulating film 130 may include multiple ferroelectric material films spaced apart from each other. The first gate insulating film 130 may include a stacked film structure in which multiple ferroelectric material films and multiple paraelectric material films are alternately stacked.

[0063] The first gate electrode stack 120 can be disposed on the first gate insulating film 130. The first gate electrode stack 120 can fill the first gate trench 110t.

[0064] As an example, the first gate electrode stack 120 may include a portion covering the upper side 100µs of the substrate. As another example, unlike the example shown, the first gate electrode stack 120 does not include a portion covering the upper side 100µs of the substrate.

[0065] Although a single first gate electrode stack 120 is shown disposed between adjacent first element isolation films 105, this is only for illustrative purposes and the embodiments are not limited thereto.

[0066] The first gate electrode stack 120 may include a first lower gate electrode 123 and a first upper gate electrode 125.

[0067] The first lower gate electrode 123 may be disposed on the first gate insulating film 130. The first lower gate electrode 123 may extend along the contour of the first gate insulating film 130. For example, the first lower gate electrode 123 may fill the portion of the first gate trench 110t in which the first gate insulating film 130 is formed.

[0068] The first lower gate electrode 123 may be, for example, a metal gate electrode comprising a metallic conductive material. That is, the first lower gate electrode 123 may be a lower metal gate electrode. For example, metals, conductive metal nitrides, conductive metal oxides, conductive metal carbides, or conductive metal carbonitrides may be included in the metallic conductive material. In the following description, the metal includes metals and metal alloys.

[0069] The first lower gate electrode 123 may include a first lower gate electrode 121 and a first lower gate electrode 122. The first lower gate electrode 121 may be disposed on the first gate insulating film 130. The first lower gate electrode 121 may extend along the contour of the first gate insulating film 130. The first lower gate electrode 122 may be disposed on the first lower gate electrode 121. The first lower gate electrode 122 may extend along the contour of the first lower gate electrode 121. The first lower gate electrode 121 may be, for example, a p-type work function film. The first lower gate electrode 121 may include, for example (but not limited to), at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), and tantalum carbonitride (TaCN). The first lower gate electrode 122 may be, for example, an n-type work function film. The first lower gate electrode 122 may include, for example (but not limited to), at least one of titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), tantalum aluminum nitride (TaAlN), and tantalum aluminum carbonitride (TaAlCN).

[0070] Unlike the example shown, the first lower gate electrode 123 may include only one of the first_1 lower gate electrode 121 and the first_2 lower gate electrode 122.

[0071] The first upper gate electrode 125 can be disposed on the first lower gate electrode 123. The first upper gate electrode 125 can fill the first gate trench 110t on which the first lower gate electrode 123 is formed.

[0072] The first upper gate electrode 125 may include a first semiconductor gate electrode 126 and a first upper metal gate electrode 127.

[0073] A first semiconductor gate electrode 126 may be disposed on a first lower gate electrode 123. The first semiconductor gate electrode 126 may fill a first gate trench 110t on which the first lower gate electrode 123 is formed. The first semiconductor gate electrode 126 comprises a semiconductor material. The first semiconductor gate electrode 126 may include, for example, a semiconductor material doped with impurities. The first semiconductor gate electrode 126 may include, for example, at least one selected from doped silicon, doped silicon-germanium, and doped germanium.

[0074] The first upper metal gate electrode 127 may be disposed on the first semiconductor gate electrode 126. Although the first upper metal gate electrode 127 is shown as a single film, this is only for illustrative purposes, and the embodiments are not limited thereto. Although not shown, a metal silicide film may be further disposed between the first semiconductor gate electrode 126 and the first upper metal gate electrode 127.

[0075] The first upper metal gate electrode 127 may include, for example, a metallic conductive material. The first upper metal gate electrode 127 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (… Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), ruthenium aluminum (RuAl), nickel aluminum (NiAl), niobium diboride (NbB2), molybdenum diboride (MoB2), tantalum diboride (TaB2), vanadium aluminum carbide (V2AlC) and chromium aluminum carbide (CrAlC), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and at least one combination thereof.

[0076] The first semiconductor gate electrode 126 includes an upper side 126US facing the first upper metal gate electrode 127. The upper side 126US of the first semiconductor gate electrode 126 may include a first wedge-shaped region 126US_W recessed toward the substrate 100.

[0077] The upper side 126US of the first semiconductor gate electrode 126 may include a first curved surface 126_CS1 and a second curved surface 126_CS2. The first curved surface 126_CS1 and the second curved surface 126_CS2 may have an upwardly convex shape based on the upper side 100US of the substrate 100.

[0078] A first wedge-shaped region 126US_W on the upper side 126US of the first semiconductor gate electrode 126 can be defined by connecting the first curved surface 126_CS1 and the second curved surface 126_CS2. As an example, the first wedge-shaped region 126US_W on the upper side 126US of the first semiconductor gate electrode 126 can be defined by directly connecting the first curved surface 126_CS1 and the second curved surface 126_CS2. As another example, unlike the example shown, in the first wedge-shaped region 126US_W on the upper side 126US of the first semiconductor gate electrode 126, the upper side 126US of the first semiconductor gate electrode 126 may also include a connecting surface connecting the first curved surface 126_CS1 and the second curved surface 126_CS2. The connecting surface may have a raised shape (such as the bottom surface of the first gate trench 110t) facing the substrate 100.

[0079] Although the upper side of the first upper metal gate electrode 127 is shown not to have a shape similar to the upper side 126US of the first semiconductor gate electrode 126, the embodiment is not limited thereto. Unlike the example shown, the upper side of the first upper metal gate electrode 127 may of course include a wedge-shaped region similar to the upper side 126US of the first semiconductor gate electrode 126.

[0080] Unlike the example shown, the first gate electrode stack 120 may not include the first semiconductor gate electrode 126. That is, the first upper gate electrode 125 may consist of only the first upper metal gate electrode 127.

[0081] A first gate mask pattern 145 may be disposed on a first gate electrode stack 120. The first gate mask pattern 145 may be disposed on a first upper metal gate electrode 127. The first gate mask pattern 145 may include (but is not limited to) an insulating material, and may include, for example, silicon oxide, silicon oxynitride, silicon nitride, etc.

[0082] A first gate spacer 140 may be disposed on a sidewall of the first gate electrode stack 120. A first gate mask pattern 145 may be disposed between the first gate spacers 140. The first gate spacers 140 cover at least a portion of the sidewall of the first gate mask pattern 145. The first gate spacers 140 comprise an insulating material and may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon oxycarbonate (SiOC). Although the first gate spacer 140 is shown as a single film, this is only for illustrative purposes, and the embodiments are not limited thereto.

[0083] The first source / drain region 150 may be disposed on both sides of the first gate electrode stack 120. The first source / drain region 150 may be formed inside the substrate 100.

[0084] The first source / drain region 150 may be formed inside a first silicon-germanium film 110 disposed on the upper side 100µs of the substrate. For example, a portion of the first source / drain region 150 may be disposed inside the first silicon-germanium film 110.

[0085] An interlayer insulating film 190 is disposed on the substrate 100. The interlayer insulating film 190 covers the first source / drain region 150 and the first gate mask pattern 145. The interlayer insulating film 190 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0086] The first contact 180 can penetrate the interlayer insulating film 190 and connect to the first source / drain region 150. The top surface of the first contact 180 can be higher than the top surface of the first gate mask pattern 145.

[0087] The first contact 180 may include, for example, a conductive material. The first contact 180 may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, a conductive metal oxide, and a two-dimensional (2D) material. Although the first contact 180 is shown as a single film, this is for illustrative purposes only, and the embodiments are not limited thereto.

[0088] Figure 3 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main focus will be on the description and use of... Figures 1 to 2B The differences explained.

[0089] Reference Figure 3 In a semiconductor device according to some embodiments, the upper side 126US of the first semiconductor gate electrode 126 does not include a wedge-shaped region. Figure 1 (126US_W).

[0090] The upper side 126US of the first semiconductor gate electrode 126 does not include a portion recessed toward the substrate 100. For example, the upper side 126US of the first semiconductor gate electrode 126 may be flat, like the upper side 100US of the substrate 100.

[0091] Figure 4 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main focus will be on the description and use of... Figures 1 to 2B The differences are explained. For reference, Figure 4 The attached diagram shown in the first region I can be compared with... Figure 1 The attached diagrams are basically the same. That is to say, Figure 4 Explanation and use of the first area I Figures 1 to 2B The descriptions are essentially the same. The explanation will be based on Region II. Figure 4 Explanation.

[0092] Reference Figure 4 A semiconductor device according to some embodiments may include a substrate 100, a first silicon-germanium film 110, a first gate electrode stack 120, a first gate insulating film 130, a first source / drain region 150, a second silicon-germanium film 210, a second gate electrode stack 220, a second gate insulating film 230, and a second source / drain region 250.

[0093] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be regions spaced apart from each other or regions connected to each other. In a semiconductor device according to some embodiments, the first region I and the second region II may be MOSFET forming regions (e.g., PMOS forming regions).

[0094] The first silicon-germanium film 110, the first gate electrode stack 120, the first gate insulating film 130, and the first source / drain region 150 can be disposed in the first region I of the substrate 100.

[0095] The second silicon-germanium film 210, the second gate electrode stack 220, the second gate insulating film 230, and the second source / drain region 250 can be disposed in the second region II of the substrate 100.

[0096] A second silicon-germanium film 210 may be formed on the substrate 100. The second silicon-germanium film 210 may be conformally formed on the substrate 100. The second silicon-germanium film 210 may be disposed on the upper side 100US of a flat substrate. The second silicon-germanium film 210 may extend along the upper side 100US of the substrate. Unlike the first silicon-germanium film 110, the second silicon-germanium film 210 does not define a gate trench extending from the upper side 100US of the substrate in the thickness direction of the substrate 100. The second silicon-germanium film 210 may be formed of a silicon-germanium film. For example, the second silicon-germanium film 210 may comprise a single-crystal silicon-germanium film.

[0097] The second gate insulating film 230 may be disposed on the second silicon-germanium film 210. The second gate insulating film 230 may be in contact with the second silicon-germanium film 210. The second gate insulating film 230 may extend along the contour of the second silicon-germanium film 210. The second gate insulating film 230 may be disposed on the upper side 100 μs of a flat substrate. The second gate insulating film 230 may include a second interface film 231 and a second high-dielectric-constant insulating film 232 sequentially disposed on the second silicon-germanium film 210. The portion concerning the material included in the second gate insulating film 230 may be the same as the description concerning the first gate insulating film 130.

[0098] The germanium fraction of the second silicon-germanium film 210 can change as the second silicon-germanium film 210 moves away from the second gate insulating film 230. For example, the germanium fraction of the second silicon-germanium film 210 decreases as the second silicon-germanium film 210 moves away from the second gate insulating film 230.

[0099] The second gate electrode stack 220 may be disposed on the second gate insulating film 230. The second gate electrode stack 220 may not include any portion disposed at a position 100 μs above the substrate. The second gate electrode stack 220 may include a second lower gate electrode 223 and a second upper gate electrode 225.

[0100] The second lower gate electrode 223 may be disposed on the second gate insulating film 230. The second lower gate electrode 223 may extend along the contour of the second gate insulating film 230. The second lower gate electrode 223 may be, for example, a metal gate electrode comprising a metallic conductive material.

[0101] The second lower gate electrode 223 may include a second -1 lower gate electrode 221 and a second -2 lower gate electrode 222 sequentially disposed on the second gate insulating film 230. The second -1 lower gate electrode 221 may be, for example, a p-type work function film. The second -2 lower gate electrode 222 may be, for example, an n-type work function film.

[0102] The second upper gate electrode 225 may be disposed on the second lower gate electrode 223. The second upper gate electrode 225 may include a second semiconductor gate electrode 226 and a second upper metal gate electrode 227. The upper side of the second semiconductor gate electrode 226 does not include a wedge-shaped region. Figure 1 (126US_W).

[0103] The second gate electrode stack 220 may be formed at the same level as the first gate electrode stack 120. Here, the term "at the same level" means that they are formed by the same manufacturing process. Except that a portion of the first gate electrode stack 120 is positioned 100 μs below the upper side of the substrate, the stacking structure of the second gate electrode stack 220 may be the same as that of the first gate electrode stack 120.

[0104] A second gate mask pattern 245 may be disposed on the second gate electrode stack 220. The second gate mask pattern 245 may be disposed on the second upper metal gate electrode 227. The second gate mask pattern 245 may include an insulating material. A second gate spacer 240 may be disposed on the sidewall of the second gate electrode stack 220. The second gate mask pattern 245 may be disposed between the second gate spacers 240. The second gate spacers 240 cover at least a portion of the sidewall of the second gate mask pattern 245. The second gate spacer 240 includes an insulating material.

[0105] The second source / drain region 250 can be disposed on both sides of the second gate electrode stack 220. The second source / drain region 250 can be formed inside the substrate 100.

[0106] The second source / drain region 250 can be formed inside the second silicon-germanium film 210 disposed on the upper side 100 μs of the substrate. For example, a portion of the second source / drain region 250 can be disposed inside the second silicon-germanium film 210.

[0107] The second contact 280 can penetrate the interlayer insulating film 190 and connect to the second source / drain region 250. The top surface of the second contact 280 can be higher than the top surface of the second gate mask pattern 245.

[0108] Figure 5 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main focus will be on the description and use of... Figures 1 to 2B and Figure 4 The differences explained.

[0109] Reference Figure 5 In a semiconductor device according to some embodiments, the first region I may be a PMOS forming region and the second region II may be an NMOS forming region.

[0110] The second gate insulating film 230 can be in contact with the substrate 100. For example, the second interface film 231 can be in contact with the substrate 100.

[0111] Figure 4 The second silicon-germanium film 210 described in the text is not set. Figure 5 The second gate insulating film 230 is between the substrate 100.

[0112] The second lower gate electrode 223 may include the second -2 lower gate electrode 222. As an example, the second lower gate electrode 223 does not include the second -1 lower gate electrode between the second -2 lower gate electrode 222 and the second gate insulating film 230. Figure 4 221). Unlike the example shown, as another example, the second lower gate electrode 223 may include a second lower gate electrode 221 between the second lower gate electrode 222 and the second gate insulating film 230. Figure 4 (221). At this time, the thickness of the first lower gate electrode 121 formed in the first region I can be greater than that of the second lower gate electrode formed in the second region II (e.g., Figure 4 The thickness of 221) is thick.

[0113] Figure 6 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main focus will be on the description and use of... Figures 1 to 2B and Figure 5 The differences explained.

[0114] Reference Figure 6 In a semiconductor device according to some embodiments, the substrate 100 of the second region II may include a second gate trench 210t.

[0115] The second gate trench 210t can extend from the upper side 100US of the substrate into the substrate 100. The second gate trench 210t can extend from the upper side 100US of the substrate in the thickness direction of the substrate 100.

[0116] The second gate insulating film 230 may extend along the contour of the second gate trench 210t.

[0117] The second gate electrode stack 220 can fill the second gate trench 210t. The second lower gate electrode 223 can extend along the contour of the second gate insulating film 230. For example, the second lower gate electrode 223 can fill the portion of the second gate trench 210t in which the second gate insulating film 230 is formed.

[0118] The second upper gate electrode 225 can fill the second gate trench 210t in which the second lower gate electrode 223 is formed. The second semiconductor gate electrode 226 can fill the second gate trench 210t in which the second lower gate electrode 223 is formed.

[0119] The second semiconductor gate electrode 226 includes an upper side 226US facing the second upper metal gate electrode 227. The upper side 226US of the second semiconductor gate electrode may include a second wedge-shaped region 226US_W recessed toward the substrate 100. The description of the second wedge-shaped region 226US_W is related to the use of… Figure 1 The description of the first wedge region 126US_W is basically the same.

[0120] Figure 7 This is a schematic layout diagram of a semiconductor device according to some embodiments. Figure 8 It is shown Figure 7 A schematic layout diagram of an enlarged portion of R3. Figure 9 It is along Figure 8 The sectional view taken by line AA.

[0121] Figure 10 It is along Figure 8 A cross-sectional view taken by line BB. For reference, although DRAM (Dynamic Random Access Memory) is shown as an example in the drawings of semiconductor devices according to some embodiments, the embodiments are not limited thereto. Furthermore, Figure 8 The layout diagram is shown, excluding the first capacitor 390.

[0122] Reference Figure 7 According to some embodiments, a semiconductor device may include a cell region 20 and a peripheral region 30 defined around the cell region 20.

[0123] To illustrate in another way, the base ( Figure 1 The memory region 20 (100) may include a cell region 20 and a peripheral region 30. For example, the cell region 20 may be a region in which memory cells are disposed. The peripheral region 30 may be a region in which circuitry for operating the memory cells of the cell region 20 is disposed.

[0124] Figure 7 A sectional view of part R1 cut in the first direction D1 or the second direction D2 can be a first sectional view. Figure 7A sectional view of portion R2 cut along either the first direction D1 or the second direction D2 can be a second sectional view. The first direction D1 may intersect with the second direction D2.

[0125] As an example, the first sectional view and the second sectional view could be Figure 1 and Figure 3 One of them. As another example, the first sectional view could be... Figures 4 to 6 The first region I shown in the diagram, and the second sectional view may be Figures 4 to 6 The diagram shown in the second region II. As yet another example, the first sectional view could be... Figures 4 to 6 The second section view is shown in the diagram of the second region II, and the second section view may be... Figures 4 to 6 The diagram shown in the first region I.

[0126] To illustrate in another way, using Figures 1 to 6 The semiconductor device described can be set in Figure 7 The outer area is 30.

[0127] because Figure 7 Part of R1 and Figure 7 The description of part R2 is similar to that using Figures 1 to 6 Those explained, therefore will be mainly based on Figure 7 The following explanation will be based on part R3.

[0128] Reference Figure 8 A semiconductor device according to some embodiments may include a plurality of first active regions ACT. The first active regions ACT may be formed on a substrate ( Figure 9 The second element, the isolation membrane, inside the 100) Figure 9 (305) is limited.

[0129] As shown, with the reduction of design rules for semiconductor devices, the first active region ACT can be arranged in the form of a diagonal or oblique strip. The first active region ACT can have the shape of a strip extending along a third direction D3.

[0130] Multiple gate electrodes may be disposed across the first active region ACT in the first direction D1. The multiple gate electrodes may extend parallel to each other. The multiple gate electrodes may, for example, be multiple word lines WL.

[0131] Word lines (WL) can be spaced at equal intervals. The width of the word lines (WL) or the spacing between them can be determined according to design rules.

[0132] Multiple bit lines BL extending along a second direction D2 orthogonal to the word line WL can be set on the word line WL. These multiple bit lines BL can extend across the first active region ACT along the second direction D2.

[0133] Multiple bit lines (BLs) can extend parallel to each other. Bit lines (BLs) can be set at equal intervals. The width of a bit line (BL) or the gap between bit lines (BLs) can be determined according to design rules.

[0134] The semiconductor device according to some embodiments may include various contact arrangements formed on a first active region ACT. These various contact arrangements may include, for example, direct contacts DC, buried contacts BC, landing pads LP, etc.

[0135] Here, the direct contact DC can represent the contact that electrically connects the first active region ACT to the bit line BL. The buried contact BC can represent the contact that connects the first active region ACT to the first capacitor ( Figure 9 The first lower electrode of (390) Figure 9 391) of the contact components.

[0136] Due to the arrangement structure, the contact area between the buried contact BC and the first active region ACT will be small. Therefore, in order to increase the contact area with the first active region ACT and the first lower electrode of the first capacitor ( Figure 9 With a contact area of ​​391, a conductive bonding pad LP can be introduced.

[0137] The bonding pad LP can be disposed between the first active region ACT and the buried contact BC, and can also be disposed between the buried contact BC and the first lower electrode of the first capacitor. Figure 9 Between 391). In a semiconductor device according to some embodiments of the present disclosure, the bonding pad LP may be disposed between the buried contact BC and the first lower electrode of the first capacitor ( Figure 9 Between 391). By increasing the contact area through the introduction of the bonding pad LP, the contact area between the first active region ACT and the first capacitor ( Figure 9 The first lower electrode of (390) Figure 9 The contact resistance between 391).

[0138] In a semiconductor device according to some embodiments, a direct contact DC may be disposed at the center portion of a first active region ACT. A buried contact BC may be disposed at both ends of the first active region ACT. When the buried contact BC is disposed at both ends of the first active region ACT, a bonding pad LP may be disposed partially overlapping with the buried contact BC to be adjacent to both ends of the first active region ACT. Alternatively, the buried contact BC may be formed as an isolation film between the first active region ACT and the second element between adjacent word lines WL and adjacent bit lines BL. Figure 9 (305) stacked.

[0139] The word line WL can be formed as a structure embedded within the substrate 100. The word line WL can be positioned across the first active region ACT between direct contacts DC or between embedded contacts BC.

[0140] As shown, two word lines WL can span a first active region ACT setting. By setting the first active region ACT diagonally, the word lines WL can have an angle of less than 90 degrees with the first active region ACT.

[0141] The direct contact element DC and the buried contact element BC can be arranged symmetrically. Therefore, the direct contact element DC and the buried contact element BC can be arranged on a straight line along the first direction D1 and the second direction D2.

[0142] On the other hand, unlike the direct contact DC and the buried contact BC, the bonding pad LP can be arranged in a zigzag pattern on the bit line BL along its second direction D2. Furthermore, the bonding pad LP can be configured to overlap the word line WL on the same side portion of each bit line BL along its first direction D1.

[0143] For example, each of the bonding pads LP of the first line is stacked to the left of the corresponding bit line BL, and each of the bonding pads LP of the second line can be stacked to the right of the corresponding bit line BL.

[0144] Reference Figures 8 to 10 According to some embodiments, a semiconductor device may include a second element isolation film 305, a plurality of gate structures 310, a plurality of bit line structures 340ST, bit line contacts 346, storage contacts 320, and a first capacitor 390.

[0145] like Figure 8 As shown, the first active region ACT defined by the second element isolation film 305 can have an island shape including a short axis and a long axis. The first active region ACT can have a slanted shape with an angle of less than 90 degrees relative to the word line WL formed in the second element isolation film 305. Furthermore, the first active region ACT can have a slanted shape with an angle of less than 90 degrees relative to the bit line BL formed on the second element isolation film 305.

[0146] A gate structure 310 may be formed in the substrate 100 and the second element isolation film 305. The gate structure 310 may be formed across the second element isolation film 305 and the first active region ACT defined by the second element isolation film 305. That is, a gate structure 310 may be formed in the substrate 100 and the second element isolation film 305 positioned in a first direction D1, and the gate structure 310 extends along the first direction D1.

[0147] The gate structure 310 may include a third gate trench 314, a third gate insulating film 311, a first gate electrode 312, and a gate cap pattern 313 formed in the substrate 100 and the second element isolation film 305. Here, the first gate electrode 312 may correspond to the word line WL.

[0148] The third gate insulating film 311 may extend along the sidewalls and bottom surface of the third gate trench 314. The third gate insulating film 311 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-dielectric-constant material having a higher dielectric constant than silicon oxide. The high-dielectric-constant material may be combined with… Figure 1 The description is the same as that of the first high dielectric constant insulating film 132.

[0149] The first gate electrode 312 may be formed on the third gate insulating film 311. The first gate electrode 312 may fill a portion of the third gate trench 314. The first gate electrode 312 may include at least one of a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The first gate electrode 312 may be made of, for example (but not limited to), doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or a combination thereof.

[0150] Although not shown, an impurity-doped region may be formed on at least one side of the gate structure 310. The impurity-doped region may be the source / drain region of the transistor.

[0151] A gate cap pattern 313 may be formed on the first gate electrode 312. The gate cap pattern 313 may fill the third gate trench 314 retained after the formation of the first gate electrode 312. The gate cap pattern 313 includes an insulating material.

[0152] Bit line structure 340ST may include cell conductors 340 and cell line capping films 344. Cell conductors 340 may be formed on a substrate 100 on which a gate structure 310 is formed, and on a second element isolation film 305. Cell conductors 340 may intersect with the second element isolation film 305 and a first active region ACT defined by the second element isolation film 305. A single cell conductor 340 may be formed on the substrate 100 and the second element isolation film 305 positioned in a second direction D2, extending along the second direction D2. Cell conductors 340 may be formed to intersect with the gate structure 310. Here, cell conductors 340 may correspond to bit lines BL.

[0153] The cell conductor 340 may include a lower cell conductor 341 and an upper cell conductor 343 located on the lower cell conductor 341. In a semiconductor device according to some embodiments, the cell conductor 340 may have a connection with a first upper gate electrode ( Figure 1 125) and the second upper gate electrode ( Figure 4 The stacking structure is the same as that of the stacking structure of the first upper gate electrode 125 and the second upper gate electrode 225. For example, when the first upper gate electrode 125 and the second upper gate electrode 225 have a multi-film structure, the unit wire 340 may have the same multi-film structure as the first upper gate electrode 125 and the second upper gate electrode 225.

[0154] Optionally, when the formation includes the unit region ( Figure 7 When the conductive material in the lower unit conductor 341 of (20) is formed, it can be included in the peripheral region ( Figure 7 The conductive material in the first semiconductor gate electrode 126 of (30). Furthermore, when forming a conductive material included in the cell region ( Figure 7 When the conductive material in the upper unit conductor 343 of (20) is formed, it can be included in the peripheral region ( Figure 7 The conductive material in the first upper metal gate electrode 127 of (30).

[0155] Bit line contact 346 can be formed between unit conductor 340 and substrate 100. That is, unit conductor 340 can be formed on bit line contact 346. For example, bit line contact 346 can be formed at the point where unit conductor 340 intersects with the central portion of the first active region ACT having an island shape. Bit line contact 346 can be formed between substrate 100 and unit conductor 340 at the central portion of the first active region ACT. Bit line contact 346 can electrically connect unit conductor 340 and substrate 100. Bit line structure 340ST can be connected to the first active region ACT through bit line contact 346. Bit line contact 346 can correspond to direct contact DC. Bit line contact 346 can include at least one of, for example, doped semiconductor material, conductive silicide compound, conductive metal nitride, conductive metal oxide, and metal.

[0156] The unit line cover 344 can be disposed on the unit conductor 340. The unit line cover 344 includes an insulating material.

[0157] The unit insulating film 330 can be formed on the substrate 100 and the second element isolation film 305. The unit insulating film 330 can be formed on the substrate 100 and the second element isolation film 305 on which the bit line contact 346 is not formed. The unit insulating film 330 can be formed between the substrate 100 and the unit wire 340, and between the second element isolation film 305 and the unit wire 340. Although the unit insulating film 330 can be a single film, as shown, the unit insulating film 330 can be a multilayer film including a first unit insulating film 331 and a second unit insulating film 332. For example, the first unit insulating film 331 may include an oxide film, and the second unit insulating film 332 may include a nitride film, but the embodiments are not limited thereto.

[0158] The unit line spacer 350 may be disposed on the sidewall of the unit line conductor 340 and the sidewall of the unit line cover film 344. Although the unit line spacer 350 may be a single film, as shown, the unit line spacer 350 may be a multilayer film including a first unit line spacer 351 and a second unit line spacer 352. For example, the first unit line spacer 351 and the second unit line spacer 352 may include (but are not limited to) a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon carbonitride (SiOCN) film, air, and combinations thereof.

[0159] Storage contacts 320 may be formed between adjacent cell conductors 340. Storage contacts 320 may be stacked with the substrate 100 and the second element isolation film 305 between adjacent cell conductors 340. Here, storage contacts 320 may correspond to buried contacts BC. Storage contacts 320 may include at least one of, for example, doped semiconductor materials, conductive silicide compounds, conductive metal nitrides, conductive metal oxides, and metals.

[0160] Storage pad 360 may be formed on storage contact 320. Storage pad 360 may be electrically connected to storage contact 320. Here, storage pad 360 may correspond to bonding pad LP. Storage pad 360 may include at least one of, for example, a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal oxide, and a metal.

[0161] A pad-type insulating film 380 can be formed on the storage pad 360 and the bit line structure 340ST. For example, the pad-type insulating film 380 can be disposed on the cell line cover film 344. The pad-type insulating film 380 can define an area of ​​the storage pad 360 forming multiple isolation regions. Furthermore, the pad-type insulating film 380 can be patterned to expose at least a portion of the upper surface of the storage pad 360. The pad-type insulating film 380 includes an insulating material.

[0162] A first capacitor 390 may be formed on a pad-insulating membrane 380. The first capacitor 390 may be electrically connected to a storage contact 320 via a storage pad 360. The first capacitor 390 includes a first lower electrode 391, a first capacitor dielectric film 392, and a first upper electrode 393.

[0163] A first lower electrode 391 may be disposed on the storage pad 360. Although the first lower electrode 391 is shown as having a cylindrical shape, the embodiment is not limited thereto. Of course, the first lower electrode 391 may have a cylindrical shape. A first capacitor dielectric film 392 is formed on the first lower electrode 391. The first capacitor dielectric film 392 may be formed along the contour of the first lower electrode 391. A first upper electrode 393 is formed on the first capacitor dielectric film 392. The first upper electrode 393 may surround the outer wall of the first lower electrode 391.

[0164] The first lower electrode 391 and the first upper electrode 393 may include, for example (but not limited to), doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride), metals (e.g., ruthenium, iridium, titanium or tantalum) and conductive metal oxides (e.g., iridium oxide or niobium oxide).

[0165] The first capacitor dielectric film 392 may include, for example (but not limited to), silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0166] Figure 11 It is a layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 12 This is a perspective view used to illustrate a semiconductor device according to some embodiments. Figure 13 It is along Figure 11 A cross-sectional view taken from lines CC and DD. For reference, Figure 11 It can be Figure 7 A magnified view of part R3.

[0167] Reference Figures 11 to 13 A semiconductor device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420, a channel layer 430, a second gate electrode 440, a fourth gate insulating film 450, and a second capacitor 480. A semiconductor device according to some embodiments may be a memory device including a vertical channel transistor (VCT). A vertical channel transistor may refer to a structure in which the channel length of the channel layer 430 extends vertically from the substrate 100.

[0168] A lower insulating layer 412 may be disposed on a substrate 100. A plurality of first conductors 420 may be spaced apart from each other in a first direction D1 and extend along a second direction D2 on the lower insulating layer 412. A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill the spaces between the plurality of first conductors 420. The plurality of first insulating patterns 422 may extend along the second direction D2. The upper surface of the plurality of first insulating patterns 422 may be disposed at the same level as the upper surface of the plurality of first conductors 420. The plurality of first conductors 420 may serve as bit lines.

[0169] The multiple first conductive lines 420 may include doped semiconductor materials, metals, conductive metal nitrides, conductive metal silicides, conductive metal oxides, or combinations thereof. For example, the multiple first conductive lines 420 may be made of (but not limited to) doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or a combination thereof. The plurality of first conductive lines 420 may comprise a single layer or multiple layers of the aforementioned materials. In an exemplary embodiment, the plurality of first conductive lines 420 may comprise graphene, carbon nanotubes, or a combination thereof.

[0170] The channel layer 430 can be arranged in a matrix form spaced apart in a first direction D1 and a second direction D2 on a plurality of first conductors 420. The channel layer 430 can have a first width along the first direction D1 and a first height along a fourth direction D4, and the first height can be greater than the first width. Here, the fourth direction D4 can be, for example, a direction that intersects the first direction D1 and the second direction D2 and is perpendicular to the upper side of the substrate 100. For example, the first height can be (but is not limited to) about 2 to 10 times the first width. The bottom of the channel layer 430 is used as a third source / drain region (not shown), the upper part of the channel layer 430 is used as a fourth source / drain region (not shown), and the portion of the channel layer 430 between the third source / drain region and the fourth source / drain region can be used as a channel region (not shown).

[0171] In an exemplary embodiment, the channel layer 430 may include an oxide semiconductor; for example, the oxide semiconductor may include In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In xZn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y O or combinations thereof. The channel layer 430 may comprise a single layer or multiple layers of oxide semiconductor. In some embodiments, the channel layer 430 may have a bandgap energy greater than that of silicon. For example, the channel layer 430 may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer 430 may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer 430 may be (but is not limited to) polycrystalline or amorphous. In exemplary embodiments, the channel layer 430 may comprise graphene, carbon nanotubes, or combinations thereof.

[0172] The second gate electrode 440 may extend along a first direction D1 on both sidewalls of the channel layer 430. The second gate electrode 440 may include a first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 and a second sub-gate electrode 440P2 facing the second sidewall opposite to the first sidewall of the channel layer 430. Since a single channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor device can have a dual-gate transistor structure. However, the technical concept of this disclosure is not limited thereto. By omitting the second sub-gate electrode 440P2, only the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 can be formed to achieve a single-gate transistor structure. The material included in the second gate electrode 440 may be compatible with… Figure 10 The description of the first gate electrode 312 is the same.

[0173] The fourth gate insulating film 450 surrounds the sidewall of the channel layer 430 and can be disposed between the channel layer 430 and the second gate electrode 440. For example, as Figure 11As shown, the entire sidewall of the channel layer 430 may be surrounded by the fourth gate insulating film 450, and a portion of the sidewall of the second gate electrode 440 may contact the fourth gate insulating film 450. In other embodiments, the fourth gate insulating film 450 extends along the extension direction of the second gate electrode 440 (i.e., the first direction D1), and among the sidewalls of the channel layer 430, only the two sidewalls facing the second gate electrode 440 may contact the fourth gate insulating film 450. In an exemplary embodiment, the fourth gate insulating film 450 may be composed of a silicon oxide film, a silicon oxynitride film, a high dielectric constant material having a higher dielectric constant than that of a silicon oxide film, or a combination thereof.

[0174] Multiple second insulating patterns 432 may extend along a second direction D2 over multiple first insulating patterns 422. A channel layer 430 may be disposed between two adjacent second insulating patterns 432. Furthermore, a first buried layer 434 and a second buried layer 436 may be disposed in the space between two adjacent channel layers 430 and between two adjacent second insulating patterns 432. The first buried layer 434 may be disposed at the bottom of the space between two adjacent channel layers 430. The second buried layer 436 may be formed on the first buried layer 434 to fill the remaining space between the two adjacent channel layers 430. The upper surface of the second buried layer 436 is disposed at the same level as the upper surface of the channel layers 430, and the second buried layer 436 may cover the upper surface of the second gate electrode 440. In contrast, the multiple second insulating patterns 432 may be formed from a material layer continuous with the multiple first insulating patterns 422, or the second buried layer 436 may also be formed from a material layer continuous with the first buried layer 434.

[0175] Capacitor contacts 460 may be disposed on the channel layer 430. The capacitor contacts 460 are configured to be vertically stacked with respect to the channel layer 430 and may be arranged in a matrix form spaced apart in a first direction D1 and a second direction D2. The capacitor contacts 460 may be made of (but not limited to) doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or a combination thereof. The upper insulating layer 462 may surround the sidewalls of the capacitor contact 460 on a plurality of second insulating patterns 432 and a second buried layer 436.

[0176] An etch stop film 470 may be disposed on the upper insulating layer 462. A second capacitor 480 may be disposed on the etch stop film 470. The second capacitor 480 may include a second lower electrode 482, a second capacitor dielectric film 484, and a second upper electrode 486. The second lower electrode 482 may penetrate the etch stop film 470 and be electrically connected to the upper surface of the capacitor contact 460. The second lower electrode 482 may (but is not limited to) be formed in a cylindrical shape extending along a fourth direction D4. In an exemplary embodiment, the second lower electrode 482 is configured to be vertically stacked with the capacitor contact 460 and may be arranged in a matrix form spaced apart in a first direction D1 and a second direction D2. In contrast, a bonding pad (not shown) may be further disposed between the capacitor contact 460 and the second lower electrode 482, and the second lower electrode 482 may be arranged in a hexagonal shape.

[0177] Figure 14 It is a layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 15 This is a perspective view used to illustrate a semiconductor device according to some embodiments.

[0178] Reference Figure 14 and Figure 15 A semiconductor device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a second capacitor 480. A semiconductor device according to some embodiments may be a memory device including a vertical channel transistor (VCT).

[0179] Multiple second active regions AC can be defined on the substrate 100 by means of a first element isolation pattern 412A and a second element isolation pattern 414A. A channel structure 430A can be disposed inside each second active region AC. The channel structure 430A may include a vertically extending first active post 430A1 and a second active post 430A2, and a connecting portion 430L respectively connected to the bottom of the first active post 430A1 and the bottom of the second active post 430A2. A fifth source / drain region SD1 can be disposed inside the connecting portion 430L. A sixth source / drain region SD2 can be disposed on the top surface of the first active post 430A1 and the top surface of the second active post 430A2. Each of the first active post 430A1 and the second active post 430A2 can form an independent unit memory cell.

[0180] Multiple first conductors 420A may extend in a direction intersecting each of the multiple second active regions AC, and may extend, for example, in a second direction D2. One of the multiple first conductors 420A may be disposed on the connection portion 430L between the first active post 430A1 and the second active post 430A2. One first conductor 420A may be disposed on the fifth source / drain region SD1. Another first conductor 420A adjacent to one first conductor 420A may be disposed between two channel structures 430A. One of the multiple first conductors 420A may be used as a common line included in two unit memory cells, the unit memory cell being composed of a first active post 430A1 and a second active post 430A2 disposed on both sides of a first conductor 420A.

[0181] A contact gate electrode 440A may be disposed between two adjacent channel structures 430A along the second direction D2. For example, the contact gate electrode 440A may be disposed between a first active post 430A1 included in a channel structure 430A and a second active post 430A2 of a channel structure 430A adjacent to the first active post 430A1. A contact gate electrode 440A may be shared by the first active post 430A1 and the second active post 430A2 disposed on its two sidewalls. A fourth gate insulating film 450A may be disposed between the contact gate electrode 440A and the first active post 430A1, and between the contact gate electrode 440A and the second active post 430A2. A plurality of second conductors 442A may extend along the first direction D1 on the top surface of the contact gate electrode 440A. The plurality of second conductors 442A may be used as word lines of a semiconductor device.

[0182] Capacitor contact 460A can be disposed on channel structure 430A. Capacitor contact 460A can be disposed on sixth source / drain region SD2, and second capacitor 480 can be disposed on capacitor contact 460A.

[0183] Figure 16 and Figure 17 These are diagrams used to illustrate a semiconductor device according to some embodiments. Figure 16 It is a layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 17 It is along Figure 16 A cross-sectional view taken from line EE. For reference, Figure 17 A finned transistor (FinFET) can be shown.

[0184] Reference Figure 16 and Figure 17 According to some embodiments, a semiconductor device may include a multi-channel active pattern 515, a third silicon-germanium film 510, a third gate electrode 520, and a fifth gate insulating film 530.

[0185] A multi-channel active pattern 515 may be formed on the substrate 100. The multi-channel active pattern 515 may protrude from the substrate 100. The multi-channel active pattern 515 may extend along a fifth direction D5. In a semiconductor device according to some embodiments, the multi-channel active pattern 515 may be a silicon fin pattern.

[0186] A field insulating film 505 may be disposed on a substrate 100. The field insulating film 505 may cover a portion of the sidewall 515SW of the multi-channel active pattern. The multi-channel active pattern 515 may protrude upward from the top of the field insulating film 505. The field insulating film 505 includes an insulating material.

[0187] The third silicon-germanium film 510 can be formed on the upwardly projecting sidewall 515SW of the field insulating film 505 of the multi-channel active pattern 515. The third silicon-germanium film 510 can be conformally formed along the contour of the upwardly projecting sidewall of the field insulating film 505 of the multi-channel active pattern 515. A portion of the third silicon-germanium film 510 can be covered by the field insulating film 505. The third silicon-germanium film 510 can be formed of a silicon-germanium film. For example, the third silicon-germanium film 510 may include a single-crystal silicon-germanium film.

[0188] A fifth gate insulating film 530 may be formed on the third silicon-germanium film 510. The fifth gate insulating film 530 may extend along the contour of the third silicon-germanium film 510 and over the field insulating film 505. The fifth gate insulating film 530 may include a third interface film 531 and a third high-dielectric-constant insulating film 532 sequentially disposed on the third silicon-germanium film 510. Although the third interface film 531 is shown as being formed on the third silicon-germanium film 510 rather than over the field insulating film 505, the embodiment is not limited thereto. The germanium fraction of the third silicon-germanium film 510 decreases as the third silicon-germanium film 510 moves away from the fifth gate insulating film 530.

[0189] For example, the semiconductor fin pattern, including the third silicon-germanium film 510 and the multi-channel active pattern 515, can be divided into an upper and a lower portion based on the top surface of the field insulating film 505. The third silicon-germanium film 510 is not formed on the multi-channel active pattern 515 by a deposition process. As a result, on the top surface of the field insulating film 505, the width of the upper portion of the semiconductor fin patterns 510 and 515 in the sixth direction D6 can be the same as, or smaller than, the width of the lower portion of the semiconductor fin patterns 510 and 515 in the sixth direction D6.

[0190] The third silicon-germanium film 510 may include a sidewall 510SW facing the fifth gate insulating film 530. As an example, when the width of the upper portion of the semiconductor fin patterns 510 and 515 in the sixth direction D6 is the same as the width of the lower portion of the semiconductor fin patterns 510 and 515 in the sixth direction D6, the sidewall 510SW of the third silicon-germanium film may be aligned with the sidewall 515SW of the multi-channel active pattern 515.

[0191] Unlike the example shown, as another example, when the width of the upper part of the semiconductor fin patterns 510 and 515 in the sixth direction D6 is smaller than the width of the lower part of the semiconductor fin patterns 510 and 515 in the sixth direction D6, the sidewall 510SW of the third silicon-germanium film may not be aligned with the sidewall 515SW of the multi-channel active pattern 515.

[0192] The third gate electrode 520 may be disposed on the fifth gate insulating film 530. The third gate electrode 520 may extend along the sixth direction D6. The fifth direction D5 may intersect with the sixth direction D6. The third gate electrode 520 may include a metallic conductive material. A third gate mask pattern 545 may be disposed on the third gate electrode 520. The third gate mask pattern 545 includes an insulating material.

[0193] Figure 18 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main focus will be on the description and use of... Figure 16 and Figure 17 The differences explained. Figure 18 Transistors that include nanowires or nanosheets can be shown.

[0194] Reference Figure 18 In a semiconductor device according to some embodiments, a multi-channel active pattern 515 may include a lower active pattern 515B and an upper active pattern 515U.

[0195] The field insulating film 505 can cover at least a portion of the sidewall of the lower active pattern 515B. The upper active pattern 515U can be in the fourth direction ( Figure 16 The upper and lower active patterns 515B are spaced apart on D4. Each upper active pattern 515U may also be spaced apart from each other on the fourth direction D4. The upper active patterns 515U and the lower active patterns 515B comprise silicon.

[0196] The third silicon-germanium film 510 can be disposed along the top of the lower active pattern 515B and the periphery of the upper active pattern 515U.

[0197] The fifth gate insulating film 530 can wrap the active pattern 515U. The third gate electrode 520 can wrap the active pattern 515U.

[0198] Figures 19 to 24This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0199] Reference Figure 19 A gate recess 100R can be formed inside the substrate 100. For example, the substrate 100 can be a silicon substrate.

[0200] A germanium supply film 110FF can be formed on substrate 100. The germanium supply film 110FF can be formed along the upper side of substrate 100 and the contour of gate recess 100R. The germanium supply film 110FF may include germanium. The germanium supply film 110FF may include at least one of a silicon-germanium film and a germanium film. The germanium supply film 110FF can be formed using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). Although the germanium supply film 110FF is shown not to be formed on the first element isolation film 105, the embodiments are not limited thereto.

[0201] The germanium supply film 110FF can have a thickness, for example (but not limited to), between 5 nm and 50 nm. The germanium fraction of the germanium supply film 110FF can be (but not limited to) 30% or more and 100% or less.

[0202] Reference Figure 20 A barrier film 110BF can be formed on the germanium supply film 110FF. The barrier film 110BF can be formed along the contour of the germanium supply film 110FF. The barrier film 110BF can extend along the top surface of the first element isolation film 105.

[0203] The barrier film 110BF prevents germanium supplied to the germanium supply film 110FF from diffusing in a direction away from the substrate 100 during a subsequent heat treatment process. The barrier film 110BF may include an insulating material, such as at least one of a silicon oxide film and a silicon nitride film.

[0204] Reference Figure 21 Germanium in the germanium supply film 110FF can be diffused into the substrate 100 through a first heat treatment process 50. As a result, a pre-silicon germanium film 110P can be formed in the substrate 100.

[0205] While performing the first heat treatment process 50, germanium in the germanium supply film 110FF can be uniformly diffused into the substrate 100, regardless of the planarity index of the substrate 100. That is, while performing the first heat treatment process 50, germanium in the germanium supply film 110FF can be isotropically diffused into the substrate 100. Therefore, a pre-silicon germanium film 110P can be conformally formed within the substrate 100.

[0206] Since the pre-silicon germanium film 110P is formed by germanium diffused from the germanium supply film 110FF, the germanium fraction of the pre-silicon germanium film 110P is less than the germanium fraction of the germanium supply film 110FF.

[0207] The barrier film 110BF is used to prevent germanium in the germanium supply film 110FF from diffusing outward in a direction away from the substrate 100. That is, when the first heat treatment process 50 is performed at a heat treatment temperature where the outward diffusion of germanium is insignificant, the first heat treatment process 50 can be performed without forming the barrier film 110BF.

[0208] Reference Figure 22 The barrier film 110BF and the germanium supply film 110FF can be removed sequentially. The germanium fraction of the germanium supply film 110FF is higher than that of the pre-silicon germanium film 110P. That is, due to the difference in germanium fraction, the pre-silicon germanium film 110P can have a different etch selectivity than the germanium supply film 110FF. The germanium supply film 110FF can be removed using a process that has different etch selectivity depending on the germanium fraction.

[0209] Reference Figure 23 The pre-silicon-germanium film 110P can be recrystallized through a second heat treatment process 55. As a result, a first silicon-germanium film 110 can be formed. The first silicon-germanium film 110 can define a first gate trench 110t.

[0210] The first time during which the second heat treatment process 55 is performed is shorter than the second time during which the first heat treatment process 50 is performed. The second heat treatment process 55 is performed for a shorter time than the first heat treatment process 50 to prevent germanium diffusion in the pre-silicon germanium film 110P.

[0211] Reference Figure 24 A pre-gate insulating film 130P can be formed on the first silicon-germanium film 110. The pre-gate insulating film 130P may include a pre-interface film 131P and a pre-high dielectric constant insulating film 132P.

[0212] Subsequently, a gate electrode stack film can be formed on the pre-gate insulating film 130P. The gate electrode stack film and the pre-gate insulating film 130P can be patterned to form a first gate insulating film 130 and a first gate electrode stack 120 on the substrate 100.

[0213] Figures 25 to 27 These are intermediate stage diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments. For reference, Figures 25 to 27 Each of them can be in Figure 20 The process that was performed previously.

[0214] Reference Figure 25 The substrate 100 does not include the gate recess 100R. A germanium supply film 110FF may be formed on the upper side of the flat substrate 100.

[0215] Reference Figure 26A multi-channel active pattern 515 is formed on a substrate 100 as a protruding structure. A field insulating film 505 is formed on the substrate 100, partially covering a portion of the sidewalls of the multi-channel active pattern 515. A germanium supply film 110FF is formed along the protrusion of the multi-channel active pattern 515 beyond the contour of the field insulating film 505.

[0216] Reference Figure 27 A multi-channel active pattern 515, including a lower active pattern 515B and an upper active pattern 515U, is formed on the substrate 100. A germanium supply film 110FF can be formed along the upper surface of the lower active pattern 515B and the periphery of the upper active pattern 515U.

[0217] Next, through the first heat treatment process ( Figure 21 50) and the second heat treatment process ( Figure 23 55) forms a silicon-germanium film.

[0218] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed preferred embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor device, the semiconductor device comprising: The substrate includes a first region and a second region; A first silicon-germanium film is conformally formed inside a substrate in a first region and defines a first gate trench; A first gate insulating film extends along the contour of the first gate trench on the first silicon-germanium film and contacts the first silicon-germanium film; The first metal gate electrode is located on the first gate insulating film; Source / drain regions are formed inside the substrate and disposed on both sides of the first metal gate electrode; A second gate insulating film is disposed in the second region; as well as The second metal gate electrode is located on the second gate insulating film.

2. The semiconductor device according to claim 1, wherein The germanium fraction of the first silicon-germanium film changes as the first silicon-germanium film moves further away from the first gate insulating film.

3. The semiconductor device according to claim 2, wherein The germanium fraction of the first silicon-germanium film decreases as the first silicon-germanium film moves further away from the first gate insulating film.

4. The semiconductor device according to claim 1, wherein, The first metal gate electrode extends along the contour of the first gate insulating film, and The first metal gate electrode fills a portion of the first gate trench.

5. The semiconductor device according to claim 4, further comprising: A semiconductor gate electrode is disposed on the first metal gate electrode and fills the first gate trench. Semiconductor gate electrodes are made of semiconductor materials.

6. The semiconductor device according to claim 5, wherein The upper surface of the semiconductor gate electrode includes a wedge-shaped region defined by connecting a first curved surface and a second curved surface.

7. The semiconductor device according to claim 1, wherein Each of the first gate insulating film and the second gate insulating film includes an interface film and a high dielectric constant insulating film located on the interface film.

8. The semiconductor device according to claim 1, wherein The second gate insulating film is disposed on the upper side of the flat substrate.

9. The semiconductor device according to claim 8, wherein, The first region is the PMOS formation region, and the second region is the NMOS formation region.

10. The semiconductor device according to claim 8, further comprising: The second silicon-germanium film extends along the upper side of the substrate in the second region. The second gate insulating film is disposed on the second silicon-germanium film, and Each of the first and second regions is a PMOS formation region.

11. The semiconductor device according to claim 1, wherein The substrate of the second region includes a second gate trench. The second gate insulating film extends along the contour of the second gate trench, and The first region is the PMOS formation region, and the second region is the NMOS formation region.

12. The semiconductor device according to claim 1, wherein The first silicon-germanium film is disposed on the upper side of the substrate in the first region, and The source / drain regions are partially disposed within the first silicon-germanium film.

13. A semiconductor device, the semiconductor device comprising: A silicon-germanium film is formed inside the substrate and defines a gate trench; A gate insulating film extends along the contour of the gate trench on a silicon-germanium film; A gate electrode stack, wherein a gate trench is filled on a gate insulating film; and Source / drain regions are formed inside the substrate and disposed on both sides of the gate electrode stack. Among them, the germanium fraction of the silicon-germanium film decreases as the silicon-germanium film moves further away from the gate insulating film. The silicon-germanium film extends along the upper side of the substrate, and The source / drain regions are partially set in a silicon-germanium film.

14. The semiconductor device according to claim 13, wherein The gate insulating film includes a silicon oxide film formed on a silicon-germanium film and a high-dielectric-constant insulating film disposed on the silicon oxide film, and The silicon oxide film comes into contact with the silicon-germanium film.

15. The semiconductor device according to claim 13, wherein The gate electrode stack includes a lower metal gate electrode on the gate insulating film, a semiconductor gate electrode on the lower metal gate electrode, and an upper metal gate electrode on the semiconductor gate electrode.

16. The semiconductor device according to claim 15, wherein The surface of the semiconductor gate electrode faces upward, and the surface of the metal gate electrode includes a wedge-shaped region defined by connecting a first curved surface and a second curved surface.

17. A semiconductor device, the semiconductor device comprising: The base includes the unit region and the peripheral region defined around the unit region; Bitline structure, comprising a unit wire and a unit line cover film located on the unit wire on the substrate of the unit region; The unit grid electrode is disposed inside the substrate of the unit region and intersects with the unit wire; A silicon-germanium film is conformally formed inside the substrate in the peripheral region and defines a gate trench; A gate insulating film extends along the contour of the gate trench on a silicon-germanium film; as well as Gate electrode stack, with gate trenches filled on the gate insulating film. The gate electrode stack includes a lower metal gate electrode and an upper gate electrode located on the lower metal gate electrode. The upper gate electrode has the same stacking structure as the cell wire stacking structure.

18. The semiconductor device according to claim 17, wherein, The germanium fraction of the silicon-germanium film decreases as the silicon-germanium film moves further away from the gate insulating film.

19. The semiconductor device according to claim 17, wherein The gate insulating film includes a silicon oxide film formed on a silicon-germanium film and a high-dielectric-constant insulating film disposed on the silicon oxide film, and The silicon oxide film comes into contact with the silicon-germanium film.

20. The semiconductor device of Claim 17, wherein, The upper gate electrode includes a semiconductor gate electrode and an upper metal gate electrode located on the semiconductor gate electrode. The lower metal gate electrode extends along the contour of the gate insulating film. The lower metal gate electrode fills a portion of the gate trench, and The semiconductor gate electrode fills the gate trench.

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