Semiconductor device, semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device, a semiconductor structure and a method for manufacturing the same. The semiconductor device comprises a support pillar, a semiconductor layer surrounding at least part of an outer surface of the support pillar, the semiconductor layer having a first end and a second end oppositely arranged along a first direction, a first electrode connected to the first end of the semiconductor layer and extending away from the semiconductor layer, a second electrode connected to the second end of the semiconductor layer and extending away from the semiconductor layer, and a gate surrounding at least part of the semiconductor layer and insulated from the semiconductor layer, wherein the first direction is an axial direction of the support pillar, and the semiconductor layer, the first electrode and the second electrode comprise a two-dimensional material. The semiconductor device has a small contact resistance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device, a semiconductor structure, and a method for manufacturing the same. Background Technology

[0002] Currently, semiconductor devices in this field all form their source and drain electrodes on etched or epitaxially grown silicon pillars. However, with the development of semiconductor technology, there is a continuous need to shrink the linewidth of semiconductor devices. However, as the linewidth of existing semiconductor devices continues to shrink, the contact resistance between the metal traces and the semiconductor becomes too high, resulting in insufficient current to meet the normal operating requirements of the semiconductor device. Therefore, there is an urgent need in this field to provide a semiconductor device with lower contact resistance.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor device, a semiconductor structure, and a method for fabricating the same. This semiconductor device can have a low contact resistance.

[0005] The first aspect of this disclosure provides a semiconductor device, comprising:

[0006] Support column;

[0007] A semiconductor layer surrounds at least a portion of the outer surface of the support pillar, and the semiconductor layer has a first end and a second end disposed opposite to each other along a first direction;

[0008] A first electrode is connected to a first end of the semiconductor layer and extends away from the semiconductor layer;

[0009] The second electrode is connected to the second end of the semiconductor layer and extends away from the semiconductor layer.

[0010] A gate, which surrounds at least a portion of the semiconductor layer and is insulated from the semiconductor layer;

[0011] Wherein, the first direction is the axial direction of the support column, and the materials of the semiconductor layer, the first electrode, and the second electrode include two-dimensional materials.

[0012] In one exemplary embodiment of this disclosure, the projection of the first electrode in the first direction coincides with the projection of the semiconductor layer in the first direction;

[0013] The projection of the second electrode in the first direction coincides with the projection of the semiconductor layer in the first direction.

[0014] In one exemplary embodiment of this disclosure, the support column has a first column portion, a second column portion, and a third column portion connected to each other, the first column portion being located between the second column portion and the third column portion, the semiconductor layer surrounding the outer surface of the first column portion, the first electrode surrounding the outer surface of the second column portion, and the second electrode surrounding the outer surface of the third column portion.

[0015] In one exemplary embodiment of this disclosure, the first electrode includes:

[0016] A first sub-electrode is connected to a first end of the semiconductor layer and extends away from the semiconductor layer.

[0017] The second sub-electrode is connected to the end of the first sub-electrode away from the semiconductor layer, and is attached to the end of the second pillar away from the first pillar.

[0018] In one exemplary embodiment of this disclosure, the semiconductor device further includes:

[0019] A gate dielectric layer is disposed between the gate and the semiconductor layer, and the material of the gate dielectric layer is an insulating material.

[0020] A second aspect of this disclosure provides a semiconductor structure, comprising:

[0021] The substrate has bit line grooves;

[0022] Bit lines are located within the bit line grooves;

[0023] A semiconductor device located on the side of the bit line away from the substrate, and the semiconductor device is any one of the semiconductor devices described above;

[0024] The first electrode trace is located on the surface of the substrate and is attached to the bit line, and the first electrode trace is connected to the first electrode.

[0025] The second electrode trace is connected to the second electrode.

[0026] In one exemplary embodiment of this disclosure, the support column has a first column portion, a second column portion, and a third column portion connected to each other, the first column portion being located between the second column portion and the third column portion, the semiconductor layer surrounding the outer surface of the first column portion, the first electrode surrounding the outer surface of the second column portion, and the second electrode surrounding the outer surface of the third column portion;

[0027] The first electrode trace is located between the semiconductor device and the bit line, and is connected to the end of the first electrode away from the semiconductor layer;

[0028] The second electrode trace wraps around the surface of the second electrode away from the third post.

[0029] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0030] A first insulating layer and a second insulating layer; wherein the first insulating layer is located between the first electrode trace and the gate; and the second insulating layer is located between the second electrode trace and the gate.

[0031] In one exemplary embodiment of this disclosure, the first electrode further includes:

[0032] The first sub-electrode is connected to the first end of the semiconductor layer and extends away from the semiconductor layer, and the first sub-electrode is connected to the first electrode trace;

[0033] The second sub-electrode is connected to the end of the first sub-electrode away from the semiconductor layer and is located between the first electrode trace and the second pillar, and the second sub-electrode is connected to the first electrode trace.

[0034] In one exemplary embodiment of this disclosure, the first electrode trace is located at the end of the support post away from the second electrode, and the first electrode is arranged around the first electrode trace;

[0035] The second electrode trace is located at the end of the support post away from the first electrode, and the second electrode is arranged around the second electrode trace.

[0036] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0037] A capacitive contact structure is located on the surface of the second electrode and the second electrode trace away from the substrate.

[0038] In one exemplary embodiment of this disclosure, the substrate has spaced bit line trenches, and the semiconductor structure has the bit lines, the semiconductor device, the first electrode trace, the second electrode trace, and the capacitive contact structure.

[0039] In this configuration, all bit lines are located within the bit line trenches, and at least one semiconductor device may be disposed on the side of the bit line away from the substrate; the first electrode trace is attached to the bit line and connected to the first electrode; and the capacitive contact structures are all located on the surface of the second electrode and the second electrode trace away from the substrate.

[0040] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0041] A third insulating layer is located between two adjacent second electrode traces and also between two adjacent capacitor contact structures.

[0042] A third aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0043] A substrate is provided, and bit line trenches are formed on the substrate;

[0044] A bit line is embedded in the bit line trench;

[0045] A first electrode trace is formed on the surface of the substrate, and the first electrode trace is made to be attached to the bit line;

[0046] A semiconductor device is formed on the side of the bit line away from the substrate, wherein the semiconductor device is any of the semiconductor devices described above, a second electrode trace is formed, the first electrode is connected to the first electrode trace, and the second electrode trace is connected to the second electrode.

[0047] In one exemplary embodiment of this disclosure, forming a first electrode trace on the surface of the substrate and attaching the first electrode trace to the bit line includes:

[0048] A first electrode wiring layer is formed on the surface of the substrate and the bit line;

[0049] The substrate and the first electrode trace layer are etched to form a first groove and a first electrode trace, wherein the orthographic projection of the first groove on the substrate extends along a second direction.

[0050] In one exemplary embodiment of this disclosure, forming a semiconductor device on the side of the bit line away from the substrate and forming a second electrode trace, connecting the first electrode to the first electrode trace and connecting the second electrode trace to the second electrode, includes:

[0051] A first insulating material layer is formed on the surface of the first electrode trace and in the first groove. The first insulating material layer located in the first groove forms a first isolation structure, and the remaining first insulating material layer forms a first insulating layer.

[0052] A gate sacrificial layer, a second insulating layer, and a second electrode wiring layer are sequentially formed on the first insulating layer;

[0053] Using the first electrode trace as a stop layer, the second electrode trace layer is etched to form a plurality of first vias, the first vias extending to the surface of the first electrode trace away from the substrate;

[0054] The support post, the first electrode, the second electrode, and the semiconductor layer are formed within the first through hole;

[0055] Remove the gate sacrificial layer to form a gate retention region;

[0056] A gate and a gate dielectric layer are formed in the gate retention region;

[0057] The second electrode trace layer is etched to form the second electrode trace;

[0058] The gate surrounds the semiconductor layer, and the gate dielectric layer is located between the gate and the semiconductor layer.

[0059] In one exemplary embodiment of this disclosure, forming the support post, the first electrode, the second electrode, and the semiconductor layer within the first through-hole includes:

[0060] Semiconductor material is deposited at least on the sidewall of the first via to form the first electrode, the second annular electrode, and the semiconductor layer, wherein the semiconductor material includes a two-dimensional material;

[0061] A support material is filled into the inner surfaces of the first electrode, the second electrode, and the semiconductor layer to form the support pillar and a support layer at least on the surface of the support pillar and the second annular electrode away from the substrate.

[0062] In one exemplary embodiment of this disclosure, removing the gate sacrificial layer to form a gate retention region includes:

[0063] Using the first insulating layer as a stop layer, the support layer is etched to form a plurality of spaced second grooves, and the second grooves extend to the surface of the first insulating layer away from the substrate. The orthographic projection of the second groove on the substrate does not overlap with the orthographic projection of the first through hole on the substrate.

[0064] The gate sacrificial layer is removed through the second groove to form the gate retention area.

[0065] In one exemplary embodiment of this disclosure, forming the gate and the gate dielectric layer in the gate retention region includes:

[0066] A gate dielectric layer is formed around the side of the semiconductor layer away from the support pillar;

[0067] The gate is formed around the side of the gate dielectric layer away from the semiconductor layer, and the orthogonal projection of the gate on the substrate does not overlap with the orthogonal projection of the second groove on the substrate.

[0068] In one exemplary embodiment of this disclosure, forming the gate around the side of the gate dielectric layer away from the semiconductor layer includes:

[0069] A gate material is formed in the gate retention area and the second groove through the second groove to form a gate material layer;

[0070] Remove the gate material layer located within the second recess to form the gate;

[0071] A second isolation structure is formed within the second groove where the gate material layer has been removed.

[0072] In one exemplary embodiment of this disclosure, etching the second electrode wiring layer to form the second electrode wiring includes:

[0073] Using the second insulating layer as a stop layer, the second electrode trace layer is etched to form a third groove. The third groove and the second groove intersect each other, dividing the second electrode trace layer into multiple spaced second electrode traces.

[0074] In one exemplary embodiment of this disclosure, the manufacturing method further includes:

[0075] An insulating material is deposited on the side of the second electrode trace away from the substrate and within the third groove to form a third insulating layer;

[0076] The third insulating layer is etched, and a second via is formed within the third insulating layer, the second via exposing the second electrode and the second electrode trace;

[0077] Conductive material is deposited within the second through-hole to form a capacitive contact structure.

[0078] The technical solution provided in this disclosure can achieve the following beneficial effects:

[0079] The semiconductor device disclosed herein includes a support pillar, a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer, the first electrode, and the second electrode are all made of two-dimensional materials. Therefore, when the first electrode and the second electrode come into contact with metal traces, the two-dimensional materials of the first and second electrodes result in a low contact resistance between them and the metal traces, thereby ensuring the normal operation of the semiconductor device.

[0080] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0081] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0082] Figure 1 A schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure is shown;

[0083] Figure 2 A schematic diagram of a semiconductor structure is shown, illustrating another exemplary embodiment of the present disclosure;

[0084] Figure 3 A schematic diagram of a semiconductor structure is shown in yet another exemplary embodiment of this disclosure;

[0085] Figure 4 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown;

[0086] Figure 5 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to another exemplary embodiment of the present disclosure is shown;

[0087] Figures 6-17 A schematic diagram of the process structure of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Attached image description:

[0089] 1. Support pillar; 2. First electrode; 3. Second electrode; 4. Semiconductor layer; 5. Gate; 6. Gate dielectric layer; 7. Substrate; 8. Bit line; 9. First electrode trace; 10. Second electrode trace; 11. First insulating layer; 12. Second insulating layer; 13. Capacitor contact structure; 14. Third insulating layer; 15. Second electrode trace layer; 16. First isolation structure; 17. Second groove; 18. First via; 19. Gate sacrificial layer; 20. Gate retention area; 21. First sub-electrode; 22. Second sub-electrode; 23. Third groove; 24. Second via; 25. First groove; 26. Photoresist layer; 27. Support layer; 28. Second isolation structure. Detailed Implementation

[0090] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0091] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0092] It should be noted that the terms "on," "formed on," and "set on" used in this article can indicate that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers.

[0093] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0094] It should be noted that while terms such as "first," "second," etc., may be used herein to describe various components, parts, elements, regions, layers, and / or portions, these components, parts, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one component, part, element, region, layer, and / or portion from another.

[0095] This disclosure first provides a semiconductor device that, when the linewidth is small, exhibits low contact resistance, thereby meeting its normal operating requirements. For example... Figures 1-3 As shown, the semiconductor device may include at least: a support pillar 1, a semiconductor layer 4, a first electrode 2, a second electrode 3, and a gate 5.

[0096] Specifically, the support post 1 can support the first electrode 2, the second electrode 3, and the semiconductor layer 4, and also has an insulating function. The material of the support post 1 can be silicon nitride, but it is not limited to this. The support post 1 can also be made of other insulating materials, such as silicon oxide, which are all within the protection scope of this disclosure.

[0097] Furthermore, the cross-sectional shape of the support column 1 can be circular, but is not limited to this; the cross-sectional shape of the support column 1 can also be elliptical, etc. At the same time, this disclosure does not limit the diameter and length of the support column 1, and can be set according to specific actual conditions.

[0098] In one embodiment of this disclosure, the support column 1 can be formed by chemical vapor deposition or atomic deposition, but it is not limited to these methods. Other methods can also be used to form the support column 1. The specific method can be determined according to the actual situation.

[0099] The semiconductor layer 4 may be disposed around at least a portion of the outer surface of the support pillar 1. That is, it can be understood that the length of the semiconductor layer 4 in the first direction Z may be the same as the length of the support pillar 1 in the first direction Z, or the length of the semiconductor layer 4 in the first direction Z may be less than the length of the support pillar 1 in the first direction Z. Here, the first direction Z mentioned above may be the axial direction of the support pillar 1.

[0100] The semiconductor layer 4 may have a first end and a second end disposed opposite to each other along the first direction Z. The first electrode 2 may be connected to the first end of the semiconductor layer 4 and may extend in a direction away from the semiconductor layer 4. In one embodiment of this disclosure, the projection of the first electrode 2 in the first direction Z may coincide with the projection of the semiconductor layer 4 in the first direction Z. It is understood that the thickness of the first electrode 2 may be the same as the thickness of the semiconductor layer 4, and the extension direction of the first electrode 2 is the same as the extension direction of the semiconductor layer 4. By making the projection of the first electrode 2 in the first direction Z the same as the projection of the semiconductor layer 4 in the first direction Z, it is possible to ensure that the first electrode 2 and the semiconductor layer 4 are perfectly aligned during the connection process, thereby ensuring good working performance of the first electrode 2.

[0101] The second electrode 3 can be connected to the second end of the semiconductor layer 4 and can extend away from the semiconductor layer 4. It is understood that the semiconductor layer 4 can be located between the first electrode 2 and the second electrode 3. In one embodiment of this disclosure, the projection of the second electrode 3 in the first direction Z can coincide with the projection of the semiconductor layer 4 in the first direction Z. It is understood that the thickness of the second electrode 3 can be the same as the thickness of the semiconductor layer 4, and the extension direction of the second electrode 3 is the same as the extension direction of the semiconductor layer 4. By making the projection of the second electrode 3 in the first direction Z the same as the projection of the semiconductor layer 4 in the first direction Z, it is possible to ensure that the second electrode 3 and the semiconductor layer 4 are perfectly aligned during connection, thereby ensuring good working performance of the first electrode 2.

[0102] Meanwhile, since the projection of the first electrode 2 in the first direction Z coincides with the projection of the semiconductor layer 4 in the first direction Z, and the projection of the second electrode 3 in the first direction Z coincides with the projection of the semiconductor layer 4 in the first direction Z, it can be concluded that the projections of the first electrode 2, the semiconductor layer 4, and the second electrode 3 in the first direction Z of this disclosure are all coincident.

[0103] In one embodiment of this disclosure, the semiconductor layer 4, the first electrode 2, and the second electrode 3 may all be made of two-dimensional materials. By using two-dimensional materials, the contact resistance generated when the first electrode 2 and the second electrode 3 contact the metal electrode traces can be reduced, thereby ensuring that there can be a large current in the semiconductor device and thus ensuring the normal operation of the semiconductor device.

[0104] Furthermore, since the semiconductor layer 4, the first electrode 2, and the second electrode 3 are made of the same material, and their projections in the first direction Z coincide, the semiconductor layer 4, the first electrode 2, and the second electrode 3 of this disclosure can be formed simultaneously in one step. It is understood that the semiconductor layer 4, the first electrode 2, and the second electrode 3 of this disclosure can use the same process and be formed simultaneously in the same step. However, this is not a limitation; the semiconductor layer 4, the first electrode 2, and the second electrode 3 can also be formed separately, and the choice can be made according to actual needs, all of which are within the scope of protection of this disclosure.

[0105] In one embodiment of this disclosure, such as Figure 2 and 3As shown, the support pillar 1 may have a first pillar portion, a second pillar portion, and a third pillar portion connected to each other. The first pillar portion may be located between the second and third pillar portions. A semiconductor layer 4 may be disposed around the outer surface of the first pillar portion, a first electrode 2 may be disposed around the outer surface of the second pillar portion, and a second electrode 3 may be disposed around the outer surface of the third pillar portion. Furthermore, the length of the semiconductor layer 4 in the first direction Z may be the same as the length of the first pillar portion in the first direction Z, the length of the first electrode 2 in the first direction Z may be the same as the length of the second pillar portion in the first direction Z, and the length of the second electrode 3 in the first direction Z may be the same as the length of the third pillar portion in the first direction Z. That is, the length of the support pillar 1 in the first direction Z may be the same as the sum of the lengths of the first electrode 2, the second electrode 3, and the semiconductor layer 4 in the first direction Z.

[0106] In one embodiment of this disclosure, the first electrode 2 may include a first sub-electrode 21 and a second sub-electrode 22. The first sub-electrode 21 may be connected to a first end of the semiconductor layer 4 and extends in a direction away from the semiconductor layer 4. The second sub-electrode 22 may be connected to the end of the first sub-electrode 21 away from the semiconductor layer 4, and may be attached to the end of the second post portion away from the first post portion.

[0107] In one embodiment of this disclosure, the first electrode 2 can be the source and the second electrode 3 can be the drain, but it is not limited thereto. The first electrode 2 can also be the drain and the second electrode 3 can also be the source, as long as the first electrode 2 and the second electrode 3 are the source and the drain, respectively.

[0108] In another embodiment of this disclosure, such as Figure 1 As shown, the length of the support pillar 1 in the first direction Z can be the same as the length of the semiconductor layer 4 in the first direction Z. That is to say, only the semiconductor layer 4 is arranged around the outer surface of the support pillar 1, while the first electrode 2 and the second electrode 3 are not arranged around the outer surface of the support pillar 1.

[0109] The gate 5 may surround at least a portion of the semiconductor layer 4 and be insulated from the semiconductor layer 4. The material of the gate 5 may be tungsten, but is not limited to this; the material of the gate 5 may also be other conductive materials, depending on the actual situation.

[0110] Meanwhile, to ensure the semiconductor device exhibits excellent performance, the length of the gate 5 in the first direction Z can be equal to or less than the length of the semiconductor layer 4 in the first direction Z. However, this is not a limitation; the length of the gate 5 in the first direction Z can also be greater than the length of the semiconductor layer 4 in the first direction Z. It should be noted that when the length of the gate 5 in the first direction Z is greater than the length of the semiconductor layer 4 in the first direction Z, the gate 5 can also surround a portion of the first electrode 2 and the second electrode 3. In this case, to prevent mutual interference between the first electrode 2, the second electrode 3, and the gate 5, the first electrode 2 and the second electrode 3 also need to be insulated from the gate 5.

[0111] In one embodiment of this disclosure, the semiconductor device may further include a gate dielectric layer 6. The gate dielectric layer 6 may be disposed between the gate 5 and the semiconductor layer 4, and the material of the gate dielectric layer 6 may be an insulating layer. Thus, the gate 5 and the semiconductor layer 4 can be mutually insulated through the gate dielectric layer 6.

[0112] Meanwhile, to prevent mutual interference between the gate 5 and the semiconductor layer 4, the length of the gate dielectric layer 6 in the first direction Z can be greater than the length of the gate 5 in the first direction Z, and the projection of the gate 5 onto the semiconductor layer 4 can be within the projection of the gate dielectric layer 6 onto the semiconductor layer 4. However, this is not a limitation; the length of the gate dielectric layer 6 in the first direction Z can also be the same as the length of the gate 5 in the first direction Z, which is also within the protection scope of this disclosure.

[0113] A second aspect of this disclosure provides a semiconductor structure that can have a low contact resistance when the linewidth is small, thereby meeting its normal operating requirements. For example... Figures 1-3 and Figures 6-17 As shown, the semiconductor structure may include at least: a substrate 7, a bit line 8, a semiconductor device, a first electrode trace 9, and a second electrode trace 10.

[0114] Specifically, the substrate 7 can be selected from silicon substrate 7 or other suitable semiconductor substrate materials such as silicon, germanium, or silicon-germanium compounds. In some embodiments of this disclosure, the substrate 7 is selected as a silicon substrate. Bit line trenches are provided on the substrate 7, and when multiple bit line trenches are provided on the substrate 7, the bit line trenches on the substrate 7 can be spaced apart.

[0115] In some embodiments of this disclosure, the bit line 8 may be located within a bit line trench to form an embedded bit line 8. The bit line 8 may include an outer titanium nitride layer and an inner tungsten structure. The bit line 8 may also be a conventional solution in related technologies, and this disclosure does not limit its specific implementation.

[0116] For details regarding the arrangement of bit line 8 within substrate 7, please refer to [link / reference]. Figure 6As shown in the attached diagram in the upper right corner. Bit line 8 extends along the X direction and is arranged along the Y direction, with the Y direction being approximately perpendicular to the X direction.

[0117] It should be noted that all the figures in this disclosure relating to the semiconductor structure are shown in the following figures: the figure on the left is a cross-sectional view perpendicular to the extension direction of the bit line 8, that is, a cross-sectional view in the Y direction; the figure on the right is a cross-sectional view parallel to the extension direction of the bit line 8, that is, a cross-sectional view in the X direction.

[0118] The aforementioned semiconductor device can be located on the side of bit line 8 away from the substrate 7, and the semiconductor device can be the semiconductor device described above. Specifically, when the first electrode 2 is the source electrode, the first electrode 2 can be closer to the bit line 8 relative to the second electrode 3.

[0119] The first electrode trace 9 can be located on the surface of the substrate 7 and attached to the bit line 8, and the first electrode trace 9 can be connected to the first electrode 2. The material of the first electrode trace 9 can include bismuth, tungsten, tellurium, selenium, antimony, etc. When the material of the first electrode trace 9 is bismuth and the material of the first electrode 2 is a two-dimensional material, the contact resistance between the first electrode trace 9 and the first electrode 2 can be further reduced, thereby further improving the working performance of the semiconductor structure.

[0120] In one embodiment of this disclosure, such as Figure 1 As shown, the first electrode trace 9 can be located inside the first electrode 2, that is, the first electrode 2 can be arranged around the first electrode trace 9. One end of the first electrode trace 9 in the first direction Z can contact the support post 1, and the other end of the first electrode trace 9 in the first direction Z can be attached to the bit line 8. Furthermore, the length of the first electrode trace 9 in the first direction Z can be the same as the length of the first electrode 2 in the first direction Z.

[0121] The second electrode trace 10 can be connected to the second electrode 3. The material of the second electrode trace 10 may include bismuth, tungsten, tellurium, selenium, antimony, etc. When the material of the second electrode trace 10 is bismuth and the material of the second electrode 3 is a two-dimensional material, the contact resistance between the second electrode trace 10 and the second electrode 3 can be further reduced, thereby further improving the working performance of the semiconductor structure.

[0122] Therefore, by using two-dimensional materials to fabricate the first electrode 2 and the second electrode 3, and using bismuth to fabricate the first electrode trace 9 and the second electrode trace 10, this disclosure can ensure that the first electrode 2 and the first electrode trace 9, the second electrode 3 and the second electrode trace 10 have a small contact resistance as the linewidth of the semiconductor structure continues to shrink, so that the current in the semiconductor structure can meet its normal operating requirements.

[0123] In one embodiment of this disclosure, the second electrode trace 10 may be located within the second electrode 3, that is, the second electrode 3 may be arranged around the second electrode trace 10. One end of the second electrode trace 10 in the first direction Z may contact the support post 1, and the other end of the first electrode trace 9 in the first direction Z may extend away from the support post 1. Furthermore, the length of the second electrode trace 10 in the first direction Z may be the same as the length of the second electrode 3 in the first direction Z.

[0124] In another embodiment of this disclosure, such as Figure 2 As shown, the support pillar 1 may have a first pillar portion, a second pillar portion, and a third pillar portion that are interconnected. The first pillar portion may be located between the second and third pillar portions. A semiconductor layer 4 may surround the outer surface of the first pillar portion, a first electrode 2 may surround the outer surface of the second pillar portion, and a second electrode 3 may surround the outer surface of the third pillar portion. A first electrode trace 9 may be located between the semiconductor device and the bit line 8, and connected to the end of the first electrode 2 away from the semiconductor layer 4. It is understood that the first electrode trace 9 may be attached to the bit line 8, and the first electrode 2 and the support pillar 1 in the semiconductor device may be located on the surface of the first electrode trace 9 away from the bit line 8. In this embodiment, the second electrode trace 10 may surround the surface of the second electrode 3 away from the third pillar portion.

[0125] In this embodiment, the semiconductor structure may further include a first insulating layer 11 and a second insulating layer 12. The first insulating layer 11 may be located between the first electrode trace 9 and the gate 5 to prevent mutual interference between the first electrode trace 9 and the gate 5 during operation. The material of the first insulating layer 11 may be silicon oxide, but it is not limited to this. The material of the first insulating layer 11 may also be other insulating materials, such as silicon nitride, silicon boron nitride, etc., all of which are within the scope of this disclosure.

[0126] The second insulating layer 12 can be located between the second electrode trace 10 and the gate 5 to prevent mutual interference between the second electrode trace 10 and the gate 5 during operation. The material of the second insulating layer 12 can also be silicon oxide, but is not limited thereto. The material of the first insulating layer 11 can also be other insulating materials, such as silicon nitride, silicon boron nitride, etc., all of which are within the protection scope of this disclosure.

[0127] In one embodiment of this disclosure, the support column 1, the first insulating layer 11, and the second insulating layer 12 may be made of the same material, namely silicon oxide or silicon nitride.

[0128] In this embodiment, the first electrode 2 may further include a first sub-electrode 21 and a second sub-electrode 22. The first sub-electrode 21 may be connected to a first end of the semiconductor layer 4 and extend away from the semiconductor layer 4, and the first sub-electrode 21 may be connected to the first electrode trace 9. The second sub-electrode 22 may be connected to the end of the first sub-electrode 21 away from the semiconductor layer 4, and the second sub-electrode 22 may be located between the first electrode trace 9 and the second pillar, and the second sub-electrode 22 may be connected to the first electrode trace 9. By providing the second sub-electrode 22, the contact area between the first electrode 2 and the first electrode trace 9 can be increased, thereby improving the signal transmission efficiency and stability between the first electrode 2 and the first electrode trace 9.

[0129] In one embodiment of this disclosure, the semiconductor structure may further include a capacitor contact structure 13, which may be located on the surface of the second electrode 3 away from the substrate 7 and the surface of the second electrode trace 10 away from the substrate 7, for connecting the semiconductor structure to a capacitor. The material of the capacitor contact structure 13 may be tungsten, but is not limited thereto; other conductive materials may also be used, all of which are within the scope of this disclosure.

[0130] In one embodiment of this disclosure, the substrate 7 may have spaced bit line trenches, and the semiconductor structure may have bit lines 8, semiconductor devices, first electrode traces 9, second electrode traces 10, and capacitive contact structures 13. Each bit line 8 may be located within a bit line trench, and at least one semiconductor device may be disposed on the side of each bit line 8 away from the substrate 7. It is understood that the semiconductor structure provided in this disclosure may have multiple bit lines 8 and multiple semiconductor devices, with each bit line 8 located within a bit line trench, and one or more semiconductor devices disposed on the side of each bit line 8 away from the substrate 7. Furthermore, to prevent mutual interference between adjacent semiconductor devices, adjacent semiconductor devices are insulated from each other.

[0131] Furthermore, the first electrode traces 9 can all be attached to the bit lines 8, and the first electrode traces 9 can all be connected to the first electrode 2. It is understood that the semiconductor structure provided in this disclosure can have multiple first electrode traces 9, which can extend along the X direction and be arranged along the Y direction. Each first electrode trace 9 can be attached to a bit line 8 and connected to at least one first electrode 2 in a semiconductor device.

[0132] In one embodiment of this disclosure, to prevent interference between multiple first electrode traces 9 arranged along the Y direction, the semiconductor structure provided in this disclosure may further include a first isolation structure 16. The first isolation structure 16 may be located between two adjacent first electrode traces 9 to isolate them. The material of the first isolation structure 16 may be silicon oxide, but is not limited thereto. The material of the first isolation structure 16 may also be silicon nitride, silicon boron nitride, etc., and can be selected according to actual needs, all of which are within the protection scope of this disclosure.

[0133] In addition, the capacitive contact structures 13 can all be located on the surfaces of the second electrode 3 and the second electrode trace 10 away from the substrate 7. It is understood that the semiconductor structure provided in this disclosure can have multiple capacitive contact structures 13, and one capacitive contact structure 13 can be provided on the surfaces of the second electrode 3 and the second electrode trace 10 away from the substrate 7 for each semiconductor device.

[0134] In one embodiment of this disclosure, to prevent interference between adjacent second electrode traces 10 and between adjacent capacitor contact structures 13, the semiconductor structure provided in this disclosure may further include a third insulating layer 14, which may be located between two adjacent second electrode traces 10 to isolate the two adjacent second electrode traces 10. Simultaneously, the second electrode traces 10 may also be located between two adjacent capacitor contact structures 13 to isolate the two adjacent capacitor contact structures 13.

[0135] The material of the aforementioned third isolation layer can be silicon oxide, but is not limited to it. The material of the third isolation layer can also be silicon nitride, silicon boron nitride, etc., which can be selected according to actual needs, and all of these are within the protection scope of this disclosure.

[0136] The third aspect of this disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure manufactured by this method can have a small contact resistance when the line width is small, thereby meeting the normal operating requirements of the semiconductor structure.

[0137] like Figure 4 and Figures 6-17 As shown, the method for manufacturing a semiconductor structure provided in this disclosure may include:

[0138] Step S10: Provide substrate 7 and create bit line trenches on substrate 7;

[0139] Step S20: Embed the bit line 8 in the bit line trench;

[0140] Step S30: Form a first electrode trace 9 on the surface of the substrate 7 and make the first electrode trace 9 fit with the bit line 8;

[0141] Step S40: Form a semiconductor device on the side of bit line 8 away from substrate 7. The semiconductor device is the semiconductor device described above. Connect the first electrode 2 to the first electrode trace 9 and form a second electrode trace 10. Connect the second electrode 3 to the second electrode trace 10.

[0142] The above steps are explained in detail below:

[0143] In step S10, the substrate 7 can be selected from silicon substrate 7 or other suitable semiconductor substrate materials such as silicon, germanium, or silicon-germanium compounds. In one embodiment of this disclosure, the substrate 7 is selected as a silicon substrate.

[0144] The substrate 7 can be etched to create spaced bit line trenches on the substrate 7. In one embodiment of this disclosure, the substrate 7 can be etched by photolithography, but it is not limited to this. The substrate 7 can also be etched by wet etching or other methods, all of which are within the protection scope of this disclosure.

[0145] In step S20, the bit line 8 can be located within a bit line trench, and the bit line 8 can include an outer titanium nitride layer and an inner tungsten structure. Therefore, titanium nitride material can be deposited first within the bit line trench to form the outer titanium nitride layer of the bit line 8, and then tungsten material can be deposited to form the inner tungsten structure. However, this is not a limitation; the bit line 8 can also be prefabricated, and the prefabricated bit line 8 can be directly placed into the bit line trench.

[0146] In step S30, a first electrode trace 9 layer can be formed on the surfaces of the substrate 7 and the bit line 8, and the substrate 7 and the first electrode trace 9 layer can be etched to form a first groove 25 and the first electrode trace 9. The orthogonal projection of the first groove 25 on the substrate 7 can extend along a second direction.

[0147] Specifically, the material of the first electrode trace layer 9 can be a conductive material. In some embodiments, the material of the first electrode trace layer 9 includes materials such as bismuth, tungsten, tellurium, selenium, and antimony. The first electrode trace layer 9 can be formed using sputtering or deposition processes, such as physical vapor deposition (PVD) to form a first electrode trace layer 9 of a certain thickness on the surfaces of the substrate 7 and the bit line 8. The first electrode trace layer 9 can be connected to the bit line 8.

[0148] After forming the first electrode trace layer 9, a patterned photoresist layer 26 can be formed on the surface of the first electrode trace layer 9 away from the substrate 7. Using the photoresist layer 26 as a mask, the first electrode trace layer 9 and the substrate 7 are etched to form a first groove 25. The first groove 25 can extend along a second direction, which can be parallel to the extension direction X of the bit line 8, or at a certain angle, which is less than 90°. The first groove 25 can divide the first electrode trace layer 9 into multiple spaced first electrode traces 9.

[0149] In step S40, a first insulating material layer can be formed on the surface of the first electrode trace 9 and in the first groove 25. The first insulating material layer located in the first groove 25 forms a first isolation structure 16, and the remaining first insulating material layer forms a first insulating layer 11.

[0150] Specifically, in this step, the material of the first insulating material layer may include silicon oxide, silicon boron nitride, or silicon nitride. In one embodiment of this disclosure, the material of the first insulating material layer may be silicon oxide. The first insulating material layer may be formed by a deposition process, such as chemical vapor deposition (CVP) or atomic layer deposition (ALD). This disclosure does not limit the specific method of forming the first insulating material layer, and it can be set according to actual needs, all of which are within the protection scope of this disclosure.

[0151] The first insulating material layer can fill the first groove 25 and cover the surface of the first electrode trace 9. The first insulating material layer located within the first groove 25 forms a first isolation structure 16, which can isolate adjacent first electrode traces 9 and also separate multiple active regions of the substrate 7. The remaining first insulating material layer can form a first insulating layer 11.

[0152] In this step, a gate sacrificial layer 19, a second insulating layer 12, and a second electrode wiring layer 15 may also be formed sequentially on the first insulating layer 11.

[0153] Specifically, a gate sacrificial layer 19 can be formed on the surface of the first insulating layer 11. The material of the gate sacrificial layer 19 can include silicon oxide, silicon boron nitride, or silicon nitride. In one embodiment of this disclosure, the material of the gate sacrificial layer 19 is silicon nitride.

[0154] A second insulating layer 12 may be formed on the surface of the gate sacrificial layer 19 away from the substrate 7, and the second insulating layer 12 may cover the surface of the gate sacrificial layer 19. The material of the second insulating layer 12 may include silicon oxide, silicon boron nitride, or silicon nitride. In one embodiment of this disclosure, the material of the second insulating layer is silicon oxide.

[0155] A second electrode wiring layer 15 can be formed on the surface of the second insulating layer 12 away from the substrate 7. Specifically, the material of the second electrode wiring layer 15 can be a conductive material. In some embodiments, the material of the second electrode wiring layer 15 may include materials such as bismuth, tungsten, tellurium, selenium, and antimony. The second electrode wiring layer 15 can be formed by sputtering or deposition processes, such as physical vapor deposition (PVD) to form a second electrode wiring layer 15 of a certain thickness on the surface of the second insulating layer 12.

[0156] In this step, the second electrode trace layer 15 can be etched using the first electrode trace 9 as a stop layer to form a plurality of first vias 18. The first vias 18 can extend to the surface of the first electrode trace 9 away from the substrate 7.

[0157] Specifically, a patterned photoresist layer 26 can be formed on the surface of the second electrode wiring layer 15 away from the substrate 7. Then, the second electrode wiring layer 15, the second insulating layer 12, the gate sacrificial layer 19, and the first insulating layer 11 are etched to form a first via 18 within these layer structures. The first via 18 has a columnar structure, and multiple first vias 18 can be arranged in an array. Furthermore, the projection of the first via 18 onto the substrate 7 can lie within the projection of the first electrode wiring 9 onto the substrate 7.

[0158] In this step, a support pillar 1, a first electrode 2, a second electrode 3, and a semiconductor layer 4 can also be formed within the first through-hole 18. Specifically,

[0159] Semiconductor material can be deposited at least on the sidewalls of the first via 18 to form a first electrode 2, a second electrode 3, and a semiconductor layer 4. The semiconductor material may include a two-dimensional material. Support material can be filled into the inner surfaces of the first electrode 2, the second electrode 3, and the semiconductor layer 4 to form a support pillar 1 and a support layer 27 located at least on the surfaces of the support pillar 1 and the second electrode 3 on the side away from the substrate 7.

[0160] The aforementioned support material may include silicon oxide. The support pillar 1 and support layer 27 may be deposited with silicon oxide on the surface of the second electrode 3 away from the substrate 7 using chemical vapor deposition or atomic deposition, and then smoothed using a chemical mechanical polishing (CMP) process.

[0161] Additionally, in this step, the gate sacrificial layer 19 can be removed to form the gate retention region 20. Specifically, using the first insulating layer 11 as a stop layer, the support layer 27 can be etched to form a plurality of spaced second grooves 17, extending the second grooves 17 to the surface of the first insulating layer 11 away from the substrate 7. The orthographic projection of the second grooves 17 on the substrate 7 does not overlap with the orthographic projection of the first via 18 on the substrate 7. Furthermore, the gate sacrificial layer 19 can be removed through these second grooves 17 to form the gate retention region 20.

[0162] Specifically, a patterned photoresist layer 26 is formed on the surface of the support layer 27 away from the substrate 7. Then, the support layer 27, the second electrode wiring layer 15, the second insulating layer 12, and the gate sacrificial layer 19 are etched to form second grooves 17 within these layer structures. There are multiple second grooves 17, which extend along a second direction perpendicular to the first direction Z. The multiple second grooves 17 are arranged along the first direction Z.

[0163] In some embodiments of this disclosure, a plurality of first through holes 18 are arranged in an array along a first direction Z and a second direction. Specifically, the plurality of first through holes 18 may be arranged in rows along the first direction Z and in columns along the second direction. In some embodiments, a second groove 17 may be formed between two adjacent rows of first through holes 18.

[0164] After forming the gate retention region 20, a gate 5 and a gate dielectric layer 6 can be formed in the gate retention region 20. The gate 5 can surround the semiconductor layer 4, and the gate dielectric layer 6 can be located between the gate 5 and the semiconductor layer 4.

[0165] Specifically, a gate dielectric layer 6 can be formed around the side of the semiconductor layer 4 away from the support pillar 1. The material of the gate dielectric layer 6 may include silicon oxide. In one embodiment, a gate dielectric layer 618 of a certain thickness can be grown around the surface of the semiconductor layer 4 away from the support pillar 1. The material of the gate dielectric layer 6 may be the same as that of the first insulating layer 11 and the second insulating layer 12, which is silicon oxide.

[0166] Furthermore, the gate 5 can be formed around the side of the gate dielectric layer 6 away from the semiconductor layer 4. The orthogonal projection of this gate 5 onto the substrate 7 can be non-overlapping with the projection of the second recess 17 onto the substrate 7. Specifically:

[0167] The gate 5 material can be filled into the gate retention region 20 and the second groove 17 via the second groove 17. In this step, the material of the gate 5 can contain various conductive materials, such as tungsten. The gate retention region 20 is filled with the second groove 17, and the gate 5 is formed within the gate retention region 20. The formed gate 5 can surround the periphery of the gate dielectric layer 6, thereby forming a GAA transistor.

[0168] The gate 5 material layer located within the second recess 17 can be removed to form the gate 5. Through an etching process, the gate 5 material layer located within the second recess 17 can be removed to form a spacer region, thereby forming a plurality of spaced gates 5. In some embodiments, the gates 5 can extend along a second direction and be arranged along a first direction Z.

[0169] A second isolation structure 28 can be formed within the second groove 17 where the gate 5 material layer has been removed. That is, an isolation material, such as silicon oxide, can be filled into the spacer region to form the second isolation structure 28. However, this disclosure does not limit the isolation material; for example, the isolation material can also be silicon nitride, etc., all of which are within the protection scope of this disclosure.

[0170] In this step, the second electrode wiring layer 15 can also be etched to form the second electrode wiring 10. Specifically, the second electrode wiring layer 15 can be etched with the second insulating layer 12 as a stop layer to form a third groove 23. The third groove 23 and the second groove 17 can intersect each other to divide the second electrode wiring layer 15 into a plurality of spaced second electrode wirings 10.

[0171] In one embodiment of this disclosure, such as Figure 5 As shown, the method for manufacturing the semiconductor structure provided in this disclosure may further include:

[0172] In step S50, an insulating material is deposited on the side of the second electrode trace 10 away from the substrate 7 and in the third groove 23 to form a third insulating layer 14. The third insulating material can be silicon nitride, but is not limited thereto; it can also be silicon oxide, all of which are within the scope of this disclosure.

[0173] Step S60: The third insulating layer 14 can be etched to form a second via 24 within the third insulating layer 14. The second via 24 can expose the second electrode 3 and the second electrode trace 10. Specifically, a patterned photoresist layer 26 can be formed on the side of the third insulating layer away from the substrate 7. The third insulating layer can be etched using photolithography to form the second via 24.

[0174] In step S70, conductive material may be deposited within the second through-hole 24 to form a capacitive contact structure 13. The conductive material may be tungsten, but is not limited to it; other conductive materials may also be used, all of which are within the scope of this disclosure.

[0175] As can be seen from the above, the semiconductor structure fabricated by this semiconductor structure fabrication method, by using two-dimensional materials to fabricate the first electrode 2 and the second electrode 3, and using bismuth to fabricate the first electrode trace 9 and the second electrode trace 10, can ensure that the contact resistance between the first electrode 2 and the first electrode trace 9, the second electrode 3 and the second electrode trace 10 is small as the linewidth of the semiconductor structure continues to shrink, so that the current in the semiconductor structure can meet its normal working requirements.

[0176] In some embodiments, the two-dimensional material may be molybdenum disulfide, tungsten disulfide, or other materials.

[0177] Furthermore, it should be noted that the method for fabricating the semiconductor structure can fabricate the semiconductor structure provided in the second aspect of this disclosure, and the specific structure of the semiconductor structure involved in the method for fabricating the semiconductor structure can be referred to the specific description of the semiconductor structure provided in the second aspect of this disclosure, all of which are within the protection scope of this disclosure.

[0178] It should be noted that although the steps of the method for fabricating thin-film transistors in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0179] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate has bit line grooves; Bit lines are located within the bit line grooves; A semiconductor device located on the side of the bit line away from the substrate, and the semiconductor device comprising: Support column; A semiconductor layer surrounds at least a portion of the outer surface of the support pillar, and the semiconductor layer has a first end and a second end disposed opposite to each other along a first direction; The first electrode is connected to a first end of the semiconductor layer and extends away from the semiconductor layer. The second electrode is connected to the second end of the semiconductor layer and extends away from the semiconductor layer. A gate, which surrounds at least a portion of the semiconductor layer and is insulated from the semiconductor layer; Wherein, the first direction is the axial direction of the support column, and the materials of the semiconductor layer, the first electrode, and the second electrode include two-dimensional materials; The first electrode trace is located on the surface of the substrate and is attached to the bit line, and the first electrode trace is connected to the first electrode. The second electrode trace is connected to the second electrode; The semiconductor structure also includes: A capacitive contact structure is located on the surface of the second electrode and the second electrode trace away from the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The projection of the first electrode in the first direction coincides with the projection of the semiconductor layer in the first direction; The projection of the second electrode in the first direction coincides with the projection of the semiconductor layer in the first direction.

3. The semiconductor structure according to claim 1, characterized in that, The support column has a first column portion, a second column portion, and a third column portion connected to each other. The first column portion is located between the second column portion and the third column portion. The semiconductor layer surrounds the outer surface of the first column portion. The first electrode surrounds the outer surface of the second column portion, and the second electrode surrounds the outer surface of the third column portion.

4. The semiconductor structure according to claim 3, characterized in that, The first electrode includes: A first sub-electrode is connected to a first end of the semiconductor layer and extends away from the semiconductor layer. The second sub-electrode is connected to the end of the first sub-electrode away from the semiconductor layer, and is attached to the end of the second pillar away from the first pillar.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor device further includes: A gate dielectric layer is disposed between the gate and the semiconductor layer, and the material of the gate dielectric layer is an insulating material.

6. The semiconductor structure according to claim 1, characterized in that, The support column has a first column portion, a second column portion, and a third column portion that are connected to each other. The first column portion is located between the second column portion and the third column portion. The semiconductor layer surrounds the outer surface of the first column portion. The first electrode surrounds the outer surface of the second column portion, and the second electrode surrounds the outer surface of the third column portion. The first electrode trace is located between the semiconductor device and the bit line, and is connected to the end of the first electrode away from the semiconductor layer; The second electrode trace wraps around the surface of the second electrode away from the third post.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: A first insulating layer and a second insulating layer; wherein the first insulating layer is located between the first electrode trace and the gate; and the second insulating layer is located between the second electrode trace and the gate.

8. The semiconductor structure according to claim 7, characterized in that, The first electrode further includes: The first sub-electrode is connected to the first end of the semiconductor layer and extends away from the semiconductor layer, and the first sub-electrode is connected to the first electrode trace; The second sub-electrode is connected to the end of the first sub-electrode away from the semiconductor layer and is located between the first electrode trace and the second pillar, and the second sub-electrode is connected to the first electrode trace.

9. The semiconductor structure according to claim 1, characterized in that, The first electrode trace is located at the end of the support post away from the second electrode, and the first electrode is arranged around the first electrode trace; The second electrode trace is located at the end of the support post away from the first electrode, and the second electrode is arranged around the second electrode trace.

10. The semiconductor structure according to claim 1, characterized in that, The substrate has spaced bit line trenches, and the semiconductor structure has the bit lines, the semiconductor device, the first electrode trace, the second electrode trace, and the capacitor contact structure. In this configuration, all bit lines are located within the bit line trenches, and at least one semiconductor device may be disposed on the side of the bit line away from the substrate; all first electrode traces are attached to the bit lines and are connected to the first electrode; and all capacitive contact structures are located on the surface of the second electrode and the second electrode trace away from the substrate.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: A third insulating layer is located between two adjacent second electrode traces and also between two adjacent capacitor contact structures.

12. A method for manufacturing a semiconductor structure, said method for manufacturing a semiconductor structure as claimed in any one of claims 1-11, characterized in that, include: A substrate is provided, and bit line trenches are formed on the substrate; A bit line is embedded in the bit line trench; A first electrode trace is formed on the surface of the substrate, and the first electrode trace is made to be attached to the bit line; A semiconductor device is formed on the side of the bit line away from the substrate, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 5, the first electrode is connected to the first electrode trace, and a second electrode trace is formed, wherein the second electrode trace is connected to the second electrode.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, Forming a first electrode trace on the surface of the substrate and aligning the first electrode trace with the bit line includes: A first electrode wiring layer is formed on the surface of the substrate and the bit line; The substrate and the first electrode trace layer are etched to form a first groove and a first electrode trace, wherein the orthographic projection of the first groove on the substrate extends along a second direction.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, The process of forming a semiconductor device on the side of the bit line away from the substrate, connecting the first electrode to the first electrode trace, and forming a second electrode trace connecting the second electrode trace to the second electrode includes: A first insulating material layer is formed on the surface of the first electrode trace and in the first groove. The first insulating material layer located in the first groove forms a first isolation structure, and the remaining first insulating material layer forms a first insulating layer. A gate sacrificial layer, a second insulating layer, and a second electrode wiring layer are sequentially formed on the first insulating layer; Using the first electrode trace as a stop layer, the second electrode trace layer is etched to form a plurality of first vias, the first vias extending to the surface of the first electrode trace away from the substrate; The support post, the first electrode, the second electrode, and the semiconductor layer are formed within the first through hole; Remove the gate sacrificial layer to form a gate retention region; In the gate retention region, a gate and a gate dielectric layer are formed; The second electrode trace layer is etched to form the second electrode trace; The gate surrounds the semiconductor layer, and the gate dielectric layer is located between the gate and the semiconductor layer.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that, The formation of the support post, the first electrode, the second electrode, and the semiconductor layer within the first through-hole includes: Semiconductor material is deposited at least on the sidewalls of the first via to form the first electrode, the second electrode, and the semiconductor layer, wherein the semiconductor material includes a two-dimensional material; A support material is filled into the inner surfaces of the first electrode, the second electrode, and the semiconductor layer to form the support pillar and a support layer at least on the surface of the support pillar and the second electrode away from the substrate.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, Removing the gate sacrificial layer to form a gate retention region includes: Using the first insulating layer as a stop layer, the support layer is etched to form a plurality of spaced second grooves, and the second grooves extend to the surface of the first insulating layer away from the substrate. The orthographic projection of the second groove on the substrate does not overlap with the orthographic projection of the first through hole on the substrate. The gate sacrificial layer is removed through the second groove to form the gate retention area.

17. The method for manufacturing a semiconductor structure according to claim 16, characterized in that, The formation of the gate and gate dielectric layer in the gate retention region includes: A gate dielectric layer is formed around the side of the semiconductor layer away from the support pillar; The gate is formed around the side of the gate dielectric layer away from the semiconductor layer, and the orthogonal projection of the gate on the substrate does not overlap with the orthogonal projection of the second groove on the substrate.

18. The method for manufacturing a semiconductor structure according to claim 17, characterized in that, The gate is formed around the side of the gate dielectric layer away from the semiconductor layer, including: The gate material is filled in the gate retention area and the second groove through the second groove to form a gate material layer; Remove the gate material layer located within the second recess to form the gate; A second isolation structure is formed within the second groove where the gate material layer has been removed.

19. The method for manufacturing a semiconductor structure according to claim 18, characterized in that, The etching of the second electrode wiring layer to form the second electrode wiring includes: Using the second insulating layer as a stop layer, the second electrode trace layer is etched to form a third groove. The third groove and the second groove intersect each other, dividing the second electrode trace layer into multiple spaced second electrode traces.

20. The method for manufacturing a semiconductor structure according to claim 19, characterized in that, The manufacturing method further includes: An insulating material is deposited on the side of the second electrode trace away from the substrate and within the third groove to form a third insulating layer; The third insulating layer is etched, and a second via is formed within the third insulating layer, the second via exposing the second electrode and the second electrode trace; Conductive material is deposited within the second through-hole to form a capacitive contact structure.

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