Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the same are provided. The display device includes: a first conductive layer disposed on a substrate; a passivation layer disposed on the first conductive layer; a second conductive layer disposed on the passivation layer; a via layer disposed on the second conductive layer; a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, and a connecting pattern, the first electrode, the second electrode, and the connecting pattern being spaced apart from each other; and a light-emitting element, a first end and a second end of the light-emitting element being respectively disposed on the first electrode and the second electrode, wherein the connecting pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0131049, filed on October 12, 2020, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device and a method of manufacturing the display device. Background Technology

[0003] With the development of multimedia, display devices are becoming increasingly important. Therefore, various types of display devices, such as organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs), are being used.

[0004] A display device is a device for displaying images and includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. As a light-emitting display panel, the display panel may include a light-emitting element such as a light-emitting diode (LED). For example, the LED may be an organic light-emitting diode (OLED) that uses organic materials as the light-emitting material, or it may be an inorganic LED that uses inorganic materials as the light-emitting material. Summary of the Invention

[0005] The disclosed aspect provides a display device manufactured by a method for manufacturing a display device with improved process efficiency.

[0006] The disclosed aspect also provides a method for manufacturing a display device with improved process efficiency.

[0007] However, the disclosures are not limited to those described herein. The above and other aspects of the disclosures will become more apparent to a person skilled in the art by referring to the detailed description of the disclosures given below.

[0008] According to one aspect of the disclosure, a display device is provided, comprising: a first conductive layer disposed on a substrate; a passivation layer disposed on the first conductive layer; a second conductive layer disposed on the passivation layer; a via layer disposed on the second conductive layer; a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, and a connecting pattern, the first electrode, the second electrode, and the connecting pattern being spaced apart from each other; and a light-emitting element, a first end and a second end of the light-emitting element being respectively disposed on the first electrode and the second electrode, wherein the connecting pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole passing through the via layer and the passivation layer.

[0009] In an embodiment, the first contact hole may expose at least a portion of the upper surface of the second conductive layer, at least a portion of the side surface of the second conductive layer, and at least a portion of the upper surface of the first conductive layer.

[0010] In an embodiment, the connection pattern may electrically contact at least a portion of the upper surface of the first conductive layer, at least a portion of the upper surface of the second conductive layer, and at least a portion of the side surface of the second conductive layer.

[0011] In an embodiment, the first contact hole may include a first portion formed by the sidewall of the via layer, a second portion formed by the side surface of the second conductive layer and the sidewall of the via layer, and a third portion formed by the sidewall of the passivation layer, and the first portion, the second portion and the third portion of the first contact hole are stacked on top of each other in the thickness direction of the substrate.

[0012] In an embodiment, the width of the first part may be larger than the width of the second part, and the width of the first part may be larger than the width of the third part.

[0013] In an embodiment, the first part, the second part, and the third part may be integral with each other and form a hole.

[0014] In one embodiment, the third portion may be stacked with the first conductive layer in the thickness direction of the substrate, and may not be stacked with the second conductive layer in the thickness direction of the substrate.

[0015] In an embodiment, the third part may not be disposed between the first conductive layer and the second conductive layer in the thickness direction of the substrate.

[0016] In one embodiment, the display device may further include a first insulating layer disposed on the third conductive layer. The first insulating layer may be completely superimposed on the connection pattern, and the light-emitting element may be disposed on the first insulating layer.

[0017] In an embodiment, the display device may further include: a first contact electrode disposed on a first insulating layer and electrically contacting a first end of a light-emitting element and a first electrode; and a second contact electrode disposed on the first insulating layer and electrically contacting a second end of a light-emitting element and a second electrode.

[0018] In one embodiment, the display device may further include a transistor disposed between the substrate and the second conductive layer. The transistor may include an active layer, a gate electrode, a first source / drain electrode, and a second source / drain electrode. The first source / drain electrode and the second source / drain electrode may be contained within the first conductive layer.

[0019] In one embodiment, the second conductive layer may include a first power line, and the connection pattern may electrically connect the first power line to the first source / drain electrode of the transistor through a first contact hole.

[0020] In one embodiment, the first electrode can be electrically connected to the second source / drain electrode of the transistor through a second contact hole that penetrates the via layer and the passivation layer.

[0021] In an embodiment, the connection pattern may electrically contact at least a portion of the upper surface of the first source / drain electrode of the transistor, at least a portion of the upper surface of the first electric field line, and the side surface of the first electric field line.

[0022] In one embodiment, the passivation layer may be disposed between the first conductive layer and the second conductive layer in the thickness direction of the substrate.

[0023] According to another aspect of the disclosure, a method for manufacturing a display device is provided. The method may include the steps of: forming a first conductive layer on a surface of a substrate; depositing a passivation layer on the first conductive layer to overlap with the first conductive layer; forming a second conductive layer on the passivation layer to overlap with at least a portion of the first conductive layer in the thickness direction of the substrate; depositing a via layer on the second conductive layer to overlap with the second conductive layer; forming a first dam layer on the via layer to include an opening, the opening overlapping with at least a portion of the upper surface of the first conductive layer, at least a portion of the upper surface of the second conductive layer, and at least a portion of the side surface of the second conductive layer in the thickness direction of the substrate; and forming a first dam by etching the first dam layer, and etching the via layer and the passivation layer by using the first dam layer as an etching mask.

[0024] In one embodiment, the first dam can be formed by etching the entire surface of the first dam layer.

[0025] In an embodiment, the step of forming a first dam layer on the via layer may include: forming a first dam layer to include a first region having a first height and a second region having a greater height than the first region; wherein the first region is etched away by etching the entire surface of the first dam layer to form the first dam; and wherein the via layer and passivation layer superimposed with the opening are etched to form a first contact hole penetrating the first dam, the via layer and the passivation layer.

[0026] In an embodiment, the method may further include forming a third conductive layer to include a first electrode, a second electrode, and a connection pattern disposed on the first dam and spaced apart from each other.

[0027] In an embodiment, the method may further include depositing a connection pattern into a first contact hole to electrically contact at least a portion of the upper surface of the first conductive layer, at least a portion of the upper surface of the second conductive layer, and at least a portion of the side surface of the second conductive layer.

[0028] In a display device according to an embodiment, the display device includes a first conductive layer, a passivation layer disposed on the surface of the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, and a third conductive layer disposed on the via layer, wherein the third conductive layer serves as a connection electrode connecting the first conductive layer and the second conductive layer. Therefore, in the process of forming the passivation layer disposed between the first conductive layer and the second conductive layer, a separate mask process can be omitted. Thus, since an additional mask process for connecting the first conductive layer and the second conductive layer is not required, the process efficiency of the display device can be improved.

[0029] However, the effects of the disclosure are not limited to those described herein. The above and other effects of the disclosure will become more apparent to a person skilled in the art by referring to the claims. Attached Figure Description

[0030] These and / or other aspects will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0032] Figure 2 This is a schematic plan view of the pixels of a display device according to an embodiment;

[0033] Figure 3 This is a schematic cross-sectional view of a display device according to an embodiment;

[0034] Figure 4 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A;

[0035] Figure 5 This is a schematic perspective view of the light-emitting element according to an embodiment;

[0036] Figure 6 yes Figure 3 A schematic enlarged cross-sectional view of an example of region B;

[0037] Figure 7 yes Figure 3 A schematic enlarged cross-sectional view of an example of region B;

[0038] Figures 8 to 15 It shows the manufacturing basis. Figure 3 A schematic cross-sectional view of some of the operations in the method of the display device in an embodiment;

[0039] Figure 16 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A;

[0040] Figure 17 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A;

[0041] Figure 18 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A;

[0042] Figure 19 This is a schematic cross-sectional view of a display device according to an embodiment;

[0043] Figure 20 This is a schematic cross-sectional view of a display device according to an embodiment; and

[0044] Figure 21 This is a schematic cross-sectional view of a display device according to an embodiment. Detailed Implementation

[0045] The disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art.

[0046] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on said other layer or substrate, or there may be intermediate layers. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements.

[0047] Throughout the specification, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0048] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0049] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an ideal or overly formal sense unless clearly defined herein.

[0050] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0051] Figure 1 This is a schematic plan view of the display device 10 according to an embodiment.

[0052] Reference Figure 1 The display device 10 can display moving or still images. The display device 10 can refer to any electronic device that provides a display screen. Examples of the display device 10 may include televisions, personal laptops (PCs), monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet PCs, electronic watches, smartwatches, watch phones, head-mounted displays (HMDs), electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, and camcorders, all of which provide a display screen.

[0053] Display device 10 may include a display panel that provides a display screen. Examples of display panels may include inorganic light-emitting diode (LED) display panels, organic light-emitting display panels, quantum dot light-emitting display panels, plasma display panels, and field emission display panels. The following describes an example of using an inorganic LED display panel as a display panel; however, the disclosure is not limited to this, and other display panels may be used, provided the same technical spirit applies.

[0054] In the accompanying drawings illustrating an embodiment of the display device 10, a first direction DR1, a second direction DR2, and a third direction DR3 may be defined. The first direction DR1 and the second direction DR2 may be directions perpendicular to each other in a plane. The third direction DR3 may be a direction perpendicular to the plane in which the first direction DR1 and the second direction DR2 are positioned. The third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2. In an embodiment illustrating the display device 10, the third direction DR3 may indicate the thickness direction (or display direction) of the display device 10.

[0055] The display device 10 may have a rectangular shape in a plan view, including a long side and a short side, and being longer in a first direction DR1 than in a second direction DR2. In the plan view, the angle where the long side and short side of the display device 10 intersect each other may be a right angle. However, the disclosure is not limited to this; the angle may also be rounded (or chamfered). The shape of the display device 10 is not limited to the above examples and may be varied. For example, the display device 10 may also have other shapes in a plan view, such as a square, a quadrilateral with rounded corners (vertices), other polygons, and circles.

[0056] The display surface of the display device 10 may be disposed on one side of the third direction DR3, which is the thickness direction. In embodiments used to describe the display device 10, unless otherwise specified, the term "above" may refer to the upward direction or the third direction DR3, and may indicate the display direction, and "upper surface" may indicate a surface disposed on the element in the third direction DR3. The term "below" may refer to the downward direction or the direction opposite to the third direction DR3, and may indicate the direction opposite to the display direction, and "lower surface" may indicate a surface below the element in the direction opposite to the third direction DR3. The terms "left," "right," "up," and "down" may indicate the orientation of the display device 10 when viewed in a plan view. For example, "right" may indicate one side in the first direction DR1, "left" may indicate the other side in the first direction DR1, "up" may indicate one side in the second direction DR2, and "down" may indicate the other side in the second direction DR2.

[0057] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an area where an image can be displayed, and the non-display area NDA may be an area where an image is not displayed.

[0058] The shape of the display area DPA can follow the shape of the display device 10. For example, in a plan view, the display area DPA can have a rectangular shape similar to the overall shape of the display device 10. The display area DPA can typically occupy the center of the display device 10.

[0059] The display area DPA may include pixels PX. Pixels PX may be arranged in a matrix direction. Each of the pixels PX may be rectangular or square in a planar view. In an embodiment, each of the pixels PX may include a light-emitting element made of inorganic particles.

[0060] The non-display area NDA can be located around or near the display area DPA. The non-display area NDA can completely or partially surround the display area DPA. The non-display area NDA can form the bezel of the display device 10.

[0061] Figure 2 This is a schematic plan view of the pixel PX of the display device 10 according to an embodiment.

[0062] Reference Figure 2 Each pixel PX of the display device 10 may include an emitting region EMA and a non-emitting region. The emitting region EMA may be the area from which light emitted from the light-emitting element ED is emitted, and the non-emitting region may be the area from which light is not emitted because the light emitted from the light-emitting element ED does not reach that area.

[0063] The emitting region EMA may include the area in which the light-emitting element ED is disposed and the area adjacent to the above area. The emitting region EMA may also include the area from which light emitted from the light-emitting element ED is output after being reflected or refracted by other components.

[0064] Each pixel PX may also include a first region CBA disposed in a non-emitting region. The first region CBA may be disposed above the emitting region EMA in the pixel PX (or on one side in the second direction DR2). The first region CBA may be disposed between the emitting regions EMA of adjacent pixels PX in the second direction DR2.

[0065] The first region CBA can be a region in which the first electrode 210 and the second electrode 220 included in adjacent pixels PX in the second direction DR2 are separated from each other. The first electrode 210 and the second electrode 220 disposed in each pixel PX can be separated from the first electrode 210 and the second electrode 220 disposed in adjacent pixels PX in the first region CBA, and portions of the first electrode 210 and the second electrode 220 disposed in each pixel PX can be disposed in the first region CBA. The light-emitting element ED may not be disposed in the first region CBA.

[0066] Figure 3 This is a schematic cross-sectional view of the display device 10 according to an embodiment.

[0067] Reference Figure 2 and Figure 3 The display device 10 may include a substrate SUB, a circuit element layer PAL disposed on the substrate SUB, and a light-emitting element layer EML disposed on the circuit element layer PAL.

[0068] The circuit element layer (PAL) can be disposed on the surface of the substrate (SUB). Within the PAL, transistors, scan lines, data lines, power lines, scan control lines, and wiring connecting the pads and data lines for each pixel (PX) can be formed. Each transistor may include a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.

[0069] The circuit element layer PAL may include a barrier layer 121, a buffer layer 122, a semiconductor layer, a conductive layer, an insulating layer, and a via layer 127 disposed on the substrate SUB.

[0070] The light-emitting element layer (EML) can be disposed on the circuit element layer (PAL). The EML can include light-emitting elements (ED) to emit light to the outside of the display device 10 by driving the transistors of the circuit element layer (PAL).

[0071] The light-emitting element layer (EML) may include a third conductive layer 200 disposed on the via layer 127 of the circuit element layer (PAL), a light-emitting element (ED), a first contact electrode 710, a second contact electrode 720, an insulating layer, a first barrier 400, and a second barrier 600. The circuit element layer (PAL) may include at least one transistor to drive the light-emitting element layer (EML).

[0072] Now refer to Figure 3 This describes the layer PAL, which is the layer of circuit elements disposed in the pixel PX of the display device 10.

[0073] The substrate SUB can be an insulating substrate. The substrate SUB can be made of insulating materials such as glass, quartz, or polymer resin. The substrate SUB can be a rigid substrate, but it can also be a flexible substrate that can be bent, folded, rolled, etc.

[0074] The barrier layer 121 can be disposed on the substrate SUB. The barrier layer 121 can prevent oxygen and moisture from entering the transistor TR.

[0075] A bottom metal layer 110 may be disposed on the barrier layer 121. The bottom metal layer 110 may be a light-blocking layer that protects the active layer ACT of the transistor TR from external light. The bottom metal layer 110 may include a light-blocking material. For example, the bottom metal layer 110 may be made of an opaque metallic material that blocks light transmission.

[0076] The bottom metal layer 110 may have a patterned shape. The bottom metal layer 110 may be disposed below the active layer ACT of the transistor TR to cover at least the channel region of the active layer ACT of the transistor TR or to overlap with at least the channel region of the active layer ACT of the transistor TR, and by extension, to cover the entire active layer ACT of the transistor TR or to overlap with the entire active layer ACT of the transistor TR. However, the disclosure is not limited thereto, and the bottom metal layer 110 may be omitted.

[0077] A buffer layer 122 may be disposed on the bottom metal layer 110. The buffer layer 122 can protect the transistor TR from moisture introduced through the moisture-permeable substrate SUB. The buffer layer 122 may include alternately stacked inorganic layers.

[0078] Transistor TR can be disposed on buffer layer 122 and can form the pixel circuit for each pixel PX. For example, transistor TR can be a driving transistor or a switching transistor for the pixel circuit. Although Figure 3 Only transistor TR among the transistors included in each pixel PX of the display device 10 is shown, but the disclosure is not limited thereto. Each pixel PX of the display device 10 may also include a larger number of transistors. For example, the display device 10 may include two or three transistors in each pixel PX.

[0079] A semiconductor layer may be disposed on the buffer layer 122. The semiconductor layer may include the active layer ACT of the transistor TR. The active layer ACT may be stacked with the bottom metal layer 110.

[0080] The semiconductor layer may include polycrystalline silicon, monocrystalline silicon, or oxide semiconductors, etc. In embodiments where the semiconductor layer includes polycrystalline silicon, the polycrystalline silicon can be formed by crystallizing amorphous silicon. When the semiconductor layer includes polycrystalline silicon, the active layer ACT may include doped regions doped with impurities and channel regions between the doped regions. In embodiments, the semiconductor layer may include oxide semiconductors. Oxide semiconductors may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO).

[0081] The gate insulating film 123 can be disposed on the semiconductor layer. The gate insulating film 123 can be used as the gate insulating film of a transistor TR. The gate insulating film 123 can be, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x An inorganic layer of inorganic material such as silicon oxynitride (SiON) or an inorganic layer thereof, or a structure in which the above materials are stacked.

[0082] A gate conductive layer may be disposed on the gate insulating film 123. The gate conductive layer may include the gate electrode GE of the transistor TR. The gate electrode GE may be stacked on the third-direction DR3 with the channel region of the active layer ACT.

[0083] The gate conductive layer can be formed as, but is not limited to, a single layer or multiple layers made of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0084] The first interlayer insulating film 124 can be disposed on the gate conductive layer. The first interlayer insulating film 124 can cover the gate electrode GE or be stacked with the gate electrode GE. The first interlayer insulating film 124 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x Inorganic insulating materials such as silicon oxynitride (SiON) or silicon oxynitride (SiON).

[0085] The second interlayer insulating film 125 may be disposed on the first interlayer insulating film 124. The second interlayer insulating film 125 can flatten the steps (or height differences) formed by the first interlayer insulating film 124. The second interlayer insulating film 125 may include an organic insulating material. However, the disclosure is not limited thereto, and the second interlayer insulating film 125 may be omitted.

[0086] The first conductive layer 130 may be disposed on the second interlayer insulating film 125. The first conductive layer 130 may include a first source / drain electrode SD1 and a second source / drain electrode SD2 of the transistor TR. Although not shown in the figures, the first conductive layer 130 may also include data lines.

[0087] The first source / drain electrode SD1 and the second source / drain electrode SD2 of transistor TR can be electrically connected to the two end regions of the active layer ACT of transistor TR (e.g., the doped regions of the active layer ACT of transistor TR) through contact holes penetrating the second interlayer insulating film 125, the first interlayer insulating film 124, and the gate insulating film 123, respectively. The first source / drain electrode SD1 of transistor TR can be electrically connected to the bottom metal layer 110 through another contact hole penetrating the second interlayer insulating film 125, the first interlayer insulating film 124, the gate insulating film 123, and the buffer layer 122.

[0088] The first conductive layer 130 may be, but is not limited to, a single layer or multiple layers made of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys (or including one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys).

[0089] Passivation layer 126 may be disposed on the first conductive layer 130. Passivation layer 126 may be disposed on transistor TR to cover transistor TR or stacked with transistor TR to protect transistor TR. Passivation layer 126 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x Inorganic insulating materials such as silicon oxynitride (SiON) or silicon oxynitride (SiON).

[0090] The second conductive layer 140 may be disposed on the passivation layer 126. The second conductive layer 140 may include a first electric field line VL1, a second electric field line VL2, and a first conductive pattern CP1.

[0091] A high potential voltage (or a first power supply voltage) can be supplied to the first power line VL1, and a low potential voltage (or a second power supply voltage) that is lower than the high potential voltage (first power supply voltage) supplied to the first power line VL1 can be supplied to the second power line VL2.

[0092] The second power line VL2 can be electrically connected to the second electrode 220 to supply a low potential voltage (second power supply voltage) to the second electrode 220. During the manufacturing process of the display device 10, alignment signals required to align the light-emitting element ED can be transmitted to the second power line VL2.

[0093] The first power line VL1 can be stacked on the third-direction DR3 with the first source / drain electrode SD1 of the transistor TR. The first power line VL1 can be electrically connected to the first source / drain electrode SD1 of the transistor TR via the connection pattern 230 described later.

[0094] The first conductive pattern CP1 can be superimposed on the second source / drain electrode SD2 of the transistor TR on the third-direction DR3. The first conductive pattern CP1 can be electrically connected to the second source / drain electrode SD2 of the transistor TR through the first electrode 210.

[0095] The second conductive layer 140 may be, but is not limited to, a single layer or multiple layers made of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys (or including one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys).

[0096] The via layer 127 can be disposed on the second conductive layer 140. The via layer 127 can be disposed on the passivation layer 126 on which the second conductive layer 140 is disposed. The via layer 127 can planarize the surface. The via layer 127 can include an organic insulating material, such as an organic material like polyimide (PI).

[0097] Now refer to Figure 2 and Figure 3 The structure of the light-emitting element layer EML disposed on the via layer 127 of the circuit element layer PAL is described in detail.

[0098] The first dike 400 can be disposed on the perforated layer 127. The first dike 400 may include a first sub-dike 410 and a second sub-dike 420 spaced apart from each other in the first direction DR1.

[0099] The first sub-dike 410 and the second sub-dike 420 may extend in the second direction DR2, but the upper and lower ends of the first sub-dike 410 and the second sub-dike 420 may terminate within a pixel PX so as not to extend into other adjacent pixels PX in the second direction DR2. However, the disclosure is not limited thereto, and the first sub-dike 410 and the second sub-dike 420 may also extend into other adjacent pixels PX in the second direction DR2.

[0100] The first sub-dam 410 and the second sub-dam 420 can be distributed throughout the emission region EMA and non-emission regions. The first sub-dam 410 and the second sub-dam 420 can be distributed throughout other adjacent pixels PX in the first direction DR1. For example, the first sub-dam 410 and the second sub-dam 420 can be disposed not only in the emission region EMA of each adjacent pixel PX in the first direction DR1, but also at the boundary of adjacent pixels PX.

[0101] In the cross-sectional view, at least a portion of each of the first sub-dam 410 and the second sub-dam 420 may protrude from the upper surface of the via layer 127. Each of the first sub-dam 410 and the second sub-dam 420 may include a sloping side surface. For example, the first sub-dam 410 and the second sub-dam 420 including sloping side surfaces may change the direction of light emitted from the light-emitting element ED and traveling toward the side surfaces of the first sub-dam 410 and the second sub-dam 420 to an upward direction (e.g., a display direction). For example, the first sub-dam 410 and the second sub-dam 420 may provide a space in which the light-emitting element ED is disposed, while also serving as a reflective barrier to change the direction of light emitted from the light-emitting element ED to a display direction.

[0102] although Figure 3 The illustration shows each side surface of the first sub-dike 410 and the second sub-dike 420 inclined in a linear shape, but the disclosure is not limited thereto. For example, each side surface of the first sub-dike 410 and the second sub-dike 420 may have a semi-circular or semi-elliptical shape.

[0103] The third conductive layer 200 may be disposed on the first dam 400. The third conductive layer 200 may include a first electrode 210, a second electrode 220 and a connecting pattern 230 spaced apart from each other.

[0104] The first electrode 210 can be disposed on the first sub-dike 410. The first electrode 210 can extend in the second direction DR2 in the plan view to overlap with a portion of the second dike 600 extending in the first direction DR1. The first electrode 210 can be electrically connected to the circuit element layer PAL through the second contact hole CT11. The first electrode 210 can be electrically connected to a portion of the first conductive layer 130 and a portion of the second conductive layer 140 through the second contact hole CT11. Specifically, the first electrode 210 can be electrically connected through the second contact hole CT11 to the second source / drain electrode SD2 of the transistor TR in the first conductive layer 130 and the first conductive pattern CP1 of the second conductive layer 140.

[0105] The first electrode 210 may cover the upper surface and inclined side surface of the first sub-dike 410 or be stacked with the upper surface and inclined side surface of the first sub-dike 410. The first electrode 210 may be disposed on the first sub-dike 410 to cover the first sub-dike 410 or be stacked with the first sub-dike 410 in the third direction DR3 (or the thickness direction of the substrate SUB).

[0106] The second electrode 220 can be disposed on the second sub-dike 420. The second electrode 220 can be spaced apart from the first electrode 210. The second electrode 220 can extend in the second direction DR2 in the plan view to overlap with a portion of the second dike 600 extending in the first direction DR1. The second electrode 220 can be electrically connected to the circuit element layer PAL through the third contact hole CT12. The second electrode 220 can be electrically connected to a portion of the second conductive layer 140 through the third contact hole CT12. Specifically, the second electrode 220 can be electrically connected to the second electric field line VL2 of the second conductive layer 140 through the third contact hole CT12.

[0107] The second electrode 220 may cover the upper surface and inclined side surface of the second sub-dike 420 or be stacked with the upper surface and inclined side surface of the second sub-dike 420. The second electrode 220 may be disposed on the second sub-dike 420 to cover the second sub-dike 420 or be stacked with the second sub-dike 420 in the third direction DR3 (or the thickness direction of the substrate SUB).

[0108] The first electrode 210 and the second electrode 220, respectively disposed on the first sub-dike 410 and the second sub-dike 420, can extend outward to be located in at least a portion of the space formed between the spaced-apart first sub-dike 410 and the second sub-dike 420. The first electrode 210 and the second electrode 220 can be spaced apart from each other in the space formed between the spaced-apart first sub-dike 410 and the second sub-dike 420 so as to face each other.

[0109] Each of the first electrode 210 and the second electrode 220 can be electrically connected to the light-emitting element ED and can receive a predetermined voltage, enabling the light-emitting element ED to emit light. For example, electrodes 210 and 220 can be electrically connected to the light-emitting element ED disposed between the first sub-dike 410 and the second sub-dike 420 via the first contact electrode 710 and the second contact electrode 720, which will be described below, and the received electrical signals can be transmitted to the light-emitting element ED via the contact electrodes 710 and 720.

[0110] Connection pattern 230 can be disposed on the first sub-dam 410. Connection pattern 230 disposed on the first sub-dam 410 can be spaced apart from the first electrode 210. Connection pattern 230 can electrically connect the first conductive layer 130 and the second conductive layer 140 of the circuit element layer PAL through the first contact hole CT13. Connection pattern 230 can electrically connect the first source / drain electrode SD1 of the transistor TR of the first conductive layer 130 to the first electric field line VL1 of the second conductive layer 140 through the first contact hole CT13. This will be described in detail below.

[0111] The third conductive layer 200 may include a conductive material with high reflectivity. For example, the third conductive layer 200 may include a metal such as silver (Ag), copper (Cu), or aluminum (Al) as a material with high reflectivity, or it may be an alloy including aluminum (Al), nickel (Ni), and lanthanum (La). The third conductive layer 200, which includes a conductive material with high reflectivity, can cause light emitted from the light-emitting element ED and traveling in parallel to the first electrode 210 and the second electrode 220 disposed on the side surface of the first dam 400 to be reflected in the display direction (e.g., third-direction DR3).

[0112] However, the disclosure is not limited thereto, and the third conductive layer 200 may also include a transparent conductive material. For example, the third conductive layer 200 may include materials such as ITO, IZO, or ITZO. In some embodiments, the third conductive layer 200 may have a structure in which the transparent conductive material and the metal layer with high reflectivity are both stacked in one or more layers or may be formed as a single layer including them. For example, the third conductive layer 200 may have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0113] The first insulating layer 510 can be disposed on the third conductive layer 200. The first insulating layer 510 can protect the first electrode 210, the second electrode 220, and the connecting pattern 230 of the third conductive layer 200, while insulating them from each other. Specifically, the first insulating layer 510 can be disposed on the first electrode 210 and the second electrode 220, as well as the area between the first electrode 210 and the second electrode 220, to insulate them from each other. The first insulating layer 510 can completely cover the upper part of the connecting pattern 230 or overlap with the upper part of the connecting pattern 230, so that the connecting pattern 230 is insulated from the first electrode 210 and the second electrode 220. The first insulating layer 510 can also prevent the light-emitting element ED disposed on the first insulating layer 510 from directly contacting other components and thus prevent the light-emitting element ED from being damaged.

[0114] In an embodiment, the fourth opening OP21 and the fifth opening OP22 may be formed in the first insulating layer 510 to expose a portion of the upper surface of the first electrode 210 disposed on the first sub-dike 410 and a portion of the upper surface of the second electrode 220 disposed on the second sub-dike 420. The first contact electrode 710, as described below, can electrically contact the first electrode 210 through the fourth opening OP21 penetrating the first insulating layer 510, and the second contact electrode 720 can electrically contact the second electrode 220 through the fifth opening OP22 penetrating the first insulating layer 510.

[0115] The second dike 600 may be disposed on the first insulating layer 510. The second dike 600 may be disposed on the upper surface of the first dike 400 on which the first insulating layer 510 is disposed. The second dike 600 may include portions extending in the first direction DR1 and the second direction DR2 to form a grid pattern in a planar view. The second dike 600 can prevent ink, including the light-emitting element ED, from spilling into adjacent pixels PX during the inkjet printing process used to align the light-emitting element ED in the manufacturing process of the display device 10.

[0116] The light-emitting element ED can be disposed on the first insulating layer 510 between the first sub-dike 410 and the second sub-dike 420. The light-emitting element ED can be disposed on the first insulating layer 510 such that the end of each light-emitting element ED in its extending direction is respectively located on the first electrode 210 and the second electrode 220. The extending direction of the light-emitting element ED can be substantially perpendicular to the direction along which each of the electrodes 210 and 220 extends. However, the disclosure is not limited thereto; some of the light-emitting elements ED can extend in a direction substantially perpendicular to the direction along which the first electrode 210 and the second electrode 220 extend, and some other light-emitting elements ED can extend in a direction inclined to the direction along which the first electrode 210 and the second electrode 220 extend.

[0117] The second insulating layer 520 may be disposed on a portion of each light-emitting element ED. The second insulating layer 520 may partially cover the outer surface of each light-emitting element ED or partially overlap with the outer surface of each light-emitting element ED, but may not cover the ends of the light-emitting elements ED.

[0118] A portion of the second insulating layer 520 disposed on the light-emitting element ED can extend in a second direction DR2 on the first insulating layer 510 in a planar view to form a linear or island pattern in each pixel PX. The second insulating layer 520 can protect the light-emitting element ED while fixing it during the manufacturing process of the display device 10.

[0119] The first contact electrode 710 can be disposed on the first electrode 210. The first contact electrode 710 can extend in one direction. The first contact electrode 710 can extend in a second direction DR2. The first contact electrode 710 can form a stripe pattern in the emission region EMA of each pixel PX.

[0120] The first contact electrode 710 can electrically contact the first electrode 210 and the first end of the light-emitting element ED. The first contact electrode 710 can be disposed on the first electrode 210 such that a portion of the first contact electrode 710 electrically contacts the surface of the first electrode 210 exposed by the fourth opening OP21 formed in the first insulating layer 510, and another portion of the first contact electrode 710 electrically contacts the first end of the light-emitting element ED. The first contact electrode 710 electrically connecting the first end of the light-emitting element ED and the first electrode 210 can electrically connect the light-emitting element ED and the first electrode 210. The first contact electrode 710 can extend from the first end of the light-emitting element ED toward the second insulating layer 520 to be located on a portion of the second insulating layer 520.

[0121] The second contact electrode 720 may be disposed on the second electrode 220. The second contact electrode 720 may extend in one direction. The second contact electrode 720 may extend in a second direction DR2. The second contact electrode 720 may form a stripe pattern in the emission region EMA of each pixel PX. The second contact electrode 720 may be spaced apart from the first contact electrode 710 so as to face the first contact electrode 710 in the first direction DR1.

[0122] The second contact electrode 720 can electrically contact the second electrode 220 and the second end of the light-emitting element ED. The second contact electrode 720 can be disposed on the second electrode 220 such that a portion of the second contact electrode 720 electrically contacts the surface of the second electrode 220 exposed by the fifth opening OP22 formed in the first insulating layer 510, and another portion of the second contact electrode 720 electrically contacts the second end of the light-emitting element ED. The second contact electrode 720 electrically connecting the second end of the light-emitting element ED and the second electrode 220 can electrically connect the light-emitting element ED and the second electrode 220. The second contact electrode 720 can extend from the second end of the light-emitting element ED toward the third insulating layer 530, which will be described below, to lie on a portion of the third insulating layer 530.

[0123] Each of the first contact electrode 710 and the second contact electrode 720 may include a conductive material, such as ITO, IZO, ITZO, or aluminum (Al). For example, each of the first contact electrode 710 and the second contact electrode 720 may include, but is not limited to, a transparent conductive material.

[0124] The third insulating layer 530 may be disposed on the first contact electrode 710. The third insulating layer 530 may be stacked with the first contact electrode 710. The end surfaces of the third insulating layer 530 and the second insulating layer 520 facing the second sub-dike 420 may be aligned with each other.

[0125] The third insulating layer 530 can electrically insulate the first contact electrode 710 and the second contact electrode 720 from each other. The third insulating layer 530 can be stacked with the first contact electrode 710, but it can be omitted from the second end of the light-emitting element ED, so that the light-emitting element ED can contact the second contact electrode 720.

[0126] The first contact electrode 710 and the second contact electrode 720 can be disposed on different layers. A portion of the first contact electrode 710 can be directly disposed on the second insulating layer 520 disposed on the light-emitting element ED, and a portion of the second contact electrode 720 can be directly disposed on the third insulating layer 530. Therefore, the third insulating layer 530 can be disposed between the first contact electrode 710 and the second contact electrode 720.

[0127] The fourth insulating layer 540 can be disposed on the entire surface of the substrate SUB. The fourth insulating layer 540 can protect the components disposed on the substrate SUB from the influence of the external environment.

[0128] Figure 4 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A.

[0129] Reference Figure 4 A passivation layer 126 can be disposed on the first conductive layer 130, a second conductive layer 140 can be disposed on the passivation layer 126, and a via layer 127 and a first dam 400 can be disposed on the second conductive layer 140. A third conductive layer 200 can be disposed on the first dam 400. Although Figure 4 The diagram shows a third conductive layer 200 disposed on the surface of the first dam 400, but the disclosure is not limited thereto. For example, the third conductive layer 200 may be disposed on the surface of the via layer 127 exposed by the first dam 400.

[0130] Now refer to Figure 4 The relationship between the first conductive layer 130, the second conductive layer 140, the third conductive layer 200, the passivation layer 126, the via layer 127, and the first dam 400 is described in detail.

[0131] At least a portion of the third conductive layer 200 can electrically connect the first conductive layer 130 and the second conductive layer 140 through the first contact hole CT13 and the second contact hole CT11 that penetrate the first dike 400, the through-hole layer 127 and the passivation layer 126.

[0132] Each of the first contact hole CT13 and the second contact hole CT11 can expose a portion of the upper surface of the first conductive layer 130 and a portion of the upper surface and side surface of the second conductive layer 140 on the third-direction DR3, and a portion of the third conductive layer 200 can electrically contact a portion of the upper surface of the first conductive layer 130 and a portion of the upper surface and side surface of the second conductive layer 140, thereby electrically connecting the first conductive layer 130 and the second conductive layer 140 to each other.

[0133] The passivation layer 126 can be placed on the third-direction DR3 between the first conductive layer 130 and the second conductive layer 140. For example, it is not necessary to form a separate contact hole penetrating the passivation layer 126 between the first conductive layer 130 and the second conductive layer 140, and the first conductive layer 130 and the second conductive layer 140 can be electrically connected through a contact hole on one side of the second conductive layer 140.

[0134] Specifically, the connection pattern 230 included in the third conductive layer 200 can electrically connect the first conductive layer 130 and the second conductive layer 140 through the first contact hole CT13 penetrating the first dike 400, the via layer 127, and the passivation layer 126. The connection pattern 230 can be disposed on the first sub-dike 410 to electrically connect the first power line VL1 included in the second conductive layer 140 to the first source / drain electrode SD1 of the transistor TR included in the first conductive layer 130 through the first contact hole CT13 penetrating the first sub-dike 410, the via layer 127, and the passivation layer 126.

[0135] The first contact hole CT13 exposes at least a portion of the upper surface of the first source / drain electrode SD1 of the first conductive layer 130, as well as a portion of the upper surface and side surface of the first electric field line VL1 of the second conductive layer 140. The connection pattern 230 can electrically contact the side surface of the first electric field line VL1, a portion of the upper surface of the first electric field line VL1, and a portion of the upper surface of the first source / drain electrode SD1 exposed through the first contact hole CT13 on the third-party DR3.

[0136] The first contact hole CT13 may include a first portion CT13A formed by the sidewall of the first sub-dike 410, a second portion CT13B formed by the sidewall of the through-hole layer 127, a third portion CT13C formed by the side surface of the first electric line VL1 and the sidewall of the through-hole layer 127, and a fourth portion CT13D formed by the sidewall of the passivation layer 126. The first portions CT13A to the fourth portions CT13D of the first contact hole CT13 may be integrally formed with each other to form a hole.

[0137] The width of the first portion CT13A of the first contact hole CT13 may be larger than the width of the second portions CT13B to the fourth portions CT13D of the first contact hole CT13. The width of the second portion CT13B of the first contact hole CT13 may be larger than the width of the third portion CT13C and the fourth portion CT13D of the first contact hole CT13. Although the width of the first contact hole CT13 may decrease in the downward direction (i.e., the direction opposite to the third direction DR3), the first contact hole CT13 may have a stepped shape in the second portion CT13B and the third portion CT13C of the first contact hole CT13.

[0138] The fourth portion CT13D of the first contact hole CT13, formed by the sidewall of the passivation layer 126, may not be stacked with the second conductive layer 140 on the third-direction DR3. Specifically, the fourth portion CT13D of the first contact hole CT13 may not be stacked with the first electric field line VL1 on the third-direction DR3. For example, the fourth portion CT13D of the first contact hole CT13 may not be placed between the first electric field line VL1 and the first source / drain electrode SD1.

[0139] The first insulating layer 510 disposed on the connection pattern 230 can completely cover the connection pattern 230 or completely overlap with the connection pattern 230. The connection pattern 230 completely overlapped by the first insulating layer 510 can be electrically insulated from the first electrode 210 and the second electrode 220.

[0140] The second contact hole CT11 can expose at least a portion of the upper surface of the second source / drain electrode SD2 of the first conductive layer 130, as well as a portion of the upper surface and side surface of the first conductive pattern CP1 of the second conductive layer 140. The first electrode 210 can make electrical contact on the third-party DR3 with the side surface of the first conductive pattern CP1, a portion of the upper surface of the first conductive pattern CP1, and a portion of the upper surface of the second source / drain electrode SD2 exposed through the second contact hole CT11.

[0141] The second contact hole CT11 may include a first portion CT11A formed by the sidewall of the first sub-dike 410, a second portion CT11B formed by the sidewall of the via layer 127, a third portion CT11C formed by the side surface of the first conductive pattern CP1 and the sidewall of the via layer 127, and a fourth portion CT11D formed by the sidewall of the passivation layer 126. The first portion CT11A to the fourth portion CT11D of the second contact hole CT11 may be integrally formed with each other to form a hole.

[0142] The width of the first portion CT11A of the second contact hole CT11 can be larger than the width of the second portions CT11B to the fourth portion CT11D of the second contact hole CT11. The width of the second portion CT11B of the second contact hole CT11 can be larger than the width of the third portion CT11C and the fourth portion CT11D of the second contact hole CT11. Although the width of the second contact hole CT11 can decrease in the downward direction (i.e., in the direction opposite to the third direction DR3), the second contact hole CT11 can have a stepped shape in the second portion CT11B and the third portion CT11C of the second contact hole CT11.

[0143] The fourth portion CT11D of the second contact hole CT11, formed by the sidewall of the passivation layer 126, may not be superimposed on the second conductive layer 140 on the third-direction DR3. Specifically, the fourth portion CT11D of the second contact hole CT11 may not be superimposed on the first conductive pattern CP1 on the third-direction DR3. For example, the fourth portion CT11D of the second contact hole CT11 may not be placed between the first conductive pattern CP1 and the second source / drain electrode SD2.

[0144] The first insulating layer 510 disposed on the first electrode 210 may include a fourth opening OP21 that exposes at least a portion of the surface of the first electrode 210. The first contact electrode 710 and the first electrode 210 may be electrically connected to each other through the fourth opening OP21.

[0145] Figure 5 This is a schematic diagram of a light-emitting element (ED) according to an embodiment.

[0146] Reference Figure 5 The light-emitting element (ED) can be a particulate element and can be shaped like a rod or cylinder with a length-to-diameter ratio. The length of the ED can be larger than the diameter of the ED, and the length-to-diameter ratio of the ED can be, but is not limited to, about 6:5 to about 100:1.

[0147] The light-emitting element (ED) can have a nanometer-scale size (about 1 nm to about 1 μm) or a micrometer-scale size (about 1 μm to about 1 mm). In embodiments, both the diameter and length of the ED can be nanometer-scale or micrometer-scale. In some embodiments, the diameter of the ED can be nanometer-scale, while the length of the ED can be micrometer-scale. In some embodiments, some of the EDs can have a nanometer-scale diameter and / or length, while other EDs can have a micrometer-scale diameter and / or length.

[0148] In an embodiment, the light-emitting element ED can be an inorganic LED. An inorganic LED can include a semiconductor layer. For example, an inorganic LED can include a first conductivity type (e.g., n-type) semiconductor layer, a second conductivity type (e.g., p-type) semiconductor layer, and an active semiconductor layer disposed therebetween. The active semiconductor layer can receive holes and electrons from the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, and the holes and electrons arriving at the active semiconductor layer can combine to emit light.

[0149] In this embodiment, the semiconductor layers can be sequentially stacked in the longitudinal direction of the light-emitting element (ED). The light-emitting element (ED) may include a first semiconductor layer 31, an active element 33, and a second semiconductor layer 32 sequentially stacked in the longitudinal direction, such as... Figure 5 As shown in the diagram, the first semiconductor layer 31, the active element layer 33, and the second semiconductor layer 32 can be the first conductivity type semiconductor layer, the active semiconductor layer, and the second conductivity type semiconductor layer, respectively.

[0150] The first semiconductor layer 31 may be doped with a first conductivity type dopant. The first conductivity type dopant may be Si, Ge, Se, or Sn. In an embodiment, the first semiconductor layer 31 may be n-GaN doped with n-type Si.

[0151] The second semiconductor layer 32 may be spaced apart from the first semiconductor layer 31, and the active layer 33 is disposed between the second semiconductor layer 32 and the first semiconductor layer 31. The second semiconductor layer 32 may be doped with a second conductivity type dopant, such as Mg, Zn, Ca, or Ba. In an embodiment, the second semiconductor layer 32 may be p-GaN doped with p-type Mg.

[0152] The active layer 33 may comprise a material having a single quantum well structure or a multiple quantum well structure. As described above, the active layer 33 may emit light based on the electrical signals received through the first semiconductor layer 31 and the second semiconductor layer 32 via the recombination of electron-hole pairs.

[0153] In some embodiments, the active layer 33 may have a structure in which semiconductor materials with large bandgap energy and semiconductor materials with small bandgap energy are alternately stacked, depending on the wavelength band in which it is emitted, or may include different group III to group V semiconductor materials.

[0154] Light emitted from the active layer 33 can be emitted not only to the outer surface of the light-emitting element ED in the longitudinal direction, but also to both side surfaces of the light-emitting element ED. For example, the direction of light emitted from the active layer 33 is not limited to one direction.

[0155] The light-emitting element (ED) may further include an element electrode layer 37 disposed on the second semiconductor layer 32. The element electrode layer 37 may contact the second semiconductor layer 32. The element electrode layer 37 may be an ohmic contact electrode. However, the disclosure is not limited thereto, and the element electrode layer 37 may also be a Schottky contact electrode.

[0156] When the light-emitting element ED is electrically connected at its end to the first contact electrode 710 and the second contact electrode 720 to transmit electrical signals to the first semiconductor layer 31 and the second semiconductor layer 32, the element electrode layer 37 may be disposed between the second semiconductor layer 32 and the first contact electrode 710 to reduce the resistance between them. The element electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The element electrode layer 37 may also include a semiconductor material doped with n-type or p-type dopants.

[0157] The light-emitting element (or light-emitting diode) ED may further include an insulating film 38 covering the outer circumferential surfaces of the first semiconductor layer 31, the second semiconductor layer 32, the active element layer 33, and / or the electrode layer 37. The insulating film 38 may surround at least the outer surface of the active element layer 33 and extend in the direction along which the light-emitting element ED extends. The insulating film 38 may protect the aforementioned components (e.g., the first semiconductor layer 31, the second semiconductor layer 32, the active element layer 33, and the electrode layer 37). The insulating film 38 may be made of a material with insulating properties to prevent electrical short circuits that may occur when the active element layer 33 directly contacts the electrodes through which electrical signals are transmitted to the light-emitting element ED. Because the insulating film 38 protects the outer circumferential surfaces of the first semiconductor layer 31, the second semiconductor layer 32, and the active element layer 33, a reduction in luminous efficiency can be prevented.

[0158] Figure 6 yes Figure 3 A schematic enlarged cross-sectional view of an example of region B.

[0159] Now refer to Figure 6 Describe the contact relationship between the end of the light-emitting element ED and the first contact electrode 710 and the second contact electrode 720.

[0160] As described above, the light-emitting element (ED) may include a first semiconductor layer 31 and a second semiconductor layer 32 doped with dopants of different conductivity types. The ED comprising the first semiconductor layer 31 and the second semiconductor layer 32 may be oriented such that a first end faces a specific direction according to the direction of the electric field generated on the first electrode 210 and the second electrode 220. Specifically, the ED may extend in one direction, and the end of the ED in the extending direction may be disposed on the first electrode 210 and the second electrode 220.

[0161] The light-emitting element (ED) can extend in a direction parallel to the substrate SUB, and the semiconductor layers included in the ED can be sequentially arranged in a direction parallel to the upper surface of the substrate SUB. Specifically, in a cross-sectional view across the end of the ED, a first semiconductor layer 31, an active element layer 33, a second semiconductor layer 32, and an electrode layer 37 can be sequentially formed in a direction horizontal to the surface of the substrate SUB. The ED can be aligned such that a first end of the second semiconductor layer 32 located elsewhere on the ED is located on a first electrode 210 and a second end of the first semiconductor layer 31 located elsewhere on the ED is located on a second electrode 220. However, the disclosure is not limited thereto; some EDs can also be aligned such that a first end of the second semiconductor layer 32 located elsewhere on the ED is located on a second electrode 220 and a second end of the first semiconductor layer 31 located elsewhere on the ED is located on a first electrode 210.

[0162] The end of the light-emitting element ED exposed by the second insulating layer 520 can make electrical contact with the first contact electrode 710 and the second contact electrode 720, respectively.

[0163] The first contact electrode 710 can electrically contact the first end of the light-emitting element ED. The first contact electrode 710 can electrically contact the element electrode layer 37 disposed at the first end of the light-emitting element ED. The first contact electrode 710 can be electrically connected to the second semiconductor layer 32 through the element electrode layer 37 of the light-emitting element ED.

[0164] The second contact electrode 720 can make electrical contact with the second end of the light-emitting element ED. The second contact electrode 720 can also make electrical contact with the first semiconductor layer 31 disposed at the second end of the light-emitting element ED.

[0165] The first end of the second semiconductor layer 32 of the light-emitting element ED is electrically connected to the first electrode 210 via the first contact electrode 710, and the second end of the first semiconductor layer 31 of the light-emitting element ED is electrically connected to the second electrode 220 via the second contact electrode 720. For example, since the ends of the light-emitting element ED are electrically contacting the first contact electrode 710 and the second contact electrode 720 respectively, the light-emitting element ED can receive electrical signals from the first electrode 210 and the second electrode 220, and can emit light from the active layer 33 of the light-emitting element ED according to the electrical signals.

[0166] Figure 7 yes Figure 3 A schematic enlarged cross-sectional view of an example of region B.

[0167] Reference Figure 7 Examples and Figure 6 The difference in the embodiments may be at least in that the third insulating layer 530 is omitted.

[0168] Specifically, the first contact electrode 710 and the second contact electrode 720_1 can be directly disposed on the second insulating layer 520. The first contact electrode 710 and the second contact electrode 720_1 disposed on the second insulating layer 520 can be spaced apart from each other to expose a portion of the second insulating layer 520. The second insulating layer 520 exposed by the first contact electrode 710 and the second contact electrode 720_1 can contact the fourth insulating layer 540 in the exposed area.

[0169] In this embodiment, even if the third insulating layer 530 is omitted from the display device 10, the second insulating layer 520, comprising an organic insulating material, can still fix the light-emitting element ED. The first contact electrode 710 and the second contact electrode 720_1 can be formed simultaneously by patterning in a mask process. Therefore, since no additional mask process is required to form the first contact electrode 710 and the second contact electrode 720_1, process efficiency can be improved. Except for omitting the third insulating layer 530, the embodiment can be compared with... Figure 6 The embodiments are the same, so repeated descriptions will be omitted.

[0170] Figures 8 to 15 It shows the manufacturing basis. Figure 3 A schematic cross-sectional view of some of the operations in the method of the display device 10 of the embodiment.

[0171] Reference Figure 8First, a transistor TR can be formed on a substrate SUB. The steps of forming the transistor TR on the substrate SUB may include: stacking a barrier layer 121 on the surface of the substrate SUB and forming a patterned bottom metal layer 110 on the surface of the barrier layer 121; stacking a buffer layer 122 on the bottom metal layer 110 and forming a semiconductor layer including an active layer ACT of the transistor TR on the buffer layer 122; stacking a gate insulating film 123 on the semiconductor layer and forming a gate conductive layer including a gate electrode GE of the transistor TR on the gate insulating film 123; stacking a first interlayer insulating film 124 and a second interlayer insulating film 125 on the gate conductive layer and forming a contact hole; and forming a patterned first conductive layer 130 on the second interlayer insulating film 125.

[0172] The step of forming a patterned bottom metal layer 110 on the surface of the barrier layer 121 can be achieved through a masking process. Specifically, a material layer for the bottom metal layer can be deposited on the entire surface of the barrier layer 121 formed on the surface of the substrate SUB. Then, a photoresist layer can be coated on the material layer for the bottom metal layer, and the photoresist layer can be formed into a photoresist pattern by exposure and development. Subsequently, the photoresist pattern can be used as an etching mask to etch the material layer for the bottom metal layer. The photoresist pattern can then be removed by a stripping process or an ashing process.

[0173] Next, a buffer layer 122 can be formed on the entire surface of the barrier layer 121 over which the bottom metal layer 110 is formed, and a semiconductor layer can be formed on the buffer layer 122. The semiconductor layer can be formed using the same mask process. Although Figure 8 The active layer ACT of only one transistor TR is shown, but the display device 10 may also include a larger number of transistors as described above.

[0174] Subsequently, a gate insulating film 123 can be stacked on the buffer layer 122 on which the semiconductor layer is formed, and a patterned gate conductive layer can be formed on the gate insulating film 123. The patterned gate conductive layer can be formed using the same mask process. Specifically, a material layer for the gate conductive layer can be deposited on the entire surface of the gate insulating film 123. Then, a photoresist layer can be coated on the material layer for the gate conductive layer, and the photoresist layer can be formed into a photoresist pattern by exposure and development. Thereafter, the photoresist pattern can be used as an etching mask to etch the material layer for the gate conductive layer. The photoresist pattern can then be removed by a stripping process or an ashing process to form the gate electrode GE of the transistor TR as shown in the figures.

[0175] Next, a first interlayer insulating film 124 and a second interlayer insulating film 125 can be sequentially stacked on the gate insulating film 123 on which a patterned gate conductive layer is formed, and contact holes can be formed. Contact holes may include contact holes that expose a portion of the active layer ACT of the transistor TR and contact holes that expose a portion of the bottom metal layer 110. Contact holes can be formed using the same mask process. For example, a photoresist pattern (contact hole pattern) that partially exposes the bottom metal layer 110 and the active layer ACT can be formed on the second interlayer insulating film 125, and the photoresist pattern can be used as an etching mask to form contact holes that partially expose the buffer layer 122, the gate insulating film 123, the first interlayer insulating film 124, and the second interlayer insulating film 125.

[0176] The contact holes exposing the bottom metal layer 110 and the contact holes partially exposing the active layer ACT of the transistor TR can also be formed using different mask sequences. The addition of mask processes may reduce the economic efficiency of the manufacturing process of the display device 10. However, since the active layer ACT of the transistor TR is not exposed to the etchant while the buffer layer 122 is etched to form the contact holes exposing the bottom metal layer 110, the surface of the active layer ACT can be preserved without damage.

[0177] Next, a patterned first conductive layer 130 can be formed on the second interlayer insulating film 125. The first conductive layer 130 can be formed using the same mask process. Specifically, a material layer for the first conductive layer can be deposited on the entire surface of the second interlayer insulating film 125. In the deposition process, the material layer for the first conductive layer can be deposited into contact holes and thus connected to the bottom metal layer 110 and the active layer ACT of the transistor TR. A photoresist layer can then be coated on the material layer for the first conductive layer, and the photoresist layer is patterned by exposure and development. Subsequently, the photoresist pattern can be used as an etching mask to etch the material layer for the first conductive layer. The photoresist pattern can then be removed by a stripping or ashing process to form the first source / drain electrode SD1 and the second source / drain electrode SD2 of the transistor TR as shown in the figures.

[0178] Next, refer to Figure 9 A passivation layer 126 can be deposited on the entire surface of the second interlayer insulating film 125 on which the first conductive layer 130 is formed. In an embodiment, the passivation layer 126 can be deposited on the entire surface of the second interlayer insulating film 125 without forming contact holes in the passivation layer 126. Therefore, a separate masking process for forming the passivation layer 126 can be omitted.

[0179] Next, refer to Figure 10A patterned second conductive layer 140 can be formed on the passivation layer 126. The second conductive layer 140 can be formed using the same mask process. Specifically, a material layer for the second conductive layer can be deposited on the entire surface of the passivation layer 126. Then, a photoresist layer can be formed or coated on the material layer for the second conductive layer, and the photoresist layer can be patterned by exposure and development. Subsequently, the material layer for the second conductive layer can be etched using the photoresist pattern as an etching mask. The photoresist pattern can then be removed by a stripping or ashing process to form the first electric field line VL1, the second electric field line VL2, and the first conductive pattern CP1 as shown in the figures.

[0180] In an embodiment, the passivation layer 126 may be disposed between the second conductive layer 140 and the first conductive layer 130 formed on the passivation layer 126. Specifically, the first electric field line VL1 formed on the passivation layer 126 may be superimposed on at least a portion of the first source / drain electrode SD1 of the transistor TR on the third-direction DR3, but may not be superimposed on another portion of the first source / drain electrode SD1 of the transistor TR on the third-direction DR3. For example, the first electric field line VL1 may be disposed on the first source / drain electrode SD1 of the transistor TR to expose at least a portion of the first source / drain electrode SD1 of the transistor TR on the third-direction DR3. The passivation layer 126 may be disposed between the first source / drain electrode SD1 of the transistor TR and the first electric field line VL1. Similarly, the first conductive pattern CP1 formed on the passivation layer 126 may be superimposed on at least a portion of the second source / drain electrode SD2 of the transistor TR on the third-direction DR3, but may not be superimposed on another portion of the second source / drain electrode SD2 of the transistor TR on the third-direction DR3. For example, a first conductive pattern CP1 may be disposed on the second source / drain electrode SD2 of the transistor TR to expose at least a portion of the second source / drain electrode SD2 of the transistor TR on the third-direction DR3. A passivation layer 126 may be disposed between the second source / drain electrode SD2 of the transistor TR and the first conductive pattern CP1.

[0181] Next, refer to Figure 11 A via layer 127 can be deposited on the entire surface of the passivation layer 126 on which the second conductive layer 140 is formed, and a patterned first dam layer 400' can be formed on the via layer 127. The patterned first dam layer 400' can have a generally flat surface, but can have different heights in each region. For example, the height of the first region 400'_2 in which the light-emitting element ED is disposed in the first dam layer 400' can be smaller than the height of the second region 400'_1 in which the light-emitting element ED is not disposed in the first dam layer 400'.

[0182] The patterned first dam layer 400' may include a first opening OP11 to a third opening OP13 superimposed on a third-direction DR3 with a first electric field line VL1, a first conductive pattern CP1, and a second electric field line VL2, respectively. In a plan view, the first opening OP11 may be superimposed with the boundary region of the first electric field line VL1 superimposed with the first source / drain electrode SD1. In a plan view, the second opening OP12 may be superimposed with the boundary region of the first conductive pattern CP1 superimposed with the second source / drain electrode SD2. In a plan view, the third opening OP13 may be superimposed with the second electric field line VL2.

[0183] The patterned first dam layer 400' can be made of, for example, an organic material including a photosensitive material (or an organic material including, for example, a photosensitive material). The patterned first dam layer 400' can be formed by the following steps: coating the entire surface of the via layer 127 with an organic material layer for the first dam layer, and then forming the first opening OP11 to the third opening OP13 by exposure and development. A halftone mask or a slit mask can be used to form the patterned first dam layer 400' with different heights in each region.

[0184] Next, refer to Figure 12 A first sub-dike 410 and a second sub-dike 420 can be formed to include a first contact hole CT13, a second contact hole CT11, and a third contact hole CT12 that partially expose the first conductive layer 130 and / or the second conductive layer 140. Contact holes CT13, CT11, and CT12 may include the first contact hole CT13, the second contact hole CT11, and the third contact hole CT12. The second contact hole CT11 can partially expose the first conductive pattern CP1 and the second source / drain electrode SD2, the third contact hole CT12 can partially expose the second electric field line VL2, and the first contact hole CT13 can partially expose the first electric field line VL1 and the first source / drain electrode SD1.

[0185] Contact holes CT11 to CT13 can be formed using an etching process that employs a patterned first embankment layer 400' as an etching mask, without the need for a separate masking process. Specifically, the contact holes CT11 to CT13 can be formed by an etching process using the patterned first embankment layer 400' as an etching mask. Figure 11 The via layer 127 and passivation layer 126 exposed by the first opening OP11 are etched to form the first contact hole CT13 that exposes the first electric field line VL1 and the first source / drain electrode SD1. This can be achieved by... Figure 11 The via layer 127 and passivation layer 126 exposed by the second opening OP12 are etched to form a second contact hole CT11 that exposes the first conductive pattern CP1 and the second source / drain electrode SD2. This can be achieved by... Figure 11The via layer 127 exposed by the third opening OP13 is etched to form the third contact hole CT12, which exposes the second electric field line VL2. Furthermore, the first region 400'_2 of the first dam layer 400' may be removed to expose the via layer 127 superimposed on the first region 400'_2 of the first dam layer 400'. In an embodiment, the etching process used to form the contact holes CT11 to CT13 may be a dry etching process.

[0186] In an embodiment, an etching process for forming contact holes CT11 to CT13 may be performed in the step. For example, in the step of using a patterned first dam layer 400' as an etching mask, an etching process may be used to form a second contact hole CT11 that exposes the first conductive pattern CP1 and the second source / drain electrode SD2 by means of an etching process; a first contact hole CT13 that exposes the first electric field line VL1 and the first source / drain electrode SD1 by means of an etching layer 127 and a passivation layer 126; and a third contact hole CT12 that exposes the second electric field line VL2 by means of an etching layer 127.

[0187] In some embodiments, the etching process for forming contact holes CT11 to CT13 can be performed sequentially in two steps. For example, a patterned first dam layer 400' can be used as an etching mask to perform an etching process for forming contact holes that expose portions and side surfaces of the upper surface of the first conductive pattern CP1 and the first electric field line VL1, as well as a portion of the upper surface of the second electric field line VL2, through the via layer 127. Then, contact holes that expose the first source / drain electrode SD1 and the second source / drain electrode SD2 can be formed by changing the process conditions. As a result, contact holes CT11 to CT13 can be formed.

[0188] Next, refer to Figure 13A patterned third conductive layer 200 can be formed on the first sub-dike 410 and the second sub-dike 420. The third conductive layer 200 can be formed using the same mask process. Specifically, a material layer for the third conductive layer can be deposited on the entire surface of the first dike 400. In the deposition process, the material layer for the third conductive layer can be deposited into the first contact hole CT13, the second contact hole CT11, and the third contact hole CT12, and thus connected to the first conductive layer 130 and the second conductive layer 140. Specifically, in the deposition process, the material layer for the third conductive layer can be deposited into the second contact hole CT11 to electrically contact the second source / drain electrode SD2 of the first conductive layer 130 and the first conductive pattern CP1 of the second conductive layer 140. In the deposition process, the material layer for the third conductive layer can be deposited into the third contact hole CT12 to electrically contact the second electric field line VL2 of the second conductive layer 140. In the deposition process, a material layer for the third conductive layer can be deposited into the first contact hole CT13 to electrically contact the first source / drain electrode SD1 of the first conductive layer 130 and the first electric field line VL1 of the second conductive layer 140.

[0189] Then, a photoresist layer can be coated on the material layer for the third conductive layer, and a photoresist pattern can be formed by exposure and development. Subsequently, the photoresist pattern can be used as an etching mask to etch the material layer for the third conductive layer. The photoresist pattern can then be removed by a stripping or ashing process to form the first electrode 210, the second electrode 220, and the connection pattern 230, as shown below. Figure 13 As shown in the image.

[0190] Next, refer to Figure 14 A first insulating layer 510 may be stacked on a first dam 400 on which a patterned third conductive layer 200 is formed, and openings OP21 and OP22 may be formed. Openings OP21 and OP22 may include a fourth opening OP21 exposing a portion of the first electrode 210 and a fifth opening OP22 exposing a portion of the second electrode 220. The first insulating layer 510 may be disposed on the third conductive layer 200 to substantially overlap with the third conductive layer 200, but at least a portion of each of the first electrode 210 and the second electrode 220 may be exposed. The first insulating layer 510 may be disposed on the connection pattern 230 to completely overlap with the connection pattern 230. The first electrode 210, the second electrode 220, and the connection pattern 230 may be insulated from each other by the first insulating layer 510.

[0191] Next, refer to Figure 15 A second barrier 600 can be formed on the first insulating layer 510. The second barrier 600 can prevent ink in which light-emitting elements ED are dispersed from spilling into adjacent pixels PX during the inkjet process used to align the light-emitting elements ED.

[0192] Next, through conventional processes, it is possible to... Figure 3 The diagram shows a light-emitting element ED, a second insulating layer 520, a first contact electrode 710, a third insulating layer 530, a second contact electrode 720, and a fourth insulating layer 540 formed in the ground.

[0193] According to a method for manufacturing a display device according to an embodiment, the display device includes a first conductive layer, a passivation layer disposed on the surface of the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, and a third conductive layer disposed on the via layer. The third conductive layer can be used as a connection electrode to electrically connect the first conductive layer and the second conductive layer. Therefore, in the process of forming the passivation layer disposed between the first conductive layer and the second conductive layer, a separate mask process for forming contact holes that penetrate the passivation layer and connect the first conductive layer and the second conductive layer can be omitted. Therefore, since the additional mask process for connecting the first conductive layer and the second conductive layer is not required, the process efficiency of the display device can be improved.

[0194] Figure 16 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A.

[0195] Reference Figure 16 Examples and Figure 4 The difference in the embodiments may be at least that a portion of the second conductive layer 140_1 and a portion of the first conductive layer 130_1 exposed by the second contact hole CT11 and the first contact hole CT13 have a predetermined roughness on their surfaces.

[0196] Specifically, as described above, the second contact hole CT11 can expose a portion of the upper surface of the second source / drain electrode SD2_1 of the first conductive layer 130_1 and a portion of the upper surface and side surface of the first conductive pattern CP1_1 of the second conductive layer 140_1. A predetermined surface roughness can be formed on the portion of the upper surface of the second source / drain electrode SD2_1 and the portion of the upper surface and side surface of the first conductive pattern CP1_1 exposed by the second contact hole CT11. Surface roughness can be formed if a portion of the surface of the second source / drain electrode SD2_1 and / or the first conductive pattern CP1_1 is damaged due to exposure to the etchant used in the etching process for forming the second contact hole CT11.

[0197] Similarly, the first contact hole CT13 can expose a portion of the upper surface of the first source / drain electrode SD1_1 of the first conductive layer 130_1 and a portion of the upper surface and side surface of the first electric field line VL1_1 of the second conductive layer 140_1. A predetermined surface roughness can be formed on the portion of the upper surface of the first source / drain electrode SD1_1 and the portion of the upper surface and side surface of the first electric field line VL1_1 exposed by the first contact hole CT13. Surface roughness can be formed if a portion of the surface of the first source / drain electrode SD1_1 and / or the first electric field line VL1_1 is damaged due to exposure to the etchant used in the etching process for forming the first contact hole CT13.

[0198] Although not shown in the figures, a predetermined surface roughness may also be formed on a portion of the upper surface of the second electric field line VL2 of the second conductive layer 140_1 exposed by the third contact hole CT12.

[0199] Figure 17 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A.

[0200] Reference Figure 17 Examples and Figure 4 The difference in the embodiments may be at least that the sidewalls constituting the first contact hole CT13_1 and the second contact hole CT11_1 are not aligned with each other.

[0201] Specifically, the sidewalls of the first portion CT11A of the second contact hole CT11_1 and the sidewalls of the second portion CT11B_1 of the second contact hole CT11_1 may not be aligned with each other. For example, the sidewall of the first portion CT11A of the second contact hole CT11_1 may protrude further outward than the sidewall of the second portion CT11B_1 of the second contact hole CT11_1. Similarly, the sidewalls of the first portion CT13A of the first contact hole CT13_1 and the sidewalls of the second portion CT13B_1 of the first contact hole CT13_1 may not be aligned with each other. For example, the sidewall of the first portion CT13A of the first contact hole CT13_1 may protrude further outward than the sidewall of the second portion CT13B_1 of the first contact hole CT13_1. Due to the different etch selectivity of each component relative to the etchant used in the etching process for forming contact holes CT11_1, CT12, and CT13_1, the structure according to the embodiment can be formed.

[0202] Figure 18 yes Figure 3 A schematic enlarged cross-sectional view of an example of region A.

[0203] Reference Figure 18 Examples and Figure 4The difference in the embodiments may be at least that the sidewalls of the portions forming (or constituting) the first contact hole CT13_2 and the second contact hole CT11_2 are not aligned with each other.

[0204] Specifically, the sidewalls of the third portion CT11C and the fourth portion CT11D_2 of the second contact hole CT11_2 may not be aligned with each other. For example, the sidewall of the third portion CT11C of the second contact hole CT11_2 may protrude further outward than the sidewall of the fourth portion CT11D_2 of the second contact hole CT11_2. Similarly, the sidewalls of the third portion CT13C and the fourth portion CT13D_2 of the first contact hole CT13_2 may not be aligned with each other. For example, the sidewall of the third portion CT13C of the first contact hole CT13_2 may protrude further outward than the sidewall of the fourth portion CT13D_2 of the first contact hole CT13_2. Due to the different etch selectivity of each component relative to the etchant used in the etching process for forming contact holes CT11_2, CT12, and CT13_2, the structure according to the embodiment can be formed.

[0205] Figure 19 This is a schematic cross-sectional view of the display device 10_1 according to an embodiment.

[0206] Reference Figure 19 The display device 10_1 according to the embodiment and Figure 3 The difference in the display device 10 may be at least that the second conductive layer 140 does not include the first conductive pattern CP1.

[0207] Specifically, the first electrode 210_1 included in the display device 10_1 according to the embodiment can electrically contact the second source / drain electrode SD2 of the transistor TR through a second contact hole CT11_1 that penetrates the first sub-dam 410, the via layer 127, and the passivation layer 126. The second contact hole CT11_1 can penetrate the first sub-dam 410, the via layer 127, and the passivation layer 126 to expose a portion of the upper surface of the second source / drain electrode SD2. The second source / drain electrode SD2 can be electrically connected to the first electrode 210_1 through the second contact hole CT11_1.

[0208] Figure 20 This is a schematic cross-sectional view of the display device 10_2 according to an embodiment.

[0209] Reference Figure 20 The display device 10_2 according to the embodiment and Figure 3 The difference in the display device 10 may be at least in that: surface roughness is formed on the outer surface of the first dam 400_1 and on the upper surface of the through-hole layer 127 exposed by the first dam 400_1.

[0210] Specifically, a roughness can be formed on the outer surface of the first dike 400_1. For example, the outer surface of the first dike 400_1 may include the upper surface and side surface of each of the first sub-dike 410_1 and the second sub-dike 420_1. A predetermined surface roughness can be formed on the upper surface and side surface of each of the first sub-dike 410_1 and the second sub-dike 420_1. A predetermined roughness can be formed on the upper surface of the through-hole layer 127 exposed by the first sub-dike 410_1 and the second sub-dike 420_1.

[0211] A predetermined surface roughness can be formed on the upper surface of the first dam 400_1 exposed by the first dam 400_1 during the etching process used to form the first contact hole CT13, the second contact hole CT11, and the third contact hole CT12. For example, refer to Figure 11 and Figure 12 The outer surfaces of the first sub-dike 410_1 and the second sub-dike 420_1 can be exposed by using the first dike layer 400' (see Figure 11 The etchant used in the process of forming the first sub-dike 410_1 and the second sub-dike 420_1 as an etching mask without additional masking processes is used. Therefore, the upper and side surfaces of the first sub-dike 410_1 and the second sub-dike 420_1 exposed to the etchant can be partially etched to form a predetermined surface roughness. Therefore, the predetermined surface roughness can also be formed on the upper surfaces of the first electrode 210 and the second electrode 220, which are conformally formed on the first sub-dike 410_1 and the second sub-dike 420_1. Light emitted from the light-emitting element ED and traveling in parallel to the first electrode 210 and the second electrode 220 can be diffusely reflected due to the surface roughness formed on the surfaces of the first electrode 210 and the second electrode 220. This can reduce total internal reflection that may occur in the insulating layer, thereby improving the light efficiency of the display device 10_2.

[0212] Figure 21 This is a schematic cross-sectional view of the display device 10_3 according to an embodiment.

[0213] Reference Figure 21 The display device 10_3 according to the embodiment and Figure 3 The difference in the display device 10 may be at least that: the first dam 400_3 and the second dam 600_3 are spaced apart from each other, and the first contact hole CT13_3, the second contact hole CT11_3 and the third contact hole CT12_3 are not superimposed on the first dam 400_3 on the third direction DR3.

[0214] Specifically, the first dike 400_3 can be located in the area defined by the second dike 600_3. Therefore, the first dike 400_3 and the second dike 600_3 can be spaced apart from each other. Each of the first sub-dikes 410_3 and the second sub-dikes 420_3 of the first dike 400_3 can be spaced apart from the second dike 600_3 in the area defined by the second dike 600_3.

[0215] The first electrode 210_3 and the second electrode 220_3 can be respectively disposed on the first sub-dike 410_3 and the second sub-dike 420_3, so as to overlap with the outer surfaces of the first sub-dike 410_3 and the second sub-dike 420_3.

[0216] The first electrode 210_3 can electrically connect the first conductive pattern CP1 to the second source / drain electrode SD2 of the transistor TR through the second contact hole CT11_3 penetrating the via layer 127 and the passivation layer 126. The second electrode 220_3 can electrically connect to the second power line VL2 through the third contact hole CT12_3 penetrating the via layer 127. The connection pattern 230_3 can electrically connect the first power line VL1 to the first source / drain electrode SD1 of the transistor TR through the first contact hole CT13_3 penetrating the via layer 127 and the passivation layer 126. The first contact hole CT13_3, the second contact hole CT11_3, and the third contact hole CT12_3 can be on the third-direction DR3 without overlapping with the first dam 400_3.

[0217] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles disclosed. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A display device, the display device comprising: A transistor, disposed on a substrate, includes: an active layer; a gate electrode; and a first source / drain electrode and a second source / drain electrode, wherein a first interlayer insulating film and a second interlayer insulating film are disposed between the gate electrode and the first source / drain electrode and the second source / drain electrode. A first conductive layer is disposed on the second interlayer insulating film, and the first source / drain electrode and the second source / drain electrode are included in the first conductive layer; A passivation layer is disposed on the first conductive layer; A second conductive layer is disposed on the passivation layer and includes a first electric field line; A via layer is disposed on the second conductive layer; A third conductive layer is disposed on the via layer, the third conductive layer comprising: a first electrode; a second electrode; and a connection pattern, wherein the first electrode, the second electrode, and the connection pattern are spaced apart from each other; and The light-emitting element has its first end and second end respectively disposed on the first electrode and the second electrode. The connection pattern electrically connects the first source / drain electrode and the first power line through a first contact hole that penetrates the via layer and the passivation layer.

2. The display device according to claim 1, wherein, The first contact hole exposes at least a portion of the upper surface of the first electric field line, at least a portion of the side surface of the first electric field line, and at least a portion of the upper surface of the first source / drain electrode.

3. The display device according to claim 2, wherein, The connection pattern electrically contacts at least a portion of the upper surface of the first source / drain electrode, at least a portion of the upper surface of the first electric field line, and at least a portion of the side surface of the first electric field line.

4. The display device according to claim 1, wherein, The first contact hole includes a first portion formed by the sidewall of the through-hole layer, a second portion formed by the side surface of the first electric field line and the sidewall of the through-hole layer, and a third portion formed by the sidewall of the passivation layer. The first portion, the second portion, and the third portion of the first contact hole are stacked on top of each other in the thickness direction of the substrate.

5. The display device according to claim 4, wherein, The width of the first part is greater than the width of the second part, and The width of the first part is greater than the width of the third part.

6. The display device according to claim 4, wherein, The first part, the second part, and the third part are integral with each other and form a hole.

7. The display device according to claim 4, wherein, The third portion is superimposed on the first source / drain electrode in the thickness direction of the substrate, and is not superimposed on the first electric field line in the thickness direction of the substrate.

8. The display device according to claim 4, wherein, The third part is not disposed between the first source / drain electrode and the first electric field line in the thickness direction of the substrate.

9. The display device according to claim 1, further comprising a first insulating layer disposed on the third conductive layer, wherein, The first insulating layer completely overlaps with the connection pattern, and The light-emitting element is disposed on the first insulating layer.

10. The display device according to claim 9, further comprising: A first contact electrode is disposed on the first insulating layer and electrically contacts the first end of the light-emitting element and the first electrode; as well as The second contact electrode is disposed on the first insulating layer and makes electrical contact with the second end of the light-emitting element and the second electrode.

11. The display device according to claim 1, wherein, The first electrode is electrically connected to the second source / drain electrode of the transistor through a second contact hole that penetrates the via layer and the passivation layer.

12. The display device according to claim 1, wherein, The connection pattern electrically contacts at least a portion of the upper surface of the first source / drain electrode of the transistor, at least a portion of the upper surface of the first electric field line, and the side surface of the first electric field line.

13. The display device according to claim 1, wherein, The passivation layer is disposed between the first conductive layer and the second conductive layer in the thickness direction of the substrate.

Images