Fast converging high precision successive approximation analog-to-digital converter digital correction circuit and method

Abstract

The application discloses a fast-converging high-precision successive approximation analog-to-digital converter digital correction circuit and method, comprising a first capacitor array unit, a second capacitor array unit, a comparator unit and a SAR control logic module, and the output end of the comparator unit is respectively connected with the SAR control logic module and a digital calibration engine; the application extracts mismatch errors by sequentially performing a bypass operation on the first capacitor array unit, and obtains a weight coefficient through an algorithm to achieve the calibration purpose. The application can be widely applied to high-precision SAR and pipelined SAR ADC, has a wide application scenario, high practicability, fast calibration speed, relatively simple analog part configuration, does not increase additional coefficients, can use a background calibration algorithm, and is irrelevant to an input signal and does not depend on the input signal.

Description

Technical Field

[0001] This invention relates to the field of encoding technology, and more particularly to the field of high-precision analog-to-digital converter (ADC) correction technology, specifically to a fast-converging, high-precision successive asymptotic ADC digital correction circuit and method. Background Technology

[0002] High-precision analog-to-digital converters (ADCs) are essential components in numerous control, monitoring, sensing, and signal acquisition applications. Currently, there are two main circuit architectures for implementing high-precision ADCs: oversampling delta-Sigma ADCs and successive asymptotic (SAR) (including pipelined successive asymptotic-SAR) ADCs. In principle, Delta-Sigma ADCs utilize oversampling and noise-shaping techniques to reduce circuit noise and quantization noise within the signal bandwidth. Out-of-band noise can then be filtered out by a subsequent digital decimation filter. The narrowband output data after downsampling by the digital filter provides a high signal-to-noise ratio (SNR). Furthermore, delta-Sigma ADCs can leverage the characteristics of oversampling to use single-bit or low-bit digital-to-analog converters (DACs), supplemented by mismatch shaping techniques, to achieve good static performance. For example, some delta-Sigma products can achieve a SNR of 110dB and a static linearity close to 24 bits. However, this architecture typically suffers from two problems: firstly, due to oversampling, its signal bandwidth is relatively small compared to Nyquist ADCs; secondly, due to the digital decimation filter, its latency is slightly larger. These two drawbacks prevent this type of ADC from meeting the needs of some low-latency and / or medium-to-high bandwidth applications. In addition, the memory effect of its internal integrator also prevents this type of ADC from being multiplexed.

[0003] To address the above issues, the successive asymptotic ADC, due to the characteristics of the Nyquist algorithm, allows for medium to high bandwidth, covering sampling rates from hundreds of kS / s to tens of MS / s. Without considering input buffers and reference bases, the charge-redistribution SAR ADC mainly consists of switches, capacitors, digital control logic, and dynamic comparators. The highly digitized circuit design offers advantages such as high energy efficiency, small area, and process scalability. Furthermore, its signal processing path has fewer or no active amplifiers, avoiding the introduction of high-order harmonics due to gain nonlinearity and incomplete setup of active amplifiers. Its weighting error is mainly a first-order capacitor mismatch error, which is less difficult to correct digitally compared to other higher-order errors. Therefore, many high-precision products, such as 16, 18, 20, and 22-bit ADCs, also adopt the SAR / Pipelined SAR architecture. This architecture can cover sampling rates from hundreds of kS / s to tens of MS / s, a range that is difficult for oversampling delta-sigma ADCs of the same precision to achieve. Summary of the Invention

[0004] The purpose of this invention is to provide a novel, fast-converging, high-precision successive asymptotic analog-to-digital converter (ADC) digital correction circuit and method. Based on the overall inventive concept of this invention, it can be widely applied to high-precision SAR and PipelinedSAR ADCs. To enable those skilled in the art to fully understand this invention and the significant technical effects that can be obtained through its implementation, the applicant first briefly describes existing alternatives.

[0005] The accuracy of traditional SAR and Pipelined SAR ADCs is mainly limited by the accuracy of capacitor matching and gain error (Pipelined-SAR). Without calibration, the effective accuracy is generally below 10 to 12 bits. To achieve higher accuracy and linearity, multiple bit weights need to be corrected using digital calibration algorithms so that the ADC output accurately corresponds to the analog input. Technically, high-precision SAR / Pipelined SAR ADC digital calibration faces the following challenges: 1) Calibration accuracy: general calibration algorithms struggle to achieve high SNDR and SFDR; 2) High complexity of calibration algorithms, resulting in large power consumption and area requirements; 3) Slow convergence speed of calibration algorithms; 4) Dependence of calibration algorithms on the input signal: generally, a significant perturbation is required at the input to complete weight iteration and convergence.

[0006] Currently, there are several calibration methods for high-precision SAR and Pipelined-SAR ADCs.

[0007] The first type is factory adjustment:

[0008] During the automated product testing phase, the ADC input is connected to a fixed voltage level. With the input known, the weight of each bit can be tested sequentially, and then the digital weights are written into non-volatile storage, allowing for digital adjustment of the weight coefficients. Alternatively, analog correction can be performed using devices such as fuses. This correction method is a one-time correction, requiring no further calibration after the product leaves the factory. However, this method has the following drawbacks: a) it requires interrupting the normal operation of the ADC; b) it increases testing costs; and c) it cannot track changes in the weight coefficients caused by factors such as temperature drift and aging.

[0009] The second method is background calibration:

[0010] There are several main types of background calibration for high-precision SAR ADCs, such as split-path and double-conversion calibration. Split-path technology breaks down an ADC into two sub-ADCs, keeping the total value of the two sampling capacitors unchanged, and maintaining the original circuit noise. The separable portion adds virtually no increase to its area or power consumption. Because the codewords of the two sub-ADCs are added together, the signal-to-noise ratio increases by 3dB. Since the input signals of the two sub-ADCs are equal, if neither sub-ADC experiences code loss, and the weights are accurate, the actual outputs of the two ADCs will always be nearly equal, with the error within the quantization error range. In this calibration method, the two sub-ADCs can serve as mutual references. Under their respective existing weight coefficients, the difference in their outputs represents their deviation from the ideal value. Based on this deviation, an adaptive calibration algorithm, such as the Least Mean Square algorithm, can iteratively calibrate the weight coefficients of the two ADCs. Unlike front-end calibration, this calibration method can calibrate the ADC performance in real time without affecting the operating status of the two sub-ADCs. This calibration method still has some dependence on the input signal. For example, when the input signal is always a DC signal, the degree of codeword traversal on both sides is insufficient, and some weights of the two sub-ADCs highly overlap, resulting in a lack of mismatch information regarding relevant capacitors in the error function. Therefore, in this case, the calibration algorithm cannot converge. To address this issue, some products employ architectures such as double conversion, where a single sample is performed, the same ADC is converted twice, and the difference is compared. The CDAC combination is reconstructed by injecting a known perturbation and randomly shuffling capacitors, allowing the ADC to quantize twice. Because the size of the injected perturbation (mainly to ensure sufficient traversal of the DAC's flip codewords) and the order of capacitor shuffling are preset and known, the error structure of the two conversion processes can be known. Therefore, this method can achieve iterative convergence of weights without relying on the input signal. However, the logic for generating random perturbations in this method is complex, resulting in numerous calibration coefficients. The calibration algorithm needs to accurately know which capacitors were used in each flip to iterate different capacitor weight coefficients accordingly, leading to significant power and area overhead in the correction. Furthermore, the two conversions must maintain a consistent surrounding environment, such as a reference source, to prevent convergence errors caused by environmental changes over time.

[0011] Furthermore, as one of the existing technologies, a Chinese patent discloses a background calibration method for capacitor mismatch and interstage gain error in a piperined SAR ADC, with publication number CN110971235A. This method discloses a correction method based on PN code correlation to simultaneously correct capacitor mismatch and interstage operational amplifier gain error. Not only can it not extract and calculate capacitor mismatch weights separately, but more importantly, it is very slow in convergence during iterative calculations, especially for high-bit (e.g., 20-bit) operations. The time required to achieve convergence according to this scheme will be several hours to tens of hours, or even hundreds of hours. This is unacceptable for high-precision design applications and also loses its practical significance for high-precision, fast-response applications.

[0012] Therefore, addressing the varying degrees and aspects of shortcomings in existing correction methods, and aiming to achieve rapid calibration results while remaining independent of input signal fluctuations, while also considering low power consumption and small area, this invention proposes a method based on resetting the capacitor array after SAR ADC quantization and performing sequential / random bypass operations. Error information is obtained by reversing the non-bypass related capacitors, and the digital correction algorithm is iterated to converge the magnitude of the related capacitor weights, thereby achieving accurate and rapid correction. This completes the invention.

[0013] Specifically, the fast-converging high-precision successive asymptotic analog-to-digital converter digital correction circuit provided by the present invention includes a first capacitor array unit, a second capacitor array unit, a comparator unit, and a SAR control logic module. The SAR control logic module is connected to the first switch array unit and the second switch array unit respectively. The first switch array unit selectively connects the first capacitor array unit to Vrefp, common-mode VCM, and Vrefn. The second switch array unit selectively connects the second capacitor array unit to Vrefp, common-mode VCM, and Vrefn.

[0014] The positive / negative input terminals of the comparator unit are connected to the output terminals of the first capacitor array unit / second capacitor array unit for comparison with the common-mode VCM and outputting the corresponding target digital codeword. The output terminals of the comparator unit are respectively connected to the SAR control logic module and a digital calibration engine for acquiring the error voltages of the first capacitor array unit and / or the second capacitor array unit and outputting the corresponding first error weight and second error weight.

[0015] The input signal Vin is connected to the input terminal of the first capacitor array unit via switch Clks, and the common-mode VCM is connected to the input terminal via switch Reset.

[0016] The present invention can adopt different specific designs depending on different application scenarios. For example, for a high-precision SAR ADC, the comparator unit only includes a first comparator, the first capacitor array unit and the second capacitor array unit are connected in parallel, the output terminal of the second capacitor array unit is connected to the positive / negative input terminal of the comparator, and the other input terminal of the comparator is connected to the common-mode VCM.

[0017] As another application scenario of the present invention, for the Pipelined SAR ADC, the comparator unit will further include a second comparator on the basis of the above-mentioned SAR ADC. Correspondingly, the SAR control logic module is also composed of a first SAR control logic module for controlling the first switch array unit and a second SAR control logic module for controlling the second switch array unit. Furthermore, an amplifier unit for amplifying the output voltage of the first capacitor array unit is provided between the first capacitor array unit and the second capacitor array unit.

[0018] Furthermore, in order to amplify the residual voltage of the first capacitor array unit after sampling-quantization and the error voltage generated by the subsequent bypass operation, preferably, the amplifier unit includes a switch Clka at the input end and a switch Clks2 at the output end, as well as an amplifier Amp, a feedback capacitor Cfb, and a switch Clkb connected in parallel.

[0019] Based on the above-described digital correction circuit, the present invention also provides a digital correction method, which is implemented by employing the above-described fast-converging high-precision successive asymptotic analog-to-digital converter digital correction circuit. In particular, as one application scenario of the present invention, when used in a high-precision SAR ADC, the method specifically includes the following steps:

[0020] Step STP100: Input signal Vin is input to the first capacitor array unit through switch Clks, and sampling is completed by disconnecting switch Clks;

[0021] Step STP200: The SAR control logic module receives the result from the comparator unit output and controls the flipping of the first switch array unit to complete the conversion and quantization of the input signal Vin, thereby obtaining the target quantized codeword.

[0022] Step STP300: Close switch Reset, and simultaneously connect all units of the first switch array to common-mode VCM via the SAR control logic module, so that all unit capacitors C of the first capacitor array unit... N Both the upper and lower plates are connected to the common-mode VCM, and then the switch Reset is disconnected;

[0023] Step STP400: Perform bypass operations according to the sequence indicated by the SAR control logic module. Simultaneously, quantize the error voltage Verror generated by each bypass operation using the second capacitor array unit to obtain the error codeword, and send it to the digital calibration engine for calibration to obtain the capacitance C of each unit. N weighting coefficient w N ;

[0024] The error voltage Verror is calculated as follows:

[0025]

[0026] Among them, w (k) The normalized weights are k bits, where k is the highest bit of the non-bypass capacitor, and k+1 to N are the number of bits for inverted flipping.

[0027] The weighting coefficient w N The calculation method is as follows:

[0028] After performing the bypass operation N times, the following normalized triangular matrix is ​​established:

[0029]

[0030] The weight coefficients w are obtained by solving the above triangular matrix. N Where N is the number of bits in the first capacitor array unit;

[0031] Step STP500: Repeat step STP400 periodically until the preset number of iterations P is reached, then execute the subsequent action, where P≥1;

[0032] Step STP600 uses the target quantized codeword obtained in step STP200 and the weighting coefficient w obtained in step STP400. N Multiplying them together yields the corrected target quantized codeword.

[0033] It is worth noting that if the above calibration method is continuously cycled, a periodic problem will arise. Specifically, one cycle is completed every N+1 intervals. Due to the periodic operation of the capacitor array and digital circuitry (specifically referring to all circuit units used in the cycle), periodic disturbances will occur in the power supply and reference voltage, potentially producing periodic glitches in the ADC's output codeword. To avoid this problem, specifically, the capacitor C of the current bit unit performing the bypass operation in step STP400 is... NThe execution method has been changed from sequential execution to random execution; the random execution method is controlled by the addition of the PRBS module to generate 2-bit pseudo-random numbers. The pseudo-random numbers are composed of 11, 00 and 10 / 01, which correspond to the three states +1, 0 and -1 respectively.

[0034] In this method, +1 indicates that the bypass bit moves one position to the right, 0 indicates that the bypass bit remains unchanged, and -1 indicates that the bypass bit moves one position to the left. This random walk of the bypass bits eliminates the definite periodicity of the calibration sequence, resulting in a cleaner output signal spectrum and reduced interference with the digital calibration algorithm.

[0035] For Pipelined SAR ADC, the digital correction method provided by this invention has the following correction process: Step STP100, input signal Vin is input to the first capacitor array unit through switch Clks, and sampling is completed by disconnecting switch Clks;

[0036] Step STP200: The first SAR control logic module receives the result from the output of the first comparator unit and controls the flipping of the first switch array unit to complete the conversion and quantization of the input signal Vin, thereby obtaining the first target quantized codeword.

[0037] After closing switch Clka and the amplifier unit is ready, close switch Clks2 and the second capacitor array unit starts sampling. The residual voltage on the first capacitor array unit is amplified by the amplifier unit and then input into the second capacitor array unit for quantization. The quantization process includes receiving the result from the output of the second comparator unit through the second SAR control logic module and controlling the flipping of the second switch array unit to complete the conversion and quantization of the amplified residual voltage to obtain the second target quantization codeword.

[0038] Step STP300: Close switch Reset, and simultaneously connect all units of the first switch array to common-mode VCM via the first SAR control logic module, so that all unit capacitors C of the first capacitor array unit... N Both the upper and lower plates are connected to the common-mode VCM, and then the switch Reset is disconnected;

[0039] Step STP400: According to the instructions of the first SAR control logic module, bypass operations are sequentially performed on the first capacitor array unit. The error voltage Verror generated by each bypass operation of the first capacitor array unit is amplified by the amplifier unit, and then the error voltage Verror generated by each bypass operation is quantized by the second capacitor array unit to obtain the error codeword, which is then sent to the digital calibration engine for calibration to obtain the capacitance C of each unit. N weighting coefficient w NThe quantization of the error voltage Verror is achieved by the second SAR control logic module controlling the toggling of the second switch array unit based on the output of the second comparator; the error voltage Verror is calculated as follows:

[0040]

[0041] Among them, w (k) The normalized weights are k bits, where k is the highest bit of the non-bypass capacitor, and k+1 to N are the number of bits for inverted flipping.

[0042] The weighting coefficient w N The calculation method is as follows:

[0043] After performing the bypass operation N times, the following normalized triangular matrix is ​​established:

[0044]

[0045] The weighting coefficient w of the first capacitor array unit is obtained by solving the above triangular matrix. N Where N is the number of bits in the first capacitor array unit;

[0046] Step STP500: Perform a bypass operation on the (N+X)th bit of the second capacitor array cell in the manner described in step STP400 to obtain the weight coefficient w of the second capacitor array cell. N+X Where X ≤ M-2;

[0047] Step STP600: Repeat steps STP400-STP500 periodically until the preset number of iterations P is reached, then execute the subsequent action, where P≥1;

[0048] Step STP700 involves combining the first target quantized codeword obtained in step STP200 with the weighting coefficient w obtained in step STP400. N The product PR1 obtained after multiplication is combined with the second target quantized codeword obtained in step STP200 and the weighting coefficient w obtained in step STP500. N+X The sum of the products PR2 is the target quantized codeword.

[0049] Similarly, to solve the periodic glitches problem, preferably, the current bit cell capacitor C that performs the bypass operation in step STP400 can be... NThe execution mode has been changed from sequential execution to random execution. The random execution mode is controlled by the addition of the PRBS module to generate a 2-bit pseudo-random number. The pseudo-random number consists of 11, 00 and 10 / 01, which correspond to three states: +1, 0 and -1, respectively. Among them, +1 means that the bypass bit moves one position to the right, 0 means that the bypass bit remains unchanged, and -1 means that the bypass bit moves one position to the left.

[0050] Beneficial effects:

[0051] A. This invention can be widely applied to high-precision SAR and Pipelined SAR ADCs, with a wide range of applications and high practicality.

[0052] B. Fast calibration speed.

[0053] C. The simulation configuration is relatively simple, does not require additional coefficients, and can use background calibration algorithms.

[0054] D. The input signals are uncorrelated and do not depend on the input signals. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is the circuit schematic diagram of the present invention applied to a high-precision SAR ADC.

[0057] Figure 2 yes Figure 1 This is a schematic diagram of one type of working sequence diagram.

[0058] Figure 3 yes Figure 1 Another working sequence diagram is shown.

[0059] Figure 4 yes Figure 1 The circuit schematic for an application scenario where there is no capacitor for the bypass state.

[0060] Figure 5 Is Figure 4 Based on this, the schematic diagram of the state circuit where the first capacitor is bypassed is shown.

[0061] Figure 6 Is Figure 4 Based on this, the schematic diagram of the state circuit for bypassing the second capacitor is shown.

[0062] Figure 7 This is a schematic diagram of the bypassing of the cell capacitors in the first capacitor array unit, where the number of bits for the capacitor is shown to be 8.

[0063] Figure 8 It is Figure 7 The diagram shows the loop after replacing the sequential bypass with a random bypass, where the capacitor bit width is shown to be 8 bits.

[0064] Figure 9 This is the circuit schematic diagram of the present invention applied to a high-precision Pipelined SAR ADC.

[0065] Figure 10 yes Figure 9 The timing diagram corresponding to the circuit. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0067] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0068] Example 1:

[0069] This invention can employ different specific designs under the same inventive concept depending on different application scenarios. This embodiment is specifically described using a high-precision SAR ADC, in conjunction with the appendix to the specification. Figures 1-7 As shown, the fast-converging high-precision successive asymptotic analog-to-digital converter digital correction circuit provided by the present invention includes a first capacitor array unit, a second capacitor array unit, a comparator unit, and a SAR control logic module. The SAR control logic module is connected to the first switch array unit and the second switch array unit respectively. The first switch array unit selectively connects one of the first capacitor array units to Vrefp, common-mode VCM, and Vrefn. The second switch array unit selectively connects one of the second capacitor array units to Vrefp, common-mode VCM, and Vrefn.

[0070] The negative input terminal of the comparator unit is connected to the output terminal of the second capacitor array unit, and is compared with the common-mode VCM to output the corresponding target digital codeword. The output terminal of the comparator unit is respectively connected to the SAR control logic module and the digital calibration engine for acquiring the error voltage of the first capacitor array unit and outputting the corresponding first error weight, and respectively connected to the input signal Vin through switch Clks and to the common-mode VCM through switch Reset.

[0071] Working principle:

[0072] First, refer to the instruction manual appendix. Figure 1 As shown, the ADC samples under the control of switch Clks (Sampling phase). The SAR control logic module receives the result from the comparator unit output and controls the switching of the first switch array unit to complete the conversion and quantization of the input signal Vin, obtaining the target quantized codeword (Conversion phase). Then, switch Reset is closed, and simultaneously, the SAR control logic module connects all units of the first switch array unit to the common-mode VCM, so that the first capacitor array unit (including unit capacitors C1-C...)... N All unit capacitors C) N Both the upper and lower plates are connected to a common-mode VCM. The goal of this operation is to reset the first capacitor array unit. At this time, V... CDAC =VCM, this reset condition is equivalent to inputting a common-mode signal and then disconnecting the Reset switch. The bypass operation is executed according to the sequence indicated by the SAR control logic module; see appendix for details. Figures 4-7 As shown, during the above bypass operation, if no bit needs to be bypassed during the operation of the first capacitor array unit, then C1 is connected to Vrefp, and C2 is connected to C... N Connect to Vrefn, and then use C. r1 To C rM The second capacitor array unit (containing unit capacitor C) N+1 -C N+M Quantizing the Verror voltage yields the error codeword for the first bypass, such as... Figure 4 As shown. Similarly, when the first bit needs to be bypassed, C1 is connected to VCM, C2 is connected to Vrefp, and C3 is connected to C... N Connect to Vrefn, and then use C. N+1 To C N+M The second capacitor array unit quantizes the Verror voltage to obtain the error codeword for the second bypass, such as... Figure 5 As shown. Furthermore, when the second bit needs to be bypassed, C1 and C2 are both connected to VCM, C3 is connected to Vrefp, and C4 is connected to C...N Connect to Vrefn, and then use C. r1 To C rM The second capacitor array unit quantizes the Verror voltage to obtain the error codeword for the third bypass, such as... Figure 6 As shown, this process continues until the bypass operation is complete. Simultaneously, the error voltage Verror (Error Extraction Phase) generated by each bypass operation is quantized using the second capacitor array unit to obtain the error codeword, which is then sent to the digital calibration engine (using the LMS algorithm in this embodiment) for calibration to obtain the capacitance C of each unit. N weighting coefficient w N By obtaining the target quantized codeword and its corresponding weight coefficient w N The product of the two is used to obtain the corrected target quantized codeword, thus completing the correction.

[0073] It is worth noting that: C N+1 To C N+M As long as the coverage error range is met, a smaller codeword range results in a smaller error, which can be used to correct the coefficients. It's worth noting that, to further pursue high precision, the actual algorithm implementation can also include C... N+1 To C N+M The weights are partially converged, and in each bypass quantization process, the digital calibration engine will include C in the quantization process. N+1 To C N+M The error itself is included, and the error generated by the bypass of the first capacitor array unit is large enough that, according to algorithm verification, it does not affect the convergence of the algorithm. However, it is important to note that when setting the second capacitor array unit, the error caused by the capacitor mismatch of the first capacitor array unit must be within a controllable range to avoid code loss. To avoid this, C1 to C... N+M Several redundant bit capacitors are inserted in the capacitor array to ensure that no code loss occurs under a certain mismatch ratio, that is, the residual voltage on the capacitor array is greater than 1 LSB.

[0074] Example 2:

[0075] This invention also provides a digital correction method, implemented by employing the fast-converging, high-precision successive asymptotic analog-to-digital converter digital correction circuit described in Example 1. Specifically, as one application scenario of this invention, when used in a high-precision SAR ADC, it is combined with... Figure 1 As shown, the specific steps include:

[0076] Step STP100: Input signal Vin is input to the first capacitor array unit (including unit capacitors C1-C) via switch Clks.N Disconnect switch Clks to complete sampling;

[0077] Step STP200: The SAR control logic module receives the result from the comparator unit output and controls the flipping of the first switch array unit to complete the conversion and quantization of the input signal Vin, thereby obtaining the target quantized codeword.

[0078] Step STP300: Close switch Reset, and simultaneously connect all units of the first switch array to common-mode VCM via the SAR control logic module, so that all unit capacitors C of the first capacitor array unit... N Both the upper and lower plates are connected to the common-mode VCM, and then the switch Reset is disconnected;

[0079] Step STP400: Perform the bypass operation according to the sequence indicated by the SAR control logic module. Simultaneously, through the second capacitor array unit (containing unit capacitor C)... N+1 -C N+M The error voltage Verror generated by each bypass operation is quantized to obtain the error codeword, which is then sent to the digital calibration engine for calibration to obtain the capacitance C of each unit. N weighting coefficient w N ;

[0080] The error voltage Verror is calculated as follows:

[0081]

[0082] Among them, w (k) The normalized weights are k bits, where k is the highest bit of the non-bypass capacitor, and k+1 to N are the number of bits for inverted flipping.

[0083] The weighting coefficient w N The calculation method is as follows:

[0084] After performing the bypass operation N times, the following normalized triangular matrix is ​​established:

[0085]

[0086] The weight coefficients w are obtained by solving the above triangular matrix. N Where N is the number of bits in the first capacitor array unit;

[0087] Step STP500: Repeat step STP400 periodically until the preset number of iterations P is reached, then execute the subsequent action, where P≥1;

[0088] Step STP600 uses the target quantized codeword obtained in step STP200 and the weighting coefficient w obtained in step STP400.N Multiplying them together yields the corrected target quantized codeword.

[0089] It is worth noting that the timing of the convergence process may vary depending on the input signal Vin. Figure 2 and Figure 3 Two typical convergence processes are shown respectively.

[0090] Example 3:

[0091] This embodiment is a further optimization based on Embodiment 2. As mentioned above, although the calibration method of Embodiment 2 can achieve fast convergence through continuous cyclic verification, there is still room for improvement in terms of high accuracy. Therefore, the periodic iteration will cause periodic problems. Specifically, one cycle is completed every N+1 intervals. Due to the periodic operation of the capacitor array and digital circuit (specifically referring to all circuit units used in the cycle), periodic disturbances will be generated on the power supply and reference voltage, which may produce periodic glitches in the output codeword of the ADC. In order to avoid this problem, specifically, based on Embodiment 2, in order to avoid the glitches caused by periodic iteration, the method described in Embodiment 2 is optimized as follows: the current bit unit capacitor C in step STP400 where the bypass operation is performed is... N The execution method has been changed from sequential to random execution. This random execution is controlled by a newly added PRBS module that generates a 2-bit pseudo-random number. This pseudo-random number consists of 11, 00, and 10 / 01, representing three states: +1, 0, and -1, respectively. +1 indicates the bypass bit moves one position to the right, 0 indicates the bypass bit remains unchanged, and -1 indicates the bypass bit moves one position to the left. The random movement of the bypass bit in this method is as follows: Figure 8 As shown, this can make the calibration sequence no longer have a clear periodicity, resulting in a cleaner output signal spectrum and reduced interference to the digital calibration algorithm.

[0092] Example 4:

[0093] This embodiment illustrates another application scenario of the present invention, specifically for Pipelined SAR ADCs. Compared to high-precision SAR, Pipelined SAR ADCs have a relatively higher structural complexity. Specifically, this embodiment further optimizes and improves upon Embodiment 1, as detailed in the appendix to the specification. Figure 9As shown, the comparator unit will also include a second comparator based on the above-mentioned SAR ADC. Correspondingly, the SAR control logic module is also composed of a first SAR control logic module for controlling the first switch array unit and a second SAR control logic module for controlling the second switch array unit. Furthermore, an amplifier unit for amplifying the output voltage of the first capacitor array unit is provided between the first capacitor array unit and the second capacitor array unit.

[0094] In this embodiment, to amplify the residual voltage of the first capacitor array unit after sampling-quantization and the error voltage generated by the subsequent bypass operation, the amplifier unit preferably includes a switch Clka at the input terminal and a switch Clks2 at the output terminal, as well as an amplifier Amp, a feedback capacitor Cfb, and a switch Clkb connected in parallel. Here, the amplifier gain is calculated based on the gain of the first capacitor array unit (including unit capacitors C1-C...). N The sum of the capacitances is divided by the feedback capacitance Cfb. The improved working principle and process of this embodiment are detailed in Embodiment 5 and will not be repeated here.

[0095] Example 5:

[0096] This embodiment uses a Pipelined SAR ADC as an example to illustrate the digital correction method provided by this invention in detail. See below for more information. Figure 9 and Figure 10 As shown, the specific correction process is as follows: Step STP100, input signal Vin is input to the first capacitor array unit through switch Clks1 (the switch Clks1 here is only to distinguish it from the sampling switch in other embodiments and has no other special meaning), and switch Clks is turned off to complete sampling;

[0097] Step STP200: The first SAR control logic module receives the result from the output of the first comparator unit and controls the flipping of the first switch array unit to complete the conversion and quantization of the input signal Vin, thereby obtaining the first target quantized codeword.

[0098] After closing switch Clka and the amplifier unit is ready to start, close switch Clks2 and the second capacitor array unit begins sampling. The residual voltage on the first capacitor array unit is amplified by the amplifier unit and then input to the second capacitor array unit (including the unit capacitor C). N+1 -C N+M The quantization process includes receiving the result from the output of the second comparator unit through the second SAR control logic module, controlling the flipping of the second switch array unit to complete the conversion and quantization of the amplified residual voltage, and obtaining the second target quantized codeword.

[0099] Step STP300: Close switch Reset, and simultaneously connect all units of the first switch array to common-mode VCM via the first SAR control logic module, so that all unit capacitors C of the first capacitor array unit... N Both the upper and lower plates are connected to the common-mode VCM, and then the switch Reset is disconnected;

[0100] Step STP400: According to the instructions of the first SAR control logic module, bypass operations are sequentially performed on the first capacitor array unit. The error voltage Verror generated by each bypass operation of the first capacitor array unit is amplified by the amplifier unit, and then the error voltage Verror generated by each bypass operation is quantized by the second capacitor array unit to obtain the error codeword, which is then sent to the digital calibration engine for calibration to obtain the capacitance C of each unit. N weighting coefficient w N The quantization of the error voltage Verror is achieved by the second SAR control logic module controlling the toggling of the second switch array unit based on the output of the second comparator; the error voltage Verror is calculated as follows:

[0101]

[0102] Among them, w (k) The normalized weights are k bits, where k is the highest bit of the non-bypass capacitor, and k+1 to N are the number of bits for inverted flipping.

[0103] The weighting coefficient w N The calculation method is as follows:

[0104] After performing the bypass operation N times, the following normalized triangular matrix is ​​established:

[0105]

[0106] The weighting coefficient w of the first capacitor array unit is obtained by solving the above triangular matrix. N Where N is the number of bits in the first capacitor array unit;

[0107] Step STP500: Perform a bypass operation on the (N+X)th bit of the second capacitor array cell in the manner described in step STP400 to obtain the weight coefficient w of the second capacitor array cell. N+X Where X ≤ M-2;

[0108] In this step, the high-order capacitors are used as bypass capacitors, and the low-order capacitors are used as quantization capacitors, but the minimum number of bits for the quantization capacitor is no less than two. For example, if M=2, it means that the second capacitor array unit has a total of two capacitors, and the number of bits for the bypass capacitor is 0; if M=8, it means that the second capacitor array unit has a total of eight capacitors, and the number of bits allowed for the bypass operation is 1-6 bits, such as 3, 4, 5, or 6 bits. The specific number of bits executed can be determined according to the actual size of the capacitors and the size of the mismatch error. However, in any case, the total mismatch error of all capacitors in the second capacitor array unit is very small compared to the capacitor mismatch weight in the first capacitor array unit. Theoretically, the bypass operation of the second capacitor array unit will be affected by the weight coefficient, but in practice, since the second capacitor array unit is mainly used to quantize the first capacitor array unit, its own mismatch error is very small. When the number of bits in the second capacitor array unit is in the digital range, in practice, a separate bypass operation is not necessary. It is worth noting that whether the second capacitor array unit described here performs a bypass operation is based on the actual situation and should not be construed as limiting the accuracy pursued or achievable by the present invention. Rather, it is that those skilled in the art can make flexible settings under the specific execution architecture and method of bypass fully disclosed in the present invention, and there are multiple choices in actual situations to achieve multi-faceted compatibility and better matching for specific application scenarios. It should not be construed as ignoring the mismatch error of the low-order quantization capacitor itself in the solution of the present invention.

[0109] Step STP600 involves periodically repeating steps STP400-STP500 until a preset number of iterations P is reached, at which point subsequent actions are performed, where P ≥ 1. The value of P can be determined by those skilled in the art in conjunction with the actual unit capacitance C. N The error, application scenario, and actual convergence efficiency determine the weighting coefficient w obtained. The larger the P-value, the greater the weighting coefficient w obtained. N+X The closer the weight coefficient w is to the true value, the better it will approximate the actual value. N+X When the P-value no longer effectively approximates the true value with increasing P-value, the critical P-value is considered to be the optimal value. In practical applications, under the guidance of this invention, those skilled in the art should weigh the actual weighting coefficient w when determining the P-value. N+X A trade-off is made between the time spent on convergence and the actual application of the invention. Of course, this only affects whether the application effect of a specific case achieves the best efficiency and accuracy, and does not affect the essence of the invention concept.

[0110] Step STP700 involves combining the first target quantized codeword obtained in step STP200 with the weighting coefficient w obtained in step STP400. NThe product PR1 obtained after multiplication is combined with the second target quantized codeword obtained in step STP200 and the weighting coefficient w obtained in step STP500. N+X The sum of the products PR2 is the target quantized codeword.

[0111] Similarly, to solve the periodic glitches problem, preferably, the current bit cell capacitor C that performs the bypass operation in step STP400 can be... N The execution method is changed from sequential execution to random execution. The random execution method is controlled by a newly added PRBS module that generates a 2-bit pseudo-random number. This pseudo-random number consists of 11, 00, and 10 / 01, representing three states: +1, 0, and -1, respectively. +1 indicates the bypass bit shifts one position to the right, 0 indicates the bypass bit remains unchanged, and -1 indicates the bypass bit shifts one position to the left. The beneficial effects of this part are the same as those produced in the corresponding part of Embodiment 3, and will not be repeated here.

[0112] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A fast-converging, high-precision successive asymptotic analog-to-digital converter digital correction circuit, characterized in that: It includes a first capacitor array unit, a second capacitor array unit, a comparator unit, and a SAR control logic module. The SAR control logic module is connected to the first switch array unit and the second switch array unit respectively. The first switch array unit selectively connects one of the lower plates of the capacitors of the first capacitor array unit to Vrefp, common-mode VCM, and Vrefn. The second switch array unit selectively connects one of the lower plates of the capacitors of the second capacitor array unit to Vrefp, common-mode VCM, and Vrefn. The negative input terminal of the comparator unit is connected to the upper plate of the second capacitor array unit and / or the first capacitor array unit, and is used to compare the voltage output by the capacitor array unit with the common-mode VCM and output the corresponding target digital codeword; wherein, when the comparator unit contains only one comparator, the negative input terminal of the comparator is connected to the upper plate of the capacitors of the first capacitor array unit and the second capacitor array unit, and the positive input terminal is connected to the common-mode VCM; when the comparator unit contains a first comparator and a second comparator, the negative input terminal of the first comparator is connected to the upper plate of the first capacitor array unit, and the positive input terminal is connected to the common-mode VCM; the negative input terminal of the second comparator is connected to the upper plate of the second capacitor array unit, and the positive input terminal is connected to the common-mode VCM; The output of the comparator unit is connected to the SAR control logic module and the digital calibration engine respectively. The digital calibration engine receives the error codeword obtained by the second capacitor array unit quantizing the error voltage generated by the first capacitor array unit in each bypass operation, and iteratively calculates and outputs the corresponding error weight based on the error codeword using the least mean square algorithm. The bypass operation is a capacitor switching operation performed by the first switch array unit controlled by the SAR control logic module: when no capacitor is performing the bypass operation, the first capacitor is switched to Vrefp, and the second to Nth capacitors are switched to Vrefn; when the kth capacitor is performing the bypass operation, the first to kth capacitors are switched to the common-mode voltage VCM, the (k+1)th capacitor is switched to Vrefp, and the (k+2)th to Nth capacitors are switched to Vrefn, where k is the current bit number performing the bypass operation, k=1,2,…,N; The input signal Vin is connected to the upper plate of the capacitor in the first capacitor array unit via switch Clks, and the common-mode VCM is connected to the upper plate of the capacitor via switch Reset.

2. The fast-converging, high-precision successive asymptotic analog-to-digital converter digital correction circuit according to claim 1, characterized in that: The comparator unit further includes a second comparator, and the SAR control logic module is also composed of a first SAR control logic module for controlling the first switch array unit and a second SAR control logic module for controlling the second switch array unit. An amplifier unit for amplifying the output voltage of the first capacitor array unit is also provided between the first capacitor array unit and the second capacitor array unit.

3. The fast-converging, high-precision successive asymptotic analog-to-digital converter digital correction circuit according to claim 2, characterized in that: The amplifier unit includes a switch Clka at the input end and a switch Clks2 at the output end. The input end of the amplifier Amp is connected to the output end of the first capacitor array unit through switch Clka, and the output end of the amplifier Amp is connected to the input end of the second capacitor array unit through switch Clks2. The feedback capacitor Cfb is connected in parallel between the input end and the output end of the amplifier Amp, and the switch Clkb is connected in parallel across the two ends of the feedback capacitor Cfb.

4. A digital correction method, implemented using a digital correction circuit comprising a fast-converging, high-precision successive asymptotic analog-to-digital converter as described in claim 1, wherein the comparator unit contains only one comparator, characterized in that, Includes the following steps: Step STP100: Input signal Vin is input to the first capacitor array unit through switch Clks, and sampling is completed by disconnecting switch Clks; Step STP200: The SAR control logic module receives the result from the comparator unit output and controls the flipping of the first switch array unit to complete the conversion and quantization of the input signal Vin, thereby obtaining the target quantized codeword. Step STP300: Close switch Reset, and simultaneously connect all units of the first switch array to common-mode VCM via the SAR control logic module, so that all unit capacitors C of the first capacitor array unit... N Both the upper and lower plates are connected to the common-mode VCM, and then the switch Reset is disconnected; Step STP400: Perform bypass operations according to the sequence indicated by the SAR control logic module. Simultaneously, quantize the error voltage Verror generated by each bypass operation using the second capacitor array unit to obtain the error codeword, and send it to the digital calibration engine for calibration to obtain the capacitance C of each unit. N weighting coefficient w N ; The error voltage Verror is calculated as follows: ； Among them, w (k) The normalized weights are k bits, where k is the highest bit of the non-bypass capacitor, and k+1 to N are the number of bits to be flipped in the reverse direction. The weighting coefficient w N The calculation method is as follows: After performing the bypass operation N times, the following normalized triangular matrix is ​​established: ； The weight coefficients w are obtained by solving the above triangular matrix. N Where N is the number of bits in the first capacitor array unit; Step STP500: Repeat step STP400 periodically until the preset number of iterations P is reached, then execute the subsequent action, where P≥1; Step STP600 uses the target quantized codeword obtained in step STP200 and the weighting coefficient w obtained in step STP400. N Multiplying them together yields the corrected target quantized codeword.

5. The digital correction method according to claim 4, characterized in that: The current bit cell capacitor C that performs the bypass operation in step STP400. N The execution method has been changed from sequential execution to random execution; the random execution method is controlled by the addition of the PRBS module to generate 2-bit pseudo-random numbers. The pseudo-random numbers are composed of 11, 00 and 10 / 01, which correspond to the three states +1, 0 and -1 respectively. Here, +1 indicates that the bypass bit moves one position to the right, 0 indicates that the bypass bit remains unchanged, and -1 indicates that the bypass bit moves one position to the left.

6. A digital correction method, implemented using a digital correction circuit comprising a fast-converging, high-precision successive asymptotic analog-to-digital converter as described in claim 3, characterized in that, Includes the following steps: Step STP100: Input signal Vin is input to the first capacitor array unit through switch Clks, and sampling is completed by disconnecting switch Clks; Step STP200: The first SAR control logic module receives the result from the output of the first comparator unit and controls the flipping of the first switch array unit to complete the conversion and quantization of the input signal Vin, thereby obtaining the first target quantized codeword. After closing switch Clka and the amplifier unit is ready, close switch Clks2 and the second capacitor array unit starts sampling. The residual voltage on the first capacitor array unit is amplified by the amplifier unit and then input into the second capacitor array unit for quantization. The quantization process includes receiving the result from the output of the second comparator unit through the second SAR control logic module and controlling the flipping of the second switch array unit to complete the conversion and quantization of the amplified residual voltage to obtain the second target quantization codeword. Step STP300: Close switch Reset, and simultaneously connect all units of the first switch array to common-mode VCM via the first SAR control logic module, so that all unit capacitors C of the first capacitor array unit... N Both the upper and lower plates are connected to the common-mode VCM, and then the switch Reset is disconnected; Step STP400: According to the instructions of the first SAR control logic module, bypass operations are sequentially performed on the first capacitor array unit. The error voltage Verror generated by each bypass operation of the first capacitor array unit is amplified by the amplifier unit, and then the error voltage Verror generated by each bypass operation is quantized by the second capacitor array unit to obtain the error codeword, which is then sent to the digital calibration engine for calibration to obtain the capacitance C of each unit. N weighting coefficient w N The quantization of the error voltage Verror is achieved by the second SAR control logic module controlling the toggling of the second switch array unit based on the output of the second comparator; the error voltage Verror is calculated as follows: ； Among them, w (k) The normalized weights are k bits, where k is the highest bit of the non-bypass capacitor, and k+1 to N are the number of bits to be flipped in the reverse direction. The weighting coefficient w N The calculation method is as follows: After performing the bypass operation N times, the following normalized triangular matrix is ​​established: ； The weight coefficients w are obtained by solving the above triangular matrix. N Where N is the number of bits in the first capacitor array unit; Step STP500: Perform a bypass operation on the (N+X)th bit of the second capacitor array cell in the manner described in step STP400 to obtain the weight coefficient w of the second capacitor array cell. N+X Where X ≤ M-2; Step STP600: Repeat steps STP400-STP500 periodically until the preset number of iterations P is reached, then execute the subsequent action, where P≥1; Step STP700 involves combining the first target quantized codeword obtained in step STP200 with the weighting coefficient w obtained in step STP400. N The product PR1 obtained after multiplication is combined with the second target quantized codeword obtained in step STP200 and the weighting coefficient w obtained in step STP500. N+X The sum of the products PR2 is the target quantized codeword.

7. The digital correction method according to claim 6, characterized in that: The execution mode of the current bit cell capacitor CN that performs the bypass operation in step STP400 is changed from sequential execution to random execution. The random execution mode is controlled by the 2-bit pseudo-random number generated by the added PRBS module. The pseudo-random number consists of 11, 00 and 10 / 01, which correspond to three states: +1, 0 and -1, respectively. Among them, +1 means that the bypass bit moves one position to the right, 0 means that the bypass bit remains unchanged, and -1 means that the bypass bit moves one position to the left.

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