Preparation method for improving single particle reinforcement structure of MOSFET with radiation resistance

Abstract

The invention discloses a preparation method for improving the single-particle reinforcement structure of radiation-resistant MOSFET, belonging to the field of MOSFET preparation. A substrate is provided, and an epitaxial layer is formed on the surface thereof; P wells of different depths and widths are made to form an inverted triangle P well; a source terminal and a body contact terminal are made; low-temperature wet oxygen oxidation SiO2 growth is performed; polysilicon is photolithographically and etched to form a polycrystalline gate control terminal. The first point of the inverted triangle P well is to utilize the charge balance principle to reduce the on-resistance; the second point is that in a single-particle radiation environment, the electron-hole pairs generated by the single particle during the movement of the device move under the action of the electric field, wherein the holes flow away from the P well of the base region, and the deep inverted triangle P well is more conducive to hole absorption, thereby achieving a higher VDMOS anti-single-particle capability.

Description

Technical Field

[0001] The invention relates to the technical field of MOSFET preparation, and in particular to a preparation method for improving a single-particle reinforcement structure of a radiation-resistant MOSFET. Background Art

[0002] In addition to meeting conventional electrical parameter requirements, radiation-resistant power MOSFET devices must also have the ability to withstand long-term radiation exposure to various ionizing radiations, high-energy particles, and cosmic rays in space. Therefore, the threshold voltage, drain breakdown voltage, and gate breakdown voltage of power MOSFET devices are all affected by such ionizing radiation. Therefore, devices used in the aerospace field should have the ability to resist TID (Total Ionizing Dose) and SEE (Single Event Effect).

[0003] The radiation hardened process is suitable for the design and manufacture of power MOSFETs for radiation-resistant application environments. For MOSFET devices used in space environments, the single particle effect becomes the main limitation for their use in a large number of heavy ion space environments. The single particle effect mainly includes single particle burnout (SEB) and single particle gate breakdown (SEGR). Single particle burnout refers to the heavy ions passing through the device structure area, epitaxial area and substrate area to generate a large number of electron-hole pairs. Under the action of the electric field, the holes will move to the base area and eventually form a current. When the current density reaches a certain level, the parasitic transistor will be turned on and eventually the device will burn out. Gate breakdown refers to the destructive burning of the conductive path formed in the gate dielectric layer after the heavy ions pass through the gate dielectric layer in the power MOSFET, that is, gate oxide breakdown.

[0004] In the manufacturing process of MOSFET power devices, a substrate material sheet with a lower resistivity is required, and the resistivity and thickness required for epitaxy are performed on the substrate material sheet to manufacture MOSFET power devices. Since MOSFET power devices using commercial conventional gate oxide processes are not reinforced with single particles in irradiated environments, they will burn out or the gate oxide will reversely break down, which cannot meet the radiation resistance requirements of circuit applications. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET, so as to solve the problem that the existing MOSFET power device is prone to single particle burnout in a radiation environment.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a single particle reinforcement structure of a radiation-resistant MOSFET, comprising:

[0007] providing a substrate and forming an epitaxial layer on the surface of the substrate;

[0008] Making P wells of different depths and widths to form an inverted triangle P well;

[0009] Making source terminal and body contact terminal;

[0010] Perform low temperature wet oxygen oxidation SiO2 growth;

[0011] Photolithography and etching of polysilicon are performed to form a polycrystalline gate control terminal.

[0012] Optionally, the substrate is a high-energy, low-resistivity substrate, whose material is silicon or arsenic, and whose resistivity is 0.002-0.004Ω·cm.

[0013] Optionally, the epitaxial layer has a resistivity of 0.3-24Ω·cm and a thickness of 3um-50um.

[0014] Optionally, the P wells with different depths and widths are made by: firstly using small stripe width and high energy injection, secondly using medium stripe width and medium energy injection, and thirdly using large stripe width and low energy injection, including:

[0015] forming a first P-well pattern according to a first P-well mask pattern;

[0016] Injecting P-type impurities and performing high temperature annealing to form a first P well; wherein the P-type impurities include B and BF2, and the injection dose is 1E12-1E13cm -2 , energy is 1000-5000Kev;

[0017] forming a second P-well pattern according to a pattern of the second P-well mask;

[0018] Injecting P-type impurities and performing high temperature annealing to form a second P well; wherein the P-type impurities include B and BF2, and the injection dose is 5E12-1E13cm -2 , energy is 100-500Kev;

[0019] forming a third P-well pattern according to the pattern of the third P-well mask;

[0020] Injecting P-type impurities and performing high temperature annealing to form a third P well; wherein the P-type impurities include B and BF2, and the injection dose is 5E13-1E14cm -2 , energy is 50-80Kev;

[0021] The first P-well, the second P-well and the third P-well form an inverted triangle pattern, wherein the first P-well is at the bottom of the inverted triangle pattern and the third P-well is at the top.

[0022] Optionally, making the source terminal and the body contact terminal includes:

[0023] According to the patterns of the N+ mask and the P+ mask, patterns of the source terminal and the body contact terminal are formed respectively;

[0024] P-type impurities are injected according to the pattern of the P+ mask and high-temperature annealing is performed to form the P+ body contact terminal; the P-type impurities include B and BF2, and the injection dose is 5E14-5E15cm -2 , energy is 50-100Kev;

[0025] N-type impurities are injected according to the pattern of the N+ mask and high-temperature annealing is performed to form the N+ source terminal; N-type impurities include P, As and In, and the injection dose is 5E14-1E16cm -2 , energy is 50-80Kev.

[0026] Optionally, the SiO2 growth temperature is 800°C-1050°C, and the growth thickness is 30nm-1000nm.

[0027] Optionally, after forming the polycrystalline gate control terminal, the method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET further includes:

[0028] The dielectric isolation layer is deposited, the contact hole and metal deposition lithography are completed, and the source terminal, body contact terminal and gate terminal are all connected to form the complete structure of the VDMOS power device.

[0029] Optionally, the P-well is manufactured for more than three times.

[0030] The preparation method of the single-particle reinforcement structure for improving radiation resistance of MOSFET provided by the present invention has the following beneficial effects:

[0031] (1) Carry out phased design and manufacturing of the P-well to achieve an inverted triangle shape of the P-well, which is conducive to the generation of holes in the process of absorbing single particles, reducing the hole current density, and effectively improving the parasitic transistor opening, thereby reducing the occurrence of single particle gate burnout and gate oxide breakdown in the chip;

[0032] (2) The processing technology is simple, no new process is added, it is highly controllable and has strong operability. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic flow chart of a method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET provided by the present invention;

[0034] Figure 2 is a schematic diagram of forming an epitaxial layer on a substrate surface;

[0035] Figure 3 is a schematic diagram of setting a first P-well mask pattern;

[0036] Figure 4 is a schematic diagram of injecting P-type impurities to form a first P well;

[0037] Figure 5 is a schematic diagram of setting a second P-well mask pattern;

[0038] Figure 6 is a schematic diagram of injecting P-type impurities to form a second P-well;

[0039] Figure 7 is a schematic diagram of setting a third P-well mask pattern;

[0040] Figure 8 is a schematic diagram of injecting P-type impurities to form a third P well;

[0041] Fig. 9 It is a schematic diagram for setting the N+ / P+ mask pattern;

[0042] Fig.10 It is a schematic diagram of injecting impurities to form the P+ body contact terminal and the N+ source terminal;

[0043] Fig.11 is a schematic diagram of forming a gate oxide layer and polysilicon;

[0044] Fig.12 It is a schematic diagram of performing photolithography and etching of polysilicon to form a polycrystalline gate control terminal. DETAILED DESCRIPTION

[0045] The following is a further detailed description of a method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0046] The present invention provides a method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET, the process of which is as follows: Figure 1 As shown, the following steps are included:

[0047] Step S11, providing a substrate, and forming an epitaxial layer on the surface thereof;

[0048] Step S12, making a pattern of the first P-well photomask to form a first P-well morphology;

[0049] Step S13, making a second P-well mask pattern to form a second P-well morphology;

[0050] Step S14, making a third P-well mask pattern to form a third P-well morphology;

[0051] Step S15, making a source terminal and a body contact terminal;

[0052] Step S16, performing gate oxide oxidation SiO2 growth;

[0053] Step S17: perform photolithography and etching of polysilicon to form a polycrystalline gate control terminal.

[0054] First, a substrate 1 is provided. The substrate 1 has the characteristics of high energy density and low resistivity. The material of the substrate 1 may be silicon or arsenic. In the first embodiment, a silicon substrate is taken as an example. The resistivity of the substrate is 0.002-0.004 Ω·cm. An epitaxial layer 2 is formed on the surface of the substrate 1. The resistivity of the epitaxial layer 2 is 3-24 Ohm and the thickness is 3um-50um. Figure 2 As shown;

[0055] Perform the first photolithography of the P well according to the device requirements. Figure 3 The figure of setting P well mask 3 is shown;

[0056] The injection dose is 1E12-1E13cm -2 , P-type impurities such as B and BF2 with energy of 1000-5000Kev form the first P well, such as Figure 4 As shown;

[0057] Perform the second photolithography of the P well according to the device requirements. Figure 5 The figure of setting P well mask 4 is shown;

[0058] The injection dose is 5E12-1E13cm -2 , P-type impurities such as B and BF2 with energy of 100-500Kev form a second P well, such as Figure 6 As shown;

[0059] Perform the third photolithography of the P well according to the device requirements. Figure 7 The figure of setting P well mask 5 is shown;

[0060] The injection dose is 5E13-1E14cm -2 , P-type impurities such as B and BF2 with energy of 50-80Kev form a third P well, such as Figure 8 As shown;

[0061] After the implantation is completed, a high temperature annealing treatment is performed to form an inverted triangle P well; the source end and body contact end of the VDMOS device are made inside, and at the same time, it plays a role in withstanding the PN junction voltage with the N-type substrate, such as Figure 8 As shown;

[0062] According to the device requirements, the source terminal and the body contact terminal are photolithographically processed respectively. First, the source terminal and the body contact terminal are patterned according to the pattern of the N+ / P+ mask 6 (including the N+ mask and the P+ mask), such as Fig. 9 As shown;

[0063] like Fig.10 As shown, B, BF2 and other P-type impurities are injected according to the pattern of the P+ mask, and the injection dose is 5E14-5E15cm -2 , the energy is 50-100Kev, and after the implantation is completed, high temperature annealing is performed to form a P+ body contact terminal; according to the pattern of the N+ mask, N-type impurities such as P, As and In are implanted, and the implantation dose is 5E14-1E16cm -2 , the energy is 50-80Kev, and after the implantation is completed, a high temperature annealing treatment is performed to form an N+ source terminal;

[0064] The gate oxide SiO2 is grown at a growth temperature of 800°C-1050°C, and a gate oxide layer 7 with a thickness of 30nm-1000nm is grown. Fig.11 ;

[0065] like Fig.12 , complete the lithography and etching process of polysilicon 8 to form the polycrystalline gate control terminal. In this way, a complete device is basically formed. The dielectric isolation layer is deposited, the contact hole and metal deposition lithography are completed, and the source terminal, body contact terminal and gate terminal are all connected to form the complete structure of the VDMOS power device.

[0066] Through the above main process, the radiation-resistant VDMOS reinforcement process device preparation is formed. Since the P-well of the radiation-resistant VDMOS is processed by three photolithography injection reinforcement processes, the first one uses a small strip width high energy injection, the second one uses a medium strip width medium energy injection, and the third one uses a large strip width low energy injection. The characteristics of the P-well prepared by this strip width and injection method are the key to forming an inverted triangle P-well. The inverted triangle P-well has two advantages. The first point is that it uses the charge balance principle to reduce the on-resistance; the second point is that in a single-particle radiation environment, the electron-hole pairs generated by a single particle during the movement of the device move under the action of the electric field, and the holes flow away from the P-well in the base region. The deep inverted triangle P-well is more conducive to hole absorption, achieving a higher VDMOS single-particle resistance capability.

[0067] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET, characterized in that: include: providing a substrate and forming an epitaxial layer on the surface of the substrate; Making P wells of different depths and widths to form an inverted triangle P well; Making source terminal and body contact terminal; Perform low temperature wet oxygen oxidation SiO2 growth; Performing photolithography and etching of polysilicon to form a polycrystalline gate control terminal; The specific method of making P wells of different depths and widths is as follows: the first time, a small stripe width and high energy injection is used; the second time, a medium stripe width and medium energy injection is used; and the third time, a large stripe width and low energy injection is used, including: forming a first P-well pattern according to a first P-well mask pattern; Injecting P-type impurities and performing high temperature annealing to form a first P well; wherein the P-type impurities include B and BF2, and the injection dose is 1E12-1E13cm -2 , energy is 1000-5000Kev; forming a second P-well pattern according to a pattern of the second P-well mask; Injecting P-type impurities and performing high temperature annealing to form a second P well; wherein the P-type impurities include B and BF2, and the injection dose is 5E12-1E13cm -2 , energy is 100-500Kev; forming a third P-well pattern according to the pattern of the third P-well mask; Injecting P-type impurities and performing high temperature annealing to form a third P well; wherein the P-type impurities include B and BF2, and the injection dose is 5E13-1E14cm -2 , energy is 50-80Kev; The first P-well, the second P-well and the third P-well form an inverted triangle pattern, wherein the first P-well is at the bottom of the inverted triangle pattern and the third P-well is at the top.

2. The method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET according to claim 1, characterized in that: The substrate is a high-energy, low-resistivity substrate made of silicon or arsenic, with a resistivity of 0.002-0.004Ω·cm.

3. The method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET according to claim 1, characterized in that: The resistivity of the epitaxial layer is 0.3-24Ω·cm, and the thickness is 3um-50um.

4. The method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET according to claim 1, characterized in that: Making the source end and the body contact end includes: According to the patterns of the N+ mask and the P+ mask, patterns of the source terminal and the body contact terminal are formed respectively; P-type impurities are injected according to the pattern of the P+ mask and high-temperature annealing is performed to form the P+ body contact terminal; the P-type impurities include B and BF2, and the injection dose is 5E14-5E15cm -2 , energy is 50-100Kev; N-type impurities are injected according to the pattern of the N+ mask and high-temperature annealing is performed to form the N+ source terminal; N-type impurities include P, As and In, and the injection dose is 5E14-1E16cm -2 , energy is 50-80Kev.

5. The method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET according to claim 1, characterized in that: The growth temperature of SiO2 is 800℃-1050℃, and the growth thickness is 30nm-1000nm.

6. The method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET according to claim 1, characterized in that: After forming the polycrystalline gate control terminal, the method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET further comprises: The dielectric isolation layer is deposited, the contact hole and metal deposition lithography are completed, and the source terminal, body contact terminal and gate terminal are all connected to form the complete structure of the VDMOS power device.

7. The method for preparing a single particle reinforcement structure for improving radiation resistance of MOSFET according to any one of claims 1 to 6, characterized in that: The P-well is made no less than twice, and the dose of P-type impurities injected each time becomes larger and larger, and the energy becomes smaller and smaller.

Images