Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises: forming a plurality of support layers on the substrate, the support layers being used to form a plate capacitor structure, the support layers extending along a first direction, and the plurality of support layers being spaced apart in a second direction, the first direction and the second direction intersecting; forming a lower electrode layer, the lower electrode layer covering at least the sidewalls of the support layers; and forming a dielectric layer, the dielectric layer covering the lower electrode layer. According to the technical solution of the present disclosure, the filling aspect ratio of the capacitor is reduced, and the problems of delamination and uneven filling at the bottom of the capacitor are prevented.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is small in size, highly integrated, and consumes little power. At the same time, it is faster than all Read Only Memory (ROM). As the integration level increases and the size of DRAM continues to shrink, the aspect ratio of capacitors is also getting higher and higher. Therefore, it brings greater and greater challenges to capacitor manufacturing methods. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0005] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] Provide a base;

[0007] Multiple support layers are formed on the substrate, the support layers are used to form a parallel plate capacitor structure, the support layers extend along a first direction, and the multiple support layers are spaced apart in a second direction, the first direction and the second direction intersect;

[0008] A lower electrode layer is formed, wherein the lower electrode layer at least covers the sidewall of the support layer;

[0009] A dielectric layer is formed, which covers the lower electrode layer.

[0010] In some exemplary embodiments of this disclosure, forming the lower electrode layer includes:

[0011] A lower electrode material is deposited, the lower electrode material covering the sidewalls of the support layer, the top surface of the support layer, and the substrate between adjacent support layers;

[0012] The lower electrode material covering the top surface of the support layer is removed to form a lower electrode layer with a double-sided capacitor structure.

[0013] In some exemplary embodiments of this disclosure, forming the lower electrode layer further includes:

[0014] A lower electrode material is deposited, the lower electrode material covering the sidewalls of the support layer, the top surface of the support layer, and the substrate between adjacent support layers;

[0015] The lower electrode material covering the substrate and the lower electrode material covering the top surface of the support layer are removed to form a lower electrode layer with a single-sided capacitor structure.

[0016] In some exemplary embodiments of this disclosure, the formation of the dielectric layer includes:

[0017] A first material layer is formed, which covers the lower electrode layer, the top surface of the support layer, and the substrate between adjacent support layers;

[0018] The dielectric layer is formed by at least one layer of the first material.

[0019] In some exemplary embodiments of this disclosure, the material of the first material layer includes at least one dielectric material, which includes one or more of titanium oxide, hafnium oxide, niobium oxide, and indium gallium zinc oxide.

[0020] In some exemplary embodiments of this disclosure, the manufacturing method further includes:

[0021] An upper electrode layer is formed, which covers the dielectric layer, and a gap is formed between adjacent support layers;

[0022] A filling layer is formed, which covers the upper electrode layer and fills the gap.

[0023] In some exemplary embodiments of this disclosure, the manufacturing method further includes:

[0024] A mask layer is formed on the filler layer, the mask layer extending along the first direction, and the mask layer including a plurality of opening patterns disposed along the second direction;

[0025] Using the mask layer as a mask, the filling layer, the upper electrode layer, and the dielectric layer are etched downwards until the substrate is exposed, so as to form a trench between the filling layer and the support layer.

[0026] In some exemplary embodiments of this disclosure, the manufacturing method further includes:

[0027] An upper electrode layer is formed, the upper electrode layer covering the dielectric layer;

[0028] A mask layer is formed on the upper electrode layer, the mask layer extending along the first direction, and the mask layer including a plurality of opening patterns disposed along the second direction;

[0029] Using the mask layer as a mask, the upper electrode layer, the dielectric layer, and the lower electrode layer are etched downwards until the substrate is exposed, so as to form a trench between adjacent support layers.

[0030] In some exemplary embodiments of this disclosure, the side surface of the support layer is a plane or a curved surface;

[0031] When the sides of adjacent support layers are planar, the adjacent planar surfaces are parallel to each other;

[0032] When the side surfaces of adjacent support layers are curved, the plane containing the second direction is taken as a cross section, and the distance between adjacent curved surfaces on the cross section is equal along the first direction.

[0033] A second aspect of this disclosure provides a semiconductor structure, characterized in that the semiconductor structure comprises:

[0034] Base;

[0035] Multiple support layers for forming a parallel plate capacitor structure are disposed on a substrate, the support layers extend along a first direction, and the multiple support layers are spaced apart along a second direction, the first direction and the second direction intersect.

[0036] A lower electrode plate for forming a planar capacitor structure, the lower electrode plate including a lower electrode layer that at least covers the sidewalls of the support layer;

[0037] A dielectric plate for forming a planar capacitor structure, the dielectric plate including a dielectric layer covering the lower electrode layer.

[0038] In some exemplary embodiments of this disclosure, the semiconductor structure further includes:

[0039] An upper electrode plate for forming a planar capacitor structure, the upper electrode plate including an upper electrode layer covering the dielectric layer.

[0040] In some exemplary embodiments of this disclosure, the semiconductor structure further includes:

[0041] A filler plate for forming a planar capacitor structure, the filler plate including a filler layer covering the upper electrode layer.

[0042] In some exemplary embodiments disclosed herein, the planar capacitor structure includes a plurality of independent single-sided planar capacitor structures, which are disposed on the support layer along the first direction. Any two adjacent single-sided planar capacitor structures are separated by a trench located between the filler plate and the dielectric plate.

[0043] In some exemplary embodiments of this disclosure, the parallel plate capacitor structure includes multiple independent double-sided parallel plate capacitor structures, which include:

[0044] Multiple independent double-sided planar capacitor structures are arranged on the support layer along the first direction, and any two adjacent planar capacitor structures are separated by a trench; the trench is located between adjacent support layers.

[0045] Multiple independent planar capacitor structures share the upper electrode plate.

[0046] In some exemplary embodiments of this disclosure, the side surface of the support layer is a plane or a curved surface;

[0047] When the sides of adjacent support layers are planar, the adjacent planar surfaces are parallel to each other;

[0048] When the side surfaces of adjacent support layers are curved, the plane containing the second direction is taken as a cross section, and the distance between adjacent curved surfaces on the cross section is equal along the first direction.

[0049] The semiconductor structure fabrication method and semiconductor structure provided in this disclosure involve forming multiple support layers on a substrate, and at least forming a lower electrode layer and a dielectric layer on the support layers. This allows for the formation of a planar capacitor using the support layers, improving the columnar capacitor to a planar capacitor. This reduces the fill aspect ratio of the capacitor and prevents delamination and uneven filling at the bottom of the capacitor.

[0050] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0051] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0052] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0053] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0054] Figure 4 This is a cross-sectional view of a substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0055] Figure 5 This is a top view of a semiconductor structure fabrication method according to an exemplary embodiment, after a support layer has been formed on a substrate.

[0056] Figure 6 This is a cross-sectional view of a semiconductor structure fabrication method according to an exemplary embodiment, after a planar support layer has been formed on a substrate.

[0057] Figure 7This is a top view of a semiconductor structure fabrication method according to an exemplary embodiment, after a curved support layer has been formed on a substrate.

[0058] Figure 8 This is a cross-sectional view after the lower electrode layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0059] Figure 9 This is a cross-sectional view of the lower electrode layer after the lower electrode has been formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0060] Figure 10 This is a cross-sectional view of a semiconductor structure fabrication method according to an exemplary embodiment, after the dielectric layer has been formed.

[0061] Figure 11 This is a cross-sectional view of a semiconductor structure fabrication method according to an exemplary embodiment, after the dielectric layer has been formed.

[0062] Figure 12 This is a cross-sectional view after the formation of the upper electrode layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0063] Figure 13 This is a cross-sectional view after the filling layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0064] Figure 14 This is a top view after a mask layer has been formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0065] Figure 15 Based on Figure 14 The cross-sectional structure diagram corresponding to the groove formed by etching the opening pattern downwards at point A.

[0066] Figure 16 yes Figure 13 The diagram shows a cross-sectional view along the BB direction in the structure shown.

[0067] Figure 17 This is a schematic diagram illustrating the hexagonal close-packing distribution of multiple single-sided planar capacitor structures in a semiconductor structure fabrication method according to an exemplary embodiment.

[0068] Figure 18 This is a schematic diagram illustrating the distribution of multiple single-sided planar capacitor structures stacked in a square in a semiconductor structure fabrication method according to an exemplary embodiment.

[0069] Figure 19 This is a cross-sectional view after the formation of the upper electrode layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0070] Figure 20 This is a top view after a mask layer has been formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0071] Figure 21 Based on Figure 19 The cross-sectional structure diagram corresponding to the groove formed by etching the opening pattern downwards at point A.

[0072] Figure 22 yes Figure 19 The cross-sectional view along the BB direction in the structure shown.

[0073] Figure 23 This is a schematic diagram illustrating the distribution of a plurality of double-sided planar capacitor structures in a method for fabricating a semiconductor structure according to an exemplary embodiment, showing the hexagonal close-packed distribution.

[0074] Figure 24 This is a schematic diagram showing the distribution of multiple double-sided planar capacitor structures stacked in a square in a semiconductor structure fabrication method according to an exemplary embodiment.

[0075] Figure label:

[0076] 100, Substrate; 200, Single-sided planar capacitor structure; 201, Lower electrode layer; 202, Dielectric layer; 2021, Dielectric plate; 2022, Second part of dielectric layer; 203, Upper electrode layer; 2031, Upper electrode plate; 30, Lower electrode material; 300, Support layer; 400, Double-sided planar capacitor structure; 600, Filler layer; 601, First part of filler layer; 700, Mask layer; 701, Opening pattern; 702, Trench. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0078] Therefore, the exemplary embodiments of this disclosure provide a method for fabricating a semiconductor structure. Figure 1-3 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 4-23 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 4-23 The methods for fabricating semiconductor structures are introduced.

[0079] This embodiment does not limit the semiconductor structure. The following description uses a planar capacitor structure as an example, but this embodiment is not limited to this; other structures are also possible. It should be understood that the semiconductor structure formed in this embodiment does not constitute a complete capacitor; this embodiment only describes the capacitor formation process.

[0080] like Figure 1 As shown, the method in this embodiment includes the following steps:

[0081] Step S110: Provide a substrate.

[0082] like Figure 4 As shown, substrate 100 may include semiconductor materials, wherein the semiconductor materials may include one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. Exemplarily, substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In other embodiments, substrate 100 may also include insulating materials such as silicon oxide or silicon nitride. Substrate 100 also includes structures such as buried word lines, shallow trench isolation structures, active regions, and bit lines (not shown in the figure).

[0083] Step S120: A plurality of support layers are formed on the substrate. The support layers are used to form a planar capacitor structure. The support layers extend along a first direction. The plurality of support layers are spaced apart in a second direction. The first direction and the second direction intersect.

[0084] like Figure 5 As shown, multiple support layers 300 can be deposited on the substrate 100 using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes to serve as capacitor supports. The support layers 300 extend along a first direction X, which can be parallel to the substrate 100. Simultaneously, the multiple support layers 300 are independently spaced along a second direction Y, which can be parallel to the substrate 100 and intersect the surface of the support layers 300. The intersection of the first direction X and the second direction Y forms a preset angle, such as 45 degrees, 60 degrees, or 90 degrees. The support layers 300 are connected to the substrate 100, and along the second direction Y, two sides of the support layers 300 expose portions of the surface of the substrate 100.

[0085] In an exemplary implementation, such as Figure 5 and Figure 7 As shown, the side surface of the support layer 300 can be either a plane or a curved surface, such as... Figure 6 As shown, in the direction perpendicular to the substrate 100, the side surface of the support layer is planar, and on the surface perpendicular to the substrate 100, the side surfaces of the support layer 300 are parallel to each other. The height and width of the support layer 300 can be set according to the storage density of the capacitor structure. The support layer 300 can extend a preset length in the first direction, and adjacent support layers can be spaced a preset distance apart, or can be set according to the storage density of the semiconductor structure; no specific limitations are imposed here. The material of the support layer 300 can be an insulating material with a certain hardness, such as silicon nitride or silicon oxynitride, and the support layer can be a support structure composed of a single layer film or multiple layers of films.

[0086] Step S130: Form a lower electrode layer, which at least covers the sidewalls of the support layer.

[0087] like Figure 8 As shown, an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process can be used to deposit a lower electrode material layer on at least the sidewall of the support layer 300 to form the lower electrode layer 201. Figure 8 In this configuration, the lower electrode layer 201 covers the sidewall surface of the support layer 300 and the substrate 100 between two adjacent support layers 300 to form the lower electrode layer 201. For example... Figure 9 As shown, the lower electrode layer 201 covers the sidewall surface of the support layer 300 to form the lower electrode layer 201. The material of the lower electrode layer 201 may be different from the material of the support layer 300. The material of the lower electrode layer 201 includes, but is not limited to, one or more combinations of materials such as titanium nitride (TiN), metallic titanium (Ti), metallic molybdenum (Mo), molybdenum nitride (MoN), metallic ruthenium (Ru), and ruthenium nitride (RuN).

[0088] When forming a single-sided planar capacitor structure, such as Figure 9 As shown, the lower electrode layer 201 covers the sidewall surfaces of both sides of the support layer 300. When a double-sided planar capacitor structure is formed, as... Figure 8 As shown, the lower electrode layer 201 covers the sidewall surface of the support layer 300 and the substrate 100 between two adjacent support layers 300.

[0089] Step S140: Form a dielectric layer that covers the lower electrode layer.

[0090] After forming the lower electrode layer 201, a dielectric layer 202 is formed on the lower electrode layer 201, that is, the dielectric layer 202 covers the lower electrode layer 201. When forming a single-sided planar capacitor structure, as... Figure 10As shown, a dielectric layer 202 is deposited on the top surface of the lower electrode layer 201, the support layer 300, and the upper surface of the exposed substrate 100 between the support layer 300. When forming a double-sided planar capacitor structure, as... Figure 19 As shown, a dielectric layer 202 is deposited on the top surface of the support layer 300 and the lower electrode layer 201. The dielectric layer 202 can be a single-layer film structure or a multi-layer film structure.

[0091] The method for fabricating the semiconductor structure in this embodiment is as follows: Figure 10 As shown, by forming multiple support layers 300 on the substrate 100, and forming a lower electrode layer 201 and a dielectric layer 202 on at least the sidewalls of the support layers 300, a plate-shaped capacitor is formed using the support layers 300, thereby improving the columnar capacitor into a plate-shaped capacitor, thereby reducing the fill aspect ratio of the capacitor and preventing the problems of delamination and uneven filling at the bottom of the capacitor.

[0092] According to an exemplary embodiment of this disclosure, this embodiment describes step S140 in the above embodiments. The dielectric layer 202 can be a single-layer film structure or a multi-layer film structure. The method for forming the dielectric layer 202 includes:

[0093] A first material layer is formed, which covers the top surface of the lower electrode layer and the support layer, as well as the substrate between adjacent support layers.

[0094] At least one first material layer forms a dielectric layer.

[0095] In this embodiment, the method of forming a dielectric layer is illustrated by taking the formation of a two-layer structure as an example:

[0096] Step S241: Form a first material layer 2026. The first material layer 2026 covers the top surface of the lower electrode layer 201, the support layer 300 and the substrate 100 between adjacent support layers, forming the first material layer 2026.

[0097] like Figure 10 As shown, an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process can be used to deposit a first material on the top surface of the lower electrode layer 201, the support layer 300, and the upper surface of the exposed substrate 100 to form a first material layer 2026. The first material layer 2026 covers the top surface of the lower electrode layer 201, the support layer 300, and the upper surface of the exposed substrate 100. In this case, the first material layer 2026 serves as a dielectric layer 202.

[0098] Step S242: Form a second material layer, the second material layer covers the first material layer, and the first material layer and the second material layer constitute a dielectric layer.

[0099] like Figure 10 As shown, a first material layer 2026 can be formed by depositing a first material, thereby forming a dielectric layer 202 of a single-layer film structure. Figure 11 As shown, the filling layer 202 can be a multilayer film structure. After forming a first material layer 2026, a second material layer 2027 can be formed by depositing material on the surface of the first material layer 2026. The first material layer 2026 and the second material layer 2027 form the dielectric layer 202 of the multilayer film structure. The second material layer 2027 and the first material layer 2026 can be made of different materials or the same materials. When the material of the second material layer 2027 is the same as the material of the first material layer 2026, the dielectric layer 202 of the multilayer film structure exhibits a single-layer structure; when the material of the second material layer 2027 is different from the material of the first material layer 2026, the dielectric layer 202 of the multilayer film structure exhibits a two-layer structure. Figure 11 For ease of illustration, the first material layer 2026 and the second material layer 2027 are shown as a two-layer structure, but this is not intended to limit the structure of the dielectric layer 202. It can certainly include more layers, such as 3, 4, or 6 layers. In other embodiments, multiple material layers can be repeatedly formed according to the thickness of the dielectric layer 202 to form a multilayer film structure of the dielectric layer 202. The materials of the multiple material layers can be the same or different.

[0100] In an exemplary implementation, such as Figure 11 As shown, the materials of the first material layer 2026 and the second material layer 2027 can be, for example, high-k dielectric materials, such as titanium oxide (TiO), hafnium oxide (HfO), niobium oxide (NbO), indium gallium zinc oxide (InGaZnO), etc., or one or more combinations thereof. For example, the first material layer 2026 is a titanium oxide layer, and the second material layer 2027 can be a hafnium oxide layer.

[0101] Figure 10 and Figure 11 The illustration shows an example of forming a single-sided parallel-plate capacitor structure 200. When forming a double-sided parallel-plate capacitor structure 400, the lower electrode layer 201 covers the substrate 100 between the support layers, and the dielectric layer 202 is formed on the top surface of the lower electrode layer 201 and the support layer 300. Figure 19 As shown. Dielectric layer 202 can also be arranged according to... Figure 10 and Figure 11 The method shown forms a single-layer or multi-layer structure.

[0102] In the semiconductor structure fabrication method of this embodiment, the columnar capacitor is improved into a planar capacitor. Since the capacitor of the planar structure formed by the support layer has a smaller storage area than the capacitor of the columnar structure, the storage capacity of the semiconductor structure can be improved by selecting the materials within the above range as the dielectric layer materials.

[0103] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure. Taking a single-sided planar capacitor structure as an example, this embodiment will be described in detail. In this embodiment, the method for fabricating the semiconductor structure is as follows: Figure 2 As shown, the steps include the following:

[0104] Step S210: Provide a substrate.

[0105] Step S220: A plurality of support layers are formed on the substrate. The support layers are used to form a planar capacitor structure. The support layers extend along a first direction. The plurality of support layers are spaced apart in a second direction. The first direction and the second direction intersect.

[0106] The implementation methods of steps S210-S220 in this embodiment and steps S110-S120 in the previous embodiment are the same, and will not be repeated here.

[0107] Step S230: Deposit the lower electrode material, which covers the sidewalls of the support layer, the top surface of the support layer, and the substrate between two adjacent support layers.

[0108] The lower electrode material can be deposited on the sidewalls of the support layer 300, the top surface of the support layer 300, and the surface of the substrate 100 between two adjacent support layers 300 using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, the lower electrode material includes one or more combinations of materials such as titanium nitride (TiN), metallic titanium (Ti), metallic molybdenum (Mo), molybdenum nitride (MoN), metallic ruthenium (Ru), and ruthenium nitride (RuN).

[0109] Step S240: Remove the lower electrode material covering the substrate and the lower electrode material covering the top surface of the support layer to form a lower electrode layer with a single-sided capacitor structure.

[0110] like Figure 9As shown, the lower electrode material covering the top surface of the support layer 300 and the surface of the substrate 100 is removed, and a lower electrode layer 201 is formed on both sides of the support layer 300. This lower electrode layer 201 is used to form a single-sided planar capacitor structure using the support layer 300, preparing for the formation of the single-sided planar capacitor structure. In this embodiment, the lower electrode material covering the top surface of the support layer 300 and the surface of the substrate 100 can be removed by dry etching or wet etching.

[0111] Step S250: Form a dielectric layer that covers the top surface of the lower electrode layer and the support layer, as well as the substrate located between two adjacent support layers.

[0112] like Figure 10 As shown, dielectric layer 202 covers lower electrode layer 201, the top surface of support layer 300, and substrate 100 located between two adjacent support layers 300. The specific deposition method is the same as the implementation method of step S140 in the aforementioned embodiment, and will not be described again here.

[0113] Step S260: Form an upper electrode layer, which covers the dielectric layer and forms a gap between adjacent support layers.

[0114] like Figure 10 or Figure 11 As shown, above the substrate 100, a dielectric layer 202 forms a first gap 10 between two adjacent support layers 300. The dielectric layer 202 covers the top surface of the support layer 300, the substrate 100 between the lower electrode layer 201 and the support layer 300, to form the first gap 10 between the support layers. Figure 12 As shown, an upper electrode material is deposited on the outer surface of the dielectric layer 202 to form an upper electrode layer 203. Within a first gap 10 between two adjacent support layers 300, the upper electrode layer 203 forms a second gap 50 on the dielectric layer 202. The upper electrode material can be the same as or different from the lower electrode material. The upper electrode material includes one or more combinations of materials such as titanium nitride (TiN), metallic titanium (Ti), metallic molybdenum (Mo), molybdenum nitride (MoN), metallic ruthenium (Ru), and ruthenium nitride (RuN).

[0115] Step S270: Form a filling layer that covers the upper electrode layer and fills the gaps.

[0116] like Figure 13 As shown, a filling layer 600 is deposited on the outer surface of the upper electrode layer 203, the filling layer 600 covers the outer surface of the upper electrode layer 203, and the first portion 601 of the filling layer 600 fills the gap 50.

[0117] The lower electrode layer 201 covers the sides of both sides of the support layer 300. The dielectric layer 202 covers the top surface of the support layer 300, the surface of the lower electrode layer 201, and the substrate 100 between the support layers 300. The upper electrode layer 203 covers the surface of the dielectric layer 202. In the initially formed single-sided planar capacitor structure, the lower electrodes 201 are located on both sides of the support layer 300 and are not connected to each other. The dielectric layer 202 covers the lower electrodes 201, the top surface of the support layer 300, and the substrate 100 between the support layers. The upper electrode layer 203 covers the dielectric layer 202, and a filler layer covers the dielectric layer 202, forming the initial planar capacitor structure.

[0118] Step S280: A mask layer is formed on the filler layer, the mask layer extending along a first direction, and the mask layer includes a plurality of opening patterns disposed along a second direction.

[0119] like Figure 14 As shown, a mask layer 700 can be formed on the surface of the filler layer 600 through processes such as spin coating, development, and exposure. The mask layer 700 extends along the first direction X, allowing the projected outline of the mask layer 700 on the substrate 100 to coincide with the outline of the substrate 100. Multiple opening patterns 701 are formed on the mask layer 700, and the opening patterns 701 extend along the second direction Y. For example... Figure 14 As shown, an exemplary schematic diagram of the distribution of the opening pattern 701 on the mask layer 700 is illustrated. The opening pattern 701 is spaced apart in the first direction X and staggered in the second direction Y, exposing a portion of the surface of 600. The opening pattern 701 is distributed between adjacent support layers 300 and fill layers 600, that is, the opening pattern 701 is distributed between the first portion 601 of adjacent support layers 300 and fill layers 600.

[0120] Step S290: Using the mask layer as a mask, etch downwards the fill layer, the top electrode layer, and the dielectric layer until the substrate is exposed, to form a trench between the fill layer and the support layer. Figure 14 As shown, using the mask layer 700 as a mask, the filling layer 600, the upper electrode layer 203, and the dielectric layer 202 are sequentially etched downwards along the opening pattern 701 until a portion of the top surface of the substrate 100 is exposed. Etching then stops, forming multiple trenches 702 located between the support layer 300 and the filling layer 600. Figure 15 As shown, Figure 15 The diagram shows a cross-sectional view of the trench 702, where the trench 702 is based on... Figure 14The trench 702, formed by etching downwards from the opening pattern 701 at point A, penetrates sequentially through the filler layer 600, the upper electrode layer 203, and the dielectric layer 202, exposing a portion of the top surface of the substrate 100. The trench 702 is located between the support layer 300 and the first portion 601 of the filler layer 600. The width of the trench 702 is equal to the distance between adjacent support layers 300 and the first portion 601 of the filler layer 600. The projection of the opening pattern 701 onto the filler layer 600 can cover a portion of the first portion 601 of the filler layer 600; that is, based on the opening pattern 701, a portion of the first portion 601 can be etched downwards, forming the trench 702. The width of the trench 702 is greater than the distance between the support layer 300 and the first portion 601 but less than the sum of the distance between the support layer 300 and the first portion 601 and the thickness of the first portion 601.

[0121] Multiple trenches 702 space the initial capacitor structure to form multiple independent single-sided planar capacitor structures 200 between the support layer 300 and the first portion 601 of the fill layer 600. For example... Figure 16 As shown, Figure 16 yes Figure 13 The diagram shows a cross-sectional view along the BB direction in the structure shown. Multiple independent single-sided planar capacitor structures 200 are separated by trenches 702, a support layer 300, and a first portion 601 of a filler layer 600. Each single-sided planar capacitor structure 200 includes a lower electrode plate 2011 formed by a retained lower electrode layer 201, a dielectric plate 2021 formed by a retained dielectric layer 202, and an upper electrode plate 2031 formed by a retained upper electrode layer 203. Since the lower electrode layers 201 are located on both sides of the support layer 300 and are not connected to each other, and do not cover the substrate between the support layers 300, the single-sided planar capacitor structures separated by the support layer 300, the first portion 601 of the filler layer 600, and the trenches 702 are independent of each other and located on both sides of the support layer 300.

[0122] Multiple independent single-sided plate capacitor structures 200 are arranged at intervals in the first direction X on one side of the support layer 300 to form a capacitor group 500, so that each support layer 300 can have a corresponding capacitor group 500, as shown in the figure. Figure 16 The two rows of capacitor banks 500 between two adjacent support layers 300 are separated by the first part 601 of the filling layer 600.

[0123] Each single-sided flat plate capacitor structure 200 includes a lower electrode plate 2011, a dielectric plate 2021, and an upper electrode plate 2031.

[0124] To improve space utilization, more independent capacitor structures can be formed by fully utilizing the capacitor material on the substrate, such as... Figure 16 As shown, refer to Figure 14The location of the opening pattern 701 in the mask layer 700 allows for the formation of independent hexagonal stacked capacitor structures on the substrate 100. The length of the opening pattern 701 can be controlled between the filling layer 600 and the support layer 300, and this can also be achieved by controlling the width of the mask layer 700. Trench 702, formed by etching along the opening pattern 701, divides the capacitor structure into a hexagonal close-packed distribution, such as... Figure 17 As shown, an exemplary distribution of a 200-cell hexagonal densest stack of independent single-sided capacitor structures is illustrated.

[0125] In this embodiment, an independent capacitor structure with a hexagonal close-packed distribution is formed above the substrate, which effectively utilizes space to form more independent capacitor structures, improves space utilization, and increases the storage density of the semiconductor.

[0126] In an exemplary embodiment, the opening patterns 701 are spaced apart in the first direction X, and adjacent opening patterns 701 can also be aligned in the second direction Y. Grooves 702 are etched along the opening patterns 701, and the independent single-sided capacitor structures 200 spaced apart by the grooves 702 form a tetrahedral stack, such as... Figure 18 As shown, an exemplary distribution of a standalone single-sided capacitor structure 200 in a square stack is illustrated.

[0127] The trench 702 can be filled with insulating material to achieve electrical isolation between the individual capacitor structures.

[0128] In this embodiment, after forming an independent capacitor structure, the process further includes removing the mask layer.

[0129] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure. Taking a double-sided capacitor as an example, this embodiment will be described in detail. Figure 3 As shown, the method for fabricating a semiconductor structure includes the following steps:

[0130] Step S310: Provide a substrate.

[0131] Step S320: A plurality of support layers are formed on the substrate. The support layers are used to form a parallel plate capacitor structure. The support layers extend along a first direction. The plurality of support layers are spaced apart in a second direction. The first direction and the second direction intersect.

[0132] Step S330: Deposit the lower electrode material, which covers the sidewalls of the support layer, the top surface of the support layer, and the substrate between two adjacent support layers.

[0133] Step S340: Remove the lower electrode material covering the top surface of the support layer to form a lower electrode layer with a double-sided capacitor structure.

[0134] Step S350: Form a dielectric layer that covers the top surface of the lower electrode layer and the support layer.

[0135] Step S360: Form an upper electrode layer, which covers the dielectric layer.

[0136] Steps S310-S330 in this embodiment are implemented in the same way as steps S210-230 in the previous embodiment, and will not be described again here.

[0137] In step S340, refer to Figure 8 The lower electrode material covering the top surface of the support layer 300 can be removed by etching, thereby disconnecting the lower electrode material on the support layer 300 and forming independent lower electrode layers on both sides of the support layer 300, in preparation for the subsequent process of forming a double-sided capacitor structure. In this embodiment, the top surface of the lower electrode material is flush with the top surface of the support layer 300.

[0138] like Figure 19 As shown, in steps S350 and S360, dielectric layer 202 covers the top surface of lower electrode layer 201 and support layer 300, and upper electrode layer 203 covers dielectric layer 202. Upper electrode layer 203 fills the gaps between dielectric layers 202. Figure 19 As shown, an upper electrode layer is filled between the dielectric layers 202 between two adjacent support layers 300. In the initially formed double-sided planar capacitor structure, the lower electrode layers 201 are disposed on both sides of the support layer 300 and on the substrate between two adjacent support layers 300, and are not connected to each other. The dielectric layer 202 covers the lower electrode layer 201 and the top surface of the support layer 300, and the upper electrode layer 203 covers the dielectric layer 202 and fills the gap of the dielectric layer 202 between two adjacent support layers 300, forming the initial planar capacitor structure.

[0139] Step S370: A mask layer is formed on the upper electrode layer, the mask layer extending along a first direction, and the mask layer includes a plurality of opening patterns disposed along a second direction.

[0140] In order to form an independent single-sided capacitor structure from the initial capacitor structure, such as Figure 20 As shown, the mask layer 700 extends along a first direction X and includes a plurality of opening patterns 701 disposed along a second direction Y. The plurality of opening patterns 701 are spaced apart in the first direction X and staggered in the second direction Y. The mask layer 700 covers the upper electrode 203, and the opening patterns 701 expose a portion of the surface of the upper electrode 203. The opening patterns 701 are distributed between two adjacent support layers 300.

[0141] Step S380: Using the mask layer as a mask, etch the upper electrode layer, dielectric layer and lower electrode layer downwards until the substrate is exposed, so as to form a trench between adjacent support layers.

[0142] like Figure 21 As shown, refer to Figure 20 Using the mask layer 700 as a mask, the upper electrode layer 203, dielectric layer 202, and lower electrode layer 201 are sequentially etched downwards along the opening pattern 701 until a portion of the top surface of the substrate 100 is exposed. Etching then stops, forming multiple trenches 702 located between two adjacent support layers 300. Figure 21 As shown, Figure 21 The diagram illustrates the basis Figure 19 The cross-sectional view of the trench 702 formed by etching the opening pattern 701 at point A downwards is shown. The trench 702 sequentially penetrates the upper electrode layer 203, the dielectric layer 202, and the lower electrode layer 201, exposing part of the top surface of the substrate 100. Its width is limited to the width of the two adjacent support layers.

[0143] like Figure 22 As shown, Figure 22 yes Figure 19 The diagram shows a cross-sectional view along the BB direction in the structure shown. Multiple trenches 702 space the initial capacitor structure to form multiple independent double-sided planar capacitor structures 400 between adjacent support layers. The multiple independent double-sided planar capacitor structures 400 are spaced by the trenches 702 and adjacent support layers. Each double-sided planar capacitor structure 400 includes a lower electrode plate 2011 formed by a retained lower electrode layer 201, a dielectric plate 2021 formed by a retained dielectric layer 202, and an upper electrode plate 2031 formed by a retained upper electrode layer 203. The lower electrode plate 2011 includes a first lower electrode plate 2012 formed by the retained lower electrode layer 201 on the first support layer 3001, a second lower electrode plate (not shown) on the substrate 100, and a third lower electrode plate 2013 formed by the retained lower electrode layer 201 on the first support layer 3002. The dielectric plate 2021 includes a first dielectric plate 2022 located on a first lower electrode plate 2012, a second dielectric plate (not shown) located on a second lower electrode plate, and a third dielectric plate 2023 located on a third lower electrode plate 2013.

[0144] Each double-sided planar capacitor structure 400 includes a first lower electrode plate 2012, a second lower electrode plate, a third lower electrode plate 2013, a first dielectric plate 2022, a second dielectric plate, a third dielectric plate 2023, and an upper electrode plate 2031. The first lower electrode plate 2012 and the third lower electrode plate 2013 are located on both sides of the upper electrode plate 2031, and the first dielectric plate 2022 and the third dielectric plate 2023 are located on both sides of the upper electrode plate 2031, forming a double-sided planar capacitor structure.

[0145] Since the upper electrode layer 203 covers the dielectric layer 202, when forming a double-sided planar capacitor structure, the multiple trenches 702 do not separate the upper electrode layer. Therefore, multiple double-sided planar capacitor structures share the upper electrode plate 2031 formed by the upper electrode layer 203.

[0146] Multiple independent double-sided parallel plate capacitor structures 400 are arranged at intervals between adjacent support layers in the first direction X, forming a capacitor group 500. Since the upper electrode layer 203 fills the gaps between the dielectric layers 202 and covers the dielectric layers 202, the upper electrode layer 203 is not cut off when the trench 702 is formed, but is interconnected. This allows multiple independent double-sided parallel plate capacitor structures to share the upper electrode plate 2031.

[0147] like Figure 23 As shown, refer to Figure 22 To improve space utilization and fully utilize the capacitor material on the substrate to form more independent double-sided planar capacitor structures 400, independent capacitor structures in a hexagonal stacking manner can be formed on the substrate 100 through the position of the opening pattern 701 of the mask layer 700, such as... Figure 22 As shown, Figure 22 An exemplary illustration shows the hexagonal densest stack distribution of multiple independent double-sided planar capacitor structures 400.

[0148] In this embodiment, a hexagonal close-packed independent double-sided planar capacitor structure is formed above the substrate, effectively utilizing space to form more independent capacitor structures, improving space utilization, and increasing the semiconductor's storage density. In another exemplary embodiment of this disclosure, multiple quadrangularly stacked double-sided capacitor structures can also be formed, such as... Figure 24 As shown, Figure 24 An exemplary illustration shows the distribution of a quadrangular stack of a double-sided planar capacitor structure 400.

[0149] According to an exemplary embodiment, such as Figure 7 As shown, the side surface of the support layer 300 formed on the substrate 100 is curved, for example, a wavy surface. When the side surfaces of two adjacent support layers are curved, the plane parallel to the second direction Y of the substrate 100 is used as the cross-section. Along the first direction X of the substrate 100, the surface distance between the two adjacent support layers is kept consistent, ensuring that the width between the two curved surfaces of the two adjacent support layers 300 is equal. This avoids the situation where inconsistent curved surfaces lead to different trench widths, causing localized connections during the subsequent formation of the filling material and affecting the semiconductor structure. The formed structure can be referenced from the corresponding structural diagram where the side surfaces of the support layer are planar. When the support layer is curved, the contact area of ​​the formed planar capacitor structure is larger, resulting in a larger storage capacity.

[0150] This disclosure provides a semiconductor structure through an exemplary embodiment, such as... Figure 16 , Figure 22 As shown, the semiconductor structure includes: a substrate 100, a plurality of support layers 300 for forming a planar capacitor structure disposed on the substrate 100, each support layer 300 extending along a first direction X, the plurality of support layers being spaced apart along a second direction Y, the first direction X and the second direction Y intersecting; a lower electrode plate 2011 for forming a planar capacitor structure, the lower electrode plate 2011 including a lower electrode layer covering at least the sidewalls of the support layers 300; and a dielectric plate 2021 for forming a planar capacitor structure, the dielectric plate 2021 including a dielectric layer covering the lower electrode layer.

[0151] The semiconductor structure provided in the exemplary embodiments of this disclosure further includes an upper electrode plate 2031 for forming a planar capacitor structure, the upper electrode plate 2031 including an upper electrode layer covering a dielectric layer.

[0152] When the parallel plate capacitor structure is a single-sided parallel plate capacitor structure, it also includes a filler plate 602 for forming the parallel plate capacitor structure, and the filler plate 602 includes a filler layer covering the upper electrode layer.

[0153] The parallel plate capacitor structure may include multiple independent single-sided parallel plate capacitor structures 200, which are disposed on the support layer along a first direction. Any two adjacent single-sided parallel plate capacitor structures 200 are separated by a trench 702 located between the filler plate 602 and the dielectric plate 2021. During the formation of the single-sided parallel plate capacitor structure 200, the lower electrode layer 201 does not cover the gap between two adjacent support layers 300. When the trench 702 is formed between adjacent support layers 300 and the first portion 601 of the filler layer 600, each independent single-sided parallel plate capacitor structure 200 is separated by the support layer 300, the first portion 601 of the filler layer 600, and the trench 702, thereby enabling the formation of mutually independent single-sided parallel plate capacitor structures 200.

[0154] The parallel plate capacitor structure may also include multiple independent double-sided parallel plate capacitor structures 400, which are arranged on the support layer along the first direction. Any two adjacent parallel plate capacitor structures are separated by a trench 702. The trench is located between the support layers. The multiple independent parallel plate capacitor structures share an upper electrode plate.

[0155] In this embodiment, the semiconductor structure forms multiple independent support layers 300 on the substrate 100, and multiple independently arranged capacitor structures on the support layers 300. This allows the support layers 300 to form a planar capacitor structure, thereby reducing the fill aspect ratio of the capacitor and preventing delamination and uneven filling at the bottom of the capacitor. According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments lies in the following: Figure 5 and Figure 7 As shown, the side surfaces of the support layers are either planes or curved surfaces; when the side surfaces of two adjacent support layers are planes, the two planes are parallel to each other; when the side surfaces of two adjacent support layers are curved surfaces, the two curved surfaces are equidistant from each other along the first direction, with the plane containing the second direction as the cross section.

[0156] like Figure 5 and Figure 7 As shown, the support layer 300 formed on the substrate 100 can be planar or curved. The planar or curved support layer can be used to form a parallel plate capacitor structure, thereby reducing the fill depth-to-width ratio of the capacitor and preventing delamination and uneven filling at the bottom of the capacitor. When the support layer is curved, the contact area of ​​the formed capacitor structure is larger and the storage capacity is greater.

[0157] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0158] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0159] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0160] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The manufacturing method includes: Provide a base; Multiple support layers are formed on the substrate, the support layers are used to form a parallel plate capacitor structure, the support layers extend along a first direction, and the multiple support layers are spaced apart in a second direction, the first direction and the second direction intersect; A lower electrode layer is formed, wherein the lower electrode layer at least covers the sidewall of the support layer; A dielectric layer is formed, which covers the lower electrode layer; An upper electrode layer is formed, which covers the dielectric layer. A mask layer is formed on the upper electrode layer, which extends along a first direction and includes a plurality of opening patterns disposed along a second direction. Using the mask layer as a mask, the upper electrode layer, the dielectric layer, and the lower electrode layer are etched downward until the substrate is exposed, so as to form trenches between adjacent support layers.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of the lower electrode layer includes: A lower electrode material is deposited, the lower electrode material covering the sidewalls of the support layer, the top surface of the support layer, and the substrate between adjacent support layers; The lower electrode material covering the top surface of the support layer is removed to form a lower electrode layer with a double-sided capacitor structure.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of the lower electrode layer further includes: A lower electrode material is deposited, the lower electrode material covering the sidewalls of the support layer, the top surface of the support layer, and the substrate between adjacent support layers; The lower electrode material covering the substrate and the lower electrode material covering the top surface of the support layer are removed to form a lower electrode layer with a single-sided capacitor structure.

4. The method for fabricating a semiconductor structure according to any one of claims 1 to 3, characterized in that, The formation of the dielectric layer includes: A first material layer is formed, which covers the lower electrode layer, the top surface of the support layer, and the substrate between adjacent support layers; The dielectric layer is formed by at least one layer of the first material.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The material of the first material layer includes at least one dielectric material, which includes one or more of titanium oxide, hafnium oxide, niobium oxide, and indium gallium zinc oxide.

6. The method for fabricating a semiconductor structure according to any one of claims 1 to 3, characterized in that, The manufacturing method further includes: The upper electrode layer forms a gap between adjacent support layers; A filling layer is formed, which covers the upper electrode layer and fills the gap.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The manufacturing method further includes: A mask layer is formed on the filler layer, the mask layer extending along the first direction, and the mask layer including a plurality of opening patterns disposed along the second direction; Using the mask layer as a mask, the filling layer, the upper electrode layer, and the dielectric layer are etched downwards until the substrate is exposed, so as to form a trench between the filling layer and the support layer.

8. The method for fabricating a semiconductor structure according to any one of claims 1 to 3, characterized in that, The side surface of the support layer is either a plane or a curved surface; When the sides of adjacent support layers are planar, the adjacent planar surfaces are parallel to each other; When the side surfaces of adjacent support layers are curved, the plane containing the second direction is taken as a cross section, and the distance between adjacent curved surfaces on the cross section is equal along the first direction.

9. A semiconductor structure, characterized in that, The semiconductor structure includes: Base; A plurality of support layers for forming a parallel plate capacitor structure are disposed on the substrate, the support layers extend along a first direction, the plurality of support layers are spaced apart in a second direction, and the first direction and the second direction intersect. A lower electrode plate for forming a planar capacitor structure, the lower electrode plate including a lower electrode layer that at least covers the sidewalls of the support layer; A dielectric plate for forming a planar capacitor structure, the dielectric plate including a dielectric layer covering the lower electrode layer; Filler plate used to form a planar capacitor structure; The parallel plate capacitor structure includes multiple independent single-sided parallel plate capacitor structures, which are arranged along the first direction on the support layer. Any two adjacent single-sided parallel plate capacitor structures are separated by a trench located between the filler plate and the support layer; or The planar capacitor structure includes multiple independent double-sided planar capacitor structures, which are arranged on the support layer along the first direction, and any two adjacent planar capacitor structures are separated by a trench; the trench is located between adjacent support layers.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: An upper electrode plate for forming a planar capacitor structure, the upper electrode plate including an upper electrode layer covering the dielectric layer.

11. The semiconductor structure according to claim 10, characterized in that, The filler plate includes a filler layer covering the upper electrode layer.

12. The semiconductor structure according to claim 10, characterized in that, Multiple independent double-sided planar capacitor structures share the upper electrode plate.

13. The semiconductor structure according to claim 9, characterized in that, The side surface of the support layer is either a plane or a curved surface; When the sides of adjacent support layers are planar, the adjacent planar surfaces are parallel to each other; When the side surfaces of adjacent support layers are curved, the plane containing the second direction is taken as a cross section, and the distance between adjacent curved surfaces on the cross section is equal along the first direction.

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