Memory device

Abstract

This disclosure provides a storage device comprising: a word line stack including word lines alternately stacked in a vertical direction over a substrate and having edge portions; at least one support extending vertically in the word line stacking direction and supporting the edge portions of the word line stack; a contact plug electrically connected to the word lines at the edge portions of the word line stack; and an active layer located between the word lines and horizontally oriented in a direction intersecting the word lines.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0134458, filed on October 16, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor memory device, and more specifically, to a memory device. Background Technology

[0004] In recent years, the size of memory cells has been continuously reduced in order to increase the net die size of memory devices.

[0005] As the size of memory cells decreases, parasitic capacitance (Cb) should be reduced and capacitance should be increased. However, due to the structural limitations of memory cells, it is difficult to increase the net die size. Summary of the Invention

[0006] The embodiments of the present invention pertain to a highly integrated storage device.

[0007] According to an embodiment of the present invention, a storage device includes: a word line stack comprising word lines alternately stacked in a vertical direction above a substrate and having edge portions; at least one support extending vertically in the direction of the word line stack and supporting the edge portions of the word line stack; a contact plug electrically connected to the word lines at the edge portions of the word line stack; and an active layer located between the word lines and horizontally oriented in a direction intersecting the word lines.

[0008] According to another embodiment of the present invention, a storage device includes: a word line stack comprising word lines alternately stacked in a direction perpendicular to a substrate, and including an edge portion and an additional edge portion parallel to the edge portion; at least one small support extending vertically in the word line stacking direction and supporting the edge portion and the additional edge portion respectively; at least one large support extending vertically in the word line stacking direction and jointly supporting the edge portion and the additional edge portion; contact plugs electrically connected to the word lines in the edge portions respectively; additional contact plugs electrically connected to the word lines in the additional edge portions respectively; and an active layer located between the word lines and horizontally oriented in a direction intersecting the word lines.

[0009] According to another embodiment of the present invention, a memory device includes: a plurality of memory cells stacked vertically relative to a substrate; and at least one support extending vertically in the direction of the stacking of the memory cells, wherein each of the memory cells includes: a bit line oriented perpendicular to the substrate; a capacitor spaced horizontally from the bit line; an active layer oriented horizontally between the bit line and the capacitor; and a word line located on at least one of the upper and lower surfaces of the active layer and extending horizontally in a direction intersecting the active layer, and the edge portion of the word line of the memory cell is supported by the support.

[0010] Those skilled in the art will better understand these and other features and advantages of this invention. Attached Figure Description

[0011] Figure 1 This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present invention.

[0012] Figure 2 It is along Figure 1 The layout diagram shown is the section cut by line A-A'.

[0013] Figure 3 It is along Figure 2 The cross-sectional view taken by line B-B' is shown.

[0014] Figure 4A and Figure 4B A storage device according to an embodiment of the present invention is shown.

[0015] Figure 4C This is a detailed plan view showing the edge portion 334E of the character line.

[0016] Figures 5A to 5D This is a perspective view showing an application example of the support component.

[0017] Figure 6 This is a diagram illustrating a storage device according to another embodiment of the present invention.

[0018] Figure 7 It is along Figure 6 The cross-sectional view shown is taken from line A12-A12'.

[0019] Figures 8A to 9B This is a diagram illustrating a storage device according to another embodiment of the present invention. Detailed Implementation

[0020] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of the invention.

[0021] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may have been enlarged to clearly show the features of the embodiments. When the first layer is referred to as "on the second layer" or "on the substrate," it means not only that the first layer is formed directly on the second layer or substrate, but also that a third layer exists between the first layer and the second layer or substrate.

[0022] In the following embodiments of the present invention, the storage cell density can be increased by stacking storage cells in the vertical direction, while reducing parasitic capacitance.

[0023] Figure 1 This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present invention. Figure 2 It is along Figure 1 The layout diagram shown is the section cut by line A-A'. Figure 3 It is along Figure 2 The cross-sectional view taken by line B-B' is shown.

[0024] refer to Figures 1 to 3 Semiconductor device 100 may include a substrate LS and a memory cell array MCA formed above the substrate LS. The memory cell array MCA may be oriented perpendicular to the substrate LS in a first direction D1. The substrate LS may include a plane defined by a second direction D2 and a third direction D3. The memory cell array MCA may be oriented perpendicular to the plane of the substrate LS. The memory cell array MCA may be oriented vertically upward from the substrate LS in the first direction D1. The memory cell array MCA may include a three-dimensional array of memory cells MC. The memory cell array MCA may include, for example, Figure 1 The multiple storage units MC1, MC2, MC3 and MC4 shown are merely examples.

[0025] For example, a memory cell array (MCA) may include a first memory cell MC1, a second memory cell MC2, a third memory cell MC3, and a fourth memory cell MC4. The first memory cell MC1 and the third memory cell MC3 may be vertically oriented in a first direction D1 to form a first vertical column. The second memory cell MC2 and the fourth memory cell MC4 may be vertically oriented in the first direction D1 to form a second vertical column. The third memory cell MC3 and the fourth memory cell MC4 may be horizontally oriented in a third direction D3 to form a first horizontal row. The first memory cell MC1 and the second memory cell MC2 may be horizontally oriented in the third direction D3 to form a second horizontal row. Note that more than two memory cells may be arranged in each column and each row. Moreover, more than two rows and / or more than two columns of memory cells may be used without departing from the scope of the claimed invention. Each of the memory cells MC1, MC2, MC3, and MC4 of the memory cell array (MCA) may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR and the capacitor CAP may be horizontally oriented in a second direction D2. Each of the memory cells MC1, MC2, MC3, and MC4 may further include a word line WL extending in a third direction D3. In each of the memory cells MC1, MC2, MC3, and MC4, the bit line BL, transistor TR, capacitor CAP, and board line PL may be positioned horizontally along a second direction D2. The memory cell array MCA may include a dynamic random access memory (DRAM) array; however, the invention is not limited to this. For example, in variations and other embodiments of the illustrated embodiment, the memory cell array MCA may include phase-change random access memory (PCRAM), resistive random access memory (RERAM), and magnetic random access memory (MRAM), etc. Similarly, in variations and other embodiments of the illustrated embodiment, the capacitor CAP may be replaced by other memory elements.

[0026] The substrate LS can be formed from one or more materials suitable for semiconductor processing. For example, suitable materials for the substrate LS may include at least one of conductive, dielectric, and semiconductor materials. Various materials can be formed on the substrate LS. The substrate LS may include a semiconductor substrate. The substrate LS may be formed from a silicon-containing material. The substrate LS may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicon, monocrystalline germanium silicon, polycrystalline germanium silicon, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate LS may also include other semiconductor materials, such as germanium. The substrate LS may include a Group III / V semiconductor substrate, such as a compound semiconductor substrate like GaAs. The substrate LS may include a silicon-on-insulator (SOI) substrate.

[0027] According to another embodiment of the present invention, the substrate LS may include a peripheral circuitry portion PC (not shown). The peripheral circuitry portion PC may include multiple control circuits for controlling the memory cell array MCA. At least one control circuit in the peripheral circuitry portion PC may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuitry portion PC may include an address decoder circuit, a read circuit, and a write circuit. At least one control circuit in the peripheral circuitry portion PC may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a FinFET, etc.

[0028] For example, at least one control circuit in the peripheral circuitry PC may be electrically connected to the bit line BL. The peripheral circuitry PC may include a sense amplifier SA, and the sense amplifier SA may be electrically connected to the bit line BL. Although not shown, a multi-level metal line MLM may be positioned between the memory cell array MCA and the substrate LS, and the peripheral circuitry PC and the bit line BL may be coupled to each other through the multi-level metal line MLM.

[0029] A memory cell array (MCA) may include a stack of at least two or more memory cells (MCs). The at least two or more memory cells (MCs) may be stacked vertically above a substrate (LS) in a first direction (D1).

[0030] Bit line BL can extend from substrate LS in a first direction D1. The plane of substrate LS can extend in a second direction D2, and the first direction D1 can be perpendicular to the second direction D2. Bit line BL can be vertically oriented from substrate LS. The bottom of bit line BL can be coupled to substrate LS. The bottom of bit line BL can be coupled to peripheral circuit portion PC of substrate LS. Bit line BL can have a columnar shape. Bit line BL can be referred to as a vertically oriented bit line or a columnar bit line. Bit line BL can include a conductive material. Bit line BL can include silicon-based materials, metal-based materials, or combinations thereof. Bit line BL can include polysilicon, metal, metal nitride, metal silicide, or combinations thereof. Vertically stacked memory cells MC can share a bit line BL. Bit line BL can include polysilicon, titanium nitride, tungsten, or combinations thereof. For example, bit line BL can include polysilicon or titanium nitride (TiN) doped with N-type impurities. Bit line BL can include a stack of titanium nitride and tungsten (TiN / W). Bit line BL can further include an ohmic contact layer, such as a metal silicide.

[0031] The transistor TR can be arranged horizontally along a second direction D2 parallel to the surface of the substrate LS. That is, the transistor TR can be horizontally located between the bit line BL and the capacitor CAP. The transistor TR can be located at a level higher than the substrate LS, and the transistor TR and the substrate LS can be spaced apart from each other.

[0032] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend in a third direction D3, and the active layer ACT may extend in a second direction D2. The third direction D3 may be perpendicular to the first direction D1. The active layer ACT may be horizontally arranged and may extend from the bit line BL in the second direction D2. The active layer ACT may be oriented parallel to the plane of the substrate LS.

[0033] The word line WL can have a dual word line structure, with an active layer ACT sandwiched between it. A gate dielectric layer GD can be formed on the upper and lower surfaces of the active layer ACT. The word line WL can include an upper word line WLU and a lower word line WLL. The upper word line WLU can be disposed above the upper surface of the active layer ACT, and the lower word line WLL can be disposed below the lower surface of the active layer ACT. The gate dielectric layer GD can be formed between the upper word line WLU and the upper surface of the active layer ACT. Alternatively, the gate dielectric layer GD can be formed between the lower word line WLL and the lower surface of the active layer ACT. The upper word line WLU and the lower word line WLL can be separated from the active layer ACT by the gate dielectric layer GD.

[0034] The gate dielectric layer (GD) may include, for example, silicon oxide, silicon nitride, metal oxide, metal nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The gate dielectric layer (GD) may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, and HfSiON, etc.

[0035] Word lines (WLs) can include metals, metal mixtures, metal alloys, or semiconductor materials. Word lines (WLs) can include titanium nitride, tungsten, polycrystalline silicon, or combinations thereof. For example, a word line (WL) can include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. Word lines (WLs) can include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function of about 4.5 or less, while P-type work function materials can have a high work function of about 4.5 or greater.

[0036] The upper word line WLU and the lower word line WLL can have different potentials. For example, in each of the memory cells MC1, MC2, MC3, and MC4, a word line drive voltage can be applied to the upper word line WLU, and a ground voltage can be applied to the lower word line WLL. The lower word line WLL can be used to prevent interference between the upper word lines WLU between memory cells MCs vertically positioned in the first direction D1. According to a variation of the illustrated embodiment or another embodiment of the invention, a ground voltage can be applied to the upper word line WLU, and a word line drive voltage can be applied to the lower word line WLL. According to another embodiment of the invention, the upper word line WLU and the lower word line WLL can be coupled to each other.

[0037] The active layer ACT can be formed of one or more suitable semiconductor materials, including, for example, polysilicon. The active layer ACT can include multiple impurity regions. The impurity regions can include a first impurity region and a second impurity region. The first impurity region and the second impurity region can be a source region and a drain region, respectively. The first impurity region and the second impurity region can be a drain region and a source region, respectively. The active layer ACT can include doped polysilicon, undoped polysilicon, amorphous silicon, or oxide semiconductor materials. The first source / drain region SD1 and the second source / drain region SD2 can be doped with N-type impurities or P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 can be doped with impurities of the same conductivity type. The first source / drain region SD1 and the second source / drain region SD2 can be doped with N-type impurities. The first source / drain region SD1 and the second source / drain region SD2 can be doped with P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The bit line BL may be electrically connected to a first edge portion of the active layer ACT, and the capacitor CAP may be electrically connected to a second edge portion of the active layer ACT. The first edge portion of the active layer ACT may be provided by the first source / drain region SD1, and the second edge portion of the active layer ACT may be provided by the second source / drain region SD2. The active layer ACT may further include a channel CH. The channel CH may be defined between the first source / drain region SD1 and the second source / drain region SD2. The upper word line WLU and the lower word line WLL may face each other, with the channel CH situated between them.

[0038] The capacitor CAP can be horizontally positioned starting from the transistor TR. The capacitor CAP can extend horizontally in the second direction D2, starting from the active layer ACT. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, dielectric layer DE, and plate node PN can be arranged horizontally in the second direction D2. The storage node SN may have a horizontally oriented cylindrical shape, and the plate node PN may have a shape extending towards the inner and outer walls of the cylinder of the storage node SN. The dielectric layer DE may be located inside the storage node SN and surround the plate node PN. The plate node PN may be coupled to the board line PL. The storage node SN may be electrically connected to the second source / drain region SD2. A portion of the second source / drain region SD2 may extend into the interior of the storage node SN.

[0039] The capacitor CAP can include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN can include metal-based materials. The dielectric layer DE can include, for example, silicon oxide, silicon nitride, high-k materials, or combinations thereof. The high-k material can have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) can have a dielectric constant of about 3.9, and the dielectric layer DE can include a high-k material with a dielectric constant of about 4 or greater. The high-k material can have a dielectric constant of about 20 or greater. The high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the invention, the dielectric layer DE can be formed as a composite layer comprising two or more layers of the above-described high-k materials.

[0040] The dielectric layer DE can be formed of zirconium-based oxide. The dielectric layer DE can have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which alumina (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can have a structure in which zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. The ZA stack and the ZAZ stack can be referred to as zirconium oxide-based layers (ZrO2-based layers). According to another embodiment of the invention, the dielectric layer DE can be formed of hafnium-based oxide. The dielectric layer DE can have a stacked structure including hafnium oxide (HfO2). Stacked structures including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a structure in which alumina (Al2O3) is stacked on top of hafnium oxide (HfO2). HAH stacks can have a structure in which hafnium oxide (HfO2), alumina (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. HA stacks and HAH stacks can be referred to as hafnium oxide-based layers (HfO2-based layers). In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, alumina (Al2O3) can have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material with a bandgap larger than that of the high-k material. Besides alumina (Al2O3), the dielectric layer DE can include, for example, silicon oxide (SiO2) as a high-bandgap material. Because the dielectric layer DE contains a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the invention, the dielectric layer DE can include a laminated structure in which high-k materials and high-bandgap materials are alternately stacked, for example, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) laminated structures. In the above-mentioned laminated structure, the aluminum oxide (Al2O3) layer can be very thin.

[0041] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a laminated structure, or a hybrid structure comprising zirconium oxide, hafnium oxide, and aluminum oxide.

[0042] According to another embodiment of the invention, an interface control layer (not shown) for reducing leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0043] Storage nodes (SN) and plate nodes (PN) can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and plate nodes (PN) can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten nitride (TiN / W) stacks, and tungsten nitride / tungsten nitride (WN / W) stacks. Plate nodes (PN) can include combinations of metal-based materials and silicon-based materials. For example, a plate node (PN) can be a stack of titanium nitride / germanium silicon / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, germanium and silicon can serve as interstitial fillers within the cylindrical interior of the storage node (SN), and titanium nitride (TiN) can be used as a solid capacitor (CAP). Tungsten nitride can be a low-resistance material. The bottom portion of the plate line (PL) can be insulated from the substrate (LS).

[0044] Storage node SN can have a three-dimensional structure. Storage node SN can have a horizontal three-dimensional structure oriented in the second direction D2. As an example of a three-dimensional structure, storage node SN can have a cylindrical shape, a columnar shape, or a cylindrical-column shape. A cylindrical-column shape can refer to a structure that combines a columnar shape and a cylindrical shape.

[0045] A portion of the dielectric layer DE can be located between the word line WL and the storage node SN.

[0046] Figure 4A This is a plan view showing a storage device 200 according to another embodiment of the present invention, and Figure 4B It is along Figure 4A The cross-sectional view shown is taken by line A11-A11'. Figure 4A and Figure 4B In, with Figures 1 to 3 The same reference numerals in the accompanying drawings can denote the same constituent elements. In the following text, reference numerals that also appear in the drawings may be omitted. Figures 1 to 3 In Figure 4A and Figure 4B A detailed description of its constituent components.

[0047] refer to Figures 4A to 4CThe storage device 200 may include a memory cell array stack 320 above the peripheral structure 310. The memory cell array stack 320 may include multiple memory cell arrays. For example, such as... Figures 1 to 3 As shown, the memory cell array stack 320 may include a memory cell array (MCA) containing multiple memory cells. Figure 4A An example is shown in which four memory cell arrays (MCAs) are arranged in the second direction D2.

[0048] The memory cell array stack 320 may include multiple word line stacks 330. Each word line stack 330 may include multiple word lines 331, 332, 333, and 334, and the word lines 331, 332, 333, and 334 may be vertically stacked in a first direction D1. The word lines 331, 332, 333, and 334 may extend in a third direction D3. The word line stacks 330 may be spaced apart from each other in a second direction D2, and each word line stack 330 may extend in a third direction D3. Each word line stack 330 may further include multiple dielectric layers 331', 332', 333', and 334'. The dielectric layers 331', 332', 333', and 334' may be alternately stacked with the word lines 331, 332, 333, and 334 in the first direction D1. Each word line stack 330 may include dielectric layers 331', 332', 333', and 334' alternating with word lines 331, 332, 333, and 334.

[0049] The memory cell array stack 320 may include a first region R1 and a second region R2. The first region R1 may be the region in which memory cells are formed. The second region R2 may be the region in which contact plug structures 340 are formed. Word lines 331, 332, 333, and 334 may each include word line body portions 331L, 332L, 333L, and 334L, and word line edge portions 331E, 332E, 333E, and 334E. The word line body portions 331L, 332L, 333L, and 334L may be located in the first region R1. The word line edge portions 331E, 332E, 333E, and 334E may be located in the second region R2. The word line edge portions 331E, 332E, 333E, and 334E may be coupled to the contact plug structures 340. The contact plug structures 340 may be coupled to the wireline structure 350. The contact plug structure 340 may include multiple contact plugs 341, 342, 343, and 344. Contact plugs 341, 342, 343, and 344 may be coupled to word line edge portions 331E, 332E, 333E, and 334E, respectively. The metal wire structure 350 may include multiple metal wires 351, 352, 353, and 354. Metal wires 351, 352, 353, and 354 may be coupled to contact plugs 341, 342, 343, and 344, respectively. Word line edge portions 331E, 332E, 333E, and 334E may have different lengths in the third direction D3, forming a stepped structure in the first direction D1. The peripheral structure 310 may include peripheral circuitry for driving word lines 331, 332, 333, and 334. The peripheral circuitry (not shown) of the peripheral structure 310 may be located at a level lower than the word line stack 330, and it may be electrically connected to word lines 331, 332, 333, and 334 via the metal wire structure 350. According to another embodiment of the invention, the peripheral structure 310 may be positioned at a level higher than the word line stack 330.

[0050] The memory cell array stack 320 may include a dual word line structure. For example, among word lines 331, 332, 333, and 334, word lines 332 and 334 may correspond to the upper word line (…). Figure 3 WLU in the middle), and word lines 331 and 333 can correspond to the lower word line ( Figure 3 (WLL in the text). Word lines 331 and 333 can be coupled to metal lines 351 and 353 via contact plugs 341 and 343, and word lines 332 and 334 can be coupled to metal lines 352 and 354 via contact plugs 342 and 344. Word line drive voltages can be applied to metal lines 352 and 354, and ground voltages can be applied to metal lines 351 and 353.

[0051] Each word line stack 330 may include a lower word line WLL and an upper word line WLU that are alternately stacked vertically above the outer structure 310. Although not shown, it is understood that... Figures 1 to 3 As shown, the horizontally oriented active layer (reference) Figures 1 to 3 The 'ACT' shown can be located between the lower letter line WLL and the upper letter line WLU. For example... Figures 1 to 3 As shown, the active layer can be horizontally oriented in the direction intersecting the lower word line WLL and the upper word line WLU. Vertically oriented bit lines (reference) Figures 1 to 3 The “BL” shown can be configured to be coupled to one side of the active layer, while the storage node (refer to…) Figure 2 and Figure 3 The “SN” shown can be configured to be coupled to the other side of the active layer.

[0052] The storage device 200 may further include a plurality of supports 360. Supports 360 may support word line stacks 330. Supports 360 may be vertically oriented in a first direction D1. Supports 360 may be coupled to at least one sidewall of the word line stack 330. Each word line stack 330 may include a first sidewall SW1 and a second sidewall SW2 facing each other. The first sidewall SW1 and the second sidewall SW2 may be parallel to each other and may extend in a third direction D3. Supports 360 may be coupled to the first sidewall SW1. Supports 360 may be coupled to the second sidewall SW2. Supports 360 may be coupled to both the first sidewall SW1 and the second sidewall SW2. Supports 360 may support all word lines 331, 332, 333, and 334. Supports 360 may support word line edge portions 331E, 332E, 333E, and 334E. The word line edge portions 331E, 332E, 333E, and 334E may partially cover the sidewall of the support 360. The support 360 may also be referred to as a slit. The support 360 may be composed of a dielectric pillar. The support 360 may include, for example, silicon oxide.

[0053] Figure 4C This is a detailed plan view showing the edge portion 334E of the character line.

[0054] refer to Figure 4C The character line edge portion 334E may include a first sidewall SW1 and a second sidewall SW2, and each of the first sidewall SW1 and the second sidewall SW2 may include a flat surface FL and a recessed surface RC. The recessed surface RC may partially cover the sidewall of the support member 360. The flat surface FL may not contact the support member 360.

[0055] Other letter edge portions 331E, 332E, and 333E may also include a flat surface FL and a recessed surface RC. The recessed surface RC may be shaped to accommodate a support member 360.

[0056] Each word line stack 330 may include a flat surface FL and a recessed surface RC, and the support 360 may contact the recessed surface RC.

[0057] Support element 360 can be formed before word lines 331, 332, 333 and 334.

[0058] As described above, the support 360 can prevent the word lines 331, 332, 333 and 334 from collapsing. Moreover, the support 360 can prevent the edge portions 331E, 332E, 333E and 334E of the word lines from bending in the second region R2.

[0059] Figures 5A to 5D This is a perspective view showing an application example of the support component. Figures 5A to 5D In, with Figures 4A to 4C The same reference numerals can denote the same constituent elements. In the following text, reference numerals that also appear in the figures may be omitted. Figures 4A to 4C In Figures 5A to 5D A detailed description of its constituent components.

[0060] refer to Figure 5A Support members 361 and 362 can contact the first sidewall SW1 of the word line edge portions 331E, 332E, 333E and 334E, and support members 363 and 364 can contact the second sidewall SW2 of the word line edge portions 331E, 332E, 333E and 334E.

[0061] refer to Figure 5B Support members 361 and 362 may contact the first sidewall SW1 of the word line edge portions 331E, 332E, 333E and 334E. Support members 361 and 362 may not contact the second sidewall SW2 of the word line edge portions 331E, 332E, 333E and 334E.

[0062] refer to Figure 5C Supports 363 and 364 may contact the second sidewall SW2 of the word line edge portions 331E, 332E, 333E and 334E. Supports 363 and 364 may not contact the first sidewall SW1 of the word line edge portions 331E, 332E, 333E and 334E.

[0063] refer to Figure 5D Support member 362 can contact the first sidewall SW1 of the word line edge portions 331E, 332E, 333E and 334E, and support member 361 can contact the second sidewall SW2 of the word line edge portions 331E, 332E, 333E and 334E.

[0064] According to other embodiments of the invention, the word line edge portions 331E, 332E, 333E, and 334E can be supported by one of the support members 361, 362, 363, and 364. For example, the word line edge portions 331E, 332E, 333E, and 334E can be supported by support member 361.

[0065] Figure 6 This is a diagram illustrating a storage device according to another embodiment of the present invention. Figure 7 It is along Figure 6 The cross-sectional view shown is taken from line A12-A12'. Figure 6 and Figure 7 In, with Figures 4A to 5D The same reference numerals in the accompanying drawings can denote the same constituent elements. In the following text, reference numerals that also appear in the drawings may be omitted. Figures 4A to 5D In Figure 6 and Figure 7 A detailed description of its constituent components.

[0066] refer to Figure 6 and Figure 7 The memory device 300 may include a peripheral structure 310 and a memory cell array stack 320 located above the peripheral structure 310. As described in the above embodiments, the memory cell array stack 320 may include a plurality of memory cells. Each memory cell may include a transistor, a word line, a capacitor, and a bit line. In the following embodiments, illustrations and descriptions of the transistors, capacitors, and bit lines may be omitted.

[0067] The memory cell array stack 320 may include multiple word line stacks, such as word line stacks 330A and 330B. Each of word line stacks 330A and 330B may include multiple word lines, such as word lines 331, 332, 333, and 334. Word lines 331, 332, 333, and 334 may be stacked vertically in a first direction D1. Word lines 331, 332, 333, and 334 may extend in a third direction D3. Word line stacks 330A and 330B may be spaced apart from each other in a second direction D2 and extend in a third direction D3.

[0068] refer to Figure 4A , Figure 4B , Figure 6 and Figure 7Word lines 331, 332, 333, and 334 may each include word line body portions 331L, 332L, 333L, and 334L, and word line edge portions 331E, 332E, 333E, and 334E, respectively. The word line body portions 331L, 332L, 333L, and 334L may be located in a first region R1, and the word line edge portions 331E, 332E, 333E, and 334E may be located in a second region R2. The word line edge portions 331E, 332E, 333E, and 334E may be coupled to a contact plug structure 340. The contact plug structure 340 may be coupled to a metal wire structure 350. The contact plug structure 340 may include multiple contact plugs 341, 342, 343, and 344, and the contact plugs 341, 342, 343, and 344 may be coupled to word line edge portions 331E, 332E, 333E, and 334E. The metal wire structure 350 may include multiple metal wires 351, 352, 353, and 354. The metal wires 351, 352, 353, and 354 may be coupled to the contact plugs 341, 342, 343, and 344, respectively. The word line edge portions 331E, 332E, 333E, and 334E may have different lengths in the third direction D3. The word line edge portions 331E, 332E, 333E, and 334E may form a stepped structure in the first direction D1.

[0069] The memory cell array stack 320 may include a dual word line structure. Word lines 331 and 333 are coupled to metal lines 351 and 353 via contact plugs 341 and 343, and word lines 332 and 334 are coupled to metal lines 352 and 354 via contact plugs 342 and 344. Word line drive voltages may be applied to metal lines 352 and 354, and ground voltages may be applied to metal lines 351 and 353.

[0070] The storage device 300 may further include a plurality of small support members 460. The small support members 460 may support all word lines 331, 332, 333, and 334. The small support members 460 may support word line edge portions 331E, 332E, 333E, and 334E. The word line edge portions 331E, 332E, 333E, and 334E may include a first sidewall SW1 and a second sidewall SW2 facing each other. The first sidewall SW1 and the second sidewall SW2 may be parallel to each other and may extend in a third direction D3. The small support members 460 may be coupled to the first sidewall SW1 of the word line edge portions 331E, 332E, 333E, and 334E. The small support members 460 may not be coupled to the second sidewall SW2 of the word line edge portions 331E, 332E, 333E, and 334E. The small support members 460 may be spaced apart from each other. The word line edge portions 331E, 332E, 333E, and 334E may partially cover the sidewall of the small support 460. The small support 460 may be referred to as a small slit. The small support 460 may be formed of a dielectric material. The small support 460 may include, for example, silicon oxide.

[0071] The storage device 300 may further include a plurality of additional word line edge portions 431E, 432E, 433E, and 434E. The additional word line edge portions 431E, 432E, 433E, and 434E may be parallel to each other with word line edge portions 331E, 332E, 333E, and 334E. The additional word line edge portions 431E, 432E, 433E, and 434E may be coupled to each other with word line edge portions 331E, 332E, 333E, and 334E via interconnection portion 435. Interconnection portion 435 may be a part of the additional word line edge portions 431E, 432E, 433E, and 434E. Word line edge portions 331E, 332E, 333E, and 334E may be electrically connected to each other with the additional word line edge portions 431E, 432E, 433E, and 434E. The additional character line edge portions 431E, 432E, 433E, and 434E may have different lengths in the third direction D3. The additional character line edge portions 431E, 432E, 433E, and 434E may form a stepped structure in the first direction D1. The sidewalls of the character line edge portions 331E, 332E, 333E, and 334E, as well as the sidewalls of the additional character line edge portions 431E, 432E, 433E, and 434E, may include, for example... Figure 4CThe flat surface FL and the recessed surface RC are shown. Additional word line edge portions 431E, 432E, 433E, and 434E may include a third sidewall SW3 and a fourth sidewall SW4 parallel to the third sidewall SW3. Each of the third sidewall SW3 and the fourth sidewall SW4 may include multiple recessed surfaces, and a large support 470 may contact the recessed surface of the third sidewall SW3, while a small support 460 may contact the recessed surface of the fourth sidewall SW4. Word line edge portions 331E, 332E, 333E, and 334E may be referred to as 'first edge portions', and additional word line edge portions 431E, 432E, 433E, and 434E may be referred to as 'second edge portions'.

[0072] The storage device 300 may also include additional contact plugs 441, 442, 443 and 444, which may be coupled to additional word line edge portions 431E, 432E, 433E and 434E, respectively.

[0073] The storage device 300 may further include a plurality of large support members 470. The large support members 470 may support word line stacks 330A and 330B. The large support members 470 may be vertically oriented in a first direction D1. The large support members 470 may be coupled to a sidewall of at least one of the word line stacks 330A and 330B. The large support members 470 may be coupled to a second sidewall SW2 of word line stack 330A. Other large support members 470 may be coupled to a second sidewall SW2 of word line stack 330B. The large support members 470 may not be coupled to a first sidewall SW1 of word line stack 330A or a first sidewall SW1 of word line stack 330B. The large support members 470 may be spaced apart from each other.

[0074] The large support member 470 can support all word lines 331, 332, 333, and 334. The large support member 470 can support the edge portions of word lines 331E, 332E, 333E, and 334E. The edge portions of word lines 331E, 332E, 333E, and 334E can partially cover the sidewall of the large support member 470. The large support member 470 can support additional edge portions of word lines 431E, 432E, 433E, and 434E. The additional edge portions of word lines 431E, 432E, 433E, and 434E can partially cover the sidewall of the large support member 470. The large support member 470 may be referred to as a large slit. The large support member 470 can be formed of a dielectric material. The large support member 470 may include, for example, silicon oxide. The small support member 460 and the large support member 470 can be formed of the same material.

[0075] The large support member 470 can be located between the word line edge portions 331E, 332E, 333E, and 334E and the additional word line edge portions 431E, 432E, 433E, and 434E. The large support member 470 can simultaneously support the word line edge portions 331E, 332E, 333E, and 334E as well as the additional word line edge portions 431E, 432E, 433E, and 434E. The small support member 460 can respectively support the word line edge portions 331E, 332E, 333E, and 334E and the additional word line edge portions 431E, 432E, 433E, and 434E. The distance between the word line edge portions 331E, 332E, 333E, and 334E and the additional word line edge portions 431E, 432E, 433E, and 434E can be less than the length of the large support member 470 in the second direction D2.

[0076] The large support member 470 may have a larger dimension than the small support member 460. Here, the dimension may include at least one of diameter, width, and length.

[0077] Referring to the reference word line stack 330A, a small support member 460 may be formed between the edge of the additional contact plug 444 and the edge of the additional word line edge portion 434E. The small support member 460 may partially penetrate the sidewall of one of the additional word line edge portions 431E, 432E, 433E, and 434E. The small support member 460 may be formed between the contact plug 344 and the edge of the word line edge portion 334E. The small support member 460 may partially penetrate the first sidewall SW1 of the word line edge portions 331E, 332E, 333E, and 334E.

[0078] As described above, the small support 460 and the large support 470 can prevent the word lines 331, 332, 333, and 334 from collapsing. Furthermore, the small support 460 and the large support 470 can prevent the word line edge portions 331E, 332E, 333E, and 334E, as well as the additional word line edge portions 431E, 432E, 433E, and 434E, from bending in the second region R2.

[0079] Since word line stacks 330A and 330B include word line edge portions 331E, 332E, 333E and 334E and additional word line edge portions 431E, 432E, 433E and 434E, the structural stability of word line stacks 330A and 330B can be further improved.

[0080] Because additional contact plugs 441, 442, 443 and 444 are also included, contact resistance can be improved, and the possibility of contact being not open can also be reduced.

[0081] Word line edge portions 331E, 332E, 333E, and 334E, as well as additional word line edge portions 431E, 432E, 433E, and 434E, may be referred to as 'word line pads' or 'word line contact pads'. Word line edge portions 331E, 332E, 333E, and 334E may be referred to as first word line pads, and additional word line edge portions 431E, 432E, 433E, and 434E may be referred to as second word line pads. Word line stacks 330A and 330B may include first word line pads and second word line pads. Therefore, the memory device 300 may include a dual word line pad structure.

[0082] Figures 8A to 9B This is a diagram illustrating a storage device according to another embodiment of the present invention.

[0083] exist Figure 8A and Figure 8B In, with Figures 4A to 5D The same reference numerals in the accompanying drawings can denote the same constituent elements. In the following text, reference numerals that also appear in the drawings may be omitted. Figures 4A to 5D In Figure 8A and Figure 8B A detailed description of its constituent components.

[0084] refer to Figure 4A , Figure 4B , Figure 4C and Figure 8A The memory device 500 may include a peripheral structure 310 and a memory cell array stack 320 located above the peripheral structure 310. As described in the above embodiments, the memory cell array stack 320 may include a plurality of memory cells, and each memory cell may include a transistor, a word line, a capacitor, and a bit line. In the following embodiments, illustrations and descriptions of the transistors, capacitors, and bit lines may be omitted.

[0085] The memory cell array stack 320 may include multiple word line stacks 330. Each word line stack 330 may include multiple word lines 331, 332, 333, and 334 vertically stacked in a first direction D1. Word lines 331, 332, 333, and 334 may extend in a third direction D3. The word line stacks 330 may be spaced apart from each other in a second direction D2, and each word line stack 330 may extend in a third direction D3.

[0086] The storage device 500 may further include a plurality of supports 360. Supports 360 may support word line stacks 330. Supports 360 may be vertically oriented in a first direction D1. Supports 360 may be coupled to the sidewalls of at least one word line stack among the word line stacks 330. Each word line stack 330 may include a first sidewall SW1 and a second sidewall SW2 facing each other. The first sidewall SW1 and the second sidewall SW2 may be parallel to each other and may extend in a third direction D3. At least some supports 360 may be coupled to the first sidewall SW1. At least some supports 360 may be coupled to the second sidewall SW2. In the illustrated embodiment, at least some supports 360 may be coupled to the first sidewall SW1 and the second sidewall SW2. Supports 360 may support all word lines 331, 332, 333, and 334. Supports 360 may support word line edge portions 331E, 332E, 333E, and 334E. The word line edge portions 331E, 332E, 333E, and 334E may partially cover the sidewall of the support 360. The support 360 may be referred to as a slit. The support 360 may be composed of a dielectric pillar. The support 360 may include, for example, silicon oxide.

[0087] The support 360 can be configured to support a corresponding stepped structure of contact plugs 341, 342, 343, and 344 on which it lands. Figure 4A In the middle, the support member 360 can be disposed in the periphery of the contact plug 344 landing on the word line stack 330, while Figure 8A In this configuration, the support member 360 can be configured to support a stepped structure on which contact plugs 341, 342, 343, and 344 land. In this way, because the stepped structure is arranged to be supported, the support effect of the word line stack 330 can be further improved.

[0088] refer to Figure 4A , Figure 4B , Figure 4C and Figure 8BThe storage device 501 may further include a plurality of supports 360. Supports 360 may support word line stacks 330. Supports 360 may be vertically oriented in a first direction D1. Supports 360 may be coupled to a sidewall of at least one word line stack among the word line stacks 330. The word line stack 330 may include a first sidewall SW1 and a second sidewall SW2 facing each other. The first sidewall SW1 and the second sidewall SW2 may be parallel to each other, and they may extend in a third direction D3. Supports 360 may be coupled to the first sidewall SW1. Supports 360 may be coupled to the second sidewall SW2. Supports 360 may be coupled to both the first sidewall SW1 and the second sidewall SW2. Supports 360 may support all word lines 331, 332, 333, and 334. Supports 360 may support word line edge portions 331E, 332E, 333E, and 334E. The word line edge portions 331E, 332E, 333E, and 334E may partially cover the sidewall of the support 360. The support 360 may be referred to as a slit. The support 360 may be composed of a dielectric pillar. The support 360 may include, for example, silicon oxide.

[0089] The support member 360 can be configured to support corresponding stepped structures on which contact plugs 341, 342, 343, and 344 land. The support member 360 can support the word line edge portions 331E, 332E, 333E, and 334E on both sides of the word line. Figure 4A and Figure 8A In the middle, the support member 360 can support the edge of the character line on one side of the character line stack 330, while Figure 8B In the middle, the support member 360 can support the edge parts of the word lines on both sides of the word line stack 330.

[0090] refer to Figure 9A and Figure 9B ,and Figures 4A to 6 The same reference numerals in the accompanying drawings can denote the same constituent elements. In the following text, reference numerals that also appear... Figures 4A to 6 In Figure 9A and Figure 9B A detailed description of its constituent components.

[0091] refer to Figure 4A , Figure 4B , Figure 4C , Figure 6 and Figure 9A The storage device 600 may include multiple small support members 460 and multiple large support members 470.

[0092] The small support 460 can support all word lines 331, 332, 333, and 334. The small support 460 can support the edge portions of word lines 331E, 332E, 333E, and 334E. The small support 460 may include, for example, silicon oxide.

[0093] Large support member 470 can support word line stacks 330A and 330B. Large support member 470 can be vertically oriented in a first direction D1. Large support member 470 can be coupled to a sidewall of at least one of the word line stacks 330A and 330B. Large support member 470 can be coupled to a second sidewall SW2 of word line stack 330A. Other large support members 470 can be coupled to the second sidewall SW2 of word line stack 330B. Large support members 470 may not be coupled to the first sidewall SW1 of word line stack 330A or the first sidewall SW1 of word line stack 330B. Large support members 470 can be spaced apart from each other.

[0094] The large support 470 can support all word lines 331, 332, 333, and 334. The large support 470 can support the edge portions of word lines 331E, 332E, 333E, and 334E. The edge portions of word lines 331E, 332E, 333E, and 334E can partially cover the sidewalls of the large support 470. The large support 470 can support additional edge portions of word lines 431E, 432E, 433E, and 434E. The additional edge portions of word lines 431E, 432E, 433E, and 434E can partially cover the sidewalls of the large support 470. The large support 470 can include, for example, silicon oxide. The small support 460 and the large support 470 can be formed of the same material.

[0095] The large support member 470 can be located between the word line edge portions 331E, 332E, 333E, and 334E and the additional word line edge portions 431E, 432E, 433E, and 434E. The large support member 470 can simultaneously support the word line edge portions 331E, 332E, 333E, and 334E as well as the additional word line edge portions 431E, 432E, 433E, and 434E. The small support member 460 can respectively support the word line edge portions 331E, 332E, 333E, and 334E and the additional word line edge portions 431E, 432E, 433E, and 434E. The distance between the word line edge portions 331E, 332E, 333E, and 334E and the additional word line edge portions 431E, 432E, 433E, and 434E can be less than the length of the large support member 470 in the second direction D2.

[0096] The large support member 470 may have a larger dimension than the small support member 460. Here, the dimension may include at least one of diameter, width, and length.

[0097] The small support 460 and the large support 470 can be configured to support corresponding stepped structures on which contact plugs 441, 442, 443, and 444 land. Figure 6 In the middle, the small support 460 and the large support 470 can be disposed in the periphery of the word line stack 330 on which the contact plug 444 lands, while Figure 9A In this configuration, the small support 460 and the large support 470 can be configured to support corresponding stepped structures on which contact plugs 441, 442, 443, and 444 land. In this way, because the stepped structures are configured to be supported, the support effect of the word line stack 330 can be further improved.

[0098] Figure 9B yes Figure 9A In the modified example, the small support 460 and the large support 470 of the storage device 601 can be configured to support corresponding stepped structures on which contact plugs 441, 442, 443, and 444 are landed. The small support 460 and the large support 470 can support the word line edge portions 331E, 332E, 333E, and 334E on both sides of the word line. Figure 6 and Figure 9A In the middle, the small support 460 and the large support 470 can support the edge of the letter lines on one side of the letter line stack 330, while... Figure 9B In the middle, the small support 460 and the large support 470 can support the edge parts of the word lines on both sides of the word line stack 330.

[0099] According to an embodiment of the present invention, the support can prevent the letter lines from collapsing and prevent the edges of the letter lines from bending.

[0100] According to embodiments of the present invention, contact plugs and additional contact plugs can improve contact resistance and improve contact-not-open.

[0101] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A storage device, comprising: A word line stack comprising word lines alternately stacked in a vertical direction above a substrate, and having edge portions; At least one support member extends vertically in the direction of the word line stacking and supports the edge portion of the word line stack; A contact plug electrically connected to the word line at the edge portion of the word line stack; as well as An active layer, located between the word lines and oriented horizontally in the direction intersecting the word lines, The edge portion of the character line stack includes a first sidewall and a second sidewall parallel to the first sidewall, and The at least one support member supports at least one of the first sidewall and the second sidewall.

2. The storage device according to claim 1, wherein, Each of the first sidewall and the second sidewall includes at least one recessed surface that extends vertically in the direction of the word line stacking. The at least one recessed surface is in direct contact with the at least one support member.

3. The storage device according to claim 1, wherein, The at least one support member includes a dielectric pillar.

4. The storage device according to claim 1, wherein, The at least one support member comprises silicon oxide.

5. The storage device according to claim 1, further comprising: Bit lines, which are coupled to one side of the active layer, extend vertically in the direction of the word line stacking.

6. The storage device according to claim 1, further comprising: Storage nodes are each coupled to the other side of the active layer. The storage nodes are stacked vertically in the direction of the word line stacking.

7. The storage device according to claim 1, wherein, The edge portion of the word line stack has a stepped structure in the direction of word line stacking.

8. A storage device comprising: A word line stack comprising word lines alternately stacked in a direction perpendicular to a substrate, and comprising an edge portion and an additional edge portion parallel to the edge portion; At least one small support member extends vertically in the direction of the word line stacking and supports the edge portion and the additional edge portion respectively; At least one large support member extends vertically in the direction of the word line stacking and jointly supports the edge portion and the additional edge portion; Contact plugs, which are electrically connected to word lines in the edge portion; Additional contact plugs, which are electrically connected to word lines in the additional edge portion; as well as An active layer is located between the word lines and is horizontally oriented in the direction intersecting the word lines.

9. The storage device according to claim 8, wherein, The edge portion of the word line stack includes a first sidewall and a second sidewall parallel to the first sidewall, and The at least one small support member supports the first sidewall, and The at least one large support member supports the second sidewall.

10. The storage device according to claim 9, wherein, Each of the first sidewall and the second sidewall includes at least one first recessed surface and at least one second recessed surface extending vertically in the direction of the word line stacking.

11. The storage device according to claim 10, wherein, The at least one first recessed surface directly contacts the at least one small support member, and The at least one second recessed surface is in direct contact with the at least one large support member.

12. The storage device according to claim 9, wherein, The additional edge portion of the word line stack includes a third sidewall facing the second sidewall and a fourth sidewall parallel to the third sidewall, and The at least one small support member supports the fourth sidewall, and The at least one large support member supports the third sidewall.

13. The storage device according to claim 12, wherein, Each of the third and fourth sidewalls includes at least one third recessed surface and at least one fourth recessed surface extending vertically in the direction of the word line stacking, wherein the at least one third recessed surface directly contacts the at least one large support member, and the at least one fourth recessed surface directly contacts the at least one small support member.

14. The storage device according to claim 8, wherein, The at least one large support member has a larger size than the at least one small support member.

15. The storage device according to claim 8, wherein, The edge portion and the additional edge portion are coupled to each other via an interconnecting portion, and The distance between the edge portion and the additional edge portion is less than the length of the at least one large support member.

16. The storage device according to claim 8, wherein, The at least one small support and the at least one large support comprise silicon oxide.

17. The storage device according to claim 8, further comprising: Bit lines, which are coupled to one side of the active layer, extend vertically in the direction of the word line stacking.

18. The storage device according to claim 8, further comprising: Storage nodes are each coupled to the other side of the active layer. The storage nodes are stacked vertically in the direction of the word line stacking.

19. The storage device according to claim 8, wherein, The substrate includes peripheral circuitry for driving the word lines, wherein the peripheral circuitry is located at a level lower than or higher than the word line stack.

20. A storage device comprising: Multiple memory cells are vertically stacked above a substrate; and At least one support member extends vertically in the direction in which the storage cells are stacked. Each of the storage units includes: Bit lines, which are perpendicular to the substrate orientation; A capacitor, which is horizontally spaced from the bit line; An active layer, which is horizontally oriented between the bit line and the capacitor; and A character line, which is located on at least one of the upper and lower surfaces of the active layer, and extends horizontally in a direction intersecting the active layer. The edge portion of the word line in the storage cell is supported by the at least one support member. Wherein, the edge portion of the character line includes a first recessed sidewall and a second recessed sidewall parallel to the first recessed sidewall, and The at least one support member supports at least one of the first recessed sidewall and the second recessed sidewall.

21. The storage device of claim 20, further comprising: The contact plug lands on the edge portion of the word line.

22. The storage device according to claim 20, wherein, The at least one support member includes a dielectric pillar.

23. The storage device according to claim 20, wherein, The at least one support member comprises silicon oxide.

24. The storage device according to claim 20, wherein, Each of the aforementioned word lines includes: The word line portion is stacked vertically in the direction in which the storage cells are stacked; The first edge portion extends from both ends of the letter body portion; and The second edge portion extends from at least one of the first edge portions and is parallel to the at least one first edge portion. The at least one support member supports the at least one first edge portion and the second edge portion.

25. The storage device according to claim 24, wherein, The at least one support member further includes: At least one small support member, extending vertically in the direction of the overlapping letter lines, supports the at least one first edge portion and the second edge portion respectively; and At least one large support member extends vertically in the direction of the word lines stacking and jointly supports the at least one first edge portion and the second edge portion.

26. The storage device according to claim 24, wherein, The first edge portion and the second edge portion are formed in a stepped structure in the direction of the word line stacking.

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