An entropy source circuit layout structure of a multi-entropy source hardware true random number generator

Abstract

The invention discloses an entropy source circuit layout structure of a multi-entropy source hardware true random number generator, and relates to the technical field of semiconductor integrated circuits. The layout structure comprises: a P-type substrate and a plurality of independent N-type well regions on the surface of the P-type substrate, wherein a plurality of groups of independent entropy source circuits are respectively manufactured in each N-type well region, and the problem of mutual crosstalk between different entropy source circuits is physically fundamentally reduced; a P-type isolation well region is formed in each N-type well region, and the bottom and surrounding of the isolation well region are surrounded by the N-type well region to achieve isolation, and NMOS devices in the entropy source circuit are all isolation-type NMOS devices and are manufactured and formed in the isolation well region, and a second deep well region of the N-type well region and a first shallow well region of an annular shape are used to cooperate with each other to form a three-dimensional container, so that the P-type isolation well region can be enclosed inside, thereby physically blocking the direct contact between the P-type well region and the P-type substrate, and reducing the noise influence between different parts of the entropy source circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to an entropy source circuit layout structure of a multi-entropy source hardware true random number generator. Background Art

[0002] With the rapid development of information technology, how to ensure the secure transmission and storage of information has become increasingly important. The core of information security is cryptography. Generally, key encryption algorithms are used to encrypt the transmission and storage of information. In order to improve the unpredictability of keys, we use true random number generators (hereinafter referred to as TRNG). The TRNG chip contains multiple sets of entropy source circuits, and each entropy source circuit is composed of several logic gate circuits. The logic gate circuit contains P-type metal-oxide semiconductor field effect transistors (hereinafter referred to as PMOS) and N-type metal-oxide semiconductor field effect transistors (hereinafter referred to as NMOS). The entropy source circuit contains a ring oscillator, which will generate a lot of noise when working. Several sets of entropy source circuits will be designed and placed in the same chip. The ring oscillators in different entropy source circuits may resonate or interlock, such as Figure 1 As shown, the outputs of different entropy source circuits have a high correlation, and this high correlation will affect the quality of the true random numbers output by the entropy source circuit, thereby affecting the working performance of the overall circuit. Summary of the invention

[0003] In view of the above problems and technical requirements, the inventors have proposed an entropy source circuit layout structure of a multi-entropy source hardware true random number generator. The technical solution of the present invention is as follows:

[0004] An entropy source circuit layout structure of a multi-entropy source hardware true random number generator comprises a P-type substrate and a plurality of independent N-type well regions on the surface of the P-type substrate, wherein a P-type isolation well region is formed in each N-type well region, and the bottom and surrounding of the isolation well region are surrounded by N-type well regions to achieve isolation; a plurality of groups of independent entropy source circuits are respectively fabricated in each N-type well region, NMOS devices in the entropy source circuits are all isolation-type NMOS devices, and the isolation-type NMOS devices are fabricated in the isolation well region in the N-type well region, and the PMOS devices in the entropy source circuits are fabricated in the region of the N-type well region excluding the isolation well region.

[0005] Its further technical solution is that each N-type well region includes a first shallow well region and a second deep well region, the first shallow well region is in a ring structure surrounding the outside of the second deep well region, and the well region depth of the first shallow well region is smaller than that of the second deep well region; the isolation well region in each N-type well region is formed at the second deep well region, and the well region depth of the isolation well region is smaller than that of the second deep well region, and the second deep well region at the bottom of the isolation well region isolates the isolation well region from the P-type substrate.

[0006] A further technical solution is that the circumferential dimension of the isolation well region is smaller than the circumferential dimension of the second deep well region, and the well region depth of the isolation well region is equal to the well region depth of the first shallow well region.

[0007] A further technical solution is that different N-type well regions are isolated through P-type well regions.

[0008] A further technical solution is that the sizes of the various N-type well regions are equal, or there are at least two N-type well regions with different sizes.

[0009] The beneficial technical effects of the present invention are:

[0010] The present invention discloses an entropy source circuit layout structure of a multi-entropy source hardware true random number generator, wherein an independent N-type well region is used for each group of entropy source circuits, and a P-type well region is used to insert between each independent N-type well region for isolation, so that the problem of crosstalk between different entropy source circuits can be reduced physically and fundamentally. At the same time, the NMOS devices used in each group of entropy source circuits all use isolated NMOS devices, and are made in an isolated well region inside the N-type well region, and a three-dimensional container is formed by using the second deep well region of the N-type well region and the first shallow well region of the annular region to cooperate with each other, so that the P-type isolated well region can be enclosed inside, thereby physically blocking the direct contact between the P-type well region and the P-type substrate, avoiding the problem of interference from the P-type substrate to the peripheral circuits and even the entire chip when some circuits in the circuit generate noise, and further optimizing the normal working performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is the entropy source circuit layout structure of a multi-entropy source hardware true random number generator according to an embodiment of the present application.

[0012] Figure 2 yes Figure 1 The entropy source circuit layout structure of the comparative example of the illustrated embodiment.

[0013] Figure 3 It is a schematic diagram of the vertical structure of the layout of a PMOS device and an isolated NMOS device in an entropy source circuit of a multi-entropy source hardware true random number generator according to an embodiment of the present application.

[0014] Figure 4 yes Figure 3 The illustrated embodiment is a comparative example and shows a schematic diagram of a vertical structure of a PMOS device and a common NMOS device in an entropy source circuit of a conventional true random number generator.

[0015] Figure 5 The structure of a ring oscillator inside a group of entropy source circuits in an example and a top view of the corresponding layout structure when the layout is designed based on the layout design principles of the present application.

[0016] Figure 6 In one example, when the structures of the ring oscillators in the four sets of entropy source circuits are all as follows Figure 5 As shown, a top view of the layout structure of the entropy source circuit layout structure of a multi-entropy source hardware true random number generator including four groups of entropy source circuits. DETAILED DESCRIPTION

[0017] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0018] In one embodiment, Figure 1 As shown, an entropy source circuit layout structure of a multi-entropy source hardware true random number generator is provided, wherein Figure 1 (a) is a top view of the entropy source circuit layout structure of the multi-entropy source hardware true random number generator. Figure 1 (b) is a cross-sectional view at AA' in (a). The layout structure includes: a P-type substrate and multiple independent N-type well regions on the surface of the P-type substrate, each N-type well region has a P-type isolation well region formed in it, and the bottom and surrounding of the isolation well region are surrounded by N-type well regions to achieve isolation from the outside.

[0019] In one embodiment, each N-type well region includes a first shallow well region and a second deep well region, the first shallow well region is in a ring structure surrounding the outside of the second deep well region, and the well region depth of the first shallow well region is less than that of the second deep well region. The isolation well region in each N-type well region is formed at the second deep well region, so that the isolation well region is surrounded by the first shallow well region on all sides to achieve isolation from the outside. The well region depth of the isolation well region is less than that of the second deep well region, so that the second deep well region at the bottom of the isolation well region isolates the isolation well region from the P-type substrate.

[0020] Further, such as Figure 1 As shown, the circumferential dimension of the isolation well region is smaller than the circumferential dimension of the second deep well region, and the well depth of the isolation well region is equal to the well depth of the first shallow well region. Thus, while the first shallow well region and the second deep well region isolate the isolation well region, the second deep well region overlaps with the first shallow well region around the isolation well region, forming a three-dimensional container similar to the outside of the isolation well region.

[0021] Each N-type well region is separated from each other, and several groups of independent entropy source circuits are respectively made in each N-type well region, such as Figure 1 In the embodiment shown, four groups of independent entropy source circuits are shown, and each group of entropy source circuits is fabricated in an N-type well region. In one embodiment, different N-type well regions are isolated by P-type well regions, such as Figure 1 shown.

[0022] The size of the N-type well region matches the circuit scale of the entropy source circuit, and the sizes of the various N-type well regions are equal, or there are at least two N-type well regions with different sizes.

[0023] Please refer to Figure 2 The comparative example shown is compared with Figure 1 The structure, Figure 2 In the embodiment, an entire N-type well region includes a plurality of second deep well regions and a first shallow well region surrounding and connected to each second deep well region. It can be considered that there are a plurality of connected N-type well regions. At this time, if each group of independent entropy source circuits is still made in the corresponding N-type well region, since each N-type well region is interconnected, the noise generated by each group of entropy sources will still interfere with each other. Figure 1 In the structure shown, each N-type well region is separated independently from each other, which can solve this problem.

[0024] Each group of entropy source circuits includes NMOS devices and PMOS devices. In the present application, the PMOS devices in the entropy source circuits are ordinary PMOS devices, while the NMOS devices are isolated NMOS devices. Figure 3 As shown, the isolated NMOS device in the entropy source circuit is made in an isolation well region in an N-type well region. The isolated NMOS device includes a P-type substrate, a P-type isolation well region, a second deep well region at the bottom of the isolation well region, an N-type heavily doped implantation region formed on the surface of the P-type isolation well region, and a polysilicon gate layer on the P-type isolation well region, and leads to the gate terminal (G), drain terminal (D), source terminal (S) and substrate terminal (B) of the isolated NMOS device.

[0025] The PMOS device in the entropy source circuit is fabricated in an area of ​​the N-type well region except the isolation well region. The PMOS device includes a P-type substrate, an area of ​​the N-type well region except the isolation well region, a P-type heavily doped implantation area formed on the surface of the N-type well region, and a polysilicon gate layer on an area of ​​the N-type well region except the isolation well region, and leads to a gate terminal (G), a drain terminal (D), a source terminal (S) and a substrate terminal (B) of the PMOS device.

[0026] The PMOS devices and the above-mentioned isolation type NMOS devices are formed alternately, so that the N-type wells of any two PMOS devices are isolated from each other through a common P-type well.

[0027] The present application adopts an isolated NMOS device, which uses one more level in the vertical structure of the layout compared to the ordinary NMOS device, namely the second deep well region at the bottom of the isolation well region. In order to more clearly illustrate the distinction between the isolated NMOS device and the ordinary NMOS device, the present application provides Figure 4 For comparison, please refer to Figure 4 and Figure 3. Specifically, PMOS devices with the same substrate potential are placed in the same N-type well, and NMOS devices with the same substrate potential are placed in the same P-type well. For PMOS devices, N-type wells with different substrate potentials can be isolated using the P-type wells of ordinary NMOS devices. For ordinary NMOS devices, P-type wells with different substrate potentials cannot be isolated by inserting an N-type well between multiple P-type wells; even if an N-type well is inserted between P-type wells with different substrate potentials, these P-type wells can be physically connected through the P-type substrate layer of the chip. Therefore, when part of the circuit generates noise, the P-type substrate of the chip will interfere with the peripheral circuits or even the entire chip, thereby affecting the normal working performance of the chip.

[0028] Therefore, by comparing the above embodiments with the comparative examples, it can be seen that the technical solution of the present invention is adopted, and an isolated NMOS device is adopted. Since it has a second deep well region at the bottom of the isolation well region more than the ordinary NMOS, the second deep well region can cooperate with the annular first deep well region to form a three-dimensional container, enclosing the P-type isolation well region therein, thereby physically blocking the direct contact between the P-type isolation well region and the P-type substrate.

[0029] In one example, the layout structure top view of the ring oscillator structure inside each group of entropy source circuits when the layout design is performed based on the layout design principle of the present application is as follows: Figure 5 As shown. Therefore, assuming that the structures of the ring oscillators in the four groups of entropy source circuits are the same, the top view of the entropy source circuit layout structure of the entire multi-entropy source hardware true random number generator is as follows: Figure 6 shown.

[0030] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. An entropy source circuit layout structure of a multi-entropy source hardware true random number generator, characterized in that: include: A P-type substrate and a plurality of independent N-type well regions on the surface of the P-type substrate, wherein different N-type well regions are isolated from each other by the P-type well regions; a P-type isolation well region is formed in each N-type well region, and the bottom and surrounding of the isolation well region are surrounded by the N-type well region to achieve isolation, thereby blocking the direct contact between the P-type isolation well region and the P-type substrate; A plurality of independent entropy source circuits are respectively fabricated in each of the N-type well regions, each of the entropy source circuits includes an NMOS device and a PMOS device, the NMOS devices in the entropy source circuits are all isolated NMOS devices, and the isolated NMOS devices are fabricated in an isolated well region in the N-type well region, the isolated NMOS device includes a P-type substrate, a P-type isolated well region, a second deep well region at the bottom of the isolated well region, an N-type heavily doped implantation region formed on the surface of the P-type isolated well region, and a polysilicon gate layer on the P-type isolated well region, and a gate of the isolated NMOS device is led out. The PMOS device in the entropy source circuit is fabricated in an area of ​​the N-type well region except the isolation well region, and the PMOS device comprises a P-type substrate, an area of ​​the N-type well region except the isolation well region, a P-type heavily doped implantation area formed on the surface of the N-type well region, and a polysilicon gate layer on an area of ​​the N-type well region except the isolation well region, and leads to a gate end, a drain end, a source end and a substrate end of the PMOS device; the PMOS device and the isolation-type NMOS device are alternately formed, so that the N-type wells of any two PMOS devices are isolated by the P-type well.

2. The entropy source circuit layout structure according to claim 1, characterized in that: Each N-type well region includes a first shallow well region and a second deep well region, wherein the first shallow well region is in a ring structure surrounding the outside of the second deep well region, and the well region depth of the first shallow well region is smaller than that of the second deep well region; The isolation well region in each N-type well region is formed at the second deep well region, and the well region depth of the isolation well region is smaller than that of the second deep well region. The second deep well region at the bottom of the isolation well region isolates the isolation well region from the P-type substrate.

3. The entropy source circuit layout structure according to claim 2, characterized in that: The circumferential dimension of the isolation well region is smaller than the circumferential dimension of the second deep well region, and the well region depth of the isolation well region is equal to the well region depth of the first shallow well region.

4. The entropy source circuit layout structure according to claim 1, characterized in that: The sizes of the N-type well regions are all equal, or there are at least two N-type well regions with different sizes.

Images