Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode disposed on the first dummy region; a second dummy electrode disposed on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an extension portion disposed on the device isolation layer, the extension portion having a width greater than a line width of a remaining portion of the power line; a power delivery network disposed on a bottom surface of the substrate; and a via extending through the substrate and the device isolation layer and electrically connecting the power delivery network to the extension portion. The via and the extension portion vertically overlap.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0133368, filed on October 15, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor. Background Technology

[0004] Semiconductor devices are essential components in the electronics industry due to their small size, versatility, and / or low cost. They can store data, process data, or both. As the electronics industry advances, the demand for semiconductor devices with improved characteristics continues to increase. For example, there is a growing need for semiconductor devices with high reliability, high performance, and / or versatility. To meet these demands, the complexity and / or integration density of semiconductor devices are increasing. Summary of the Invention

[0005] One or more example embodiments provide a highly integrated semiconductor device including a field-effect transistor with improved electrical characteristics.

[0006] According to one aspect of an example embodiment, a semiconductor device includes: a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode disposed on the first dummy region; a second dummy electrode disposed on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an extension portion disposed on the device isolation layer, the width of the extension portion being greater than the linewidth of the remaining portion of the power line; a power delivery network disposed on a bottom surface of the substrate; and a via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the extension portion. The via and the extension portion vertically overlap.

[0007] According to one aspect of an exemplary embodiment, a semiconductor device includes: a substrate; first and second power lines disposed on the substrate, the first and second power lines being alternately arranged in a first direction and extending in a second direction; a first tap unit disposed on a first tap unit track on the substrate, the first tap unit track extending in the first direction; a second tap unit disposed on a second tap unit track on the substrate, the second tap unit track extending in the first direction; a logic unit disposed on the substrate between the first and second tap unit tracks; and a power delivery network disposed on a bottom surface of the substrate. The first and second tap unit tracks are spaced apart from each other in the second direction. Each of the first tap units includes a first through-hole extending through the substrate and electrically connecting the power delivery network to a corresponding one of the first power lines, and each of the second tap units includes a second through-hole extending through the substrate and electrically connecting the power delivery network to a corresponding one of the second power lines.

[0008] According to one aspect of an example embodiment, a semiconductor device includes: logic cells and tap cells arranged two-dimensionally on a substrate; a first metal layer disposed on the logic cells and tap cells; a second metal layer disposed on the first metal layer; and a power transmission network disposed on a bottom surface of the substrate. The first logic cell, as one of the logic cells, includes: a first active region and a second active region; a gate electrode disposed on the first active region and the second active region; an active contact adjacent to the gate electrode; and a gate contact electrically coupled to the gate electrode. The first tap cell, as one of the tap cells and adjacent to the first logic cell, includes: a first dummy region adjacent to the first active region; a second dummy region adjacent to the second active region; a dummy electrode disposed on the first dummy region and the second dummy region; and a via extending vertically through the substrate from the power transmission network. The first metal layer includes a first power line and a second power line extending parallel across the first logic cell and the first tap cell, and the power transmission network and the first power line are electrically connected to each other through the via in the first tap cell. Attached Figure Description

[0009] The above and other aspects, features, and advantages will become clearer through the following detailed description taken in conjunction with the accompanying drawings:

[0010] Figures 1 to 3 This is a conceptual diagram illustrating the logic unit of a semiconductor device according to an example embodiment.

[0011] Figure 4 This is a plan view illustrating logic cells and tap cells in a semiconductor device according to an example embodiment.

[0012] Figure 5 This is a plan view showing the detailed structure of the first logic unit according to an example embodiment.

[0013] Figure 6A , Figure 6B , Figure 6C and Figure 6D According to the example embodiments, respectively along Figure 5 The cross-sectional views taken from lines A-A', B-B', C-C', and D-D'.

[0014] Figure 7 This illustrates an example embodiment. Figure 4 A detailed plan view of the tap unit structure.

[0015] Figure 8A and Figure 8B According to the example embodiments, respectively along Figure 7 The cross-sectional view taken from lines A-A' and B-B'.

[0016] Figure 9 According to the example embodiment Figure 8B Enlarged cross-sectional view of part M.

[0017] Figures 10 to 12 This is a plan view showing the tap unit according to an example embodiment.

[0018] Figure 13 This illustrates an example embodiment. Figure 4 A detailed plan view of the tap unit structure.

[0019] Figure 14 According to the example embodiment along Figure 13 A cross-sectional view taken from line A-A'.

[0020] Figures 15 to 17 This illustrates an example embodiment. Figure 13 A plan view of the hybrid tap unit.

[0021] Figure 18 This is a plan view illustrating logic cells and tap cells in a semiconductor device according to an example embodiment.

[0022] Figure 19 This illustrates an example embodiment. Figure 18 A detailed plan view of the tap unit structure.

[0023] Figure 20 According to the example embodiment along Figure 19 A cross-sectional view taken from line A-A'.

[0024] Figure 21 This illustrates an example embodiment. Figure 18A detailed plan view of the tap unit structure.

[0025] Figure 22 According to the example embodiment along Figure 21 A cross-sectional view taken from line A-A'.

[0026] Figure 23 This illustrates an example embodiment. Figure 18 A detailed plan view of the tap unit structure.

[0027] Figure 24 and Figure 25 This is a plan view illustrating a method for designing a semiconductor device according to an example embodiment.

[0028] Figures 26 to 28 Each is a plan view showing the relative arrangement of tapped units and logic units in a semiconductor device according to an example embodiment.

[0029] Figure 29A and Figure 29B This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0030] Figure 30A , Figure 30B , Figure 30C and Figure 30D This illustrates the semiconductor device according to an example embodiment, with each edge... Figure 5 The cross-sectional views taken from lines A-A', B-B', C-C', and D-D'.

[0031] Figure 31 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0032] Figure 32 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0033] Figure 33 According to the example embodiment along Figure 32 A cross-sectional view taken from line A-A'.

[0034] Figure 34 This illustrates the example embodiment along... Figure 32 Another example of a cross-sectional view of a vertical section taken by line A-A'. Detailed Implementation

[0035] Figure 1 , Figure 2 and Figure 3 This is a conceptual diagram illustrating the logic unit of a semiconductor device according to an example embodiment.

[0036] Reference Figure 1A single-height cell (SHC) can be provided. Specifically, a first electric field line M1_R1 and a second electric field line M1_R2 can be disposed on the substrate 100. The first electric field line M1_R1 can be a conduction path for providing a drain voltage VDD (e.g., a power supply voltage). The second electric field line M1_R2 can be a conduction path for providing a source voltage VSS (e.g., ground voltage).

[0037] A single-height cell SHC can be defined between a first power line M1_R1 and a second power line M1_R2. The single-height cell SHC can include a first active region PR and a second active region NR. For example, the first active region PR can be a PMOSFET region, and the second active region NR can be an NMOSFET region. In other words, the single-height cell SHC can have a CMOS structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0038] Each of the first active region PR and the second active region NR may have a first width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first electric field line M1_R1 and the second electric field line M1_R2.

[0039] A single-height cell (SHC) can constitute a single logic cell. A logic cell can represent a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic cell can include transistors that constitute the logic device and interconnects that connect the transistors to each other.

[0040] Reference Figure 2 A dual-height cell DHC can be provided. Specifically, a first electric field line M1_R1, a second electric field line M1_R2, and a third electric field line M1_R3 can be disposed on the substrate 100. The first electric field line M1_R1 can be disposed between the second electric field line M1_R2 and the third electric field line M1_R3. The third electric field line M1_R3 can be a conduction path for which the source voltage VSS is provided.

[0041] The dual-height cell (DHC) can be defined between the second power line M1_R2 and the third power line M1_R3. The dual-height cell (DHC) may include a first active region PR1 and PR2 and a second active region NR1 and NR2.

[0042] The second active region NR1 can be located near the second power line M1_R2. The second active region NR2 can be located near the third power line M1_R3. The first active regions PR1 and PR2 can be located near opposite sides of the first power line M1_R1, respectively. When viewed in a plan view, the first power line M1_R1 can be located between the first active regions PR1 and PR2.

[0043] The length of the dual-height unit DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be... Figure 1 The first height HE1 is approximately twice that of the first height. The first active regions PR1 and PR2 of the dual-height cell DHC can be combined to serve as a single PMOSFET region. Therefore, the channel size of the PMOS transistor in the dual-height cell DHC can be larger than that of the previously referenced… Figure 1 The channel dimensions of the PMOS transistor in the single-height cell SHC are described.

[0044] For example, the channel size of the PMOS transistor in a dual-height cell DHC can be approximately twice that of the PMOS transistor in a single-height cell SHC. In this case, the dual-height cell DHC can operate at a higher speed than the single-height cell SHC. In the example embodiment, Figure 2 The dual-height unit DHC shown can be defined as a multi-height unit. Although a dual-height unit DHC is shown, the example embodiment is not limited thereto, and a multi-height unit may include a tri-height unit whose unit height is approximately three times that of a single-height unit SHC.

[0045] Reference Figure 3 A first single-height cell SHC1, a second single-height cell SHC2, and a double-height cell DHC can be disposed on the substrate 100. The first single-height cell SHC1 can be disposed between the first electric field line M1_R1 and the second electric field line M1_R2. The second single-height cell SHC2 can be disposed between the first electric field line M1_R1 and the third electric field line M1_R3. The second single-height cell SHC2 can be adjacent to the first single-height cell SHC1 in the first direction D1.

[0046] The dual-height unit DHC can be located between the second power line M1_R2 and the third power line M1_R3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second direction D2.

[0047] The partition structure DB can be set between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The active region of the dual-height unit DHC can be electrically separated from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2 through the partition structure DB.

[0048] Figure 4 This is a plan view illustrating logic cells and tap cells in a semiconductor device according to an example embodiment. (Refer to...) Figure 4 The first logic unit LC1, the second logic unit LC2, and the tap unit TC can be arranged two-dimensionally on the substrate 100. Specifically, the first logic unit LC1 can be configured to replace... Figure 3 The first single-height unit SHC1 and the second logic unit LC2 can be set to replace Figure 3 The second single-height unit SHC2, the tap unit TC can be set to replace Figure 3 The dual-height unit DHC.

[0049] The tap unit TC can be used to apply a voltage from the power transmission network described below to at least one of the first power line M1_R1 and the third power line M1_R3. Compared to the first logic unit LC1 and the second logic unit LC2, the tap unit TC may not include any logic devices. That is, the tap unit TC can be configured to apply voltage to the power line, but it can be a dummy unit that is not used as a circuit element.

[0050] like Figure 4 As shown, the tap unit TC can be disposed in the cell region where logic units are disposed or between logic units. The relative arrangement of the tap unit TC, the first logic unit LC1, and the second logic unit LC2 is not limited to... Figure 4 The example shown can be modified in various ways.

[0051] Figure 5 It is shown Figure 4 A plan view of the detailed structure of the first logic unit. Figures 6A to 6D They are respectively along Figure 5 The cross-sectional views are taken from lines A-A', B-B', C-C', and D-D'. Referring to these views below... Figure 5 and Figures 6A to 6D The first logic unit LC1 is described in more detail.

[0052] The substrate 100 may include a first active region PR and a second active region NR. In an example embodiment, the first active region PR may be a PMOSFET region, and the second active region NR may be an NMOSFET region. The substrate 100 may be a semiconductor substrate formed of silicon, germanium, silicon-germanium, compound semiconductor materials, etc., or may be a semiconductor substrate including silicon, germanium, silicon-germanium, compound semiconductor materials, etc. As an example, the substrate 100 may be a silicon wafer.

[0053] A first active region PR and a second active region NR can be defined by a second trench TR2 formed in the upper portion of the substrate 100. The second trench TR2 can be located between the first active region PR and the second active region NR. The first active region PR and the second active region NR can be spaced apart from each other in a first direction D1, and the second trench TR2 is interposed between them. Each of the first active region PR and the second active region NR can extend in a second direction D2, which is different from the first direction D1.

[0054] A first active pattern AP1 and a second active pattern AP2 can be disposed on a first active region PR and a second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 can extend parallel to each other in a second direction D2. The first active pattern AP1 and the second active pattern AP2 can be vertical protrusions of the substrate 100. A first trench TR1 can be defined between adjacent first active patterns AP1 in the first active pattern AP1 and between adjacent second active patterns AP2 in the second active pattern AP2. The first trench TR1 can be shallower than the second trench TR2.

[0055] The device isolation layer ST can fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be formed of silicon oxide or may include silicon oxide. The upper portion of the first active pattern AP1 and the second active pattern AP2 can be in the device isolation layer ST (e.g., see...). Figure 6D The upper part of the first active pattern AP1 and the second active pattern AP2 can be a fin-shaped pattern. The device isolation layer ST may not cover the upper part of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may not cover the upper surface of the first active pattern AP1 and the second active pattern AP2.

[0056] A first source / drain pattern SD1 can be disposed on the upper part of a first active pattern AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be interposed between each pair of first source / drain patterns SD1. A second source / drain pattern SD2 can be disposed on the upper part of a second active pattern AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type). A second channel pattern CH2 can be interposed between each pair of second source / drain patterns SD2.

[0057] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selected epitaxial growth process. As an example, the first source / drain pattern SD1 and the second source / drain pattern SD2 can have top surfaces that are coplanar with the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. As another example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0058] The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the substrate 100. Therefore, the first source / drain pattern SD1 may apply compressive stress to the first channel pattern CH1. As an example, the second source / drain pattern SD2 may be formed of the same semiconductor material as the substrate 100 (e.g., Si), or may comprise the same semiconductor material as the substrate 100 (e.g., Si).

[0059] The gate electrode GE can be configured to intersect with the first active pattern AP1 and the second active pattern AP2, and extend in the first direction D1. The gate electrode GE can also extend in the second direction D2 (e.g., see...). Figure 5 The gate electrodes GE are arranged at a first pitch P1. The gate electrodes GE can be vertically overlapped with the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE can be configured to face the top surface and the opposite side surface of each of the first channel pattern CH1 and the second channel pattern CH2.

[0060] Reference Figure 6DThe gate electrode GE can be disposed on the first top surface TS1 of the first channel pattern CH1 and on at least one first side surface SW1 of the first channel pattern CH1. The gate electrode GE can be disposed on the second top surface TS2 of the second channel pattern CH2 and on at least one second side surface SW2 of the second channel pattern CH2. In other words, the transistor can be a three-dimensional field-effect transistor (e.g., FinFET), in which the gate electrode GE is configured to surround the channel patterns CH1 and CH2 in three dimensions.

[0061] Reference Figure 5 and Figures 6A to 6D A pair of gate spacers GS can be disposed on opposite side surfaces of each of the gate electrodes GE. The gate spacers GS can extend along the gate electrodes GE in a first direction D1. The top surface of the gate spacers GS can be higher than the top surface of the gate electrodes GE. The top surface of the gate spacers GS can be coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. The gate spacers GS can be formed of at least one of SiCN, SiCON, and SiN, or include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers GS can be a multilayer structure including at least two of SiCN, SiCON, and SiN.

[0062] A gate cap pattern GP may be disposed on each of the gate electrodes GE. The gate cap pattern GP may extend along the gate electrode GE in a first direction D1. The gate cap pattern GP may be formed of a material having etch selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below, or may include a material having etch selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. Specifically, the gate cap pattern GP may be formed of at least one of SiON, SiCN, SiCON, and SiN, or may include at least one of SiON, SiCN, SiCON, and SiN.

[0063] A gate dielectric pattern GI can be interposed between the gate electrode GE and the first active pattern AP1, and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI can extend along the bottom surface of the gate electrode GE disposed thereon. As an example, the gate dielectric pattern GI can cover the first top surface TS1 and the first side surface SW1 of the first channel pattern CH1. The gate dielectric pattern GI can cover the second top surface TS2 and the second side surface SW2 of the second channel pattern CH2. The gate dielectric pattern GI can cover the top surface of the device isolation layer ST beneath the gate electrode GE (e.g., see...). Figure 6D ).

[0064] In an example embodiment, the gate dielectric pattern GI may be formed of a high-k dielectric material with a dielectric constant higher than that of the silicon oxide layer, or may include a high-k dielectric material with a dielectric constant higher than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0065] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate dielectric pattern GI to be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be achieved.

[0066] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include at least one metallic material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). The first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked work function metal layers.

[0067] The second metal pattern may include a metallic material with a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0068] Reference Figure 6D The dicing pattern CT can be disposed at both ends of the gate electrode GE. The dicing pattern CT can separate the gate electrode GE of the first logic unit LC1 from the gate electrode of the adjacent second logic unit LC2. The dicing pattern CT can be formed of at least one of insulating materials (e.g., silicon oxide and / or silicon nitride) or can include at least one of insulating materials (e.g., silicon oxide and / or silicon nitride).

[0069] A first interlayer insulating layer 110 may be disposed on a substrate 100. The first interlayer insulating layer 110 may cover a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate cap pattern GP. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In an exemplary embodiment, at least one of the first to fourth interlayer insulating layers 140 may be formed of silicon oxide or may include silicon oxide.

[0070] A pair of partition structures DB, which are opposite each other in the second direction D2, can be set on the opposite boundary of the first logic cell LC1. The partition structure DB can extend parallel to the gate electrode GE in the first direction D1.

[0071] The partition structure DB can pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The partition structure DB can pass through the upper part of each of the first active pattern AP1 and the second active pattern AP2. The partition structure DB can separate the active regions PR and NR of the first logic cell LC1 from the active regions of adjacent logic cells.

[0072] Active contact AC can pass through the first interlayer insulation layer 110 and the second interlayer insulation layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the active contact AC of the first logic cell LC1 can be disposed between the gate electrode GE and the partition structure DB. The active contact AC can extend in the first direction D1 to connect the second source / drain pattern SD2 to the first source / drain pattern SD1 (e.g., see...). Figure 6C ).

[0073] The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed using a gate cap pattern GP and a gate spacer GS via a self-aligned process. For example, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. The active contact AC can be configured to cover a portion of the top surface of the gate cap pattern GP.

[0074] A silicide pattern SC can be inserted between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 via the silicide pattern SC. The silicide pattern SC can be formed of at least one of a metal silicide material (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide) or can include at least one of a metal silicide material (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide).

[0075] The gate contact GC can pass through the second interlayer insulating layer 120 and the gate cap pattern GP, ​​and can be electrically connected to the gate electrode GE, respectively. (Refer to...) Figure 6A The area on each active contact AC located near the gate contact GC can be filled with an insulating pattern UIP. Therefore, it is possible to prevent the gate contact GC from contacting the adjacent active contact AC, thereby preventing short circuit problems.

[0076] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM. The conductive pattern FM may be formed of at least one metallic material (e.g., aluminum, copper, tungsten, molybdenum, or cobalt) or may include at least one metallic material (e.g., aluminum, copper, tungsten, molybdenum, or cobalt). The blocking pattern BM may cover the side and bottom surfaces of the conductive pattern FM. The blocking pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum, or may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may be formed of at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN), or may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0077] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. The first metal layer M1 of the first logic unit LC1 may include a first power line M1_R1, a second power line M1_R2, and a first interconnect line M1_I located between them.

[0078] Each of the first power line M1_R1 and the second power line M1_R2 may extend in the second direction D2 to intersect with the first logic cell LC1. A first interconnect M1_I may be disposed between the first power line M1_R1 and the second power line M1_R2. Each of the first interconnect M1_I may be a linear or strip pattern extending in the second direction D2.

[0079] The first metal layer M1 may further include first vias VI1. Each of the first vias VI1 may be disposed below an interconnect of the first metal layer M1. For example, a first via VI1 may be inserted between an active contact AC and a first interconnect M1_I to electrically connect them to each other. A first via VI1 may be inserted between an active contact AC and a power line M1_R1 or M1_R2 to electrically connect them to each other. A first via VI1 may be inserted between a gate contact GC and a first interconnect M1_I to electrically connect them to each other.

[0080] In an example embodiment, the interconnects of the first metal layer M1 can be formed separately using a different process than that used for the first via VI1 beneath the interconnects of the first metal layer M1. For example, the interconnects of the first metal layer M1 and the first via VI1 can be formed using separate single damascene processes. The semiconductor device according to this embodiment can be fabricated using a sub-20 nanometer (nm) process.

[0081] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include second interconnect lines M2_I. Each of the second interconnect lines M2_I in the second metal layer M2 may be a linear or strip pattern extending in the first direction D1. In other words, the second interconnect lines M2_I may extend in the first direction D1 and be parallel to each other.

[0082] The second metal layer M2 may further include second vias VI2. Each of the second vias VI2 may be disposed below the second interconnect M2_I. For example, the second interconnect M2_I may be electrically connected to the first interconnect M1_I through the second vias VI2.

[0083] As an example, the second interconnect M2_I of the second metal layer M2 and the second via VI2 below it can be formed simultaneously using the same process. For instance, the second interconnect M2_I and the second via VI2 of the second metal layer M2 can be formed together using a dual damascene process.

[0084] The interconnects of the first metal layer M1 may be formed of a conductive material that is the same as or different from the conductive material of the second metal layer M2, or may include a conductive material that is the same as or different from the conductive material of the second metal layer M2. For example, the interconnects of the first metal layer M1 and the second metal layer M2 may be formed of at least one of aluminum, copper, tungsten, molybdenum, and cobalt, or may include at least one of aluminum, copper, tungsten, molybdenum, and cobalt. Multiple metal layers (e.g., M3, M4, M5, M6, M7, etc.) may be additionally stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers may include interconnects constituting a wiring structure.

[0085] A power delivery network (PDN) can be disposed on the bottom surface of the substrate 100. The PDN may include a fifth interlayer insulating layer 150 and a sixth interlayer insulating layer 160 sequentially stacked on the bottom surface of the substrate 100.

[0086] The power transmission network (PDN) may also include a first lower interconnect LM1 and a second lower interconnect LM2. The first lower interconnect LM1 may be disposed in the fifth interlayer insulation layer 150, and the second lower interconnect LM2 may be disposed in the sixth interlayer insulation layer 160. A lower via LVI may be disposed between the first lower interconnect LM1 and the second lower interconnect LM2.

[0087] A power transmission network (PDN) can be configured to apply voltage to the first power line M1_R1 and the second power line M1_R2. A lower metal layer can be additionally disposed below the sixth interlayer insulation layer 160.

[0088] Figure 7 This illustrates an example embodiment. Figure 4 A detailed plan view of the tap unit structure. Figure 8A and Figure 8B They are respectively along Figure 7 The cross-sectional view taken from lines A-A' and B-B'. Figure 9 yes Figure 8B An enlarged cross-sectional view of part M. Referring to the following text... Figure 7 , Figure 8A and Figure 8B The tap unit TC will be described in more detail below. Some features of the tap unit TC that overlap with the first logic unit LC1 may be omitted in the following description.

[0089] The tap unit TC may include at least one first dummy region PRd and a second dummy region NRd. The first dummy region PRd may be structurally identical to the first active region PR on the substrate 100, but may not constitute a logic circuit. The second dummy region NRd may be structurally identical to the second active region NR on the substrate 100, but may not constitute a logic circuit.

[0090] The first dummy region PRd and the second dummy region NRd can be used as buffers between the tap unit TC and its adjacent logic units (e.g., LC1 and LC2). Due to the first dummy region PRd and the second dummy region NRd, the impact of the tap unit TC on adjacent logic units can be reduced.

[0091] The dummy electrode GEd can be disposed on the first dummy region PRd and the second dummy region NRd. The dummy electrode GEd can be arranged in the second direction D2 at a second pitch P2 (for example, see...). Figure 7The second pitch P2 can be substantially equal to the first pitch P1 between the gate electrodes GE. The dummy electrode GEd can include the same structure as the gate electrode GE described above, but may not be used as part of the circuit.

[0092] At least one of the active contacts AC can be disposed on at least one of the first dummy region PRd and the second dummy region NRd. At least one active contact AC in the tap unit TC may not be connected to the first metal layer M1. For example, at least one active contact AC in the tap unit TC may be a dummy active contact.

[0093] At least one of the power lines in the tap unit TC (e.g., the first power line M1_R1) may include an extension portion EXP. The first dummy region PRd and the second dummy region NRd may be spaced apart from the extension portion EXP by a specific distance. In other words, the extension portion EXP of the first power line M1_R1 may not overlap with the first dummy region PRd and the second dummy region NRd. The extension portion EXP of the first power line M1_R1 may be disposed on the device isolation layer ST that fills the second trench TR2.

[0094] Due to the extended portion EXP, the first electric field line M1_R1 can have an increased effective width in the first direction D1. Specifically, the extended portion EXP can have a first width W1 in the first direction D1 and a second width W2 in the second direction D2. The first width W1 can be equal to or different from the second width W2. As an example, the first width W1 can be less than the second width W2. The first width W1 can be 3 to 10 times the linewidth W3 of the first electric field line M1_R1. The first width W1 can be 1.5 to 7 times the first pitch P1. The second width W2 can be 2 to 8 times the first pitch P1.

[0095] The tap unit TC may include a via TVI that passes through the substrate 100 and extends from the power delivery network PDN to an extension EXP of the first power line M1_R1. The via TVI may be a cylindrical pattern extending in a vertical direction (e.g., third direction D3). The bottom surface of the via TVI may be connected to the first lower interconnect LM1. The top surface of the via TVI may be connected to the extension EXP of the first power line M1_R1. A via or contact may be inserted between the via TVI and the first lower interconnect LM1.

[0096] The first lower interconnect LM1 of the power transmission network PDN and the first power line M1_R1 of the first metal layer M1 can be electrically connected to each other via via TVI. In other words, voltage from the power transmission network PDN can be applied to the power line of the first metal layer M1 through via TVI. The tap unit TC can be a power tap unit configured to apply voltage from the power transmission network PDN to the power line of the first metal layer M1.

[0097] The via TVI can vertically overlap with the extended portion EXP. The via TVI can sequentially pass through the substrate 100, the device isolation layer ST filling the second trench TR2, and the first to third interlayer insulating layers 110, 120, and 130. The via TVI can be disposed between first dummy regions PRd that are adjacent to each other in the second direction D2. The via TVI can be disposed between second dummy regions NRd that are adjacent to each other in the first direction D1.

[0098] The via (TVI) can have a width that decreases as the distance from the power transmission network (PDN) increases or as the distance from the first metal layer (M1) decreases. The TVI can have a fourth width W4 at its bottom horizontal position and a fifth width W5 at its top horizontal position that is smaller than the fourth width W4. In an example embodiment, the fourth width W4 can be 1.2 to 2 times the fifth width W5. The TVI can have side surfaces that are inclined relative to the bottom surface of the substrate 100. The angle θ1 between the side surface of the TVI and the bottom surface of the substrate 100 can be in the range of 85° to 89.5°.

[0099] The via (TVI) may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM may be formed of at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt, or may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may be formed of at least one metal selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN), or may include at least one metal selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0100] Reference Figure 9 The first electric field line M1_R1 may include a blocking pattern BM and a conductive pattern FM. The conductive pattern FM may be disposed on the blocking pattern BM. The extended portion EXP of the first electric field line M1_R1 may include a recessed region RS disposed in its lower part. The recessed region RS may be recessed to a specific depth DEP from the bottom surface of the extended portion EXP.

[0101] The upper part of the via TVI can be disposed in the recessed region RS of the extended portion EXP. The top surface of the via TVI can contact the conductive pattern FM of the first electric field line M1_R1. In the recessed region RS, the blocking pattern BM of the via TVI can contact the conductive pattern FM of the first electric field line M1_R1.

[0102] The spacer ISP can be disposed on the side surface of the through-hole TVI. For example, the spacer ISP can be inserted between the through-hole TVI and the interlayer insulation layers 120 and 130. The spacer ISP may not be disposed in the recessed region RS. The spacer ISP may have a top surface that covers a portion of the blocking pattern BM of the first power line M1_R1.

[0103] The spacer ISP may include a liner LIL extending along the side surface of the through-hole TVI and a plurality of sector elements SLP protruding from the liner LIL. In other words, the spacer ISP in contact with the interlayer insulation layers 120 and 130 may have a non-flat or uneven surface.

[0104] The blocking pattern BM of the through-hole TVI can have a first thickness T1 on the side surface of the through-hole TVI and a second thickness T2 on the top surface of the through-hole TVI. The second thickness T2 can be greater than the first thickness T1. The second thickness T2 can be less than the depth DEP of the recessed region RS.

[0105] The liner LIL of the spacer ISP can have a third thickness T3. The third thickness T3 can be greater than the second thickness T2. The maximum width of the sector SLP of the spacer ISP can be a sixth width W6. The third thickness T3 can be 10 to 30 times the sixth width W6. The sixth width W6 can be less than the first thickness T1.

[0106] According to the example embodiment, power delivery lines can be omitted from the stacked metal layers M2, M3, M4, M5, M6, M7, etc., and the power delivery network (PDN) can be disposed on the bottom surface of the substrate 100. Therefore, the integration density of the semiconductor device can be increased, and the degree of freedom in constructing the wiring structure in the stacked metal layers M2, M3, M4, M5, M6, M7, etc. can be increased.

[0107] According to the example embodiment, the tap unit TC can be set in the cell region where the logic unit LC is provided, thus enabling the voltage from the power transmission network PDN to be stably applied to the power line. Furthermore, a dummy region PRd or NRd, serving as a buffer, can be set in the tap unit TC, thereby reducing the impact of the tap unit TC on the active regions PR or NR of the adjacent logic unit LC.

[0108] The power lines in the tap unit TC may include an extension portion EXP. Because the extension portion EXP is formed to have a width greater than that of the through-hole TVI, the relatively large-diameter through-hole TVI can be stably coupled to the power lines.

[0109] Figures 10 to 12 This illustrates an example embodiment. Figure 4 A plan view of the tapped unit. For brevity, refer to the previous... Figure 7 , Figure 8A and Figure 8B The described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0110] Reference Figure 10 The first power line M1_R1 in the tap unit TC may include a first extension portion EXP1 and a second extension portion EXP2. The first extension portion EXP1 and the second extension portion EXP2 may be adjacent to each other in the second direction D2. As shown, the first extension portion EXP1 and the second extension portion EXP2 may have the same size. However, the example embodiment is not limited to this, and the first extension portion EXP1 and the second extension portion EXP2 may have different sizes.

[0111] The first through-hole TVI1 can overlap with the first extended portion EXP1, and the second through-hole TVI2 can overlap with the second extended portion EXP2. For example... Figure 8A and Figure 8B As shown, the first via TVI1 can connect the power transmission network (PDN) to the first extension portion EXP1. Similarly, the second via TVI2 can connect the PDN to the second extension portion EXP2. The first distance S1 between the first extension portion EXP1 and the second extension portion EXP2 can be 0.8 to 10 times the second pitch P2 between the dummy electrodes GED.

[0112] Reference Figure 11 The first power line M1_R1, the second power line M1_R2, and the third power line M1_R3 in the tap unit TC may each include a first extension portion EXP1, a second extension portion EXP2, and a third extension portion EXP3. The first to third extension portions EXP1, EXP2, and EXP3 may be aligned with each other in the first direction D1. The first through-hole TVI1, the second through-hole TVI2, and the third through-hole TVI3 may overlap with the first, second, and third extension portions EXP1, EXP2, and EXP3, respectively. The first to third power lines M1_R1, M1_R2, and M1_R3 may be connected to the power transmission network PDN through the first to third through-holes TVI1, TVI2, and TVI3.

[0113] Reference Figure 12 At least two of the first to third extension portions EXP1, EXP2, and EXP3 may not be arranged in a straight line in the first direction D1. For example, the second extension portion EXP2 and the third extension portion EXP3 may be aligned with each other in the first direction D1, while the first extension portion EXP1 may be offset from each of the second extension portions EXP2 and the third extension portion EXP3 in the second direction D2. In other words, the first to third extension portions EXP1, EXP2, and EXP3 may be arranged in a zigzag or staggered pattern.

[0114] Figure 13 This illustrates an example embodiment. Figure 4 A detailed plan view of the tap unit structure. Figure 14 It is along Figure 13 The cross-sectional view taken by line A-A'. For a brief description, refer to the previous... Figure 7 , Figure 8A and Figure 8B The described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0115] Reference Figure 13 and Figure 14 The extended portion EXP of the first electric field line M1_R1 in the tap unit TC can have a seventh width W7 in the first direction D1 and an eighth width W8 in the second direction D2. The seventh width W7 and the eighth width W8 can each be greater than... Figure 7 The first width W1 and the second width W2.

[0116] As previously referred to Figure 1 The distance between the first electric field line M1_R1 and the second electric field line M1_R2 can be a first height HE1. The seventh width W7 can be 0.7 to 0.9 times the first height HE1. When the size of the extended portion EXP increases, the second dummy region NRd can be omitted from the region adjacent to the extended portion EXP in the first direction D1. The eighth width W8 can be 2.5 to 4 times the second pitch P2 between the dummy electrodes GEd.

[0117] The first well contact WC1 can be disposed on the first dummy region PRd, and the second well contact WC2 can be disposed on the second dummy region NRd. Each of the first well contact WC1 and the second well contact WC2 can be configured to have substantially the same structure and position as the active contact AC described above. Each of the first well contact WC1 and the second well contact WC2 can be used to apply voltage to the well region; in this sense, the well contacts WC1 and WC2 can differ from the active contact AC in terms of their function.

[0118] The first well contact WC1 can be disposed below the first electric field line M1_R1 and can extend in the first direction D1. The first electric field line M1_R1 and the first well contact WC1 can be connected to each other through at least one first via VI1 disposed between them. As a result, the voltage from the first electric field line M1_R1 can be applied to the well region in the substrate 100 through the first well contact WC1, the first source / drain pattern SD1, and the first active pattern AP1.

[0119] Each of the first dummy regions PRd can be, for example, a PMOSFET region. The first source / drain pattern SD1 on the first dummy region PRd can be n-type. The first active pattern AP1 and the substrate 100 located below the first source / drain pattern SD1 can be impurity regions used as n-wells. The drain voltage VDD from the power delivery network PDN can be applied to the first power line M1_R1 through the via TVI, and then the drain voltage VDD from the first power line M1_R1 can be applied to the n-well through the first well contact WC1.

[0120] The second well contact WC2 may be disposed below the second electric field line M1_R2 or the third electric field line M1_R3, and may extend in the first direction D1. Each of the second electric field line M1_R2 and the third electric field line M1_R3 may be connected to the second well contact WC2 through the first via VI1. The voltage from each of the second electric field line M1_R2 and the third electric field line M1_R3 may be applied to the well region in the substrate 100 through the second well contact WC2, the second source / drain pattern SD2, and the second active pattern AP2.

[0121] For example, each of the second dummy regions NRd can be an NMOSFET region. The second source / drain pattern SD2 on the second dummy region NRd can be p-type. The second active pattern AP2 located below the second source / drain pattern SD2 and the substrate 100 can be impurity regions used as p-wells. The source voltage VSS from each of the second power line M1_R2 and the third power line M1_R3 can be applied to the p-well through the second well contact WC2.

[0122] The tap unit TC may include not only power tap units configured to apply voltage from the power transmission network PDN to the power lines of the first metal layer M1, but also well tap units configured to apply voltage from the power lines of the first metal layer M1 to the well region. In other words, the tap unit TC may be a hybrid tap unit combining power taps and well taps.

[0123] Figures 15 to 17 This illustrates an example embodiment. Figure 13A plan view of an example of a hybrid tapped unit. (Refer to...) Figure 15 The extended portion EXP may have a shape protruding from the first electric field line M1_R1 toward the second electric field line M1_R2. The extended portion EXP may be located in the region between the first electric field line M1_R1 and the second electric field line M1_R2. The center line CTL of the first electric field line M1_R1 may be offset from the center point CTP of the extended portion EXP in the first direction D1. The through-hole TVI may overlap with the extended portion EXP. The through-hole TVI may not overlap with the center line CTL of the first electric field line M1_R1, and may be offset from the center line CTL.

[0124] Because the extended portion EXP is positioned closer to the second electric field line M1_R2, the distance from the second dummy region NRd adjacent to the third electric field line M1_R3 to the via TVI can be increased. Therefore, the second dummy region NRd adjacent to the third electric field line M1_R3 can extend continuously in the second direction D2 between the partition structures DB, without any area cut off by the extended portion EXP. A second well contact WC2 can be provided on the second dummy region NRd adjacent to the third electric field line M1_R3. The additional second well contact WC2 reduces the resistance between the third electric field line M1_R3 and the well region in the substrate 100.

[0125] Reference Figure 16 The first power line M1_R1 may include a first extension portion EXP1 protruding toward the second power line M1_R2, and the third power line M1_R3 may include a second extension portion EXP2 protruding toward the first power line M1_R1. The first through-hole TVI1 and the second through-hole TVI2 may overlap with the first extension portion EXP1 and the second extension portion EXP2, respectively.

[0126] Reference Figure 17 The tap unit TC can be a three-height unit disposed on the first power line M1_R1 to the fourth power line M1_R4. The first power line M1_R1 may include a first extension portion EXP1 protruding toward the second power line M1_R2, and the third power line M1_R3 may include a second extension portion EXP2 protruding toward the fourth power line M1_R4. The first through hole TVI1 and the second through hole TVI2 may overlap with the first extension portion EXP1 and the second extension portion EXP2, respectively.

[0127] The tap unit TC can be configured not only to apply voltage from the power delivery network (PDN) to the power lines, but also to apply voltage from the power lines to the well region in the substrate 100. Because a tap unit TC comprises two distinct units (i.e., a power tap unit and a well tap unit), the integration density of the semiconductor device can be increased.

[0128] Figure 18 This is a plan view illustrating logic cells and tap cells in a semiconductor device according to an example embodiment. (Refer to...) Figure 18 The first logic unit LC1, the second logic unit LC2, the third logic unit LC3, and the tap unit TC can be arranged two-dimensionally on the substrate 100. Specifically, each of the first to third logic units LC1, LC2, and LC3 can be a single-height unit. The tap unit TC can also be a single-height unit. The tap unit TC can be disposed on the first electric field line M1_R1 and the second electric field line M1_R2. The tap unit TC can be adjacent to the first logic unit LC1 in the second direction D2.

[0129] Figure 19 This illustrates an example embodiment. Figure 18 A detailed plan view of the tap unit structure. Figure 20 It is along Figure 19 The cross-sectional view taken by line A-A'. For a brief description, refer to the previous... Figure 7 , Figure 8A and Figure 8B The described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0130] Reference Figure 19 and Figure 20 , compared with previous references Figure 7 Compared to the described dual-height tap unit, the tap unit TC can be a single-height tap unit. The extension contact EAC can be disposed between the first power line M1_R1 and the device isolation layer ST. The extension contact EAC can extend from the first power line M1_R1 toward the second power line M1_R2.

[0131] The extended contact element EAC can be positioned at the same level as the active contact element AC described above. For example, the extended contact element EAC can be formed together with the active contact element AC. When viewed in a plan view, the width or size of the extended contact element EAC can be larger than the width or size of the active contact element AC.

[0132] The through-hole TVI can overlap with the extended contact EAC. The through-hole TVI extends from the power delivery network PDN to the bottom surface of the extended contact EAC. The extended contact EAC and the power delivery network PDN can be connected to each other via the through-hole TVI. The first power line M1_R1 on the extended contact EAC can be connected to the extended contact EAC via the first via VI1. As a result, voltage from the power delivery network PDN can be applied to the first power line M1_R1.

[0133] In the tap unit TC, the voltage from the power transmission network PDN is not directly applied to the power lines of the first metal layer M1. In the tap unit TC, the voltage can be applied to the power lines through the extended contact EAC and the first via VI1. In the tap unit TC, the voltage from the power transmission network PDN can be effectively applied to the power lines, despite the relatively small unit size of the tap unit TC (i.e., single height, rather than double height).

[0134] Figure 21 This illustrates an example embodiment. Figure 18 A detailed plan view of the tap unit structure. Figure 22 It is along Figure 21 The cross-sectional view taken by line A-A'. (Refer to...) Figure 21 and Figure 22 The first metal layer M1 may include a pad M1_P disposed between a first power line M1_R1 and a second power line M1_R2. A via TVI may overlap with the pad M1_P. The via TVI extends from the power delivery network (PDN) to the bottom surface of the pad M1_P. The pad M1_P and the power delivery network (PDN) can be connected to each other via the via TVI.

[0135] The second metal layer M2 may include an upper power line M2_R, which is disposed on the pad M1_P and extends to the area on the first power line M1_R1. The upper power line M2_R can be connected to the pad M1_P via a second via VI2. The upper power line M2_R can also be connected to the first power line M1_R1 via another second via VI2. In other words, the upper power line M2_R can be used as a bridge to connect the pad M1_P to the first power line M1_R1. As a result, voltage from the power delivery network PDN can be applied to the first power line M1_R1.

[0136] Figure 23 This illustrates an example embodiment. Figure 18 A detailed plan view of the tapped unit. (Refer to...) Figure 23 The first power line M1_R1 may include an extension EXP projecting toward the second power line M1_R2. A via TVI may overlap with the extension EXP. The extension EXP and the via TVI of the first power line M1_R1 may be consistent with previously referenced... Figure 15 The extended portion EXP of the first power line M1_R1 and the through-hole TVI are basically the same.

[0137] Figure 24 and Figure 25 This is a plan view illustrating a method for designing a semiconductor device according to an example embodiment. (Refer to...) Figure 24The semiconductor device, according to the example embodiment, can be manufactured based on the designed layout. A layout design tool can be used to generate the layout of the semiconductor device.

[0138] In detail, electric field lines M1_R1 and M1_R2 can be placed in this layout. Electric field lines M1_R1 and M1_R2 can include a first electric field line M1_R1 defining a conduction path for the drain voltage VDD and a second electric field line M1_R2 defining a conduction path for the source voltage VSS. The first electric field line M1_R1 and the second electric field line M1_R2 can be arranged alternately at a specific pitch in the first direction D1.

[0139] The tap unit TC can be placed on the first power line M1_R1 and the second power line M1_R2. The tap unit TC can be positioned at the location required to supply stable voltage to the first power line M1_R1 and the second power line M1_R2.

[0140] Reference Figure 25 Logic cells LC and fill cells FC can be placed on the first power line M1_R1 and the second power line M1_R2. Logic cells LC can be placed on the remaining area where no tap cells TC are set. Logic cells LC can be placed in this layout based on the designed circuitry. As an example, logic cells LC may include at least one single-height cell SHC, at least one double-height cell DHC, and at least one triple-height cell THC. Fill cells FC can fill the empty spaces between logic cells LC. Fill cells FC can be dummy cells.

[0141] Once the placement of the logic cells (LCs) is complete, wiring operations can be performed to connect the LCs to each other. Masks for each layer can be fabricated based on the layout with completed wiring, and the masks for each layer can then be used to implement conductor devices on the substrate.

[0142] Figures 26 to 28 This is a plan view showing the relative arrangement of tap cells and logic cells in a semiconductor device according to an example embodiment.

[0143] Reference Figure 26 The first electric field line M1_R1 and the second electric field line M1_R2 can be alternately arranged on the substrate 100 in the first direction D1. The first tap unit track TCR1, the second tap unit track TCR2, and the third tap unit track TCR3 can be defined on the substrate 100. Each of the first tap unit tracks to the third tap unit tracks TCR1, TCR2, and TCR3 can extend in the first direction D1. The first tap unit tracks to the third tap unit tracks TCR1, TCR2, and TCR3 can be arranged with a uniform pitch in the second direction D2.

[0144] Tap unit TC can be arranged in the first direction D1 on each of the first tap unit tracks TCR1, TCR2, and TCR3 to the third tap unit tracks TCR3. Each of the tap units TC may include, for example... Figure 7 tap unit TC or Figure 13 The hybrid tap unit TC.

[0145] The tap unit TC of the first tapped unit track TCR1 can be configured to apply voltage from the power transmission network PDN to the first power line M1_R1. The tap unit TC of the second tapped unit track TCR2 can be configured to apply voltage from the power transmission network PDN to the second power line M1_R2. The tap unit TC of the third tapped unit track TCR3 can be configured to apply voltage from the power transmission network PDN to the first power line M1_R1. However, the exemplary embodiment is not limited thereto; for example, the tap unit TC of the third tapped unit track TCR3 can be configured to apply voltage from the power transmission network PDN to another set of power lines (such as the third power line M1_R3).

[0146] Reference Figure 27 The tapping unit TC can be arranged on a first direction D1 on each of the first tapping unit tracks TCR1, TCR2, and TCR3 to the third tapping unit tracks TCR3. Each of the tapping units TC can be a single-height unit and can be, for example... Figure 19 , Figure 21 or Figure 23 Tap units TC. On each of the first tap unit tracks to the third tap unit tracks TCR1, TCR2 and TCR3, logic units LC or fill units FC can be inserted between tap units TC that are adjacent to each other on the first direction D1.

[0147] Reference Figure 28 The tap unit TC extending in the first direction D1 can be disposed on each of the first tap unit tracks to the third tap unit tracks TCR1, TCR2, and TCR3. The tap unit TC can be a multi-height unit and can include, for example... Figure 17 The tap unit TC.

[0148] Figure 29A This is a cross-sectional view showing a tap unit of a semiconductor device according to an example embodiment. (Refer to...) Figure 29A The power lines can be omitted from the first metal layer M1. Buried power lines BR1 and BR2 can be disposed in the substrate 100. Buried power lines BR1 and BR2 may include a first buried power line BR1 supplied with a drain voltage VDD and a second buried power line BR2 supplied with a source voltage VSS.

[0149] Each of the first buried power line BR1 and the second buried power line BR2 may include a lower portion buried in the substrate 100 and an upper portion buried in the device isolation layer ST that fills the second trench TR2.

[0150] Figure 29A The tap unit TC may include a through-hole TVI extending from the power transmission network PDN to the first buried power line BR1 and the second buried power line BR2, respectively. The first lower interconnect LM1 may be electrically connected to the first buried power line BR1 and the second buried power line BR2 through the through-hole TVI, respectively.

[0151] Figure 29B This is a cross-sectional view showing the logic cells of a semiconductor device according to an example embodiment. (Refer to...) Figure 29B The logic unit LC may include a through-hole TVI. The first lower interconnect LM1 can be electrically connected to the first buried power line BR1 and the second buried power line BR2 through the through-hole TVI of the logic unit LC.

[0152] The active contact AC may include a vertical protrusion VPP disposed between adjacent first active regions PR. The vertical protrusion VPP may be connected to a first embedded power line BR1. As a result, the drain voltage VDD from the power transmission network PDN can be applied to the first source / drain pattern SD1 through the via TVI, the first embedded power line BR1, and the vertical protrusion VPP of the active contact AC.

[0153] Figures 30A to 30D This illustrates the semiconductor device according to an example embodiment, with each edge... Figure 5 The cross-sectional views are taken from lines A-A', B-B', C-C', and D-D'. For brevity, refer to the previous description. Figure 5 and Figures 6A to 6D The described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0154] Reference Figure 5 and Figures 30A to 30D A first active region PR and a second active region NR can be disposed in the first logic cell LC1. A device isolation layer ST can be disposed on the substrate 100. The device isolation layer ST can define a first active pattern AP1 and a second active pattern AP2 in the upper part of the substrate 100. The first active pattern AP1 and the second active pattern AP2 can be disposed on the first active region PR and the second active region NR, respectively.

[0155] The first active pattern AP1 may include vertically stacked first channel patterns CH1. The stacked first channel patterns CH1 may be spaced apart from each other in the third direction D3. The stacked first channel patterns CH1 may vertically overlap each other. The second active pattern AP2 may include vertically stacked second channel patterns CH2. The stacked second channel patterns CH2 may be spaced apart from each other in the third direction D3. The stacked second channel patterns CH2 may vertically overlap each other. The first channel pattern CH1 and the second channel pattern CH2 may be formed of at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0156] The first active pattern AP1 may also include a first source / drain pattern SD1. A stacked first channel pattern CH1 may be inserted between each adjacent pair of first source / drain patterns SD1. The stacked first channel pattern CH1 can connect adjacent pairs of first source / drain patterns SD1 to each other.

[0157] The second active pattern AP2 may also include a second source / drain pattern SD2. A stacked second channel pattern CH2 may be inserted between each adjacent pair of second source / drain patterns SD2. The stacked second channel pattern CH2 can connect adjacent pairs of second source / drain patterns SD2 to each other.

[0158] The gate electrode GE can be configured to intersect with the first channel pattern CH1 and the second channel pattern CH2, and extend in the first direction D1. The gate electrode GE can vertically overlap with the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS can be disposed on opposite side surfaces of the gate electrode GE. A gate cap pattern GP can be disposed on the gate electrode GE.

[0159] The gate electrode GE can be configured to surround the first channel pattern CH1 and the second channel pattern CH2 (e.g., see...). Figure 30D Each of the first channel pattern CH1 and the second channel pattern CH2. For example, the gate electrode GE may be configured to face the top surface, bottom surface, and opposite side surface of each of the first channel pattern CH1 and the second channel pattern CH2. The transistor may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE is configured to surround the channel pattern CH1 or CH2 in three dimensions.

[0160] The gate dielectric pattern GI can be disposed between the gate electrode GE and each of the first channel pattern CH1 and the second channel pattern CH2. The gate dielectric pattern GI can surround each of the first channel pattern CH1 and the second channel pattern CH2.

[0161] An insulating pattern IP can be interposed on the second active region NR between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the gate dielectric pattern GI and the insulating pattern IP. In an example embodiment, the insulating pattern IP can be omitted on the first active region PR.

[0162] The active contact AC can pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 120 on the substrate 100, and is connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The gate contact GC can pass through the second interlayer insulating layer 120 and the gate cap pattern GP, ​​and is connected to the gate electrode GE. The first metal layer M1 can be disposed in the third interlayer insulating layer 130. The second metal layer M2 can be disposed in the fourth interlayer insulating layer 140.

[0163] Figure 31 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. (Refer to...) Figure 31 The semiconductor device may include vertical transistors (e.g., vertical FETs) and interconnects for connecting the vertical transistors to each other.

[0164] Specifically, the substrate 100 may include a first active region and a second active region NR. The active regions may be defined by trenches TR formed in the upper portion of the substrate 100. A lower epitaxial pattern SOP may be disposed on the second active region NR. The lower epitaxial pattern SOP may be an epitaxial pattern formed by selecting an epitaxial manufacturing process. The lower epitaxial pattern SOP may be disposed in the upper portion of the substrate 100.

[0165] An active pattern AP can be disposed on a second active region NR. The active pattern AP can be a vertically protruding fin-shaped pattern. When viewed in a plan view, the active pattern AP can be a strip-shaped pattern extending in a first direction D1. The active pattern AP can include a channel pattern CHP vertically protruding from a lower epitaxial pattern SOP and an upper epitaxial pattern DOP on the channel pattern CHP.

[0166] A device isolation layer ST can be disposed on the substrate 100 to fill the trench TR. The device isolation layer ST can cover the top surface of the lower epitaxial pattern SOP. The active pattern AP can protrude vertically above the device isolation layer ST.

[0167] The gate electrode GE can be disposed on the device isolation layer ST. The gate electrode GE can be configured to surround the channel pattern CHP of the active pattern AP. The gate dielectric pattern GI can be interposed between the gate electrode GE and the channel pattern CHP. The gate dielectric pattern GI can cover the bottom surface and the inner surface of the gate electrode GE. For example, the gate dielectric pattern GI can directly cover the side surface of the active pattern AP.

[0168] The upper epitaxial pattern DOP can protrude vertically above the gate electrode GE. The top surface of the gate electrode GE can be lower than the bottom surface of the upper epitaxial pattern DOP. In other words, the active pattern AP can protrude vertically from the substrate 100 and can have a structure that extends through the gate electrode GE.

[0169] Semiconductor devices may include vertical transistors in which charge carriers move along a third direction, D3. For example, when the transistor is turned on by a voltage applied to the gate electrode GE, charge carriers can move from the lower epitaxial pattern SOP to the upper epitaxial pattern DOP through the channel pattern CHP. The gate electrode GE may be configured to completely surround the side surface of the channel pattern CHP. The transistor may be a three-dimensional field-effect transistor (e.g., a VFET) with a gate-to-ring structure. Because the gate electrode is configured to completely surround the channel pattern, the semiconductor device can have excellent electrical characteristics.

[0170] The spacer SPC can be disposed on the device isolation layer ST to cover the gate electrode GE and the active pattern AP. The spacer SPC can contain a silicon nitride layer or a silicon oxynitride layer. The spacer SPC can include a lower spacer LS, an upper spacer US, and a gate spacer GS between the lower spacer LS and the upper spacer US.

[0171] The lower spacer LS can directly cover the top surface of the device isolation layer ST. The gate electrode GE can be spaced from the device isolation layer ST in the third direction D3 by the lower spacer LS. The gate spacer GS can cover the top and outer surfaces of each of the gate electrodes GE. The upper spacer US can also cover the upper epitaxial pattern DOP. However, the upper spacer US can not cover the top surface of the upper epitaxial pattern DOP, thus exposing the top surface of the upper epitaxial pattern DOP.

[0172] The first interlayer insulating layer 110 can be disposed on the spacer SPC. The top surface of the first interlayer insulating layer 110 can be substantially coplanar with the top surface of the upper epitaxial pattern DOP. The second to fourth interlayer insulating layers 120, 130 and 140 can be sequentially stacked on the first interlayer insulating layer 110. The second interlayer insulating layer 120 can cover the top surface of the upper epitaxial pattern DOP.

[0173] At least one first active contact AC1 can pass through the second interlayer insulating layer 120 and be coupled to the upper epitaxial pattern DOP. At least one second active contact AC2 can be configured to sequentially pass through the second interlayer insulating layer 120, the first interlayer insulating layer 110, the lower spacer LS, and the device isolation layer ST, and be coupled to the lower epitaxial pattern SOP. The gate contact GC can be configured to sequentially pass through the second interlayer insulating layer 120, the first interlayer insulating layer 110, and the gate spacer GS, and be coupled to the gate electrode GE. The top surfaces of the first active contact AC1, the second active contact AC2, and the gate contact GC can be substantially coplanar with the top surface of the second interlayer insulating layer 120. A first metal layer M1 can be disposed in the third interlayer insulating layer 130. A second metal layer M2 can be disposed in the fourth interlayer insulating layer 140.

[0174] The power delivery network (PDN) can be disposed on the bottom of the substrate 100. The PDN can be connected to the extension portion EXP of the first power line M1_R1 via a via TVI.

[0175] Figure 32 This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 33 It is along Figure 32 A cross-sectional view taken from line A-A'.

[0176] Reference Figure 32 and Figure 33 The tapping unit TC can be set on the first electric field line M1_R1 and the second electric field line M1_R2. The tapping unit TC can be arranged in the first direction D1 to form the tapping unit track TCR. For example, Figure 32 The tap unit TC of the tap unit track TCR can be configured to apply voltage from the power transmission network PDN to the first power line M1_R1.

[0177] The well region of a logic cell LC located on one side of the tapped unit track TCR can be separated from the well region of a logic cell LC located on the opposite side of the tapped unit track TCR. In other words, the well regions located on opposite sides of the tapped unit track TCR can be disconnected from each other through the tapped unit track TCR.

[0178] In order to apply a bias voltage to the well regions that are disconnected from each other by the tap unit tracks TCR, a first well tap unit WTC1 can be arranged on one side of the tap unit track TCR in the first direction D1. A second well tap unit WTC2 can be arranged on the opposite side of the tap unit track TCR in the first direction D1.

[0179] Reference Figure 33Each of the first well tap unit WTC1 and the second well tap unit WTC2 may include at least one well contact WC. In the first well tap unit WTC1, the well contact WC can be used to apply voltage to a first well region WR1 located on one side of the tap unit TC. In the second well tap unit WTC2, the well contact WC can be used to apply voltage to a second well region WR2 located on the opposite side of the tap unit TC.

[0180] Figure 34 It shows along Figure 32 Another example of a cross-sectional view of a vertical section intercepted by line A-A'. (Refer to...) Figure 34 The first well tap unit WTC1 and the second well tap unit WTC2 can be respectively disposed on two opposite sides of the tap unit TC. The tap unit TC may not include the second trench TR2 and the device isolation layer ST that fills the second trench TR2.

[0181] The via TVI can penetrate the substrate 100 and directly contact the first well region WR1 and the second well region WR2. The via TVI can also directly contact the first source / drain pattern SD1. As a result, not only can the well contact WC be used to apply voltage to well regions WR1 or WR2, but the via TVI can also be used to apply voltage to well regions WR1 or WR2. For example, voltage can be directly applied to well regions WR1 or WR2 through the via TVI.

[0182] In the semiconductor device according to the example embodiment, a power delivery network can be disposed on the bottom surface of the substrate, thereby increasing the integration density of the semiconductor device and improving the freedom of wiring structures in the stacked metal layers. The semiconductor device may also include tap units additionally disposed in the cell regions where logic cells are disposed, thus enabling the stable application of voltage from the power delivery network to the power lines. Dummy regions acting as buffers can be disposed in the tap units, thereby reducing the impact of the tap units on adjacent logic cells. According to the example embodiment, the power lines may include extensions that allow stable connection of vias to them.

[0183] Although exemplary embodiments have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate, comprising a first dummy region and a second dummy region spaced apart from the first dummy region; A device isolation layer is disposed in a trench between the first dummy region and the second dummy region; The first dummy electrode is disposed on the first dummy region; The second dummy electrode is disposed on the second dummy region; A power line extending from the first dummy region to the second dummy region, the power line including an extension portion disposed on the device isolation layer, the width of the extension portion being greater than the line width of the remaining portion of the power line; A power transmission network disposed on the bottom surface of the substrate; as well as Through-holes extend through the substrate and the device isolation layer, and electrically connect the power delivery network to the extension portion. The through hole and the extended portion overlap vertically.

2. The semiconductor device according to claim 1, wherein, The recessed area is formed in the bottom surface of the extended portion, and The upper part of the through hole is located in the recessed area.

3. The semiconductor device according to claim 2, wherein, The through-hole includes a conductive pattern and a blocking pattern surrounding the conductive pattern, and Wherein, the thickness of the blocking pattern at the top surface of the through hole located in the recessed region is less than the depth of the recessed region.

4. The semiconductor device according to claim 1, wherein, The first dummy electrode includes a plurality of first dummy electrodes arranged with a uniform pitch, and The width of the extended portion is 1.5 to 7 times the uniform pitch between the plurality of first dummy electrodes.

5. The semiconductor device of claim 1, further comprising a well contact connected to at least one of the first dummy region and the second dummy region. in, The trap contact is connected to the power line.

6. A semiconductor device, comprising: Substrate; A first electric field line and a second electric field line are disposed on the substrate, the first electric field line and the second electric field line are arranged alternately in a first direction and extend in a second direction; A first tap unit is disposed on a first tap unit track extending in the first direction on the substrate; A second tap unit is disposed on a second tap unit track extending in the first direction on the substrate; A logic unit is disposed on a substrate between the first tap unit track and the second tap unit track; as well as A power transmission network is disposed on the bottom surface of the substrate. The first tap unit track and the second tap unit track are spaced apart from each other in the second direction. Each of the first tap units includes a first through-hole extending through the substrate and electrically connecting the power delivery network to a corresponding line of the first power lines. Each of the second tap units includes a second through-hole that extends through the substrate and electrically connects the power delivery network to a corresponding one of the second power lines.

7. The semiconductor device according to claim 6, wherein, Each of the first power lines includes a first extension portion disposed on the first device isolation layer of the corresponding first tap unit. Each of the second power lines includes a second extension portion disposed on the second device isolation layer of the corresponding second tap unit. Wherein, the first through hole is connected to the first extension portion, and The second through hole is connected to the second extension portion.

8. The semiconductor device according to claim 6, wherein, One of the first tap units also includes: The first virtual region includes the first active pattern; The second virtual region includes the second active pattern; A device isolation layer is disposed in a trench between the first dummy region and the second dummy region; A first source / drain pattern is disposed on the first active pattern; and The second source / drain pattern is disposed on the second active pattern, and The first through-hole extends through the device isolation layer.

9. The semiconductor device according to claim 8, wherein, The first tap unit further includes a trap contact connected to one of the first source / drain pattern and the second source / drain pattern, and The trap contact is connected to one of the first power lines.

10. The semiconductor device of claim 6, further comprising a device isolation layer disposed on a substrate in a trench between adjacent active regions. in, Each of the first and second power lines includes an embedded power line embedded in the device isolation layer and extending in the second direction.

11. A semiconductor device, comprising: Logic cells and tap cells arranged in two dimensions on a substrate; A first metal layer is disposed on the logic unit and the tap unit; A second metal layer is disposed on the first metal layer; as well as A power transmission network is disposed on the bottom surface of the substrate. The first logical unit, which is one of the logical units, includes: First active region and second active region; A gate electrode is disposed on the first active region and the second active region; An active contact element adjacent to the gate electrode; and A gate contact, electrically coupled to the gate electrode, The first tap unit, which is one of the tap units and adjacent to the first logic unit, includes: The first virtual region is adjacent to the first active region; The second virtual region is adjacent to the second active region; A dummy electrode is disposed on the first dummy region and the second dummy region; and Through-holes that extend vertically from the power transmission network through the substrate. The first metal layer includes a first power line and a second power line extending parallel to each other across the first logic cell and the first tap cell, and The power transmission network and the first power line are electrically connected to each other through a through hole in the first tap unit.

12. The semiconductor device according to claim 11, wherein, The first power line includes an extension portion disposed on the first tap unit. Wherein, the through hole and the extended portion vertically overlap, and The through-hole extends from the power transmission network to the extension portion.

13. The semiconductor device according to claim 12, wherein, The width of the extended portion is 3 to 10 times the width of the first power line.

14. The semiconductor device according to claim 12, wherein, The gate electrode includes a plurality of gate electrodes arranged at a uniform pitch on the first active region and the second active region, and The width of the extended portion is 1.5 to 7 times the uniform pitch between the plurality of gate electrodes.

15. The semiconductor device of claim 11, further comprising a spacer disposed on a side surface of the through-hole. in, The spacer includes a liner extending along the side surface of the through-hole and a plurality of fan-shaped members projecting from the liner, and The thickness of the lining is 10 to 30 times the maximum width of the plurality of fan-shaped components.

16. The semiconductor device according to claim 11, wherein, The first tap unit further includes a device isolation layer disposed in a trench between the first dummy region and the second dummy region, and The via passes through the device's isolation layer.

17. The semiconductor device according to claim 11, wherein, The first tap unit further includes an extension contact, which is positioned at the same level as the active contact, and The extended contact electrically connects the first power line and the through hole.

18. The semiconductor device according to claim 11, wherein, The first metal layer includes pads disposed on the first tap unit. The second metal layer includes an upper power line disposed on the first tap unit. The via extends from the power transmission network to the pad, and The upper power line connects the pad to the first power line.

19. The semiconductor device according to claim 11, wherein, The first tap unit further includes a trap contact connected to the first dummy region, and The trap contact is connected to the first power line.

20. The semiconductor device according to claim 11, wherein, The first tap unit track and the second tap unit track are defined on the substrate and extend in a first direction. The second tap unit track is spaced apart from the first tap unit track in the second direction. The tap unit includes a second tap unit arranged along the track of the first tap unit in the first direction. The tap unit includes a third tap unit arranged along the track of the second tap unit in the first direction. The first power line includes multiple first power lines. The second power line includes multiple second power lines. Each of the second tap units is configured to electrically connect the power transmission network to a corresponding one of the plurality of first power lines, and Each of the third tap units is configured to electrically connect the power transmission network to a corresponding one of the plurality of second power lines.

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