Semiconductor device having a transistor device with a three-dimensional structure

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a bit line conductive layer provided on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate; first and second channel structures provided on the bit line conductive layer and spaced apart from each other in the first lateral direction; first and second gate dielectric layers provided on side surfaces of the first and second channel structures above the substrate; first and second gate line conductive layers provided on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers being adjacent to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate; and first and second storage node electrode layers provided above the first and second channel structures, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2020-0134536, filed on October 16, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a semiconductor device, and more specifically, to a semiconductor device having a transistor device having a three-dimensional structure. Background Technology

[0004] Recently, semiconductor devices with three-dimensional structures that depart from planar structures have been studied. These three-dimensional semiconductor devices can effectively address industry demands for reduced design size and increased integration density. In particular, research on three-dimensional structures has been actively pursued in the field of memory devices requiring high integration and high capacity. Summary of the Invention

[0005] A semiconductor device according to one aspect of this disclosure may include: a substrate; a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to the surface of the substrate; a first channel structure and a second channel structure disposed on the bit line conductive layer and spaced apart from each other in the first lateral direction; a first gate dielectric layer and a second gate dielectric layer disposed on side surfaces of the first channel structure and the second channel structure above the substrate; a first gate line conductive layer and a second gate line conductive layer respectively disposed on the first gate dielectric layer and the second gate dielectric layer, the first gate line conductive layer and the second gate line conductive layer being adjacent to the first channel structure and the second channel structure respectively in the first lateral direction and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate; and a first storage node electrode layer and a second storage node electrode layer respectively disposed above the first channel structure and the second channel structure. The first storage node electrode layer and the second storage node electrode layer are configured to be spaced apart from each other in a third lateral direction, which is not parallel to either the first lateral direction or the second lateral direction and is substantially parallel to the surface of the substrate.

[0006] In a method of manufacturing a semiconductor device according to one aspect of the present disclosure, a plurality of bit line structures extend on a substrate in a first lateral direction substantially parallel to the surface of the substrate and are spaced apart from each other in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate. Each of the plurality of bit line structures may include a bit line patterning layer and a first insulating layer disposed on the bit line patterning layer. A second insulating layer may be formed to fill the space above the substrate and between the plurality of bit line structures. A plurality of insulating line structures extending in the second lateral direction and spaced apart from each other in the first lateral direction may be formed by patterning the first insulating layer and the second insulating layer along the second lateral direction. A plurality of channel structures may be formed on the side surfaces of the plurality of insulating line structures. The plurality of channel structures may be disposed on the plurality of bit line conductive layers. A first dielectric material layer covering the plurality of channel structures and the plurality of insulating line structures may be formed above the substrate. A plurality of first gate line patterning layers may be formed above the first dielectric material layer, the first gate line patterning layers extending along the second lateral direction and adjacent to both sides of each of the plurality of insulating line structures. The plurality of insulating line structures above the substrate can be etched to selectively expose the plurality of channel structures and the first dielectric material layer. A second dielectric material layer can be formed to cover the exposed plurality of channel structures and the first dielectric material layer above the substrate. A plurality of second gate line pattern layers extending in the second lateral direction can be formed over the second dielectric material layer.

[0007] A semiconductor device according to another aspect of this disclosure may include: a substrate; a bit line conductive layer extending in a first lateral direction substantially parallel to the surface of the substrate; a first insulating wire structure extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate; a first channel structure and a second channel structure configured to contact a first side and a second side of the first insulating wire structure, respectively, and partially overlap the bit line conductive layer; a first gate dielectric layer and a second gate dielectric layer disposed above the substrate and on the side surfaces of the first channel structure and the second channel structure, respectively; and a first gate line conductive layer and a second gate line conductive layer extending above the substrate in the second lateral direction and respectively covering at least a portion of each of the first gate dielectric layer and the second gate dielectric layer.

[0008] In a method of manufacturing a semiconductor device according to another embodiment of the present disclosure, a plurality of bit line conductive layers may be formed extending on a substrate in a first lateral direction parallel to the surface of the substrate and spaced apart from each other in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate. A first insulating layer and a second insulating layer may be sequentially formed covering the plurality of bit line conductive layers over the substrate. The second insulating layer over the substrate may be selectively etched to form a plurality of first trench line patterns extending in the second lateral direction and spaced apart from each other in the first lateral direction, each of the plurality of first trench line patterns having a protruding patterned portion extending in a direction not parallel to the second lateral direction. A gate line conductive layer may be formed on the side surfaces of the plurality of first trench line patterns. The first insulating layer inside the plurality of first trench line patterns over the substrate may be etched to form a plurality of second trench line patterns. A dielectric material layer may be formed on the surface of the gate line conductive layer and the side surfaces of the plurality of second trench line patterns. A channel material layer is formed inside the plurality of first trench line patterns and the plurality of second trench line patterns. The dielectric material layer and the channel material layer disposed within the plurality of first trench line patterns and second trench line patterns can be selectively removed to form a gate dielectric layer and a channel structure in the protruding pattern portion. Attached Figure Description

[0009] Figure 1A This is a schematic plan view of a semiconductor device having transistor devices according to an embodiment of the present disclosure, and Figure 1B It is along Figure 1A A cross-sectional view of a semiconductor device taken from line I-I'.

[0010] Figure 2 It is shown schematically. Figure 1A A diagram showing the layout of semiconductor devices.

[0011] Figure 3A This is a schematic plan view of a semiconductor device having transistor devices and capacitor devices according to embodiments of the present disclosure, and Figure 3B It is along Figure 3A A cross-sectional view of a semiconductor device taken along line II-II'.

[0012] Figures 4A to 14A This is a plan view schematically illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. Figures 4B to 14B They are along Figures 4A to 14A A cross-sectional view of the semiconductor device taken along line A-A', and Figure 4C and Figure 5C They are along Figure 4A and Figure 5A A cross-sectional view of a semiconductor device taken along line B-B'.

[0013] Figure 15A This is a schematic plan view of a semiconductor device having transistor devices according to another embodiment of the present disclosure, and Figure 15B It is along Figure 15A A cross-sectional view of a semiconductor device taken from line III-III'.

[0014] Figure 16 yes Figure 15A A schematic layout diagram of semiconductor devices.

[0015] Figure 17A This is a schematic plan view of a semiconductor device having a transistor device and a storage node electrode layer according to another embodiment of the present disclosure, and Figure 17B It is along Figure 17A A cross-sectional view of a semiconductor device taken along line IV-IV'.

[0016] Figures 18A to 24A This is a plan view schematically illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. Figures 18B to 24B They are along Figures 18A to 24A A cross-sectional view of the semiconductor device taken along line C-C', and Figure 18C and Figure 19C They are along Figure 18A and Figure 19A A cross-sectional view of a semiconductor device taken along line D-D'.

[0017] Figure 25A and Figure 25B This is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure.

[0018] Figure 26A and Figure 26B This is a schematic plan view of a semiconductor device according to yet another embodiment of the present disclosure. Detailed Implementation

[0019] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (e.g., width and thickness of the components) have been enlarged to clearly illustrate the components of each device. The terms used herein may correspond to words chosen in consideration of their function in the embodiments, and the meaning of the terms may be interpreted differently by those skilled in the art to which the embodiments pertain. If they have been explicitly and specifically defined, these terms may be interpreted in accordance with those definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0020] Furthermore, unless explicitly used otherwise in the context, the singular form of a word should be understood to include the plural form of the word. It will be understood that the terms “comprising,” “including,” or “having” are intended to specify the presence of a feature, number, step, operation, component, element, part, or combination thereof, and not to exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

[0021] Furthermore, when performing a method or manufacturing method, each process constituting the method may be performed in a different order than the prescribed order unless a specific order is explicitly described in the context. In other words, each process may be performed in the same manner as the stated order, or substantially simultaneously, or in a different order. Moreover, at least a portion of each of the above processes may be performed in reverse order.

[0022] In this specification, the term "predetermined direction" can mean a direction that has been defined in the coordinate system and a direction opposite to that direction. For example, in the xyz coordinate system, the x-direction can include directions parallel to the x-direction. That is, the x-direction can represent all directions in which the absolute value of the x-axis increases from the origin 0 in the positive direction along the x-axis and all directions in which the absolute value of the x-axis increases from the origin 0 in the negative direction along the x-axis. In the xyz coordinate system, the "y" direction and the "z" direction can be interpreted in substantially the same way.

[0023] Figure 1A This is a schematic plan view of a semiconductor device having transistor devices according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A A cross-sectional view of a semiconductor device taken from line I-I'. Figure 2 yes Figure 1A A schematic layout diagram of semiconductor devices. Figure 3A This is a schematic plan view of a semiconductor device having transistor devices and capacitor devices according to an embodiment of the present disclosure. Figure 3B It is along Figure 3A A cross-sectional view of a semiconductor device taken along line II-II'.

[0024] refer to Figure 1A and Figure 1BThe semiconductor device 1 may include a substrate 101, a bit line conductive layer 120, a first channel structure 145a and a second channel structure 145b, a first gate dielectric layer 150a and a second gate dielectric layer 150b, and a first gate line conductive layer 160a and a second gate line conductive layer 160b. The first channel structure 145a and the second channel structure 145b may include conductive channels formed, respectively, in the channel interior regions adjacent to the first gate dielectric layer 150a and the second gate dielectric layer 150b during operation of the semiconductor device 1. The first gate line conductive layer 160a and the second gate line conductive layer 160b can control the formation of the conductive channels. The conductive channels are formed to extend in a direction perpendicular to the surface of the substrate 101 (i.e., the z-direction), and during operation of the semiconductor device 1, charge can be conducted from the bit line conductive layer 120 through the conductive channels in the z-direction.

[0025] The substrate 101 may be made of or comprise a semiconductor material. The semiconductor material may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or combinations of two or more of these. As an example, the semiconductor material may be doped with n-type or p-type dopants. In some other embodiments, the substrate 101 may be an insulating substrate or a conductive substrate.

[0026] A substrate insulating layer 110 may be disposed on the substrate 101. The substrate insulating layer 110 can electrically insulate the bit line conductive layer 120 from the substrate 101. The substrate insulating layer 110 may be composed of or include an insulating material. The insulating material may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more thereof.

[0027] Although not shown, an integrated circuit may be disposed between substrate 101 and substrate insulating layer 110. The integrated circuit may include, for example, active devices such as transistors, passive devices such as resistors or capacitors, or combinations thereof. The integrated circuit may include at least one circuit pattern layer and at least one insulating layer that insulates the at least one circuit pattern layer.

[0028] A bit line conductive layer 120 may be disposed on the substrate insulating layer 110. The bit line conductive layer 120 may extend in a first lateral direction (i.e., the x-direction) substantially parallel to the surface of the substrate insulating layer 110. Multiple bit line conductive layers 120 may be configured and spaced apart from each other in a second lateral direction (i.e., the y-direction) perpendicular to the first lateral direction. The first and second lateral directions may be directions substantially parallel to the surface of the substrate 101. The bit line conductive layer 120 may be composed of or comprise a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si) (doped with n-type or p-type dopant), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of these.

[0029] refer to Figure 1A and Figure 1B The first channel structure 145a and the second channel structure 145b can be disposed on the bit line conductive layer 120. Each of the first channel structure 145a and the second channel structure 145b can be a columnar structure. As shown, on the bit line conductive layer 120, the first channel structure 145a and the second channel structure 145b can have a rectangular cross-section having a width along a first lateral direction (i.e., the x-direction) and a length along a second lateral direction (i.e., the y-direction). Each of the first channel structure 145a and the second channel structure 145b can have a height extending from the bit line conductive layer 120 in a direction substantially perpendicular to the surface of the substrate 101 (i.e., in the z-direction perpendicular to the first and second lateral directions).

[0030] refer to Figure 1A The first channel structure 145a may have first to fourth sides S1a, S2a, S3a, and S4a of the first channel. The first side S1a and the second side S2a of the first channel are sides perpendicular to the first lateral direction (i.e., the x-direction), while the third side S3a and the fourth side S4a of the first channel are sides perpendicular to the second lateral direction (i.e., the y-direction). The second channel structure 145b may have first to fourth sides S1b, S2b, S3b, and S4b of the second channel. The first side S1b and the second side S2b of the second channel are sides perpendicular to the first lateral direction (i.e., the x-direction), while the third side S3b and the fourth side S4b of the second channel are sides perpendicular to the second lateral direction (i.e., the y-direction).

[0031] The first channel structure 145a and the second channel structure 145b can be alternately arranged along the first lateral direction (i.e., the x-direction). The first channel structure 145a and the second channel structure 145b can be spaced apart from each other in the first lateral direction (i.e., the x-direction).

[0032] In addition, the first channel structures 145a can be spaced apart from each other in a row along the second lateral direction (i.e., the y direction), and the second channel structures 145b can be spaced apart from each other in another row along the second lateral direction (i.e., the y direction).

[0033] Each of the first channel structure 145a and the second channel structure 145b may be constituted or comprise a semiconductor material. The semiconductor material may include, for example, silicon (Si), germanium (Ge), and gallium arsenide (GaAs). The semiconductor material may include, for example, a two-dimensional (2D) semiconductor material. The 2D semiconductor material may include transition metal dichalcogenides (TMDC) and black phosphorus, etc. The transition metal dichalcogenides may include, for example, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), and gallium selenide (GaSe). The semiconductor material may include, for example, a metal oxide, such as indium gallium zinc oxide (IGZO).

[0034] A first gate dielectric layer 150a and a second gate dielectric layer 150b may be disposed on a substrate insulating layer 110 and a bit line conductive layer 120. The first gate dielectric layer 150a and the second gate dielectric layer 150b may be configured to respectively surround the first to fourth sides S1a, S2a, S3a, and S4a of the first channel of the first channel structure 145a and the first to fourth sides S1b, S2b, S3b, and S4b of the second channel of the second channel structure 145b. (Reference) Figure 1A and Figure 1B The first gate dielectric layer 150a may include: a first portion 150a1 surrounding a first channel first side S1a, a first channel third side S3a, and a first channel fourth side S4a of the first channel structure 145a; and a second portion 150a2 surrounding a first channel second side S2a of the first channel structure 145a. The first portion 150a1 and the second portion 150a2 may be made of or comprise substantially the same material.

[0035] Similarly, the second gate dielectric layer 150b may include: a first portion 150b1 surrounding a first side S1b, a third side S3b, and a fourth side S4b of the second channel structure 145b; and a second portion 150b2 surrounding a second side S2b of the second channel structure 145b. The first portion 150b1 and the second portion 150b2 may be made of or comprise substantially the same material.

[0036] Each of the first gate dielectric layer 150a and the second gate dielectric layer 150b may be composed of or include a dielectric material. The dielectric material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, titanium oxide, hafnium oxide, and zirconium oxide.

[0037] The first gate line conductive layer 160a and the second gate line conductive layer 160b can be disposed adjacent to the first channel structure 145a and the second channel structure 145b, respectively, on adjacent first gate dielectric layers 150a and 150b. The first gate line conductive layer 160a may include a first gate first line pattern 160a1 and a first gate second line pattern 160a2. The first gate first line pattern 160a1 may be configured to be adjacent to the first channel first side S1a of the first channel structure 145a and extend in the second lateral direction (i.e., the y direction). The first gate second line pattern 160a2 may be configured to be adjacent to the first channel second side S2a of the first channel structure 145a and extend in the second lateral direction (i.e., the y direction).

[0038] The first gate first line pattern 160a1 and the first gate second line pattern 160a2 can be configured to have the same potential. During operation of the semiconductor device 1, substantially the same gate voltage can be applied to the first gate first line pattern 160a1 and the first gate second line pattern 160a2. By applying the gate voltage to the first gate first line pattern 160a1 and the first gate second line pattern 160a2, a pair of conductive channels can be formed in the internal regions of the first channel structure 145a that are respectively adjacent to the first side S1a and the second side S2a of the first channel. Due to this pair of conductive channels, the charge density moving along the vertical channel of the transistor device in the semiconductor device 1 can be increased.

[0039] Similarly, the second gate line conductive layer 160b may include a second gate first line pattern 160b1 and a second gate second line pattern 160b2. The second gate first line pattern 160b1 may be configured to be adjacent to the second channel first side S1b of the second channel structure 145b and extend in the second lateral direction (i.e., the y-direction). The second gate second line pattern 160b2 may be configured to be adjacent to the second channel second side S2b of the second channel structure 145b and extend in the second lateral direction (i.e., the y-direction). The second gate first line pattern 160b1 and the second gate second line pattern 160b2 may be configured to have substantially the same potential. The gate voltage applied to the second gate first line pattern 160b1 and the second gate second line pattern 160b2 may form a pair of conductive channels in the internal region of the second channel structure 145b adjacent to the second channel first side S1b and the second channel second side S2b.

[0040] Each of the first gate line conductive layer 160a and the second gate line conductive layer 160b may be composed of or include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si) (doped with an n-type or p-type dopant), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of these.

[0041] Refer again Figure 1A and Figure 1B A first portion 150a1 of the first gate dielectric layer 150a may have a first thickness t1 in a first lateral direction (i.e., the x-direction) between the first gate first line pattern 160a1 and the first channel first side S1a of the first channel structure 145a. A second portion 150a2 of the first gate dielectric layer 150a may have a second thickness t2 in the first lateral direction (i.e., the x-direction) between the first gate second line pattern 160a2 and the first channel second side S2a of the first channel structure 145a. In one embodiment, the first thickness t1 and the second thickness t2 may be substantially the same.

[0042] Similarly, the first portion 150b1 of the second gate dielectric layer 150b may have a third thickness t3 in the first lateral direction (i.e., the x-direction) between the second gate first line pattern 160b1 and the first side S1b of the second channel structure 145b. The second portion 150b2 of the second gate dielectric layer 150b may have a fourth thickness t4 in the first lateral direction (i.e., the x-direction) between the second gate second line pattern 160b2 and the second side S2b of the second channel structure 145b. In one embodiment, the third thickness t3 and the fourth thickness t4 may be substantially the same.

[0043] refer to Figure 1A and Figure 1B An insulating layer 170 can be provided to fill the space between the first gate line conductive layer 160a and the second gate line conductive layer 160b. The insulating layer 170 can be composed of or include an insulating material. The insulating material can include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of them.

[0044] Figure 2 It is shown schematically. Figure 1A A layout diagram of semiconductor devices. Please refer to it. Figure 1A and Figure 2 The unit cell (UC1) of semiconductor device 1 can have 4F 2 Layout. Within the unit cell UC1, a pair of electrically isolated channel structures 145a and 145b, and a pair of gate line conductive layers 160a and 160b, can be provided. As a result, a pair of independently driven transistor devices can be implemented within the unit cell UC1.

[0045] Figure 3A This is a schematic plan view of a semiconductor device having transistor devices and capacitor devices according to an embodiment of the present disclosure. Figure 3B It is along Figure 3A A cross-sectional view taken from line Ⅱ-Ⅱ' of semiconductor device 2. Figure 3A and Figure 3B The semiconductor device 2 may have a storage node electrode layer disposed therein. Figure 1A and Figure 1B The structure above the semiconductor device 1.

[0046] refer to Figure 3A and Figure 3BThe first storage node electrode layer 210a and the second storage node electrode layer 210b can be disposed above the first channel structure 145a and the second channel structure 145b, respectively. The first storage node electrode layer 210a and the second storage node electrode layer 210b can be electrically connected to the corresponding first channel structure 145a and the second channel structure 145b through contact plugs 180. Each of the contact plugs 180 and the storage node electrode layers 210a and 210b can be made of or include conductive materials. The conductive materials can include, for example, silicon (Si) (doped with n-type or p-type dopant), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. An interlayer insulating layer 190 can be disposed on the side of the contact plug 180.

[0047] like Figure 3A As shown, the first storage node electrode layer 210a and the second storage node electrode layer 210b can be configured to be spaced apart from each other in a third direction (i.e., direction D1 and direction D2) that is not parallel to the first or second lateral direction. Figure 3A In the first storage node electrode layer 210a and the second storage node electrode layer 210b, the first storage node electrode layer 210a and the second storage node electrode layer 210b may be respectively disposed on the edge portions of the first channel structure 145a and the second channel structure 145b that are opposite to each other in the second lateral direction (i.e., the y direction).

[0048] Despite Figure 3A and Figure 3B Not shown in the diagram, but the semiconductor device 2 may further include a capacitor dielectric layer disposed on the first storage node electrode layer 210a and the second storage node electrode layer 210b, and a plate electrode layer disposed on the capacitor dielectric layer. This is in accordance with the description to be followed later. Figure 14B The cross-sectional view shows a substantially identical structure, with the capacitor dielectric layer potentially covering the first storage node electrode layer 210a and the second storage node electrode layer 210b, respectively. The plate electrode layer can also cover the capacitor dielectric layer and can serve as a common electrode.

[0049] The first storage node electrode layer 210a, capacitor dielectric layer, and plate electrode layer, electrically connected to the first channel structure 145a, can constitute a first capacitor device. The second storage node electrode layer 210b, capacitor dielectric layer, and plate electrode layer, electrically connected to the second channel structure 145b, can constitute a second capacitor device. The first capacitor device and the second capacitor device can store signal information independently of each other.

[0050] As described above, embodiments of this disclosure can provide a semiconductor device including a transistor device having a pair of channel structures. Additionally, embodiments of this disclosure can provide a semiconductor device including a pair of capacitor devices electrically connected to the pair of channel structures. The semiconductor device includes 4F... 2 A pair of transistor devices and a pair of capacitor devices operate independently in a unit cell layout, thereby increasing device integration.

[0051] Figures 4A to 14A This is a plan view schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 4B to 14B They are along Figures 4A to 14A A cross-sectional view of a semiconductor device taken along line A-A'. Figure 4C and Figure 5C They are along Figure 4A and Figure 5A A cross-sectional view of a semiconductor device taken along line B-B'. In one embodiment, reference... Figures 4A to 14A , Figures 4B to 14B as well as Figure 4C and Figure 5C The described method for manufacturing semiconductor devices can be applied to the manufacture of the above-mentioned references. Figure 1A and Figure 1B The method for manufacturing the semiconductor device 1, or the method described above (see reference). Figure 3A and Figure 3B The method described for semiconductor device 2.

[0052] refer to Figure 4A , Figure 4B and Figure 4C Substrate 301 can be provided. Substrate 301 can be used in conjunction with the above reference. Figure 1A and Figure 1B The substrate 101 described is substantially the same.

[0053] A substrate insulating layer 310 may be formed on the substrate 301. The substrate insulating layer 310 may be composed of or include an insulating material. The insulating material may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of them.

[0054] Although not shown, an integrated circuit may be disposed between substrate 301 and substrate insulating layer 310. As an example, the integrated circuit may include active devices such as transistors, passive devices such as resistors and capacitors, or combinations thereof. The integrated circuit may include at least one circuit pattern layer and at least one insulating layer insulating the at least one circuit pattern layer.

[0055] Next, a conductive material layer and an insulating material layer can be sequentially formed on the substrate insulating layer 310, and the conductive material layer and the insulating material layer can be patterned. As a result, a plurality of bit line structures 30 can be formed on the substrate insulating layer 310. The plurality of bit line structures 30 can extend in a first lateral direction (i.e., the x-direction) substantially parallel to the surface of the substrate insulating layer 310, and can be configured to be spaced apart from each other in a second lateral direction (i.e., the y-direction) perpendicular to the first lateral direction. The first lateral direction and the second lateral direction can be directions substantially parallel to the surface of the substrate 301. In addition, each of the plurality of bit line structures 30 may include: a bit line pattern layer 320 disposed on the substrate insulating layer 310, and a first insulating layer 330 disposed on the bit line pattern layer 320.

[0056] The conductive material layer may be composed of or include, for example, silicon (Si) (doped with n-type or p-type dopants), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. The insulating material layer may be composed of, for example, oxides, nitrides, oxynitrides, or a combination of two or more thereof. The insulating material layer may have etch selectivity relative to the substrate insulating layer 310.

[0057] refer to Figure 5A , Figure 5B and Figure 5C A second insulating layer 335 can be formed on the base insulating layer 310 by filling the area between the multiple bit line structures 30 with an insulating material. The upper surface of the second insulating layer 335 can be located at the same level as the upper surface of the first insulating layer 330. The insulating material can include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of them.

[0058] refer to Figure 6A and Figure 6BThe first insulating layer 330 on the bit line patterning layer 320 and the second insulating layer 335 on the substrate insulating layer 310 can be patterned along a second lateral direction (i.e., the y-direction) to form a plurality of insulating line structures 40. The plurality of insulating line structures 40 can extend in the second lateral direction (i.e., the y-direction) and can be spaced apart from each other in a first lateral direction (i.e., the x-direction). Each of the plurality of insulating line structures 40 may include a portion of the first insulating layer 330 directly located on the bit line patterning layer 320 and a portion of the second insulating layer 335 directly located on the substrate insulating layer 310. In one embodiment, when forming the plurality of insulating line structures 40, the bit line patterning layer 320 and the substrate insulating layer 310 can be selectively exposed by etching the first insulating layer 330 and the second insulating layer 335.

[0059] refer to Figure 7A and Figure 7B A channel material layer 340 can be formed on both sides of each of the plurality of insulated wire structures 40. The channel material layer 340 may include a portion directly located on the substrate insulation layer 310 along the second transverse direction (i.e., the y-direction) and a portion directly located on the bit line pattern layer 320. Therefore, the portion of the channel material layer 340 directly disposed on the bit line pattern layer 320 can be electrically connected to the bit line pattern layer 320. The channel material layer 340 may be formed by referring to the above-mentioned... Figure 1A and Figure 1B The first channel structure 145a and the second channel 145b of the semiconductor device 1 described are made of substantially the same material.

[0060] refer to Figure 8A and Figure 8B The portion of the channel material layer 340, excluding the portion directly located on the plurality of bit line pattern layers 320, can be etched to form a plurality of channel structures 345. As an example, after forming the plurality of channel structures 345, the portion of the channel material layer 340 directly disposed on the substrate insulating layer 310 can be removed. Therefore, a plurality of channel structures 345 can be disposed on the plurality of bit line pattern layers 320. The plurality of channel structures 345 can be configured to be spaced apart from each other in a first lateral direction (i.e., the x-direction) and a second lateral direction (i.e., the y-direction).

[0061] refer to Figure 9A and Figure 9BA first dielectric material layer 350 can be formed on the substrate insulating layer 310 and the bit line pattern 320 to cover the side surfaces of the plurality of channel structures 345 and the side surfaces of the plurality of insulating wire structures 40. The thickness t1 of the portion of the first dielectric material layer 350 formed on the side surface of each of the plurality of channel structures 345 adjacent to the bit line pattern layer 320 can be thinner than the thickness t1' of the portion of the side surface of each of the plurality of insulating wire structures 40 adjacent to the substrate insulating layer 310. The first dielectric material layer 350 can be formed from the portion referenced above. Figure 1A and Figure 1B The first portion 150a1 of the first gate dielectric layer 150a and the first portion 150b1 of the second gate dielectric layer 150b of the semiconductor device 1 described are made of substantially the same material.

[0062] Next, a first gate conductive layer 360a can be formed on the first dielectric material layer 350. The first gate conductive layer 360a can be formed from the above reference material. Figure 1A and Figure 1B The first gate first line pattern 160a1 and the second gate first line pattern 160b1 of the semiconductor device 1 described are made of substantially the same material.

[0063] refer to Figure 10A and Figure 10B The first gate conductive layer 360a can be selectively etched to form a plurality of first gate line pattern layers 360, the plurality of first gate line pattern layers 360 being configured to be adjacent to both sides of each of the plurality of insulating line structures 40. The plurality of first gate line pattern layers 360 can each extend along a second lateral direction (i.e., the y-direction).

[0064] Subsequently, a first filler insulating layer 370 can be formed to fill the space between the plurality of first gate line pattern layers 360. The first filler insulating layer 370 can be formed from the above reference. Figure 1A and Figure 1B The filling insulating layer 170 of the semiconductor device 1 described is made of substantially the same material.

[0065] refer to Figure 11A and Figure 11B Multiple insulating wire structures 40 can be removed over the substrate insulating layer 310 and the bit line pattern layer 320 to form a trench T. As a result, multiple channel structures 345 and the first dielectric material layer 350 can be selectively exposed on the sidewall surface of the trench T, and the bit line pattern layer 320 and the substrate insulating layer 310 can be selectively exposed on the bottom surface of the trench T.

[0066] refer to Figure 12A and Figure 12BA second dielectric material layer 450 can be formed to cover the plurality of channel structures 345 above the bit line pattern layer 320 and the substrate insulating layer 310, and the exposed side surfaces of the first dielectric material layer 350. The thickness t2 of the portion of the second dielectric material layer 450 formed on the side surface of each of the plurality of channel structures 345 can be substantially equal to the thickness t2' of the portion of the second dielectric material layer 450 formed on one surface of the first dielectric material layer 350. The second dielectric material layer 450 can be formed from the portion referenced above. Figure 1A and Figure 1B The second portion 150a2 of the first gate dielectric layer 150a and the second portion 150b2 of the second gate dielectric layer 150b of the semiconductor device 1 described are made of substantially the same material.

[0067] Subsequently, a plurality of second gate line pattern layers 460 may be formed on the second dielectric material layer 450 such that they are adjacent to the side surfaces of the plurality of channel structures 345. The plurality of second gate line pattern layers 460 may be formed only on the second dielectric material layer 450 adjacent to the sidewall surfaces of the trench T, and after the plurality of second gate line pattern layers 460 are formed, the portion of the second dielectric material layer 450 above the bit line pattern layer 320 and the substrate insulating layer 310 may be exposed. The plurality of second gate line pattern layers 460 may extend along a second lateral direction (i.e., the y-direction). The plurality of second gate line pattern layers 460 may be formed by referring to the above reference... Figure 1A and Figure 1B The first gate second line pattern 160a2 and the second gate second line pattern 160b2 of the semiconductor device 1 described are made of substantially the same material.

[0068] Refer again Figure 12A and Figure 12B A second filling insulating layer 470 can be formed to fill the space between the plurality of second gate line pattern layers 460. The second filling insulating layer 470 can be formed by referring to the above. Figure 10A and Figure 10B The first filling insulating layer 370 described is made of substantially the same material. By performing the above-described process, a semiconductor device including a plurality of channel structures according to embodiments of the present disclosure can be manufactured. Subsequently, additional processes can be performed... Figure 13A , Figure 13B , Figure 14A and Figure 14B The process is used to form capacitor devices over multiple channel structures 345.

[0069] refer to Figure 13A and Figure 13B Contact plugs 380 can be formed on multiple channel structures 345. Contact plugs 380 can be electrically connected to multiple channel structures 345. Contact plugs 380 can be made from materials referenced above. Figure 3A and Figure 3B The contact plugs 180 of the described semiconductor device 2 are made of substantially the same material. Additionally, an interlayer insulating layer 390 may be formed in the lateral direction and cover the sidewalls of the contact plugs 380. The interlayer insulating layer 390 may be composed of or include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of these materials.

[0070] Subsequently, storage node electrode layers 510a and 510b can be formed on the contact plug 380 and the interlayer insulating layer 390. For example... Figure 13A As shown, the first storage node electrode layer 510a and the second storage node electrode layer 510b can be formed on a pair of adjacent channel structures 345 in the first lateral direction (i.e., the x-direction). The first storage node electrode layer 510a and the second storage node electrode layer 510b can be formed to be spaced apart from each other in a third lateral direction that is not parallel to or at an angle to the first lateral direction (i.e., the x-direction) and the second lateral direction (i.e., the y-direction). The first storage node electrode layer 510a and the second storage node electrode layer 510b can be formed from materials referenced above. Figure 3A and Figure 3B The first storage node electrode layer 210a and the second storage node electrode layer 210b of the semiconductor device 2 described are made of substantially the same material.

[0071] refer to Figure 14A and Figure 14B A capacitor dielectric layer 520 can be formed on the first storage node electrode layer 510a and the second storage node electrode layer 510b. The capacitor dielectric layer 520 can be formed to cover the first storage node electrode layer 510a and the second storage node electrode layer 510b on the interlayer insulating layer 390. The capacitor dielectric layer 520 can be composed of or include metal oxides such as aluminum oxide, hafnium oxide, and zirconium oxide. Subsequently, a plate electrode layer 530 can be formed on the capacitor dielectric layer 520. The plate electrode layer 530 can be composed of or include a conductive material.

[0072] The above process can be used to manufacture Figure 3A and Figure 3B The semiconductor device 2 shown has multiple channel structures and capacitor devices.

[0073] Figure 15A This is a schematic plan view of a semiconductor device having transistor devices according to another embodiment of the present disclosure. Figure 15B It is along Figure 15A A cross-sectional view of a semiconductor device taken from line III-III'. Figure 16 yes Figure 15A A schematic layout diagram of semiconductor devices.

[0074] refer to Figure 15A and Figure 15B The semiconductor device 3 may include a bit line conductive layer 1120, an insulating wire structure 1130, a first channel structure 1145a and a second channel structure 1145b, a first gate dielectric layer 1150a and a second gate dielectric layer 1150b, and a first gate line conductive layer 1160a and a second gate line conductive layer 1160b. The first channel structure 1145a and the second channel structure 1145b may each include conductive channels formed in internal regions adjacent to the first gate dielectric layer 1150a and the second gate dielectric layer 1150b. The formation of the conductive channels may be controlled by the first gate line conductive layer 1160a and the second gate line conductive layer 1160b. The conductive channels may be formed to extend in a direction perpendicular to the surface of the substrate 1101 (i.e., the z-direction), such that when operating the semiconductor device 3, charge can be conducted from the bit line conductive layer 1120 through the conductive channels in the first channel structure 1145a and the second channel structure 1145b in the z-direction.

[0075] Substrate 1101 may be made of or include semiconductor material. Substrate 1101 may be related to the above references. Figure 1A and Figure 1B The substrate 101 of the semiconductor device 1 described is substantially the same. A substrate insulating layer 1110 may be disposed on the substrate 1101. The substrate insulating layer 1110 may be the same as the one described above. Figure 1A and Figure 1B The substrate insulating layer 110 of the semiconductor device 1 described is substantially the same.

[0076] Although not shown, an integrated circuit may be disposed between the substrate 1101 and the base insulating layer 1110. The integrated circuit may include, for example, active devices such as transistors, passive devices such as resistors and capacitors, or combinations thereof. The integrated circuit may include at least one circuit pattern layer and at least one insulating layer for insulating the circuit pattern layer.

[0077] A bit line conductive layer 1120 can be disposed on the substrate insulating layer 1110. The bit line conductive layer 1120 can extend in a first lateral direction (i.e., the x-direction) substantially parallel to the surface of the substrate insulating layer 1110. Multiple bit line conductive layers 1120 can be provided in a manner that they are spaced apart from each other in a second lateral direction (i.e., the y-direction) perpendicular to the first lateral direction. The first and second lateral directions can be directions substantially parallel to the surface of the substrate 1101. The bit line conductive layer 1120 can be related to the above reference. Figure 1A and Figure 1B The bit line conductive layer 120 of the semiconductor device 1 described is substantially the same.

[0078] The insulated wire structure 1130 can be disposed on the substrate insulating layer 1110 and extend in the second lateral direction (i.e., the y-direction). Some portions of the insulated wire structure 1130 can be directly disposed on the substrate insulating layer 1110, and other portions of the insulated wire structure 1130 can be directly disposed on the bit-wire conductive layer 1120. Multiple insulated wire structures 1130 can be arranged in a manner that they are spaced apart from each other in the first lateral direction (i.e., the x-direction). The insulated wire structure 1130 can be composed of or include insulating materials such as oxides, nitrides, and oxynitrides.

[0079] refer to Figure 15A Above the substrate insulating layer 1110, the first channel structure 1145a and the second channel structure 1145b can be configured to contact the first side surface S10 and the second side surface S20 of the insulating wire structure 1130, respectively. Each of the first channel structures 1145a and the second channel structure 1145b can have a columnar shape extending above the substrate insulating layer 1110 in a vertical direction (i.e., the z-direction) perpendicular to the first and second lateral directions. Certain portions of each of the first channel structures 1145a and the second channel structure 1145b can be directly disposed on the substrate insulating layer 1110, and other portions of each of the first channel structures 1145a and the second channel structure 1145b can be directly disposed on the bit line conductive layer 1120. In other words, at least a portion of each of the first channel structures 1145a and the second channel structure 1145b can be configured to overlap with the bit line conductive layer 1120 in the vertical direction. Therefore, the first channel structure 1145a and the second channel structure 1145b can be electrically connected to the bit line conductive layer 1120.

[0080] Each of the first channel structure 1145a and the second channel structure 1145b may have a curved side surface. The first channel structure 1145a and the second channel structure 1145b may be configured to protrude in the opposite lateral direction to the first side surface S10 and the second side surface S20 of the insulating wire structure 1130.

[0081] In one embodiment, at least a portion of the first channel structure 1145a and at least a portion of the second channel structure 1145b may be configured to face each other in a first lateral direction (i.e., the x-direction), with an insulating wire structure 1130 between them. For example, in a plan view, the first channel structure 1145a and the second channel structure 1145b may be symmetrically arranged relative to the first insulating wire structure 1130 in the x-direction.

[0082] refer to Figure 15A and Figure 15BThe first gate dielectric layer 1150a and the second gate dielectric layer 1150b can be disposed above the substrate insulating layer 1110 to surround the side surfaces of the first channel structure 1145a and the second channel structure 1145b, respectively. The first gate dielectric layer 1150a and the second gate dielectric layer 1150b can be formed by referring to the above-mentioned... Figure 1A and Figure 1B The first gate dielectric layer 150a and the second gate dielectric layer 150b of the semiconductor device 1 described are made of substantially the same material.

[0083] A first gate line conductive layer 1160a and a second gate line conductive layer 1160b may be disposed above the substrate insulating layer 1110, and the two extend in the second lateral direction (i.e., the y direction). The first gate line conductive layer 1160a and the second gate line conductive layer 1160b may be configured to cover at least a portion of the first gate dielectric layer 1150a and the second gate dielectric layer 1150b, respectively.

[0084] refer to Figure 15B An interlayer insulating layer 1172 may be disposed between the first gate line conductive layer 1160a and the second gate line conductive layer 1160b and the bit line conductive layer 1120. The interlayer insulating layer 1172 can be used to prevent the first gate line conductive layer 1160a and the second gate line conductive layer 1160b from short-circuiting with the bit line conductive layer 1120.

[0085] refer to Figure 15A and Figure 15B An insulating layer 1174 can be provided to fill the space between the first gate line conductive layer 1160 and the second gate line conductive layer 1160b. The insulating layer 1174 can be composed of or include an insulating material. The insulating material can include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of them.

[0086] Figure 16 It is shown schematically. Figure 15A A layout diagram of the semiconductor devices. (Reference) Figure 15A and Figure 16 The unit cell UC2 of semiconductor device 3 can have 4F 2 Layout. Within unit cell UC2, a pair of electrically isolated channel structures and a pair of gate line conductive layers can be configured. As a result, a pair of independently driven transistor devices can be implemented within unit cell UC2.

[0087] refer to Figure 16The present invention discloses a first insulated wire structure 1130A and a second insulated wire structure 1130B as examples of a pair of adjacent insulated wire structures. A first insulated wire first channel structure 1145a-A, a first insulated wire first gate dielectric layer 1150a-A, and a first insulated wire first gate conductive layer 1160a-A may be disposed on one side surface of the first insulated wire structure 1130A. A first insulated wire second channel structure 1145b-A, a first insulated wire second gate dielectric layer 1150b-A, and a first insulated wire second gate conductive layer 1160b-A may be disposed on the other side surface of the first insulated wire structure 1130A.

[0088] Similarly, a first channel structure 1145a-B, a first gate dielectric layer 1150a-B, and a first gate conductive layer 1160a-B can be formed on one side surface of the second insulated wire structure 1130B. A second channel structure 1145b-B, a second gate dielectric layer 1150b-B, and a second gate conductive layer 1160b-B can be formed on the other side surface of the second insulated wire structure 1130B.

[0089] like Figure 16 As shown, the second channel structure 1145b-A of the first insulated wire can be configured to be spaced apart from the first channel structure 1145a-B of the second insulated wire in a third lateral direction (D3 or D4 direction) that is not parallel to the first and second lateral directions. Similarly, the first channel structure 1145a-A of the first insulated wire can be configured to be spaced apart from the second channel structure of another adjacent insulated wire structure in the third lateral direction. The second channel structure 1145b-B of the second insulated wire can be configured to be spaced apart from the first channel structure of another adjacent insulated wire structure in the third lateral direction.

[0090] Figure 17A This is a schematic plan view of a semiconductor device having a transistor device and a storage node electrode layer according to another embodiment of the present disclosure. Figure 17B It is along Figure 17A A cross-sectional view of a semiconductor device taken along line IV-IV'. Figure 17A and Figure 17B The semiconductor device 4 may have a storage node electrode layer disposed therein. Figure 15A , Figure 15B and Figure 16 The structure above the semiconductor device 3.

[0091] refer to Figure 17A and Figure 17BThe first storage node electrode layer 1210a and the second storage node electrode layer 1210b can be respectively disposed above the first channel structure 1145a and the second channel structure 1145b. The first storage node electrode layer 1210a and the second storage node electrode layer 1210b can be electrically connected to the corresponding first channel structure 1145a and the second channel structure 1145b through contact plugs 1180a and 1180b, respectively. The contact plugs 1180a and 1180b and the storage node electrode layers 1210a and 1210b can each be composed of or include conductive materials. The conductive materials can include, for example, silicon (Si) (doped with n-type or p-type dopant), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of them. An interlayer insulation layer 1190 may be provided on the side surfaces of the contact plugs 1180a and 1180b.

[0092] Let's refer to each other. Figure 16 and Figure 17A The first storage node electrode layer 1210a-A disposed above the first channel structure 1145a-A of the first insulating wire and the second storage node electrode layer 1210b-A disposed above the second channel structure 1145b-A of the first insulating wire can be configured to be spaced apart from each other in the first lateral direction (i.e., the x-direction). Similarly, the first storage node electrode layer 1210a-B disposed above the first channel structure 1145a-B of the second insulating wire and the second storage node electrode layer 1210b-B disposed above the second channel structure 1145b-B of the second insulating wire can be configured to be spaced apart from each other in the first lateral direction (i.e., the x-direction).

[0093] Furthermore, the second storage node electrode layer 1210b-A disposed above the second channel structure 1145b-A of the first insulating wire and the first storage node electrode layer 1210a-B disposed above the first channel structure 1145a-B of the second insulating wire can be configured to be spaced apart from each other in a third lateral direction (i.e., the D5 or D6 direction) that is not parallel to the first and second lateral directions. For example, in a plan view, the second storage node electrode layer 1210b-A and the first storage node electrode layer 1210a-B are arranged in a zigzag pattern in the y-direction.

[0094] As described above, on the top of the channel structure disposed on the side surfaces of different insulating wire structures, the first storage node electrode layer and the second storage node electrode layer disposed adjacent to each other can be configured to be spaced apart from each other in the third lateral direction.

[0095] Despite Figure 17Aand Figure 17B As not shown, the semiconductor device 4 may further include: a capacitor dielectric layer disposed on the first storage node electrode layer 1210a and the second storage node electrode layer 1210b, and a plate electrode layer disposed on the capacitor dielectric layer. The capacitor dielectric layer may be configured to cover the first storage node electrode layer 1210a and the second storage node electrode layer 1210b respectively, and may have the same characteristics as described later. Figure 24B The cross-sectional view shows a structure that is essentially the same. The plate electrode layer can be configured to cover the capacitor dielectric layer and can also be used as a common electrode.

[0096] Simultaneously, the first storage node electrode layer 1210a, the capacitor dielectric layer, and the plate electrode layer, which are electrically connected to the first channel structure 1145a, can constitute a first capacitor device. The second storage node electrode layer 1210b, the capacitor dielectric layer, and the plate electrode layer, which are electrically connected to the second channel structure 1145b, can constitute a second capacitor device. The first capacitor device and the second capacitor device can independently store signal information.

[0097] As described above, embodiments of this disclosure can provide a semiconductor device comprising transistor devices each having a pair of channel structures. Additionally, embodiments of this disclosure can provide a semiconductor device comprising a pair of capacitor devices each electrically connected to the pair of channel structures. The semiconductor device may include components in a 4F... 2 A pair of transistor devices and a pair of capacitor devices operate independently in a unit cell layout, thereby improving device integration.

[0098] Figures 18A to 24A This is a schematic plan view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure, and Figures 18B to 24B They are along Figures 18A to 24B A cross-sectional view of a semiconductor device taken along line C-C'. In one embodiment, combined with Figures 18A to 24A and Figures 18B to 24B The method described herein for manufacturing semiconductor devices is applicable to the manufacture of the above-mentioned references. Figure 15A , Figure 15B and Figure 16 The method for manufacturing the semiconductor device 3, as described above, is referenced. Figure 17A and Figure 17B The method for the semiconductor device 4.

[0099] refer to Figure 18A and Figure 18B Substrate 1301 can be provided. Substrate 1301 can be used with the above reference. Figure 15A and Figure 15B The substrate 1101 described is substantially the same.

[0100] A substrate insulating layer 1310 may be formed on the substrate 1301. The substrate insulating layer 1310 may be composed of or include an insulating material. The insulating material may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of them.

[0101] Although not shown, an integrated circuit may be disposed between the substrate 1301 and the base insulating layer 1310. The integrated circuit may include, for example, active devices such as transistors, passive devices such as resistors and capacitors, or combinations thereof. The integrated circuit may include at least one circuit pattern layer and at least one insulating layer for insulating the at least one circuit pattern layer.

[0102] Next, a conductive material layer can be formed on the substrate insulating layer 1310, and the conductive material layer can be patterned to form a plurality of bit line conductive layers 1320. The plurality of bit line conductive layers 1320 can extend substantially parallel to the surface of the substrate insulating layer 1310 in a first lateral direction (i.e., the x-direction) and can be configured to be spaced apart from each other in a second lateral direction (i.e., the y-direction) perpendicular to the first lateral direction. The first lateral direction and the second lateral direction can be directions substantially parallel to the surface of the substrate 1301.

[0103] Subsequently, a first insulating layer 1331 covering a plurality of bit line conductive layers 1320 can be formed on the substrate insulating layer 1310, and a second insulating layer 1333 can be formed on the first insulating layer 1331. The first insulating layer 1331 and the second insulating layer 1333 can have etch selectivity with each other.

[0104] Multiple bit line conductive layers 1320 can be derived from the above reference. Figure 15A and Figure 15B The bit line conductive layer 1120 of the semiconductor device 3 described is made of substantially the same material.

[0105] refer to Figure 19A and Figure 19B The second insulating layer 1333 can be selectively etched over the substrate insulating layer 1310 to form a plurality of first trench line patterns TR1 extending along a second lateral direction (i.e., the y-direction) and spaced apart from each other in a first lateral direction (i.e., the x-direction). For the process of selectively etching the second insulating layer 1333, an etching method utilizing the etching selectivity of the first insulating layer 1331 can be employed. Each of the plurality of first trench line patterns TR1 may have a protruding pattern portion P extending in a direction (e.g., the x-direction) that is not parallel to the second lateral direction (i.e., the y-direction). As an example, such as Figure 19AAs shown, the protruding pattern portion P can protrude in the first lateral direction (i.e., the x-direction). Furthermore, the protruding pattern portion P of one of the plurality of first groove line patterns TR1 can be spaced apart from the protruding pattern portion P of another adjacent first groove line pattern in a direction not parallel to the first and second lateral directions.

[0106] refer to Figure 20A and 20B A gate line conductive layer 1340 can be formed on the side surface of the first trench line pattern TR1. The gate line conductive layer 1340 can be formed by combining the above... Figure 15A and Figure 15B The first gate line conductive layer 1160a and the second gate line conductive layer 1160b of the semiconductor device 3 described are made of substantially the same material.

[0107] refer to Figure 21A and Figure 21B A first insulating layer 1331 can be etched over a substrate insulating layer 1310 within a plurality of first trench line patterns TR1 to form a plurality of second trench line patterns TR2. The plurality of second trench line patterns TR2 may selectively expose the bit line conductive layer 1320 and the substrate insulating layer 1310.

[0108] Subsequently, a dielectric material layer 1350 can be formed on the side surface of the gate line conductive layer 1340 and the side surface of the first insulating layer 1331 (which is the side surface of the plurality of second trench line patterns TR2). The dielectric material layer 1350 can be formed by bonding with the above. Figure 15A and Figure 15B The first gate dielectric layer 1150a and the second gate dielectric layer 1150b of the described semiconductor device 3 are made of substantially the same material. Next, the interiors of a plurality of first trench line patterns TR1 and second trench line patterns TR2 can be filled with a channel material to form a channel material layer 1360. The channel material layer 1360 can be made of the same material as described above. Figure 15A and Figure 15B The first channel structure 1145a and the second channel structure 1145b of the semiconductor device 3 described are made of substantially the same material.

[0109] refer to Figure 22A and Figure 22BThe dielectric material layer 1350 and channel material layer 1360 in the plurality of first trench line patterns TR1 and second trench line patterns TR2 can be selectively removed, so that only the portion inside the protruding portion P is retained. The remaining portion is formed in the first gate dielectric layer 1355a and second gate dielectric layer 1355b, as well as the first channel structure 1365a and second channel structure 1365b inside the protruding portion P. As a result, each of the first gate dielectric layer 1355a and second gate dielectric layer 1355b and each of the first channel structure 1365a and second channel structure 1365b can be discontinuously disposed above the substrate insulating layer 1310 along the second lateral direction (i.e., the y direction). A portion of each of the first gate dielectric layer 1355a and second gate dielectric layer 1355b and a portion of each of the first channel structure 1365a and second channel structure 1365b can be formed as a contact bit line conductive layer 1320. Subsequently, insulating material disposed in the space from which the dielectric material layer 1350 and the channel material layer 1360 have been removed can form an insulated wire structure 1370.

[0110] By performing the above-described process, a semiconductor device including a plurality of channel structures according to embodiments of the present disclosure can be manufactured. Next, by further performing... Figure 23A , Figure 23B , Figure 24A and Figure 24B The process shown can form capacitor devices over multiple channel structures.

[0111] refer to Figure 23A and Figure 23B A first contact plug 1380a and a second contact plug 1380b can be formed on the first channel structure 1365a and the second channel structure 1365b, respectively. The first contact plug 1380a and the second contact plug 1380b can be electrically connected to the first channel structure 1365a and the second channel structure 1365b, respectively. The first contact plug 1380a and the second contact plug 1380b can be formed by combining with the above... Figure 17A and Figure 17B The first contact plug 1180a and the second contact plug 1180b of the described semiconductor device 4 are made of substantially the same material. Additionally, an insulating layer 1390 may be formed in the lateral direction of the first contact plug 1180a and the second contact plug 1380b. The insulating layer 1390 may be made of or include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of these materials.

[0112] Next, a first storage node electrode layer 1410a and a second storage node electrode layer 1410b can be formed on the first contact plug 1380a and the second contact plug 1380b, respectively. The first storage node electrode layer 1410a and the second storage node electrode layer 1410b can be formed by combining the above. Figure 17A and Figure 17B The first storage node electrode layer 1210a and the second storage node electrode layer 1210b of the semiconductor device 4 described are made of substantially the same material.

[0113] refer to Figure 24A and 24B A capacitor dielectric layer 1420 can be formed on the first storage node electrode layer 1410a and the second storage node electrode layer 1410b. The capacitor dielectric layer 1420 can be formed to cover the first storage node electrode layer 1410a and the second storage node electrode layer 1410b on the insulating layer 1390. The capacitor dielectric layer 1420 can be composed of or include metal oxides such as aluminum oxide, hafnium oxide, and zirconium oxide. Subsequently, a plate electrode layer 1430 can be formed on the capacitor dielectric layer 1420. The plate electrode layer 1430 can be composed of or include a conductive material. Through the above process, a capacitor can be manufactured... Figure 17A and Figure 17B The semiconductor device 4 shown includes a channel structure and a capacitor device.

[0114] Figure 25A and Figure 25B This is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure. Figure 25A A semiconductor device 5 including a channel structure is shown, and Figure 25B A semiconductor device 6, including a channel structure and capacitor devices, is shown. As an example, Figure 25B The semiconductor device 6 may further include a semiconductor device disposed in a manner that allows for the application of semiconductor devices ... Figure 25A Capacitor devices above the channel structure.

[0115] Figure 25A The semiconductor device 5 is similar in shape to the first channel structure 3145a and the second channel structure 3145b. Figure 15A and Figure 15B The semiconductor devices 3 are different. Although Figure 15A The first channel structure 1145a and the second channel structure 1145b of the semiconductor device 3 shown are arranged symmetrically with respect to the insulating wire structure 1130, but in Figure 25A middle, Figure 25AThe first channel structure 3145a and the second channel structure 3145b of the semiconductor device 5 shown may be arranged asymmetrically with respect to the insulating wire structure 1130. A portion of the first channel structure 3145a and a portion of the second channel structure 3145b may be arranged facing each other, with the insulating wire structure 1130 between them. However, the first channel structure 3145a and the second channel structure 3145b may also be arranged in a zigzag pattern on both sides of the insulating wire structure 1130 along a second lateral direction (i.e., the y-direction). For example, the first channel structure 3145a and the second channel structure 3145b may have an elliptical shape separated by the insulating wire structure 1130, wherein the major axis of the ellipse is not parallel to the first lateral direction (i.e., the x-direction) and the second lateral direction (i.e., the y-direction).

[0116] Additionally, the first channel structure 3145a and the second channel structure 3145b facing each other on the sides of adjacent different insulated wire structures 1130 can be configured to be spaced apart from each other in a third lateral direction (i.e., the D11 direction or D12) that is not parallel to the first lateral direction (i.e., the x direction) and the second lateral direction (i.e., the y direction).

[0117] manufacture Figure 25A The method of semiconductor device 5 can be combined with the above. Figures 18A to 22A as well as Figures 18B to 22B The methods for manufacturing semiconductor devices are essentially the same.

[0118] Figure 25B The semiconductor device 6 is similar in shape or arrangement to the first storage node electrode layer 3210a and the second storage node electrode layer 3210b. Figure 17A and Figure 17B The semiconductor devices are different. Figure 17A In the semiconductor device 4, the first storage node electrode layer 1210a and the second storage node electrode layer 1210b are configured to be spaced apart from each other in the first lateral direction (i.e., the x-direction), while Figure 25B In the semiconductor device 6, the first storage node electrode layer 3210a and the second storage node electrode layer 3210b can be configured to be spaced apart from each other in a third lateral direction that is not parallel to the first lateral direction (i.e., the x-direction) and the second lateral direction (i.e., the y-direction). Although not in Figure 25B As shown, a capacitor dielectric layer and a plate electrode layer can be sequentially disposed on the first storage node electrode layer 3210a and the second storage node electrode layer 3210b to form a capacitor device.

[0119] manufacture Figure 25B The method of semiconductor device 6 can be combined with the above. Figures 18A to 24A as well as Figures 18B to 24BThe methods for manufacturing semiconductor devices are essentially the same.

[0120] Figure 26A and Figure 26B This is a schematic plan view of a semiconductor device according to yet another embodiment of the present disclosure. According to one embodiment, Figure 26A A semiconductor device 7 including a channel structure is shown, and Figure 26B A semiconductor device 8, including a channel structure and capacitor devices, is shown. As an example, Figure 26B The semiconductor device 8 may further include a semiconductor device disposed in a manner that allows for the application of semiconductor devices ... Figure 26A Capacitor devices above the channel structure.

[0121] Figure 26A The semiconductor device 7 is similar in shape to the first channel structure 4145a and the second channel structure 4145b. Figure 15A and Figure 15B The semiconductor devices are different. Figure 15A The first channel structure 1145a and the second channel structure 1145b of the semiconductor device 3 shown are symmetrically arranged with respect to the insulating wire structure 1130, while Figure 26A The first channel structure 4145a and the second channel structure 4145b of the semiconductor device 7 shown can be arranged asymmetrically with respect to the insulating wire structure 1130. The first channel structure 4145a and the second channel structure 4145b can be configured not to face each other on both sides of the insulating wire structure 1130. In addition, the first channel structure 4145a and the second channel structure 4145b can be arranged alternately in a Z-shape or pattern on both sides of the insulating wire structure 1130 along a second lateral direction (i.e., the y-direction).

[0122] Furthermore, the first channel structure 4145a and the second channel structure 4145b facing each other on the sides of adjacent different insulated wire structures 1130 can be spaced apart from each other in a third lateral direction (i.e., the D21 direction or the D22 direction) that is not parallel to the first lateral direction (i.e., the x direction) and the second lateral direction (i.e., the y direction).

[0123] manufacture Figure 26A The method of semiconductor device 7 can be combined with the above. Figures 18A to 22A as well as Figures 18B to 22B The methods for manufacturing semiconductor devices are essentially the same.

[0124] Figure 26B The semiconductor device 8 is similar in shape or arrangement to the first storage node electrode layer 4210a and the second storage node electrode layer 4210b. Figure 17A and Figure 17B The semiconductor devices are different. Figure 17A and Figure 17BIn the semiconductor device 4, the first storage node electrode layer 1210a and the second storage node electrode layer 1210b are configured to be spaced apart from each other in the first lateral direction (i.e., the x-direction), while Figure 26B The first storage node electrode layer 4210a and the second storage node electrode layer 4210b in the semiconductor device 8 can be configured to be spaced apart from each other in a third lateral direction that is not parallel to the first lateral direction (i.e., the x direction) and the second lateral direction (i.e., the y direction).

[0125] manufacture Figure 26B The method of semiconductor device 8 can be combined with the above. Figures 18A to 24A as well as Figures 18B to 24B The methods for manufacturing semiconductor devices described are essentially the same.

[0126] Embodiments of this disclosure have been disclosed for illustrative purposes. Those skilled in the art will understand that various modifications, additions, and substitutions may be made without departing from the scope and spirit of this disclosure and the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; Multiple bit line conductive layers are disposed above the substrate and extend in a first lateral direction parallel to the surface of the substrate. The multiple bit line conductive layers are spaced apart from each other in a second lateral direction, which is perpendicular to the first lateral direction and parallel to the surface of the substrate. Multiple channel structures are disposed on the multiple bit line conductive layers. The multiple channel structures include a first channel structure and a second channel structure spaced apart from each other in the first lateral direction, and a third channel structure and a fourth channel structure spaced apart from each other in the first lateral direction. The first channel structure and the third channel structure are spaced apart from each other in the second lateral direction, and the second channel structure and the fourth channel structure are spaced apart from each other in the second lateral direction. A first gate dielectric layer and a second gate dielectric layer are disposed above the substrate on the side surfaces of the plurality of channel structures. The first gate dielectric layer extends continuously in the second lateral direction to cover the first channel structure and the third channel structure, and the second gate dielectric layer extends continuously in the second lateral direction to cover the second channel structure and the fourth channel structure. A first gate line conductive layer and a second gate line conductive layer are respectively disposed on the first gate dielectric layer and the second gate dielectric layer. The first gate line conductive layer and the second gate line conductive layer are adjacent to the first channel structure and the second channel structure in the first lateral direction, and extend in a second lateral direction that is perpendicular to the first lateral direction and parallel to the substrate surface. as well as A first storage node electrode layer, a second storage node electrode layer, a third storage node electrode layer, and a fourth storage node electrode layer are respectively disposed above the first channel structure, the second channel structure, the third channel structure, and the fourth channel structure. The first storage node electrode layer and the second storage node electrode layer are configured to be spaced apart from each other in a third lateral direction, which is not parallel to either the first lateral direction or the second lateral direction and is parallel to the substrate surface.

2. The semiconductor device according to claim 1, wherein, Each of the first and second channel structures has a columnar shape extending above the substrate in a direction perpendicular to the first and second lateral directions.

3. The semiconductor device according to claim 1, wherein, The first channel structure has a first channel first side and a first channel second side parallel to the second transverse direction. The first gate line conductive layer has a first gate first line pattern adjacent to the first side of the first channel and a first gate second line pattern adjacent to the second side of the first channel, and The first gate first line pattern and the first gate second line pattern are configured to have the same potential.

4. The semiconductor device according to claim 3, wherein, The first gate dielectric layer has a first thickness in the first lateral direction between the first gate first line pattern and the first side surface of the first channel. Wherein, the first gate dielectric layer has a second thickness in the first lateral direction between the first gate second line pattern and the second side surface of the first channel, and The first thickness is the same as the second thickness.

5. The semiconductor device according to claim 1, wherein, The second channel structure has a first side of the second channel and a second side of the second channel parallel to the second transverse direction. The second gate line conductive layer has a second gate first line pattern adjacent to the first side of the second channel and a second gate second line pattern adjacent to the second side of the second channel, and The second gate first line pattern and the second gate second line pattern are configured to have the same potential.

6. The semiconductor device according to claim 5, wherein, The second gate dielectric layer has a third thickness in the first lateral direction between the second gate first line pattern and the second channel first side. Wherein, the second gate dielectric layer has a fourth thickness in the first lateral direction between the second gate second line pattern and the second side of the second channel, and The third thickness is the same as the fourth thickness.

7. The semiconductor device according to claim 1, further comprising: A capacitor dielectric layer is disposed on the first storage node electrode layer and the second storage node electrode layer; and A plate electrode layer is disposed on the dielectric layer of the capacitor.

8. A method for manufacturing a semiconductor device, the method comprising: A plurality of bit line structures are formed above a substrate, the plurality of bit line structures extending in a first lateral direction parallel to the surface of the substrate and spaced apart from each other in a second lateral direction perpendicular to the first lateral direction and parallel to the surface of the substrate, and each of the plurality of bit line structures includes a bit line pattern layer and a first insulating layer disposed on the bit line pattern layer. A second insulating layer is formed, which fills the space above the substrate and between the plurality of bit line structures; A plurality of insulating wire structures are formed by patterning the first insulating layer and the second insulating layer along the second transverse direction, the plurality of insulating wire structures extending in the second transverse direction and spaced apart from each other in the first transverse direction; Multiple channel structures are formed on the side surfaces of the multiple insulating wire structures and the multiple bit line pattern layers; A first dielectric material layer covering the plurality of channel structures and the plurality of insulating wire structures is formed above the substrate; A plurality of first gate line pattern layers are formed above the first dielectric material layer, the first gate line pattern layers extending along the second lateral direction and adjacent to both sides of each of the plurality of insulating wire structures; Selectively remove the plurality of insulating wire structures above the substrate to selectively expose the plurality of channel structures and the first dielectric material layer; A second dielectric material layer is formed, which covers the exposed plurality of channel structures above the substrate and the first dielectric material layer; as well as A plurality of second gate line pattern layers extending in the second lateral direction are formed above the second dielectric material layer.

9. The method of claim 8, further comprising: A storage node electrode layer is formed above the plurality of channel structures. Wherein, the first storage node electrode layer and the second storage node electrode layer, respectively formed on a pair of adjacent channel structures in the first lateral direction within the plurality of channel structures, are configured to be spaced apart from each other in the third lateral direction, and The third lateral direction is parallel to the substrate surface, but not parallel to the first lateral direction and the second lateral direction.

10. The method of claim 9, further comprising: A capacitor dielectric layer is formed on the storage node electrode layer; as well as A plate electrode layer is formed on the dielectric layer of the capacitor.

11. The method according to claim 8, wherein, Forming the plurality of insulated wire structures includes etching the first insulating layer to selectively expose the bit line pattern layer.

12. The method of claim 11, wherein, The formation of the plurality of channel structures includes: A channel material layer is formed on the side surface of each of the plurality of insulated wire structures, the channel material layer being electrically connected to the exposed bit line pattern layer; and The portion of the channel material layer not directly disposed on the bit line pattern layer is etched.

13. The method according to claim 8, wherein, The portions of the first dielectric material layer and the second dielectric material layer formed on the plurality of channel structures have the same thickness.

14. A semiconductor device, comprising: Substrate; The bit line conductive layer extends in a first lateral direction parallel to the surface of the substrate; A first insulating wire structure extends in a second lateral direction that is perpendicular to the first lateral direction and parallel to the surface of the substrate; A first channel structure and a second channel structure are configured to contact a first side and a second side of the first insulating wire structure, respectively, and at least a portion of the first channel structure and the second channel structure overlaps with the bit line conductive layer. A first gate dielectric layer and a second gate dielectric layer are respectively disposed above the substrate and on the side surfaces of the first channel structure and the second channel structure; and A first gate line conductive layer and a second gate line conductive layer extend on the substrate in the second lateral direction and respectively cover at least a portion of each of the first gate dielectric layer and the second gate dielectric layer.

15. The semiconductor device according to claim 14, wherein, Each of the first and second channel structures has a columnar shape extending in a direction perpendicular to the substrate surface and perpendicular to the first and second lateral directions.

16. The semiconductor device according to claim 14, wherein, The first channel structure and the second channel structure are configured to protrude from the first side and the second side of the first insulating wire structure in opposite directions, respectively. Each of the first channel structure and the second channel structure has a side surface with curvature.

17. The semiconductor device according to claim 14, wherein, At least a portion of each of the first and second channel structures is configured to face each other in the first lateral direction, with the first insulating wire structure located between them.

18. The semiconductor device according to claim 14, wherein, The first channel structure and the second channel structure are arranged symmetrically with respect to the first insulated wire structure.

19. The semiconductor device according to claim 14, wherein, The first channel structure and the second channel structure are arranged in a Z-shape on the first and second sides of the first insulating wire structure along the second lateral direction.

20. The semiconductor device of claim 14, further comprising: The first storage node electrode layer and the second storage node electrode layer are respectively disposed on the first channel structure and the second channel structure; A capacitor dielectric layer is disposed on the first storage node electrode layer and the second storage node electrode layer; and A plate electrode layer is disposed on the dielectric layer of the capacitor.

21. The semiconductor device of claim 14, further comprising: The second insulating wire structure is configured to be spaced apart from the first insulating wire structure in the first transverse direction and is configured to extend in the second transverse direction. The third and fourth channel structures are configured to contact the first and second side surfaces of the second insulating wire structure, respectively, and at least a portion of the third and fourth channel structures overlaps with the bit line conductive layer. A third gate dielectric layer and a fourth gate dielectric layer are disposed above the substrate and surround the side surfaces of the third channel structure and the fourth channel structure, respectively. as well as A third gate line conductive layer and a fourth gate line conductive layer extend over the substrate in the second lateral direction and are configured to cover the third gate dielectric layer and the fourth gate dielectric layer, respectively. In this configuration, one of the third and fourth channel structures is spaced apart from one of the first and second channel structures in a third lateral direction, wherein the third lateral direction is not parallel to the first and second lateral directions and is parallel to the substrate surface.

22. A method for manufacturing a semiconductor device, the method comprising: Multiple bit line conductive layers are formed, which extend on the substrate in a first lateral direction parallel to the surface of the substrate and are configured to be spaced apart from each other in a second lateral direction perpendicular to the first lateral direction and parallel to the surface of the substrate. A first insulating layer and a second insulating layer covering the plurality of bit line conductive layers are sequentially formed over the substrate; The second insulating layer above the substrate is selectively etched to form a plurality of first trench line patterns that extend in the second lateral direction and are spaced apart from each other in the first lateral direction, each of the plurality of first trench line patterns having a protruding pattern portion extending in a direction not parallel to the second lateral direction. A gate line conductive layer is formed on the side surface of the plurality of first trench line patterns; The first insulating layer is etched inside the plurality of first trench line patterns above the substrate to form a plurality of second trench line patterns; A dielectric material layer is formed on the surface of the gate line conductive layer and on the side surfaces of the plurality of second trench line patterns; A channel material layer is formed inside the plurality of first groove line patterns and the plurality of second groove line patterns; as well as The dielectric material layer and the channel material layer disposed within the plurality of first trench line patterns and the plurality of second trench line patterns are selectively removed to form a gate dielectric layer and a channel structure in the protruding pattern portion.

23. The method according to claim 22, wherein, In the step of forming the gate dielectric layer and the channel structure, each of the gate dielectric layer and the channel structure is formed above the substrate and arranged discontinuously along the second lateral direction.

24. The method according to claim 22, wherein, The first insulating layer and the second insulating layer have etch selectivity towards each other.

25. The method according to claim 22, wherein, In the step of forming the plurality of first groove line patterns The protruding pattern portion of one of the first groove line patterns is formed to be spaced apart from the protruding pattern portion of the adjacent first groove line pattern in a direction that is not parallel to the first lateral direction and the second lateral direction.

26. The method according to claim 22, wherein, The step of forming the plurality of second trench line patterns includes: etching the first insulating layer to expose a portion of each of the plurality of bit line conductive layers.

27. The method of claim 22, further comprising: The space in which the dielectric material layer and the channel material layer have been removed is filled with insulating material.

28. The method of claim 22, further comprising: A storage node electrode layer is formed on the channel structure; A capacitor dielectric layer is formed on the storage node electrode layer; as well as A plate electrode layer is formed on the dielectric layer of the capacitor.

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