Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a plurality of active layers stacked in a first direction perpendicular to a substrate and oriented laterally in a second direction intersecting the first direction; a plurality of bit lines, each of which is coupled to one side of each active layer and oriented laterally in a direction intersecting the first direction and the second direction; a plurality of capacitors, each of which is coupled to the other side of each active layer; and a word line, which is oriented vertically in the first direction and passes through the active layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0134490, filed on October 16, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a memory cell stack and a method of manufacturing the semiconductor device. Background Art

[0004] Recently, in order to increase the net die of a memory device, the size of a memory cell has been continuously reduced.

[0005] As the size of the memory cell becomes smaller, the parasitic capacitance Cb should decrease and the capacitance should increase. However, it is difficult to increase the net die due to the structural limitations of the memory cell. Summary of the invention

[0006] Embodiments of the present invention relate to a semiconductor device including a highly integrated memory cell and a method for manufacturing the semiconductor device.

[0007] According to one embodiment of the present invention, a semiconductor device includes: a plurality of active layers stacked in a first direction perpendicular to a substrate and laterally oriented in a second direction intersecting the first direction; a plurality of bit lines, each of which is coupled to one side of each active layer and laterally oriented in a direction intersecting the first direction and the second direction; a plurality of capacitors, each of which is coupled to the other side of each active layer; and word lines, which are vertically oriented to pass through the active layers in the first direction.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming an etch stop layer on a substrate; forming a mold stack body in which dielectric layers and semiconductor layers are alternately stacked on the etch stop layer; forming a first groove by etching the mold stack body; recessing one side of the semiconductor layer through the first groove to form a first recessed portion between the dielectric layers; forming a laterally oriented bit line in the first recessed portion; etching the mold stack body in a direction intersecting the bit line to form a second groove dividing the mold stack body into a plurality of linear stack bodies; and forming a vertically oriented word line passing through the linear stack body.

[0009] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: preparing a substrate including a peripheral circuit; forming a die stack on the substrate in which dielectric layers and active layers are alternately stacked; replacing one side of the active layer with a laterally oriented bit line; forming an isolation layer that divides the die stack into a plurality of linear stacks; forming a vertically oriented word line passing through the active layer; and forming a laterally oriented capacitor coupled to the other side of the active layer.

[0010] These and other features and advantages will become better understood from the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 2 It is the layout of semiconductor devices.

[0013] Figure 3 is along Figure 2 A cross-sectional view taken along lines AA' and BB'.

[0014] Figure 4A to Fig.18B A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0015] Fig.19 is a layout of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will describe various embodiments of the present invention in more detail with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the present disclosure, throughout the various drawings and embodiments of the present invention, the same reference numerals represent the same parts.

[0017] The drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it means not only the case where the first layer is formed directly on the second layer or substrate, but also the case where a third layer exists between the first layer and the second layer or substrate.

[0018] In the following embodiments of the present invention, memory cells may be vertically stacked to increase memory cell density and reduce parasitic capacitance.

[0019] Figure 1is a schematic perspective view of a semiconductor device 100 according to an embodiment of the present invention. Figure 2 is the layout of the semiconductor device 100 . Figure 3 Shown along Figure 2 A cross-sectional view taken along lines AA' and BB' shown in FIG.

[0020] Reference Figures 1 to 3 , the semiconductor device 100 may include a substrate LS and a plurality of memory cell stacks, for example, memory cell stacks MCS1 and MCS2 formed on the substrate LS. The memory cell stacks MCS1 and MCS2 may be oriented in a first direction D1 perpendicular to the substrate LS. The substrate LS may extend in a plane defined by a second direction D2 and a third direction D3. The memory cell stacks MCS1 and MCS2 may be oriented perpendicular to the plane of the substrate LS. The memory cell stacks MCS1 and MCS2 may be oriented vertically upward from the substrate LS in the first direction D1. Figure 3 As shown in , the memory cell stacks MCS1 and MCS2 may be located on the EST etch stop layer. The memory cell stacks MCS1 and MCS2 may include a three-dimensional array of memory cells MC. Each of the memory cell stacks MCS1 and MCS2 may include a plurality of memory cells MC. Each memory cell MC of the memory cell stacks MCS1 and MCS2 may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR and the capacitor CAP may be oriented laterally in the second direction D2. Each memory cell MC may also include a word line WL. The word line WL may be oriented vertically in the first direction D1. The bit line BL may be oriented laterally in the third direction D3. In each memory cell MC, the bit line BL, the transistor TR, the capacitor CAP, and the plate line PL may be arranged in a lateral arrangement in the second direction D2. The memory cell stacks MCS1 and MCS2 may be referred to as memory cell arrays. The memory cell stacks MCS1 and MCS2 may include a dynamic random access memory (DRAM) memory cell array. According to another embodiment of the present invention, the memory cell stacks MCS1 and MCS2 may include phase change random access memory (PCRAM), resistance random access memory (RERAM), and magnetic random access memory (MRAM), etc. The capacitor CAP may be replaced with other memory elements.

[0021] The substrate LS may be made of any material suitable for semiconductor processing. The substrate LS may include at least one of a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed on the substrate LS. The substrate LS may include a semiconductor substrate. The substrate LS may be formed of a silicon-containing material. The substrate LS may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers thereof. The substrate LS may also include other semiconductor materials, such as germanium. The substrate LS may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate LS may include a silicon-on-insulator (SOI) substrate.

[0022] The substrate LS may include a peripheral circuit (not shown). The peripheral circuit may include a plurality of control circuits for controlling the memory cell stacks MCS1 and MCS2. At least one control circuit of the peripheral circuit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit may include an address decoder circuit, a read circuit, and a write circuit. At least one control circuit of the peripheral circuit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0023] For example, at least one control circuit of the peripheral circuit may be electrically connected to the bit line BL. The peripheral circuit may include a sense amplifier SA, and the sense amplifier SA may be electrically connected to the bit line. Although not shown, a multi-level metal line MLM may be located between the memory cell stacks MCS1 and MCS2 and the substrate LS. The peripheral circuit and the bit line BL may be coupled to each other through the multi-level metal line MLM.

[0024] The bit line BL may extend in a third direction D3 parallel to the upper surface of the substrate LS. The bit line BL may be spaced apart from the substrate LS and oriented laterally. The bit line BL may be referred to as a laterally oriented bit line. The bit line BL may include a conductive material. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Memory cells MC arranged laterally in the same row in the third direction may share one bit line BL. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The bit line BL may include a stack (TiN / W) of titanium nitride and tungsten. The bit line BL may also include an ohmic contact layer, such as a metal silicide.

[0025] The transistor TR may be arranged in a lateral arrangement along a second direction D2 parallel to the surface of the substrate LS. The transistor TR may be positioned laterally between the bit line BL and the capacitor CAP. The transistor TR may be located at a level higher than the substrate LS. The transistor TR and the substrate LS may be spaced apart from each other.

[0026] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend vertically in a first direction D1, and the active layer ACT may extend in a second direction D2. The first direction D1 may be a direction perpendicular to the second direction D2. The active layer ACT may be arranged laterally with respect to the bit line BL. The active layer ACT may be oriented parallel to the plane of the substrate LS.

[0027] The word line WL may have a pillar shape passing through the active layer ACT. The word line WL may have a Figure 1 The cross-sectional area is a circle as shown in FIG. 1 , however, other shapes may be adopted without departing from the scope of the present invention. The gate dielectric layer GD may be formed on the sidewall of the word line WL. The gate dielectric layer GD may surround the sidewall of the pillar-type word line WL.

[0028] The gate dielectric layer GD may include, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material, or a combination thereof. For example, the gate dielectric layer GD may include SiO 2 、Si 3 N 4 , HfO 2 、Al 2 O 3 、ZrO 2 , AlON, HfON, HfSiO, and HfSiON, etc.

[0029] The word line may include a metal, a metal mixture, a metal alloy, or a semiconductor material. For example, the word line WL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the word line WL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The word line WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 or less, while the P-type work function material may have a high work function of about 4.5 or more.

[0030] The word lines WL and the bit lines BL may extend in intersecting directions.

[0031] The active layer ACT may include any suitable semiconductor material, including, for example, polysilicon. The active layer ACT may include a plurality of impurity regions. The impurity regions may include a first region SD1 and a second region SD2, which may be a source or a drain and are also referred to below as a first source / drain region SD1 and a second source / drain region SD2. The active layer ACT may include, for example, doped polysilicon, undoped polysilicon, amorphous silicon, or an oxide semiconductor material. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type impurities or P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with impurities of the same conductivity type. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The bit line BL may be electrically connected to a first edge portion of the active layer ACT, and the capacitor CAP may be electrically connected to a second edge portion of the active layer ACT. The first edge portion of the active layer ACT may be provided by the first source / drain region SD1, and the second edge portion of the active layer ACT may be provided by the second source / drain region SD2.

[0032] The adjacent active layer ACT in the third direction D3 can be Figure 2 The isolation layer IL shown in the figure isolates and supports. The isolation layer IL can be located between adjacent memory cells MC in the third direction D3. The isolation layer IL can also be located between adjacent memory cells MC in the second direction D2. The isolation layer IL can also be located between adjacent memory cells MC in the first direction D1. The isolation layer IL can include a dielectric material, such as an oxide.

[0033] The capacitor CAP may be disposed laterally relative to the transistor TR. The capacitor CAP may extend laterally from the active layer ACT in the second direction D2. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The dielectric layer DE may be referred to as a capacitor dielectric layer. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged laterally in the second direction D2. The storage node SN may have a laterally oriented barrel shape, and the plate node PN may have a shape of a barrel inner wall and a barrel outer wall extending to the storage node SN. The dielectric layer DE may be located inside the storage node SN while surrounding the plate node PN. The plate node PN may be coupled to the plate line PL. The storage node SN may be electrically connected to the second source / drain region SD2.

[0034] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include, for example, silicon oxide, silicon nitride, a high-k material, or a combination thereof. The dielectric constant of the high-k material may be higher than that of silicon oxide. Silicon oxide (SiO 2 ) may have a dielectric constant of about 3.9, and the dielectric layer DE may include a high dielectric constant material having a dielectric constant of about 4 or more. The dielectric constant of the high-k material may be about 20 or more. The high-k material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ) or strontium titanium oxide (SrTiO 3 According to another embodiment of the present invention, the dielectric layer DE may be composed of a composite layer, which includes two or more layers of the above-mentioned high-K material.

[0035] The dielectric layer DE may be formed of zirconium-based oxide. The dielectric layer DE may have a zirconium oxide (ZrO 2 ) stacked structure. Including zirconium oxide (ZrO 2 ) can include a stacked structure of ZA(ZrO 2 / Al 2 O 3 ) stack or ZAZ(ZrO 2 / Al 2 O 3 / ZrO 2 ) stack. The ZA stack may have an aluminum oxide (Al 2 O 3 ) stacked on zirconium oxide (ZrO 2 ) on a ZAZ stack. The ZAZ stack may have a structure in which zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ) and zirconium oxide (ZrO 2 ) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide-based layer. According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium-based oxide. The dielectric layer DE may have a structure including hafnium oxide (HfO2 ) stacked structure. Including hafnium oxide (HfO 2 ) can include a stacked structure of HA(HfO 2 / Al 2 O 3 ) stack or HAH(HfO 2 / Al 2 O 3 / HfO 2 ) stack. The HA stack may have an aluminum oxide (Al 2 O 3 ) stacked on hafnium oxide (HfO 2 ) on a HAH stack. The HAH stack may have a structure in which hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ) are stacked sequentially. The HA stack and the HAH stack can be referred to as a hafnium oxide based layer (HfO 2 In ZA stacks, ZAZ stacks, HA stacks and HAH stacks, aluminum oxide (Al 2 O 3 ) can have a larger band gap than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Aluminum oxide (Al 2 O 3 ) can have a lower dielectric constant than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material having a bandgap greater than that of the high-k material. The dielectric layer DE may include, for example, silicon oxide (SiO 2 ) as aluminum oxide (Al 2 O 3 ). Since the dielectric layer DE includes the high bandgap material, leakage current can be suppressed. The high bandgap material can be very thin. The high bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure in which the high-k material and the high bandgap material are alternately stacked. For example, the dielectric layer DE may include ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 )、ZAZAZ(ZrO 2 / Al 2 O 3 / ZrO2 / Al 2 O 3 / ZrO 2 ), HAHA(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) or HAHAH(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 In the above-mentioned laminated structure, aluminum oxide (Al 2 O 3 ) can be very thin.

[0036] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a laminated structure, or a mixed structure including zirconium oxide, hafnium oxide, and aluminum oxide.

[0037] According to another embodiment of the present invention, an interface control layer (not shown) for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO 2 ). An interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0038] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material inside the barrel filling the storage node SN, and titanium nitride (TiN) may be used as a plate node of an actual capacitor CAP, while tungsten nitride may be a low resistance material. Adjacent plate nodes PN are coupled to the plate line PL in common. The bottom of the plate line PL may be insulated from the substrate LS.

[0039] The storage node SN may have a three-dimensional (3D) structure, and the storage node SN having the 3D structure may have a lateral 3D structure oriented in the second direction D2. As an example of a three-dimensional structure, the storage node SN may have a barrel, a column, or a cylindrical barrel shape. The cylindrical barrel shape may indicate a structure in which a column and a barrel are combined.

[0040] Reference Figure 3 , the isolation layer IL and the active layer ACT may be alternately stacked in the first direction D1, and a plurality of word lines WL vertically passing through the active layer ACT and the isolation layer IL may be formed. A plurality of bit lines BL laterally oriented in the third direction D3 may be formed in a direction intersecting the WL word lines. The active layer ACT, the bit lines BL, and the storage node SN may be located at the same level.

[0041] Figures 1 to 3 The semiconductor device 100 may have a mirror structure sharing the plate line PL.

[0042] FIG. 4A to FIG. 18B A method for manufacturing a semiconductor device is shown. FIG. 4A to FIG. 18A is along Figure 2 A cross-sectional view taken along line A-A', and FIG. 4B to FIG. 18B is along Figure 2 A cross-sectional view taken along line BB'.

[0043] Reference Figure 4A and 4B, a mold stack 20 may be formed on the substrate 11. The mold stack 20 may include a dielectric layer 21 and a semiconductor layer 22. For example, the mold stack 20 may include a plurality of dielectric layers 21 and a plurality of semiconductor layers 22 that are alternately stacked. The dielectric layers 21 and the semiconductor layers 22 may be vertically stacked in a first direction D1 perpendicular to the surface of the substrate 11. The dielectric layer 21 may include, for example, silicon oxide, and the semiconductor layer 22 may include, for example, a polysilicon layer. The lowermost layer and the uppermost layer of the mold stack 20 may be the dielectric layer 21. The lowermost dielectric layer 21 may be used as an etch stop layer EST.

[0044] Reference Figure 5A and Figure 5B , a first trench 23 may be formed in the mold stack 20. In order to form the first trench 23, a portion of the mold stack 20 may be etched. The first trench 23 may extend vertically in a first direction D1, and may extend laterally in a third direction D3. The bottom surface of the first trench 23 may be provided by the lowermost dielectric layer 21. For example, the first trench 23 may not expose the substrate 11, and the lowermost dielectric layer 21 may be located between the lowermost semiconductor layer 22 and the substrate 11. The dielectric layer 21 and the semiconductor layer 22 may extend laterally in a second direction D2 parallel to the surface of the substrate 11.

[0045] Reference Fig. 6A and Figure 6B , the semiconductor layer 22 may be laterally recessed near their ends by the first trench 23 to form a first recessed portion 24. Therefore, the first recessed portion 24 and the recessed semiconductor layer 22R may be located between the dielectric layers 21 vertically arranged in the first direction D1. The first recessed portion 24 may also be referred to as an air gap. The first recessed portion 24 may expose the first edge E1 of the recessed semiconductor layer 22R, respectively.

[0046] Reference Fig. 7A and Figure 7B , first impurity regions 25 may be formed on first edges E1 of the recessed semiconductor layer 22R, respectively. The first impurity regions 25 may be formed by ion implantation of impurities through the trench 23. For example, the first impurity regions 25 may be formed by plasma doping. The first impurity regions 25 may include N-type impurities or P-type impurities. The first impurity regions 25 may include, for example, phosphorus, arsenic, antimony, boron, or indium. The first impurity regions 25 may be referred to as source / drain regions.

[0047] Reference Fig. 8A and Figure 8B, bit lines 26 coupled to the first impurity regions 25, respectively, may be formed. The bit lines 26 may be formed of a metal-based material, including, for example, titanium nitride, tungsten, titanium silicide, or a combination thereof. The bit lines 26 may fill each first recess 24. The bit lines 26 may be vertically arranged in the first direction D1. In addition, each bit line 26 may extend laterally in the third direction D3. The bit lines 26 may be electrically connected to the recessed semiconductor layer 22R through the first impurity regions 25, respectively.

[0048] Reference Fig. 9A and Fig. 9B , a first isolation layer 27 may be formed in the first trench 23. The first isolation layer 27 may completely fill the first trench 23. The first isolation layer 27 may include a dielectric material. The first isolation layer 27 may include, for example, silicon oxide. For example, the first isolation layer 27 may be formed by forming silicon oxide to fill the first trench 23 and planarizing the silicon oxide.

[0049] Reference Fig. 10A and Fig. 10B , a plurality of second trenches 28 may be formed by etching a portion of the mold stack 20. From a top view perspective, the second trenches 28 may be elongated in the second direction D2, and may divide the mold stack 20 into a plurality of line-type stacks 20L. The second trenches 28 may be formed between the line-type stacks 20L. Both ends of the second trenches 28 may contact the first impurity region 25. The line-type stack 20L may be formed by alternately stacking a plurality of dielectric layer lines 21L and a plurality of semiconductor layer lines 22L. The dielectric layer lines 21L may be formed by etching the dielectric layer 21, and the semiconductor layer lines 22L may be formed by etching the recessed semiconductor layer 22R. The lowermost dielectric layer 21 may remain unetched.

[0050] Reference Fig.11A and Fig. 11B , a second isolation layer 29 may be formed in the second trench 28. The second isolation layer 29 may completely fill the second trench 28. The second isolation layer 29 may include a dielectric material. The second isolation layer 29 may include, for example, silicon oxide. For example, the second isolation layer 29 may be formed by forming silicon oxide to fill the second trench 28 and then planarizing the silicon oxide.

[0051] The line-type stacked bodies 20L may be separated from each other not only by the second isolation layer 29 but also by the adjacent first isolation layer 27. Each of the line-type stacked bodies 20L may be formed by alternately stacking a plurality of dielectric layer lines 21L and a plurality of semiconductor layer lines 22L.

[0052] Reference Fig. 12A and Fig. 12B, a through hole 30 may be formed passing through the line type stacked body 20L. The through hole 30 may extend vertically in the first direction D1. At least two through holes 30 may pass through a single line type stacked body 20L. The through hole 30 may pass through the dielectric layer line 21L and the semiconductor layer line 22L. The through hole 30 may not pass through the lowermost dielectric layer 21. The through hole 30 may be positioned closer to the end of the line type stacked body 20L but not contacting the impurity region 25.

[0053] Reference Fig.13A and Fig. 13B , a gate dielectric layer 31 may be formed. The gate dielectric layer 31 may be formed on the sidewalls of the semiconductor layer line 22L exposed by the through hole 30. For example, to form the gate dielectric layer 31, the sidewalls of the semiconductor layer line 22L exposed by the through hole 30 may be selectively oxidized. The gate dielectric layer 31 and the semiconductor layer line 22L may be located at the same level. The gate dielectric layer 31 may not be formed on the sidewalls of the dielectric layer line 21L.

[0054] Subsequently, a word line 32 filling the via hole 30 may be formed on the gate dielectric layer 31. The word line 32 may be formed by depositing a conductive material to fill the via hole 30 and performing a planarization process such as chemical mechanical polishing (CMP). The word line 32 may extend vertically in the first direction D1. At least two word lines 32 may pass through a single linear stack 20L. The word line 32 may pass through the dielectric layer line 21L and the semiconductor layer line 22L.

[0055] Reference Fig.14A and 14B , the line type stacked body 20L may be divided into a plurality of unit stacked bodies 20M separated by the third groove 33. For example, the third groove 33 may have a shape that crosses the center of the line type stacked body 20L in the third direction D3. The third groove 33 may also divide the dielectric layer line 21L. The third groove 33 may cut the dielectric layer line 21L and the semiconductor layer line 22L.

[0056] Due to the formation of the third trench 33, a plurality of unit stacks 20M may be formed on the substrate 11. Each unit stack 20M may include a plurality of isolation layers 21M and a plurality of active layers 22M. Each unit stack 20M may be formed by alternately stacking isolation layers 21M and active layers 22M. The isolation layer 21M may be formed by cutting the dielectric layer line 21L. The active layer 22M may be formed by cutting the semiconductor layer line 22L.

[0057] Reference Fig.15A and Fig. 15B , the side surface of each active layer 22M adjacent to the third trench 33 may be selectively recessed by the third trench 33. As a result, a second recessed portion 34 for forming a capacitor may be formed.

[0058] Subsequently, second impurity regions 35 may be formed in the second edges E2 of the active layer 22M exposed by the second recessed portion 34, respectively. The second impurity regions 35 may be formed by ion implantation of impurities introduced via the third trench 33. The second impurity regions 35 may be formed by a plasma doping process. The second impurity regions 35 may include N-type impurities or P-type impurities. The second impurity regions 35 may include phosphorus, arsenic, antimony, boron, or indium. The second impurity regions 35 may be referred to as source / drain regions. The word line 32 may pass through the active layer 22M, and the first impurity region 25 and the second impurity region 35 may be formed on both sides of the word line 32.

[0059] Reference Fig.16A and Fig. 16B , a storage node 36 directly coupled to the second impurity region 35 may be formed. The storage node 36 may be formed of a metal-based material, including, for example, titanium nitride, tungsten, titanium silicide, or a combination thereof. The storage nodes 36 may fill the second recesses 34, respectively. The storage nodes 36 may have a cylindrical shape extending laterally in the second direction D2. Adjacent storage nodes 36 in the second direction D2 may face each other, with the third trench 33 disposed therebetween. The storage nodes 36 and the isolation layer 21M may be stacked in the first direction D1.

[0060] Reference Fig.17A and Fig. 17B , one side of each isolation layer 21M may be recessed by an etching process indicated by reference numeral 37. The second isolation layer 29 may be recessed together with the isolation layer 21M. Therefore, both the inner wall and the outer wall of the storage node 36 may be exposed.

[0061] Reference Fig.18A and Fig.18B , a capacitor dielectric layer 38 may be formed on the storage node 36. A plate node 39 may be formed on the capacitor dielectric layer 38 to fill the trench 33.

[0062] Fig.19 is a layout of a semiconductor device 200 according to another embodiment of the present invention.

[0063] Reference Fig.19 ,and Figures 1 to 3 The same reference numerals in the drawings may denote the same components. The semiconductor device 200 may be similar to Figures 1 to 3 The semiconductor device 100 shown in FIG. Fig.19 Also appears in Figures 1 to 3 A detailed description of the constituent elements may be omitted.

[0064] Reference Fig.19, the semiconductor device 200 may include a plurality of memory cells MC. Each memory cell MC may include a bit line BL, a word line WL, a transistor TR including an active layer ACT', and a capacitor CAP. The bit line BL may be laterally oriented in a third direction D3, and the word line WL may be vertically oriented in a first direction D1. The transistor TR may include an active layer ACT' laterally oriented in a second direction D2.

[0065] The active layer ACT' may include an active layer body BE and protrusions PE on both sides of the active layer body BE. The protrusions PE may be symmetrical to each other relative to a center line of the active layer body BE. The active layer body BE and the protrusions PE may form a generally cross shape, and both the active layer body BE and the protrusions PE have a generally rectangular shape. The protrusions PE may be much smaller than the active layer body BE. The width of the protrusions PE may be smaller than the width of the active layer body BE. For example, the width of the protrusions PE in the third direction may be smaller than that of the active layer body BE. The word line WL may pass through the active layer body BE.

[0066] According to an embodiment of the present invention, since memory cells are vertically stacked, cell density can be improved.

[0067] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A semiconductor device, comprising: a plurality of active layers stacked in a first direction perpendicular to the substrate and laterally oriented in a second direction intersecting the first direction; a plurality of common impurity regions, each of the common impurity regions being coupled to one side of a plurality of active layers arranged in a third direction intersecting the first direction and the second direction; a plurality of bit lines, each of the bit lines being coupled to each of the common impurity regions extending parallel to the bit lines and being laterally oriented in the third direction; a plurality of capacitors, each capacitor coupled to the other side of each of the active layers; as well as A word line is vertically oriented and passes through the active layer in a first direction.

2. The semiconductor device according to claim 1, wherein The active layer comprises: an active layer body oriented in the second direction; and A protrusion extends from the active layer body in the second direction.

3. The semiconductor device according to claim 2, wherein: Each protrusion has a smaller width than the active layer body.

4. The semiconductor device according to claim 1, wherein: The active layer, the bit line, and the capacitor are located at the same level.

5. The semiconductor device according to claim 1, wherein Each capacitor consists of: A cylindrical storage node is coupled to the other side of each active layer: a dielectric layer on the storage node; and a plate node on the dielectric layer, wherein The cylindrical storage nodes are oriented laterally in the second direction.

6. The semiconductor device according to claim 5, further comprising: plate lines, commonly coupled to the plate nodes of the capacitor, Wherein, the plate lines are oriented vertically in the first direction.

7. The semiconductor device according to claim 1, further comprising: A gate dielectric layer is between the active layer and the word line.

8. The semiconductor device according to claim 1, further comprising: a first impurity region between one side of the active layer and the bit line; as well as A second impurity region is between the other side of the active layer and the capacitor.

9. The semiconductor device according to claim 1, wherein: The substrate includes at least one peripheral circuit.

10. A method for manufacturing a semiconductor device, comprising: forming an etch stop layer on the substrate; forming a mold stack in which dielectric layers and semiconductor layers are alternately stacked on the etch stop layer; Forming a first groove by etching the mold stack; recessing one side of the semiconductor layer through the first trench to form a first recessed portion between the dielectric layers; forming a common impurity region in the first recessed portion; forming a bit line in the first recess, the bit line coupled to the common impurity region extending parallel to the bit line and oriented laterally; Etching the mold stack in a direction intersecting the bit line to form a second trench, wherein the second trench divides the mold stack into a plurality of line-type stacks; as well as A vertically-oriented word line is formed through the line stack.

11. The method according to claim 10, wherein: The semiconductor layer includes polycrystalline silicon.

12. The method according to claim 10, further comprising: After forming a vertically oriented word line passing through the line type stack, forming a third trench separated from the word line by etching the line type stack; recessing the other side of the semiconductor layer through the third trench to form a second recessed portion between the dielectric layers; forming a storage node inside the second recess; forming a capacitor dielectric layer on the storage node; as well as A plate node is formed on the capacitor dielectric layer.

13. The method according to claim 12, wherein: The storage node includes a cylindrical storage node.

14. The method according to claim 12, further comprising: Plate lines are formed that are commonly coupled to the plate nodes.

15. A method for manufacturing a semiconductor device, comprising: preparing a substrate including peripheral circuits; forming a die stack on the substrate in which dielectric layers and active layers are alternately stacked; forming laterally oriented common impurity regions, each of the common impurity regions being coupled to one side of a plurality of laterally arranged active layers; forming laterally oriented bit lines, each of the laterally oriented bit lines being coupled to each of the common impurity regions extending parallel to the bit lines; forming an isolation layer that divides the mold stack into a plurality of linear stacks; forming a vertically oriented word line through the active layer; as well as A laterally oriented capacitor is formed coupled to the other side of the active layer.

16. The method according to claim 15, wherein: Replacing one side of the active layer with a laterally oriented bit line comprises: forming a first trench by etching the mold stack; recessing one side of the active layer through the first trench to form a first recessed portion between the dielectric layers; and The first recess is filled with a conductive material to form a laterally oriented bit line.

17. The method according to claim 15, wherein: Forming an isolation layer to divide the mold stack into a plurality of linear stacks includes: forming a second trench extending in a direction intersecting the bit line by etching the mold stack; and The second trench is filled with a dielectric material.

18. The method according to claim 15, wherein: Forming a laterally oriented capacitor coupled to another side of the active layer comprises: forming a third trench by etching the mold stack; recessing the other side of the active layer through the third trench to form a second recessed portion between the dielectric layers; filling the second recess with a conductive material to form a cylindrical storage node; forming a capacitor dielectric layer on the cylindrical storage node; and A plate node is formed on the capacitor dielectric layer.

19. The method according to claim 15, wherein: Each active layer consists of: an active layer body through which the word line passes; and The protrusions extend from both sides of the active layer body, wherein the protrusions are formed to have a smaller width than that of the active layer body.

20. The method according to claim 15, wherein: Each active layer includes polycrystalline silicon.

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