Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system are provided. The semiconductor device includes: a first substrate; a device located on the first substrate; a second substrate located on the device; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; a channel structure penetrating the gate electrodes, extending in the first direction, and including a channel layer; an isolation region penetrating the gate electrodes and extending in a second direction; a through-contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrodes to the device; a barrier structure spaced apart from and surrounding the through-contact plug; and a support structure located on the gate electrodes and including a support pattern, wherein the support structure has a first through-region spaced apart from each other in the second direction on the isolation region and a second through-region contacting the upper surface of the barrier structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0133360, filed on October 15, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some exemplary embodiments of the present invention relate to semiconductor devices and data storage systems including such semiconductor devices. Background Technology

[0004] Semiconductor devices capable of storing high-capacity data have been used as data storage systems. Therefore, methods to increase the data storage capacity of semiconductor devices have been investigated. For example, as one method for increasing the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensionally arranged memory cells (rather than two-dimensionally arranged memory cells) have been proposed. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide semiconductor devices with improved reliability.

[0006] Optionally or additionally, some exemplary embodiments of the present invention provide a data storage system including semiconductor devices with improved reliability.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device includes: a peripheral circuit structure comprising a first substrate and at least one of an active device or a passive device located on the first substrate; a memory cell structure comprising a second substrate located on the peripheral circuit structure and having a first region and a second region, the memory cell structure including gate electrodes stacked spaced apart from each other in a first direction on the first region and extending in a second direction and arranged in a stepped shape on the second region, the memory cell structure including interlayer insulating layers stacked alternately with the gate electrodes, the memory cell structure including penetrations extending in the first direction. The storage cell structure includes a channel structure for the gate electrode, each channel structure comprising a channel layer, and an isolation region extending through the gate electrode in a second direction and spaced apart from each other in a third direction; a through-wiring region comprising a sacrificial insulating layer located on the second region, spaced apart from the gate electrode and alternately stacked with the interlayer insulating layer, the through-wiring region comprising a through-contact plug penetrating the sacrificial insulating layer and electrically connecting the gate electrode to at least one of the active device or the passive device; and a barrier structure surrounding the through-wiring region and comprising a core insulating layer, a first barrier layer, and a second barrier layer. The core insulating layer is located in the central region of the barrier structure and comprises silicon oxide, the second barrier layer covers the side surface and bottom surface of the core insulating layer, and the first barrier layer covers the outer surface and bottom surface of the second barrier layer.

[0008] According to some exemplary embodiments of the present invention, a semiconductor device includes: a first substrate; at least one of an active device or a passive device located on the first substrate; a second substrate located on the active device or the passive device; a gate electrode stacked on the second substrate in a first direction and spaced apart from each other; a channel structure penetrating the gate electrode, extending in the first direction, and all including a channel layer; an isolation region penetrating the gate electrode and extending in a second direction; a through contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrode to the active device or the passive device; a barrier structure spaced apart from and surrounding the through contact plug; and a support structure located on the gate electrode and including a support pattern. The support structure has a first through region spaced apart from each other in the second direction on the isolation region and a second through region contacting the upper surface of the barrier structure.

[0009] According to some exemplary embodiments of the present invention, a data storage system includes a semiconductor memory device comprising: a first substrate; at least one of an active device or a passive device located on the first substrate; a second substrate located on the at least one of the active device or the passive device; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; channel structures penetrating the gate electrodes, the channel structures extending in the first direction, and each of the channel structures including a channel layer; an isolation region penetrating the gate electrodes and extending in a second direction; a through contact plug penetrating the second substrate and extending in the first direction, while electrically connecting the gate electrodes to the at least one of the active device or the passive device; a barrier structure spaced apart from and surrounding the through contact plug; a support structure located on the gate electrodes and including a support pattern; and input and output pads electrically connected to the at least one of the active device or the passive device, wherein the support structure includes a first through region spaced apart from each other in the second direction on the isolation region and a second through region contacting the upper surface of the barrier structure. The data storage system further includes a controller circuit that is electrically connected to the semiconductor memory device via the input and output pads and is configured to control the semiconductor memory device. Attached Figure Description

[0010] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0011] Figure 1A and Figure 1B This is a top view illustrating some exemplary embodiments of a semiconductor device according to a concept of the present invention;

[0012] Figure 2A and Figure 2B This is a top view illustrating some exemplary embodiments of a semiconductor device according to a concept of the present invention;

[0013] Figures 3A to 3C This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention;

[0014] Figure 4 This is a cross-sectional view illustrating a portion of a semiconductor device according to some exemplary embodiments of the concept of the present invention;

[0015] Figures 5A to 6 This is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to some exemplary embodiments of the concept of the present invention;

[0016] Figure 7This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention;

[0017] Figures 8A to 19C These are top views and cross-sectional views illustrating methods for manufacturing semiconductor devices according to some exemplary embodiments of the present invention;

[0018] Figure 20 This is a view illustrating a data storage system including semiconductor devices, based on some exemplary embodiments of a concept according to the present invention;

[0019] Figure 21 This is a perspective view illustrating a data storage system including semiconductor devices, based on some exemplary embodiments of the concept according to the present invention; and

[0020] Figure 22 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention. Detailed Implementation

[0021] In the following description, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0022] Figure 1A and Figure 1B This is a top view showing a semiconductor device according to some example embodiments. Figure 1B Also included in Figure 1A The top view shows the support structure in the semiconductor device.

[0023] Figure 2A and Figure 2B This is a top view showing a semiconductor device according to some example embodiments. Figure 2A It is shown Figure 1B A magnified view of area "A" in the image. Figure 2B It is shown Figure 1B A magnified view of region "B" in the image.

[0024] Figures 3A to 3C This is a cross-sectional view of a semiconductor device according to some example embodiments. Figure 3A It is along Figure 1B A cross-sectional view taken from line I-I' in the diagram. Figure 3B It is along Figure 1B The cross-sectional view taken from line II-II' in the diagram, and Figure 3C It is along Figure 1B The cross-sectional view taken from line III-III' in the diagram.

[0025] Figure 4 This is a cross-sectional view showing a portion of a semiconductor device according to some example embodiments, to illustrate... Figure 3A The region "C" in the text.

[0026] refer to Figures 1A to 4 The semiconductor device 100 may include a peripheral circuit structure (PERI) and a memory cell structure (CELL). The PERI includes a first substrate 201, and the CELL includes a second substrate 101. The semiconductor device 100 may include a through-wiring region TR, which includes through-contact plugs 180 electrically connecting the PERI to the CELL. The CELL may be disposed above the PERI, and the through-wiring region TR may penetrate the CELL and connect (e.g., directly) the CELL to the PERI. In some example embodiments, the CELL may be disposed below the PERI. Furthermore, in some example embodiments, the CELL and PERI may be joined by, for example, a copper (Cu)-copper (Cu) bond. However, the example embodiments are not limited to this, and the CELL and PERI may be joined by other bonding methods.

[0027] The peripheral circuit structure PERI may include a first substrate 201, a source / drain region 205 and a device isolation layer 210 located in the first substrate 201, at least one of an active device or a passive device disposed in the first substrate 201 (e.g., a circuit device 220), a circuit contact plug 270, a circuit wiring line 280 and a peripheral region insulating layer 290.

[0028] The first substrate 201 may have an upper surface extending in both the X and Y directions. An active region may be defined on the first substrate 201 by a device isolation layer 210. A source / drain region 205 comprising at least one impurity such as boron, phosphorus, or arsenic may be disposed within a portion of the active region. The first substrate 201 may comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 201 may be configured as a bulk wafer or an epitaxial layer, such as a uniform epitaxial layer.

[0029] Circuit device 220 may be an active device and / or a passive device, or a device corresponding to an active device and / or a passive device, and may include transistors such as planar transistors. Circuit device 220 may include other active devices, such as diodes; however, the exemplary embodiments are not limited thereto. Circuit device 220 may include passive devices, such as at least one of resistors, capacitors, inductors, or memristors; however, the exemplary embodiments are not limited thereto. Circuit device 220 may include two-terminal devices and / or three-terminal devices, and / or devices with more than three terminals. Each or at least one of circuit devices 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed in a first substrate 201 on both sides of the circuit gate electrode 225.

[0030] A peripheral region insulating layer 290 may be disposed on the circuit device 220 on the first substrate 201. A circuit contact plug 270 may penetrate the peripheral region insulating layer 290 and may be connected to (e.g., directly connected and / or ohmically connected) the source / drain region 205. Electrical signals may be applied to the circuit device 220 through the circuit contact plug 270. In areas not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. Circuit wiring lines 280 may be connected to the circuit contact plug 270 and may be disposed in multiple layers.

[0031] The memory cell structure (CELL) may include a second substrate 101 having a first region R1 and a second region R2, a first horizontal conductive layer 102 on the first region R1 of the second substrate 101, a horizontal insulating layer 110 disposed side-by-side with the first horizontal conductive layer 102 on the second region R2 of the second substrate 101, a second horizontal conductive layer 104 located on the first horizontal conductive layer 102 and the horizontal insulating layer 110, a gate electrode 130 stacked on the second horizontal conductive layer 104, a first isolation region MS1 ​​and a second isolation region MS2a and MS2b extending through a stacked structure GS penetrating the gate electrode 130, a barrier structure 160 configured to surround a through wiring region TR in the second region R2, an upper isolation region SS penetrating a portion of the stacked structure GS, a channel structure CH configured to penetrate the stacked structure GS, and a support structure 170 disposed on the stacked structure GS of the gate electrode 130. The memory cell structure (CELL) may also include an interlayer insulating layer 120, a metal oxide layer 175, a cover insulating layer 190, and an upper insulating layer 195.

[0032] In the first region R1 of the second substrate 101, gate electrodes 130 can be stacked vertically, for example, in a direction perpendicular to the surface of the second substrate 101, and a channel structure CH / memory cell can be disposed in the first region R1. In the second region R2, the gate electrodes 130 can extend to different lengths, and the second region R2 can be configured to electrically connect the memory cell to the peripheral circuit structure PERI. The second region R2 can be disposed at at least one end of the first region R1 in at least one direction (e.g., in the X direction).

[0033] The second substrate 101 may have an upper surface extending in both the X and Y directions. The X and Y directions may be perpendicular to each other. The second substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate 101 may also include impurities. The second substrate 101 may be configured as a polycrystalline semiconductor layer (e.g., a polycrystalline silicon layer) and / or an epitaxial layer (e.g., a homoepitaxial layer and / or a heteroepitaxial layer).

[0034] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be stacked sequentially on the upper surface of the first region R1 of the second substrate 101. The first horizontal conductive layer 102 may not extend to the second region R2 of the second substrate 101, while the second horizontal conductive layer 104 may extend to the second region R2.

[0035] The first horizontal conductive layer 102 can be used as part of the common source line of the semiconductor device 100, and can be used together with the second substrate 101 as, for example, a common source line. Figure 3B As shown, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 around the channel layer 140.

[0036] The second horizontal conductive layer 104 may contact the second substrate 101 in a portion of the area where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The second horizontal conductive layer 104 may be bent to cover the ends of the first horizontal conductive layer 102 and / or the horizontal insulating layer 110, and may extend onto the second substrate 101 in the aforementioned area.

[0037] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise a semiconductor material, and the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise polysilicon, such as doped polysilicon. In this case, at least the first horizontal conductive layer 102 may be configured as a doped layer, and the second horizontal conductive layer 104 may be configured as a doped layer and / or may comprise impurities diffused from the first horizontal conductive layer 102. In some example embodiments, the second horizontal conductive layer 104 may be replaced with an insulating layer such as an insulating layer comprising at least one of silicon oxide or silicon nitride.

[0038] The horizontal insulating layer 110 may be disposed on the second substrate 101 side-by-side / adjacent to the first horizontal conductive layer 102 in at least a portion of the second region R2. For example... Figure 4 As shown, the horizontal insulating layer 110 may include first to third horizontal insulating layers 111, 112, and 113 sequentially stacked on the second region R2 of the second substrate 101. In the process of manufacturing the semiconductor device 100, the horizontal insulating layer 110 may be retained after a portion of the horizontal insulating layer 110 is replaced with the first horizontal conductive layer 102.

[0039] The horizontal insulating layer 110 may include at least one of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may include different insulating materials from the second horizontal insulating layer 112; for example, they may be composed of different insulating materials. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may include the same material; for example, they may be composed of the same material. For example, the first horizontal insulating layer 111 and the third horizontal insulating layer 113 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the sacrificial insulating layer 118.

[0040] Gate electrodes 130 may be stacked on the second substrate 101 in the Z direction and spaced apart from each other, forming a stacked structure GS. Gate electrodes 130 may include a lower gate electrode 130L forming / corresponding to the gate of a ground select transistor, a memory gate electrode 130M forming / corresponding to a plurality of memory cells, and an upper gate electrode 130U forming / corresponding to the gate of a string select transistor. The number of memory gate electrodes 130M forming memory cells can be determined according to the capacity of the semiconductor device 100. In some example embodiments, the number of upper gate electrodes 130U and lower gate electrodes 130L may be one to four or more, and they may have the same or different structures as the memory gate electrodes 130M. The number of upper gate electrodes 130U may be the same or different from the number of lower gate electrodes 130L. In some example embodiments, gate electrodes 130 may also include gate electrodes 130 disposed above the upper gate electrode 130U and / or below the lower gate electrode 130L and formed in an erase transistor used in an erase operation utilizing the gate-induced drain leakage (GIDL) phenomenon. In addition, a portion of the gate electrode 130 (e.g., the storage gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) may be a dummy gate electrode, such as a dummy structure that is not electrically activated during the operation of the semiconductor device 100.

[0041] The gate electrodes 130 can be stacked vertically, spaced apart from each other on the first region R1, and extended from the first region R1 to the second region R2 at different lengths to form a stepped structure with a stepped shape / staircase shape. For example... Figure 3C As shown, gate electrodes 130 may form a stepped structure between gate electrodes 130 in the X direction. In some example embodiments, at least a portion of the gate electrodes 130 (e.g., two to six gate electrodes 130) may form a single gate group, and a stepped structure may be formed between the gate groups in the X direction. In this case, the gate electrodes 130 forming the single gate group may be configured to have a stepped structure in the Y direction. By including the stepped structure, the gate electrodes 130 can form a stepped shape, wherein the lower gate electrode 130 extends further than the upper gate electrode 130, and may provide an end exposed upward from the interlayer insulating layer 120. In some example embodiments, the gate electrodes 130 may have an increased thickness at the end.

[0042] like Figure 3A As shown, the gate electrodes 130 can be isolated from each other in the Y direction by first isolation regions MS1 extending in the X direction. The gate electrodes 130 between pairs of first isolation regions MS1 can form a single memory block, but some example embodiments of the memory block are not limited thereto. A portion of the gate electrodes 130 (e.g., memory gate electrode 130M) can form a single layer within a single memory block.

[0043] The gate electrode 130 may include a metallic material, such as tungsten (W). In some example embodiments, the gate electrode 130 may include doped or undoped polycrystalline silicon and / or metal silicide materials. In some example embodiments, the gate electrode 130 may also include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0044] Interlayer insulating layers 120 may be stacked alternately with gate electrodes 130 on the second substrate 101. Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may be configured to be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate 101 (e.g., the Z direction) and extend in the X direction. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide and / or silicon nitride.

[0045] The first isolation region MS1 ​​and the second isolation regions MS2a and MS2b can penetrate the gate electrode 130 and can extend in the X direction. The first isolation regions MS1 and the second isolation regions MS2a and MS2b can be arranged parallel to each other. The first isolation regions MS1 and the second isolation regions MS2a and MS2b can penetrate all the gate electrodes 130 stacked on the second substrate 101 and can be connected to the second substrate 101. The first isolation region MS1 ​​can extend in the X direction as a single region, and the second isolation region MS2 can extend intermittently between pairs of first isolation regions MS1, or can be disposed only in a portion of the region. For example, the second central isolation region MS2a can extend as a single region in the first region R1 and can extend intermittently in the X direction in the second region R2. The second auxiliary isolation region MS2b can be disposed only in the second region R2 and can extend intermittently in the X direction. In some example embodiments, the arrangement order and number of the first isolation regions MS1 and the second isolation regions MS2a and MS2b are not limited to... Figure 1A The example shown. The first isolation region MS1 ​​and the second isolation regions MS2a and MS2b may not overlap with the through cabling region TR, and may be spaced apart from the through cabling region TR.

[0046] like Figures 3A to 3CAs shown, an isolation insulating layer 105 may be disposed in the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. In some example embodiments, the isolation insulating layer 105 may be connected to the upper insulating layer 190 at its upper end. Due to the high aspect ratio, the isolation insulating layer 105 may have a shape in which the width decreases toward the second substrate 101, for example, it may have a tapered shape, but the example embodiments are not limited thereto, and the isolation insulating layer 105 may have a side surface perpendicular to the upper surface of the second substrate 101. In some example embodiments, a conductive layer may be further disposed in the isolation insulating layer 105 in the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. In this case, the conductive layer may be used as a common source line of the semiconductor device 100 or a contact plug connected to the common source line.

[0047] like Figure 1A As shown, the upper isolation region SS can extend in the X direction on the first region R1 between the first isolation region MS1 ​​and the second central isolation region MS2a, and between the second central isolation region MS2a. The upper isolation region SS can be configured to penetrate a portion of the gate electrode 130, including the uppermost upper gate electrode 130U of the gate electrode 130. Figure 2B As shown, the upper isolation region SS can isolate the four gate electrodes 130, including the upper gate electrode 130U, from each other in the Y direction. In some example embodiments, the number of gate electrodes 130 isolated by the upper isolation region SS can vary. The upper gate electrodes 130U isolated by the upper isolation region SS can form different string select lines. The upper isolation region SS can include an insulating material. For example, the insulating material can include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0048] like Figure 2B As shown, the channel structure CH can form a single string of memory cells, which can be spaced apart from each other, while forming rows and columns on the first region R1. The channel structure CH can be configured to form a grid pattern, such as a rectangular or square grid pattern, or it can be configured as a zigzag pattern in one direction to form another pattern, such as a hexagonal pattern. The channel structure CH can have a columnar shape, and / or can have a tapered shape, such as a shape with sloping side surfaces, the width of which decreases toward the second substrate 101 according to the aspect ratio.

[0049] like Figure 3BAs shown, a channel layer 140 may be disposed in a channel structure CH. In the channel structure CH, the channel layer 140 may be formed in an annular shape surrounding a core region 150 disposed therein, and optionally, in some example embodiments, without the core region 150, the channel layer 140 may have a columnar shape, such as a cylinder or prism. The core region 150 may include an insulating material, such as silicon oxide. The channel layer 140 may be connected at its lower portion to a first horizontal conductive layer 102. The channel layer 140 may include a semiconductor material, such as doped or undoped polycrystalline silicon and / or doped or undoped monocrystalline silicon.

[0050] The channel pad 155 may be disposed above the channel layer 140 in the channel structure CH. The channel pad 155 may be configured to cover the upper surface of the core region 150 and be electrically connected to the channel layer 140. The channel pad 155 may comprise, for example, doped polysilicon.

[0051] The gate dielectric layer 145 can be disposed between the gate electrode 130 and the channel layer 140. For example... Figure 3B As shown, the gate dielectric layer 145 may include a tunneling layer 143, a charge storage layer 142, and a barrier layer 141 sequentially stacked from the channel layer 140. The tunneling layer 143 may be configured to allow charge to tunnel to the charge storage layer 142 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer 142 may be configured as a charge trapping layer or a floating gate conductive layer. The barrier layer 141 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In some example embodiments, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130.

[0052] The dummy channel structure (DCH) can have the same or similar structure as the channel structure (CH) and can be spaced apart from each other, forming rows and columns in a portion of the first region R1 and the second region R2. Unlike the channel structure (CH), the dummy channel structure (DCH) may not be electrically connected to the wiring structure disposed on top, and / or may not form a string of memory cells in the semiconductor device 100. The dummy channel structure (DCH) can improve process margins (e.g., photolithography process margins) during the manufacture of the semiconductor device 100. In the first region R1, the dummy channel structure (DCH) can be disposed in a region adjacent to the second region R2.

[0053] like Figure 4As shown, the dummy channel structure DCH in the second region R2 can be configured to penetrate the horizontal insulating layer 110 in the Z direction. The lower part of the dummy channel structure DCH can be surrounded by the second horizontal conductive layer 104 and the horizontal insulating layer 110, and the dummy channel structure DCH can be spaced apart from the first horizontal conductive layer 102. Specifically, the dummy channel structure DCH can penetrate the interlayer insulating layer 120 and the gate electrode 130, and can penetrate the second horizontal conductive layer 104 and the horizontal insulating layer 110 at its lower end. In some example embodiments, the dummy channel structure DCH can be configured to penetrate the interlayer insulating layer 120 and the sacrificial insulating layer 118, and penetrate the second horizontal conductive layer 104 and the horizontal insulating layer 110 at its lower end in the through wiring region TR.

[0054] like Figure 4 As shown, the dummy channel structure DCH in the second region R2 may include a barrier layer 141, a charge storage layer 142, and first to third dielectric layers 141d, 142d, and 143d corresponding to the tunneling layer 143 of the gate dielectric layer 145 of the channel structure CH. The first to third dielectric layers 141d, 142d, and 143d may be stacked sequentially starting from the inner wall of the hole of the dummy channel structure DCH. The dummy channel structure DCH may include a dummy channel layer 140d, a dummy core region 150d, and a dummy channel pad 155d, which may correspond to the channel layer 140, core region 150, and channel pad 155 of the channel structure CH, respectively, and may be formed simultaneously with the channel layer 140, core region 150, and channel pad 155 of the channel structure CH. Each of the first to third dielectric layers 141d, 142d, and 143d may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the dummy channel layer 140d may comprise a semiconductor, such as doped or undoped polysilicon or doped or undoped monocrystalline silicon. The dummy core region 150d may comprise silicon oxide.

[0055] In the channel structure CH, the gate dielectric layer 145 can be partially penetrated by the first horizontal conductive layer 102 and can be divided into an upper gate dielectric layer and a lower gate dielectric layer. The first to third dielectric layers 141d, 142d and 143d of the structure DCH can have a continuous structure.

[0056] The through-wiring region TR can be configured to include a wiring structure for electrically connecting the memory cell structure CELL to the peripheral circuit structure PERI. The through-wiring region TR can be configured to penetrate the second region R2. The through-wiring region TR may include a through contact plug 180 penetrating the second substrate 101 and extending in the Z direction, and an insulating region IR surrounding the through contact plug 180. In some example embodiments, the region within the blocking structure 160 may be referred to as the through-wiring region TR. For example, a single through-wiring region TR may be provided in each memory block and may be further provided in the first region R1. In some example embodiments, at least one of the number, size, arrangement, and shape of the through-wiring regions TR may vary. For example, in some example embodiments, a single through-wiring region TR may be provided for multiple memory blocks.

[0057] like Figure 1A and Figure 1B As shown, the through-wiring region TR can be configured to be spaced apart from the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. For example, the through-wiring region TR can be spaced apart from the first isolation regions MS1 that are adjacent to each other in the Y direction, and can be positioned between pairs of first isolation regions MS1. With this arrangement, the sacrificial insulation layer 118 can be retained in the through-wiring region TR. When viewed in a top view, the through-wiring region TR can have a rectangular shape, such as a square shape; however, the example embodiment is not limited to this.

[0058] The insulating region IR can penetrate the memory cell structure and can be disposed parallel to the second substrate 101 and the gate electrode 130. The insulating region IR may include an insulating stack structure formed of insulating material, wherein the gate electrode 130 is not disposed therein or the gate electrode 130 does not extend therein. The insulating region IR may include a substrate insulating layer 109 as a first insulating layer disposed at the same horizontal height as the second substrate 101 and disposed side by side with the second substrate 101, an interlayer insulating layer 120 as a second insulating layer alternately stacked on the upper surface of the second substrate 101, and a sacrificial insulating layer 118 as a third insulating layer.

[0059] A substrate insulating layer 109 (e.g., a first insulating layer) may be disposed in the region where a portion of the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 is removed, and may be surrounded by the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The lower surface of the substrate insulating layer 109 may be substantially coplanar with the lower surface of the second substrate 101, or may be disposed at a horizontal height lower than the horizontal height of the lower surface of the second substrate 101. In some example embodiments, the substrate insulating layer 109 may include multiple insulating layers. Since the second insulating layer is formed by extending the interlayer insulating layer 120, the second insulating layer may be disposed at a horizontal height substantially the same as the horizontal height of the interlayer insulating layer 120. A third insulating layer may include a sacrificial insulating layer 118 and may be disposed at a horizontal height substantially the same as the horizontal height of the gate electrode 130, but some example embodiments are not limited thereto.

[0060] The substrate insulating layer 109, interlayer insulating layer 120, and sacrificial insulating layer 118 forming the insulating region IR can be formed of or may include an insulating material. For example, each of the substrate insulating layer 109, interlayer insulating layer 120, and sacrificial insulating layer 118 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. In some example embodiments, the substrate insulating layer 109 and sacrificial insulating layer 118 may have different widths or may have the same width.

[0061] The through-contact plug 180 can vertically penetrate the entire insulating region IR and extend perpendicularly to the upper surface of the second substrate 101, electrically connecting the memory cell structure CELL to the circuit device 220 of the peripheral circuit structure PERI. For example, the through-contact plug 180 can electrically connect the gate electrode 130 and / or channel structure CH of the memory cell structure CELL to the circuit device 220 of the peripheral circuit structure PERI. The through-contact plug 180 can be connected to the upper wiring line 188. The through-contact plug 180 can be connected to the lower wiring line 280, such as the lower wiring structure.

[0062] The through-contact plug 180 can penetrate the interlayer insulation layer 120 and the sacrificial insulation layer 118 of the insulating region IR, and can penetrate the substrate insulation layer 109 at the bottom. In some example embodiments, the number, form, and shape of the through-contact plugs 180 in a single through-wiring region TR can vary. According to some example embodiments, the through-contact plug 180 can have a multilayer connection. In addition, besides the through-contact plug 180, in some example embodiments, the wiring structure can also be provided in the insulating region IR in the form of wiring lines. The through-contact plug 180 can include a conductive material, and can include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0063] The barrier structure 160 can be configured to surround the through-wiring region TR in the second region R2. In a top view, the barrier structure 160 may include a horizontal region aligned on the same straight line and a vertical region extending in the Y direction, wherein a first isolation region MS1 ​​and second isolation regions MS2a and MS2b extending in the X direction are aligned on the same straight line. In some example embodiments, the horizontal and vertical regions may form a single closed curve, and in a top view, the barrier structure 160 may be configured as a slit having a quadrilateral ring or a shape similar to a quadrilateral ring (e.g., a square ring or a chamfered / beveled ring). The barrier structure 160 can prevent or reduce the likelihood of material forming the gate electrode 130 during the fabrication of the semiconductor device flowing into the through-wiring region TR.

[0064] like Figure 2A , Figure 2B and Figure 4 As shown, the barrier structure 160 can be disposed on the boundary between the gate electrode 130 and the sacrificial insulating layer 118. The outer surface S1 of the barrier structure 160 can face the gate electrode 130, and the inner surface S2 of the barrier structure 160 can face the sacrificial insulating layer 118. In some example embodiments, the terms "outer surface" and "inner surface" used in connection with the barrier structure 160 can refer to the side surface pointing towards the outer region of the barrier structure 160 and the side surface pointing towards the inner region surrounded by the barrier structure 160, respectively. The barrier structure 160 can be disposed at a horizontal height substantially the same as the horizontal height of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. The barrier structure 160 can be configured as described above because, for example, the barrier structure 160 can be formed in a trench formed in the same process as that used to form the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. Furthermore, similar to the arrangement of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b in the second region R2, the barrier structure 160 can be disposed in the region where the second horizontal conductive layer 104 contacts / directly contacts the second substrate 101. Therefore, the barrier structure 160 can penetrate the second horizontal conductive layer 104, and can contact / directly contact the second horizontal conductive layer 104 at its lower end, while being spaced apart from the first horizontal conductive layer 102 and the horizontal insulating layer 110. The upper surface of the barrier structure 160 can be disposed at a horizontal height higher than the upper surface of the dummy channel structure DCH.

[0065] like Figure 4As shown, the barrier structure 160 may include a first barrier layer 161, a second barrier layer 162, and a core insulating layer 165 stacked sequentially from the inner surface and bottom surface of the slit. The first barrier layer 161 and the second barrier layer 162 may include different materials, for example, be composed of different materials, and the core insulating layer 165 may include a material different from the material of the second barrier layer 162. The core insulating layer 165 may include, for example, the same material as the first barrier layer 161, or may be composed of the same material as the first barrier layer 161. For example, each of the first barrier layer 161, the second barrier layer 162, and the core insulating layer 165 may include one of silicon oxide, silicon nitride, and silicon oxynitride (e.g., only one). For example, the first barrier layer 161 may include silicon oxide and may not include silicon nitride, the second barrier layer 162 may include silicon nitride and may not include silicon oxide, and the core insulating layer 165 may include silicon oxide and may not include silicon nitride. The barrier structure 160 may not include polysilicon.

[0066] The first barrier layer 161 may cover the bottom and side surfaces of the slit and may extend in the Z direction. The first barrier layer 161 may cover the outer and bottom surfaces of the second barrier layer 162. The first barrier layer 161 may be adjacent to the gate electrode 130 on the outer surface S1 of the barrier structure 160 and may be adjacent to the sacrificial insulating layer 118 on the inner surface S2 of the barrier structure 160. The lower end of the first barrier layer 161 may be configured to contact the upper surface of the second substrate 101 or be partially recessed into the second substrate 101.

[0067] For example, a second barrier layer 162 may be disposed on the first barrier layer 161, and may be disposed on the opposing inner surface of the first barrier layer 161. The second barrier layer 162 may be disposed between the first barrier layer 161 and the core insulating layer 165. The second barrier layer 162 may cover the side and bottom surfaces of the core insulating layer 165. The second barrier layer 162 may cover the portion of the bottom surface of the slit where the first barrier layer 161 covers, and may extend along the inner surface of the first barrier layer 161 in the Z direction. The second barrier layer 162 may contact / directly contact the inner surface of the first barrier layer 161. The inner surface of the second barrier layer 162 may contact / directly contact the core insulating layer 165.

[0068] The lower and side surfaces of the core insulating layer 165 may be surrounded by the second barrier layer 162. The core insulating layer 165 may have a horizontal thickness t3 greater than the horizontal thickness t1 of the first barrier layer 161 and the horizontal thickness t2 of the second barrier layer 162. The core insulating layer 165 may be configured to have a quadrilateral ring in a plane (e.g., in a top view), such as a square ring or a shape similar to a quadrilateral ring. The core insulating layer 165 may be disposed in a central region between the opposing inner surfaces of the second barrier layer 162 of the barrier structure 160. The central region may be, for example, a region within the barrier structure 160 including a central axis located between the outer surface S1 and the inner surface S2. The core insulating layer 165 may fill the opening OP2 ( Figure 11B The second barrier layer 162 in the middle has an internal space, and the barrier structure 160 is disposed in the opening OP2. According to some example embodiments, a seam may be formed in the core insulation layer 165.

[0069] The horizontal thickness of each of the first barrier layer 161 and the second barrier layer 162 of the barrier structure 160 may be greater than the horizontal thickness of the first to third dielectric layers 141d, 142d, and 143d of the dummy channel structure DCH. The horizontal thickness of the core insulating layer 165 of the barrier structure 160 may be greater than the horizontal thickness of the dummy core region 150d of the dummy channel structure DCH.

[0070] Since the core insulating layer 165 is not formed of a semiconductor material, but of an insulating material such as silicon oxide, defects such as cracks in the barrier structure 160 or its structure (e.g., the support structure 170) can be prevented or reduced (which can be caused by the semiconductor material shrinking or expanding due to heat).

[0071] The support structure 170 can be disposed on the stacked structure GS of the gate electrode 130. The support structure 170 can cover the insulating layer 190. The support structure 170 can be disposed above the channel structure CH, the dummy channel structure DCH, the first isolation region MS1, the second isolation regions MS2a and MS2b, and the blocking structure 160.

[0072] like Figures 1B to 2BAs shown, the support structure 170 may include a support pattern 170P disposed at a position overlapping with the gate electrode 130, first through regions OS1a and OS1b disposed at a position overlapping with the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b, and a second through region OS2 disposed at a position overlapping with the blocking structure 160. The first through regions OS1a and OS1b and the second through region OS2 may penetrate the support pattern 170P in the Z direction. The first width W1 of the first through regions OS1a and OS1b may be greater than the second width W2 of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. The first width Wa1 of the second through region OS2 may be greater than the second width Wa2 of the blocking structure 160. In some example embodiments, the first widths W1 and Wa1 may be substantially the same as, or smaller than, the second widths W2 and Wa2.

[0073] like Figures 1B to 2B As shown, the support structure 170 may further include bridge patterns 170B spaced apart from each other in the X direction. The bridge patterns 170B may be disposed in regions where the first through regions OS1a and OS1b and the second through region OS2 are not provided, and may connect the support patterns 170P to each other. In the semiconductor device 100, since the support structure 170 may include the support patterns 170P and the bridge patterns 170B, the possibility of tilting of the stacked structure GS formed by the gate electrode 130 can be prevented or reduced.

[0074] The first through regions OS1a and OS1b, located in the first region R1, can be discontinuously arranged and spaced apart from each other in the X direction. The first through regions OS1a and OS1b, located in the first region R1, can be arranged in a Z-shape in the Y direction. The portions of the first through regions OS1a and OS1b located on the first isolation region MS1 ​​in the second region R2 can extend continuously in the X direction. Another portion of the first through regions OS1a and OS1b located on the second isolation regions MS2a and MS2b in the second region R2 can be spaced apart from each other in the X direction. The spaced-apart portion of the first through region OS1b in the X direction can overlap with the spaced-apart portion of the second central isolation region MS2a and the spaced-apart portion of the second auxiliary isolation region MS2b in the X direction of the second region R2 in the Z direction.

[0075] The first through regions OS1a and OS1b can provide an inflow path for etchant (e.g., a wet etchant such as buffered hydrogen fluoride) to pass through the first opening OP1 (in Figure 13C (in the middle) replace the sacrificial insulation layer 118 with Figure 4The gate electrode 130 in the structure. According to some exemplary embodiments, the arrangement of the first through regions OS1a and OS1b can be changed, and therefore, the arrangement of the bridge pattern 170B of the support structure 170 can also be changed.

[0076] The second through region OS2, disposed in the second region R2, can contact the upper surface of the blocking structure 160. The second through region OS2 can have a shape corresponding to the planar shape of the blocking structure 160. For example, in a top view, the second through region OS2 may include a horizontal region extending in the X direction and a vertical region extending in the Y direction. In some example embodiments, the horizontal and vertical regions of the second through region OS2 may form a single closed curve. Therefore, the support structure 170 may include a support pattern 170PH surrounded by the second through region OS2, such as... Figure 2A As shown. The second through regions OS2 can be adjacent to each other in the Y direction, can be spaced apart from the first through regions OS1a disposed on the first isolation region MS1, and can be disposed between pairs of first through regions OS1a. In the top view, the second through region OS2 can have a quadrilateral ring or a similar shape.

[0077] In the barrier structure 160, the materials of the stacked structures in contact with the outer and inner surfaces are different, which may cause different stresses, such as thermal stress, on the outer and inner surfaces, and the structure surrounding the barrier structure 160 (e.g., the support structure 170) may have a physically weaker structure. Since the conductive material forming the gate electrode 130, such as tungsten (W), has the property of thermal shrinkage, stepped portions of the stacked structure can be formed on the outer and inner regions of the barrier structure 160. In this case, when the support structure 170 does not have a second through region OS2, defects such as cracks may occur in the support structure 170. However, since the support structure 170 has a second through region OS2 on the barrier structure 160, the support patterns 170P and 170PH of the support structure 170 can be isolated from each other on the outer and inner regions of the barrier structure 160. Therefore, the physical fragility of the support structure 170 caused by the stepped portions of the stacked structure formed on the outer and inner regions of the barrier structure 160 can be improved / resolved. By providing improved or resolved physical vulnerabilities to the support structure 170, the stacked structure GS of the gate electrode 130 can be formed more stably, thereby providing a semiconductor device with improved reliability and electrical properties.

[0078] refer to Figure 12BThe support structure 170 may have a second through region OS2 on the barrier structure 160 because the core insulation layer 165 of the barrier structure 160 may include a material different from the material of the sacrificial core layer 165PS in the first opening OP1, or be composed of a material different from the material of the sacrificial core layer 165PS in the first opening OP1.

[0079] A first metal oxide layer 175A may be disposed on the side surface of the support pattern 170P exposed to the first through region OS1a. The first metal oxide layer 175A may extend in the Z direction along the side surfaces of the isolation regions MS1, MS2a, and MS2b and along the side surface of the first through region OS1a. The first metal oxide layer 175A may cover the sidewalls of the interlayer insulating layer 120 exposed to the isolation regions MS1a, MS2a, and MS2b, may extend horizontally between the interlayer insulating layers 120, and may surround at least a portion of the conductive layer forming the gate electrode 130. The first metal oxide layer 175A may include, for example, a metal oxide, such as aluminum oxide.

[0080] An insulating layer 105 may be disposed in the isolation regions MS1, MS2a, and MS2b and the first through region OS1. The insulating layer 105 may include multiple insulating layers, and may include, for example, a first insulating layer 105A and a second insulating layer 105B located on the first insulating layer 105A. The side and lower surfaces of the second insulating layer 105B may be surrounded by the first insulating layer 105A. The first insulating layer 105A of the insulating layer 105 may cover at least a portion of the first metal oxide layer 175A. The second insulating layer 105B of the insulating layer 105 may be connected to the upper insulating layer 195. The first insulating layer 105A may include a recessed portion recessed inward toward the gate electrode 130.

[0081] A second metal oxide layer 175B may be disposed on the side surface of the support pattern 170P exposed to the second through region OS2. The second metal oxide layer 175B may be configured to extend in the Z direction along the side surface of the support pattern 170P exposed to the second through region OS2 and cover the upper surface of the barrier structure 160. A through insulating layer 178 may be disposed in the second through region OS2. The through insulating layer 178 may include multiple insulating layers, and may include, for example, a first insulating layer 178A and a second insulating layer 178B located on the first insulating layer 178A. The side and lower surfaces of the second insulating layer 178B may be surrounded by the first insulating layer 178A. The first insulating layer 178A of the through insulating layer 178 may cover the second metal oxide layer 175B. The second insulating layer 178B of the through insulating layer 178 may be connected to the upper insulating layer 195.

[0082] The boundaries between the first through-region OS1 and the second through-region OS2 and the isolation regions MS1, MS2a, and MS2b can be clearly defined by a first metal oxide layer 175A and a second metal oxide layer 175B disposed on the sidewalls therein. The covering insulating layer 190, which contacts the first through-region OS1 and the second through-region OS2 and the support pattern 170P of the support structure 170, may include an insulating material, such as silicon oxide and / or silicon nitride, and one of the first metal oxide layer 175A and the second metal oxide layer 175B may include a material different from the other of the first metal oxide layer 175A and the second metal oxide layer 175B. For example, it may be composed of a material different from the other of the first metal oxide layer 175A and the second metal oxide layer 175B, such that the boundary between them can be distinct. In some example embodiments, the shape of the second metal oxide layer 175B may vary. For example, due to process factors, the second metal oxide layer 175B may have a shape corresponding to the contour of the upper surface of the barrier structure 160. The boundary between the first insulating layer 105A and the second insulating layer 105B of the insulating layer 105 and the boundary between the first insulating layer 178A and the second insulating layer 178B of the insulating layer 178 can be distinct or indistinct.

[0083] like Figure 3C As shown, the gate contact plug 185 can be connected to the gate electrode 130, the upper surface of which is exposed upward in the second region R2.

[0084] Wiring lines 188 can form an upper wiring structure electrically connected to memory cells in a memory cell structure CELL. For example, wiring lines 188 can be electrically connected to through contact plugs 180, gate electrodes 130, and channel structures CH. In some example embodiments, the number of contact plugs and wiring lines forming the wiring structure can vary. Wiring lines 188 can include metal and can include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0085] The covering insulating layer 190 can be configured to cover the second substrate 101, the gate electrode 130 located on the second substrate 101, and the peripheral region insulating layer 290. The covering insulating layer 190 can be formed of an insulating material and can be formed of multiple insulating layers.

[0086] The upper insulating layer 195 can be configured to cover the support structure 170. The upper insulating layer 195 can be formed of an insulating material and can be formed of multiple insulating layers.

[0087] Figures 5A to 5D This is an enlarged cross-sectional view showing a portion of a semiconductor device according to some example embodiments, to illustrate the corresponding... Figure 3AThe region "C" in the text.

[0088] refer to Figure 5A In the semiconductor device 100a, the layer disposed in the barrier structure 160a may be partially different from... Figure 4 Example embodiments are provided. The barrier structure 160a may include a core insulating layer 165 disposed in a central region and first to third barrier layers 161a, 162a, and 163a stacked sequentially from the bottom surface and side surface of the barrier structure 160a. The first barrier layer 161a and the second barrier layer 162a may include silicon oxide and may not include silicon nitride, and the third barrier layer 163a may include silicon nitride and may not include silicon oxide. In some example embodiments, the configuration, number, and / or stacking order of the barrier layers disposed in the barrier structure 160a may vary. For example, the first barrier layer 161a may include silicon oxide and may not include silicon nitride, and the second barrier layer 162a and the third barrier layer 163a may include silicon nitride and may not include silicon oxide.

[0089] refer to Figure 5B In the semiconductor device 100b, the second barrier layer 162b and the core insulating layer 165S disposed in the barrier structure 160b may be partially different from the example embodiment in FIG3.

[0090] The second barrier layer 162b may include protrusions PA projecting toward the core insulating layer 165S. The protrusions PA may be disposed on the upper region of the barrier structure 160b and at a horizontal height higher than the horizontal height of the gate electrode 130. The protrusions PA may be disposed in pairs on both sides of the upper portion of the core insulating layer 165S located on the cut surface of the semiconductor device 100b, and the pairs of protrusions PA may be opposite each other. The protrusions PA may have a triangular or similar shape. In some example embodiments, the corners of the protrusions PA may have a rounded shape due to process factors. In some example embodiments, it is understood that the second barrier layer 162b may have a first horizontal thickness ta1 at the lower portion and a second horizontal thickness ta2 at the upper portion that is greater than the first horizontal thickness ta1.

[0091] A seam SP can be formed in the core insulation layer 165S. The seam SP can refer to the empty space / void / air gap surrounded by the insulating material layer forming the core insulation layer 165S. Since the second barrier layer 162b includes a protrusion PA, the seam SP formed in the core insulation layer 165S can be formed at a horizontal height lower than the horizontal height of the protrusion PA. The seam SP can be configured to extend in the Z direction. The seam SP in the core insulation layer 165S can be formed by more than just the protrusion PA. For example, the seam SP can be formed in the core insulation layer 165S even without the protrusion PA, and the seam SP can be not formed in the core insulation layer 165S even with the protrusion PA.

[0092] refer to Figure 5C In the semiconductor device 100c, the second barrier layer 162c disposed in the barrier structure 160c can be partially different from... Figure 5B The example embodiment is shown below. The second barrier layer 162c may include protrusions PA, and the protrusions PA may have a semi-circular or similar shape. The protrusions PA may be disposed in pairs on both sides of the upper core insulating layer 165S located in the cut surface of the semiconductor device 100c, and the pair of protrusions PA may be opposite each other. A seam SP may be formed in the core insulating layer 165S. In some example embodiments, the shape of the protrusions PA may vary.

[0093] refer to Figure 5D In the semiconductor device 100d, the layer disposed in the barrier structure 160d can be partially different from... Figure 4 Example embodiments are shown. The barrier structure 160d may include a core insulation layer 165S disposed in a central region and having a seam SP, and a first barrier layer 161 in contact with the core insulation layer 165S. The barrier structure 160d may also include components for contact with... Figure 5B In the example embodiment, the protrusion PA has the same shape as the second barrier layer 162P disposed between the upper region of the first barrier layer 161 and the upper region of the core insulating layer 165S. The second barrier layer 161P can contact the first barrier layer 161 and can be spaced apart from each other in pairs on both sides of the core insulating layer 165S. The example embodiment may correspond to a structure in which the portion of the second barrier layer 162b other than the protrusion PA is omitted. In this case, the first barrier layer 161 and the core insulating layer 165S can be in direct contact with each other.

[0094] refer to Figure 4 and Figures 5A to 5C The described example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include Figure 4 and Figures 5A to 5C Some features of one of the attached figures, and may include Figure 4 and Figures 5A to 5CSome features of the other figures in the diagram.

[0095] Figure 6 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to some example embodiments, to illustrate the corresponding... Figure 3C The region "D" in the text.

[0096] refer to Figure 6 In the semiconductor device 100e, there may be a step difference between the stacked structure disposed inside the barrier structure 160 and the stacked structure disposed outside the barrier structure 160. The gate electrode 130 facing the outer surface S1 of the barrier structure 160 and the sacrificial insulating layer 118 facing the inner surface S2 of the barrier structure 160 may be disposed at different horizontal heights. For example, the uppermost gate electrode 130 facing the outer surface S1 of the barrier structure 160 and the uppermost sacrificial insulating layer 118 contacting the inner surface S2 of the barrier structure 160 may be disposed at different horizontal heights.

[0097] The vertical thickness of the gate electrode 130 facing the outer surface S1 of the barrier structure 160 can be less than the vertical thickness of the sacrificial insulating layer 118 that contacts the inner surface S2. Alternatively, the vertical distance between adjacent interlayer insulating layers 120 on the outer surface S1 of the barrier structure 160 can be less than the vertical distance between adjacent interlayer insulating layers 120 on the inner surface S2.

[0098] In some example embodiments, the conductive material (e.g., tungsten (W)) forming the gate electrode 130 can be contracted in the vertical direction, such that the stacked structure of the insulating region IR disposed inside the barrier structure 160 and the stacked structure GS disposed outside the barrier structure 160 can have different heights relative to the barrier structure 160.

[0099] Figure 7 This is a cross-sectional view of a semiconductor device according to some example embodiments.

[0100] refer to Figure 7 In semiconductor device 100f, the stacked structure of gate electrode 130 can be formed by a vertically stacked lower stacked structure and an upper stacked structure, and the channel structure CHf can include a vertically stacked first channel structure CH1 and a second channel structure CH2. A dummy channel structure DCH (see...) Figure 2A It can also be configured in the same shape as the channel structure CHf. When the number of stacked gate electrodes 130 is relatively large, the channel structure CHf can be configured as above to form the channel structure CHf more stably / more stably.

[0101] In the channel structure CHf, the lower first channel structure CH1 can be connected to the upper second channel structure CH2, and the channel structure CHf can have a curved portion formed by the width difference in the connection region. The channel layer 140, the gate dielectric layer 145, and the core region 150 can be interconnected between the first channel structure CH1 and the second channel structure CH2. The channel pad 155 can be disposed only at the upper end of the upper second channel structure CH2. In some example embodiments, each of the first channel structure CH1 and the second channel structure CH2 may include a channel pad 155, and in this case, the channel pad of the first channel structure CH1 can be connected to the channel layer 140 of the second channel structure CH2. A relatively thick upper interlayer insulating layer 125 can be disposed on the uppermost part of the lower stack structure. In some example embodiments, the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 can vary. The number of first channel structures CH1 can be the same as or different from the number of second channel structures CH2.

[0102] In some example embodiments, the number of stacked structures and the number of channel structures stacked in the Z direction can vary.

[0103] Figures 8A to 19C This is a top view illustrating a method for manufacturing a semiconductor device according to some example embodiments.

[0104] refer to Figures 8A to 8C A peripheral circuit structure PERI, including circuit devices 220 and a lower wiring structure, can be formed on the first substrate 201. A second substrate 101, a horizontal insulating layer 110, a second horizontal conductive layer 104, and a substrate insulating layer 109, on which a memory cell structure CELL is disposed, can be formed above the peripheral circuit structure PERI. A sacrificial insulating layer 118 and an interlayer insulating layer 120 can be stacked alternately.

[0105] A device isolation layer 210 can be formed in a first substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 can be sequentially formed on the first substrate 201. The device isolation layer 210 can be formed, for example, by a shallow trench isolation (STI) process and / or a spin-on glass (SOG) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using thermal oxidation and / or atomic layer deposition (ALD) and / or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 can be formed from silicon oxide, and the circuit gate electrode 225 can be formed from at least one of doped or undoped polysilicon or metal silicide layers, but some exemplary embodiments are not limited thereto. Subsequently, a spacer layer 224 and source / drain regions 205 can be formed on the two sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In some exemplary embodiments, the spacer layer 224 can be formed from multiple layers. Ion implantation processes such as beamline ion implantation and / or plasma-assisted doped ion implantation can be performed to form the source / drain regions 205.

[0106] The circuit contact plug 270 of the lower wiring structure can be formed by partially forming an insulating layer 290 in the outer area, removing a portion of it by etching, and burying conductive material. The circuit wiring lines 280 can be formed by depositing and patterning conductive material.

[0107] The peripheral region insulating layer 290 can be formed by multiple insulating layers. The peripheral region insulating layer 290 can be partially formed in each process of forming the lower wiring structure, and can be partially formed above the circuit wiring line 280, thereby covering the circuit device 220 and the lower wiring structure.

[0108] A second substrate 101 may be formed on the peripheral region insulating layer 290. The second substrate 101 may be formed of, for example, polysilicon and may be formed by a CVD process such as plasma-enhanced CVD (PECVD). The polysilicon forming the second substrate 101 may include impurities, such as at least one of boron, phosphorus, or arsenic.

[0109] First to third horizontal insulating layers 111, 112, and 113 of the horizontal insulating layer 110 can be sequentially stacked on the second substrate 101. Through subsequent processes, the horizontal insulating layer 110 can be partially replaced with... Figure 2BThe first horizontal conductive layer 102 is present. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may comprise materials different from those of the second horizontal insulating layer 112, for example, they may be composed of materials different from those of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 and the third horizontal insulating layer 113 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the sacrificial insulating layer 118. The horizontal insulating layer 110 may be removed in certain areas by a patterning process.

[0110] A second horizontal conductive layer 104 may be formed on the horizontal insulating layer 110, and the second horizontal conductive layer 104 may contact the second substrate 101 in the region where the horizontal insulating layer 110 has been removed. Therefore, the second horizontal conductive layer 104 may be bent along the end of the horizontal insulating layer 110, may cover the end, and may extend to the second substrate 101.

[0111] This can be achieved by using the through-wiring area TR (see...) Figure 3A The corresponding area is partially removed from the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104, and filled with insulating material to form a substrate insulating layer 109. The substrate insulating layer 109 can be formed over the entire through-wiring region TR, or it can be formed in an area smaller than the entire region. After applying the insulating material, a planarization process can be further performed using chemical mechanical polishing (CMP) and / or etching-back processes. Therefore, the upper surface of the substrate insulating layer 109 can be substantially coplanar with the upper surface of the second horizontal conductive layer 104.

[0112] The sacrificial insulating layer 118 can be partially replaced by the gate electrode 130 through subsequent processes (see...). Figure 3A The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material selectively etched relative to the interlayer insulating layer 120 under specific etch conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride, or from the group consisting of silicon, silicon oxide, silicon carbide, and silicon nitride, different from the material of the interlayer insulating layer 120. In some example embodiments, the interlayer insulating layer 120 may not have the same thickness. The thicknesses of the interlayer insulating layer 120 and the sacrificial insulating layer 118, as well as the number of layers forming the interlayer insulating layer 120 and the sacrificial insulating layer 118, may differ from the example shown in the figures.

[0113] A cover insulation layer 190 can be formed on the upper part of a stacked structure that covers the sacrificial insulation layer 118 and the interlayer insulation layer 120.

[0114] refer to Figures 9A to 9C This can form a channel structure CH that penetrates the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120 (see [link]). Figure 2B It can form openings OP1 and OP2 that penetrate the stacked structure and a virtual channel structure DCH.

[0115] The upper isolation region SS can be formed by removing a portion of the sacrificial insulation layer 118 and the interlayer insulation layer 120. The upper isolation region SS can be formed by exposing the area where the upper isolation region SS will be formed using a mask layer, removing a specific (or, alternatively, predetermined) number of sacrificial insulation layers 118 and interlayer insulation layers 120 from the top, and filling with insulating material. The upper isolation region SS can be formed in the Z direction compared to the area where it is formed. Figure 3B The region of the upper gate electrode 130U extends further downward.

[0116] The channel structure CH and the dummy channel structure DCH can be formed by anisotropic etching (e.g., using dry etching) of the sacrificial insulating layer 118, the interlayer insulating layer 120, and the horizontal insulating layer 110, and can also be formed by forming and filling channel holes of the same shape. In some example embodiments, the dummy channel structure DCH may be formed to have a size / diameter larger than that of the channel structure CH. Due to the height of the stacked structure, the sidewalls of the channel holes may not be perpendicular to the upper surface of the second substrate 101. The channel holes may be formed to be recessed into a portion of the second substrate 101.

[0117] It is possible Figure 1A The first opening OP1 in the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b are set at their positions, and the first opening OP1 in OP2 can be set at its position. Figure 1A A second opening OP2 is positioned at the location of the blocking structure 160. Before forming openings OP1 and OP2, a covering insulating layer 190 can be further formed on the channel structure CH and the dummy channel structure DCH. Openings OP1 and OP2 can be formed by forming a mask layer using a photolithography process and performing anisotropic etching on the stacked structure. The first opening OP1 can be formed as a trench shape extending in the X direction, and the second opening OP2 can be formed as a quadrilateral ring, such as a square ring or a similar shape.

[0118] refer to Figures 10A to 10D After the first horizontal conductive layer 102 is formed, the first barrier layer 161, the second barrier layer 162 and the sacrificial core layer 165PS can be stacked in the openings OP1 and OP2 to form the preliminary barrier structure 160P.

[0119] By performing a back etching process while forming a sacrificial spacer layer in the first opening OP1, the second horizontal insulating layer 112 can be exposed in the first region R1, such as... Figure 3B As shown. The second horizontal insulating layer 112 can be selectively removed from the exposed area, and the first horizontal insulating layer 111 and the third horizontal insulating layer 113 disposed above and below the second horizontal insulating layer 112 can also be removed.

[0120] The first to third horizontal insulating layers 111, 112, and 113 can be removed by a wet etching process, for example, using acidic and / or alkaline chemicals such as buffered hydrogen fluoride. In the process of removing the first horizontal insulating layer 111 and the third horizontal insulating layer 113, the portion of the gate dielectric layer 145 exposed in the region where the second horizontal insulating layer 112 has been removed can also be removed. The first horizontal conductive layer 102 can be formed by depositing conductive material in the region where the first to third horizontal insulating layers 111, 112, and 113 have been removed, and the sacrificial spacer layer can be removed from the opening. Through this process, the first horizontal conductive layer 102 can be formed in the first region A.

[0121] A first barrier layer 161, a second barrier layer 162, and a sacrificial core layer 165PS can be sequentially formed from the inner and bottom surfaces of openings OP1 and OP2. The first barrier layer 161 and the second barrier layer 162 can be formed to have a relatively reduced thickness compared to the sacrificial core layer 165PS. The first barrier layer 161 and the second barrier layer 162 can include different materials, for example, they can be composed of different materials. The sacrificial core layer 165PS can include a material different from that of the second barrier layer 162. For example, the first barrier layer 161 can include a material different from that of the sacrificial insulating layer 118 to have etch selectivity towards the sacrificial insulating layer 118. The sacrificial core layer 165PS formed in the second opening OP2 can be replaced with the core insulating layer 165 by a subsequent process (see [link to relevant documentation]). Figure 4 ).

[0122] In this process, after forming the second barrier layer 162, a third barrier layer can be further formed to cover a portion of the upper part of the inner surface of the second barrier layer 162, so that the second barrier layer 162 can have the following characteristics: Figure 5B The raised PA is shown. By further performing a back-etching process, a portion of the third barrier layer can be removed to form the raised PA. Therefore, it is possible to manufacture / produce Figures 5B to 5D Semiconductor devices in some example embodiments.

[0123] refer to Figure 11A and Figure 11B This can remove the sacrificial core layer 165PS of the initial barrier structure 160P formed in the second opening OP2.

[0124] Using photolithography, a mask layer can be formed to cover the upper region of the first opening OP1, and the sacrificial core layer 165PS of the initial blocking structure 160P can be selectively removed from the second opening OP2. The sacrificial core layer 165PS can be removed from the second opening OP2 to re-form a portion OP2' of the second opening OP2.

[0125] refer to Figure 12A and Figure 12B A core insulation layer 165 can be formed in the region of the second opening OP2 where the sacrificial core layer 165PS has been removed. A support layer can be formed over the stacked structure of the sacrificial insulation layer 118 and the interlayer insulation layer 120, and through regions OS1a, OS1b and OS2 penetrating the support layer can be formed, thereby forming a support structure 170.

[0126] The core insulating layer 165 can be formed by filling the region of the second opening OP2 where the sacrificial core layer 165PS has been removed with an insulating material. The core insulating layer 165 may include a material different from that of the sacrificial core layer 165PS to allow for etch selectivity towards the sacrificial core layer 165PS. For example, the core insulating layer 165 may be formed of silicon oxide. After filling with the insulating material, a planarization process, such as a CMP process and / or an etch-back process, can be further performed. Thus, a barrier structure 160 comprising a first barrier layer 161, a second barrier layer 162, and a core insulating layer 165 can be formed.

[0127] It can be in the corresponding Figure 1A The first through-region OS1a and OS1b of OS1a and OS2 are set at the upper part of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b, and can be set at the corresponding position. Figure 1AA second through region OS2 is formed at the upper part of the blocking structure 160. Before forming the through regions OS1a, OS1b, and OS2, a cover insulating layer 190 can be further formed on the first isolation region MS1, the second isolation regions MS2a and MS2b, and the initial blocking structure 160P. The through regions OS1a, OS1b, and OS2 can be formed by forming a mask layer and etching a support layer using a photolithography process. During the etching process of the support layer, the cover insulating layer 190 can also be partially etched. The first through regions OS1a and OS1b can be formed into a trench shape extending in the X direction, and the second through region OS2 can be formed into a quadrilateral ring or a similar shape. By forming the first through regions OS1a and OS1b and the second through region OS2, a support structure 170 including support patterns 170P and 170PH and a bridge pattern 170B can be formed. The support layer can be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate (TEOS). In some example embodiments, the depths of the first through regions OS1a and OS1b and the second through region OS2 can be varied. For example, the first through regions OS1a and OS1b and the second through region OS2 can be formed deeper than in the example shown, such that their lower ends can be positioned at a horizontal height lower than the upper surface of the dummy channel structure DCH. For example, the first through regions OS1a and OS1b and the second through region OS2 can be formed with a thickness less than in the example shown, such that their lower ends can be positioned at a horizontal height substantially the same as the lower surface of the support patterns 170P and 170PH.

[0128] Now for reference Figure 13A As shown in Figure 13D, the initial blocking structure 160P formed in the first opening OP1 can be removed through the first through regions OS1a and OS1b.

[0129] After removing the sacrificial core layer 165PS of the initial barrier structure 160P from the first opening OP1, the first barrier layer 161 and the second barrier layer 162 can be removed to re-form the first opening OP1. Since the initial barrier structure 160P in the first opening OP1 has been removed, the side surface of the sacrificial insulation layer 118 can be exposed to the first opening OP1.

[0130] refer to Figures 14A to 14D The tunnel section TL can be formed by partially removing the sacrificial insulation layer 118 through the first through regions OS1a and OS1b and the first opening OP1.

[0131] The sacrificial insulation layer 118 can be removed from the outside of the through-wiring area TR (see...). Figure 2AThe sacrificial insulating layer 118 can be retained in the through-wiring region TR and can form an insulating region IR of the through-wiring region TR together with the interlayer insulating layer 120 and the substrate insulating layer 109. For example, the sacrificial insulating layer 118 can be selectively removed relative to the interlayer insulating layer 120, the second horizontal conductive layer 104, the substrate insulating layer 109, and the barrier structure 160 using wet etching. Therefore, multiple tunnel portions TL can be formed between the interlayer insulating layers 120.

[0132] The region forming the through wiring region TR can be spaced apart from the first opening OP1, preventing etchants such as chemical wet etchants from reaching this region, thus preserving the sacrificial insulating layer 118. Therefore, the through wiring region TR can be formed at the center between the first isolation regions MS1 and the second isolation regions MS2a and MS2b, which are adjacent first isolation regions MS1 and MS2a and MS2b. Alternatively or additionally, since the inflow of etchant is blocked by the blocking structure 160, the region where the sacrificial insulating layer 118 has been removed can be more precisely controlled. The region where the sacrificial insulating layer 118 is retained may not coincide with the region where the substrate insulating layer 109 is disposed, but some exemplary embodiments are not limited to this.

[0133] refer to Figure 15 A metal oxide layer 175 can be formed in the tunnel portion TL through the first through regions OS1a and OS1b and the first opening OP1, and a conductive material can be applied to form a gate electrode 130. Alternatively, the metal oxide layer 175 can be formed in the second through region OS2.

[0134] The metal oxide layer 175 can conformally cover the inner wall of the tunnel portion TL. The metal oxide layer 175 can be formed to cover the inner wall of the tunnel portion TL and extend in the Z direction along the side surface of the first opening OP1. The metal oxide layer 175 can extend to cover the side surfaces of the first through regions OS1a and OS1b and the second through region OS2, and cover the upper surface of the support pattern 170P. The metal oxide layer 175 can be formed to extend in the Z direction along the side surface of the second through region OS and can cover the upper surface of the blocking structure 160. In some example embodiments, the metal oxide layer 175 can be formed from multiple layers. In some example embodiments, the process of forming the metal oxide layer 175 may not be performed. Through subsequent processes, the thickness of the metal oxide layer 175 formed on the second through region OS2 can be greater than the thickness of the metal oxide layer 175 formed on the first through region OS1.

[0135] At least one surface of the gate electrode 130 may be covered by a metal oxide layer 175 in the tunnel portion TL. The metal oxide layer 175 covering at least one surface of the gate electrode 130 may be referred to as a "barrier layer". The conductive material forming the gate electrode 130 may fill the tunnel portion TL. The conductive material may include at least one of a metal, doped or undoped polysilicon, or a metal silicide material. The barrier structure 160 may prevent or reduce the possibility of conductive material flowing into the through-wiring region TR when the gate electrode 130 is formed. After the gate electrode 130 is formed, the conductive material deposited in the first opening OP1 may be removed by an additional process. Therefore, the side surface of the gate electrode 130 exposed through the first opening OP1 may be more recessed inward than the side surface of the first opening OP1.

[0136] refer to Figure 16 An insulating layer 195' can be formed to fill the first through regions OS1a and OS1b, the second through region OS2, and the first opening OP1.

[0137] An insulating layer 195' may cover a metal oxide layer 175. The insulating layer 195' may include a first insulating layer 195A' and a second insulating layer 195B' located on the first insulating layer 195A'. The first insulating layer 195A' may be conformally formed on the inner surface of the metal oxide layer 175 covering the first opening OP1, the first through regions OS1a and OS1b, and the second through region OS2. The first insulating layer 195A' may be formed by performing an atomic layer deposition (ALD) process. The interface surface between the first insulating layer 195A' and the second insulating layer 195B' may be distinct or indistinct. However, since the insulating layer 195' comprises a material different from that of the metal oxide layer 175, the interface surface between the insulating layer 195' and the metal oxide layer 175 may be distinct. The interface surface between the metal oxide layer 175 and the support pattern 170P and the covering insulating layer 190 may also be distinct.

[0138] refer to Figure 17 and Figure 18 Planarization processes, such as CMP and / or etch-back processes, can be performed to expose the upper surface of the supporting insulation layer 170P.

[0139] The insulating layer 195' can be partially removed by performing a planarization process. A portion of the metal oxide layer 175 and the first insulating layer 195A' formed on the support pattern 170P can be partially removed by the planarization process, or a portion of the metal oxide layer 175 and the first insulating layer 195A' formed on the support pattern 170P can be partially removed by an etch-back process performed after the planarization process. Thereafter, an upper insulating layer 195 can be further formed. Therefore, the first metal oxide layer 175A can be formed in the first through regions OS1a and OS1b, the first opening OP1, and the tunnel portion TL, and an insulating isolation layer 105 can be formed on the first through regions OS1a and OS1b and the first opening OP1. A second metal oxide layer 175B and a through insulating layer 178 can be formed in the second through region OS2. In some example embodiments, the etch-back process may not be performed in this process.

[0140] Reference Figures 19A to 19C A through-connection plug 180 can be formed in the through-wiring area TR (see...) Figure 2A ) through hole VH.

[0141] A via VH can be formed that penetrates the insulating layer 190 and the insulating region IR. The circuit wiring 280 of the peripheral circuit structure PERI can be exposed at the lower end of the via VH. In this process, a gate contact plug 185 for forming a connection to the gate electrode 130 can also be formed (see...). Figure 3C ) pore PH.

[0142] refer to Figures 1A to 4 A through-contact plug 180 can be formed by filling the through-hole VH with conductive material to form a through-wiring region TR, and a wiring line 188 connected to the upper end of the through-contact plug 180 can be formed to manufacture a semiconductor device 100.

[0143] Figure 20 This is a view illustrating a data storage system including semiconductor devices according to some example embodiments.

[0144] refer to Figure 20 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be configured as a storage device including one or more semiconductor devices 1100 or as an electronic device including a storage device. For example, the data storage system 1000 may be configured as a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0145] Semiconductor device 1100 can be configured as a non-volatile memory device, such as those shown in Figures 1 to 14 above. Figure 7 The NAND flash memory device described herein. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In some example embodiments, the first structure 1100F may be configured to be adjacent to the second structure 1100S. The first structure 1100F may be configured as a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be configured as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line and a second gate lower line, and a memory cell string CSTR located between the bit line BL and the common source line CSL.

[0146] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, an upper transistor adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In some example embodiments, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0147] In some example embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0148] In some example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used for an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0149] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0150] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor (MCT) among a plurality of memory cell transistors. The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input and output pads 1101 electrically connected to the logic circuit 1130. The input and output pads 1101 can be electrically connected to the logic circuit 1130 via input and output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0151] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to some example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1000.

[0152] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted through NAND interface 1221. Host interface 1230 can provide communication functionality between data storage system 1000 and external host. When a control command is received from an external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0153] Figure 21 This is a perspective view illustrating a data storage system including semiconductor devices according to some example embodiments.

[0154] refer to Figure 21According to some example embodiments, the data storage system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the main substrate 2001.

[0155] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some example embodiments, the data storage system 2000 may communicate with the external host via one of an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Memory (UFS). In some example embodiments, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that may distribute power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0156] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0157] DRAM 2004 can be configured as a buffer memory to mitigate speed differences between semiconductor package 2003, data storage space, and external host. DRAM 2004 included in data storage system 2000 can also function as a cache memory and can provide space for temporary data storage during the control operation of semiconductor package 2003. When DRAM 2004 is included in data storage system 2000, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0158] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0159] The package substrate 2100 can be configured as a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input and output pads 2210. The input and output pads 2210 may correspond to... Figure 20 The input and output pads 1101 are shown in Figure 1. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may be included in the reference figures 1 to 2000. Figure 7 The semiconductor devices described in the foregoing example embodiments.

[0160] In some example embodiments, the connection structure 2400 may be configured to electrically connect the input and output pads 2210 to bonding leads on the package-on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding leads and may be electrically connected to the package-on-package pads 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including a through-silicon via (TSV) rather than a bonding lead type connection structure 2400.

[0161] In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on an intermediate substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip may be interconnected by wiring formed on the intermediate substrate.

[0162] Figure 22 This is a cross-sectional view showing a semiconductor package according to some example embodiments. Figure 22 The cut-off line IV-IV' is shown. Figure 21 Some example embodiments of the semiconductor package 2003.

[0163] refer to Figure 22 In the semiconductor package 2003, the package substrate 2100 can be configured as a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120 and package upper pads 2130 disposed on the upper surface of the package substrate body portion 2120 (see See...). Figure 21 The package includes a lower pad 2125 disposed on or exposed through the lower surface of the main body portion 2120 of the package substrate, and internal wiring 2135 within the main body portion 2120 that electrically connects the upper pad 2130 to the lower pad 2125. The upper pad 2130 can be electrically connected to the connection structure 2400. The lower pad 2125 can be connected to, for example, a conductive connection portion 2800. Figure 21 Wiring pattern 2005 of the main substrate 2001 of the data storage system 2000 shown.

[0164] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region, which includes peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 located on the common source line 3205, a bit line 3240 electrically connected to a memory channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see [link to relevant documentation]). Figure 20 The gate contact plug 3235. See the reference above. Figures 1A to 4 As described, the barrier structure 160 surrounding the through-wiring region TR in each semiconductor chip 2200 may include a core insulating layer 165 disposed in a central region comprising silicon oxide, a first barrier layer 161 comprising silicon oxide, and a second barrier layer 162 comprising silicon nitride. Furthermore, as referenced above... Figures 1A to 4 The description may further include a support structure 170 comprising a first through region OS1a and OS1b and a second through region OS2 in each semiconductor chip 2200, and a metal oxide layer 175 may be disposed on the inner surface of the first through region OS1a and OS1b and the second through region OS2.

[0165] Each semiconductor chip 2200 may include peripheral wiring 3110 electrically connected to the first structure 3100 and extending through wiring 3245 into the second structure 3200. Through wiring 3245 may be disposed outside the gate stack structure 3210 and may penetrate the gate stack structure 3210. Each semiconductor chip 2200 may also include input and output pads 2210 electrically connected to the peripheral wiring 3110 of the first structure 3100 (see...). Figure 21 ).

[0166] According to some of the exemplary embodiments described above, by including a barrier structure having a core insulating layer containing silicon oxide in the central region, a semiconductor device with improved reliability and a data storage system including the semiconductor device can be provided.

[0167] Furthermore, by including a support structure with a through region that contacts the upper surface of the barrier structure, a semiconductor device with improved reliability and a data storage system including the semiconductor device can be provided.

[0168] Any element disclosed above may include or be implemented in processing circuitry, which may be, for example, hardware including logic circuitry; a hardware / software combination, such as a processor executing software; or a combination thereof. More specifically, for example, processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0169] Although some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A peripheral circuit structure, the peripheral circuit structure including a first substrate and at least one of an active device or a passive device located on the first substrate; A memory cell structure includes a second substrate located on a peripheral circuit structure and having a first region and a second region. The memory cell structure includes gate electrodes stacked on the first region spaced apart from each other in a first direction and extending in a second direction and arranged in a stepped shape on the second region. The memory cell structure includes interlayer insulating layers stacked alternately with the gate electrodes. The memory cell structure includes channel structures extending in the first direction and penetrating the gate electrodes, each channel structure including a channel layer. The memory cell structure includes isolation regions penetrating the gate electrodes, extending in the second direction and spaced apart from each other in a third direction. A through-wiring region, the through-wiring region including a sacrificial insulating layer located on the second region, spaced apart from the gate electrode and alternately stacked with the interlayer insulating layer, the through-wiring region including a through-contact plug that penetrates the sacrificial insulating layer and electrically connects the gate electrode to at least one of the active device or the passive device; as well as A barrier structure, the barrier structure surrounding the through wiring area and including a core insulation layer, a first barrier layer, and a second barrier layer, The core insulating layer is located in the central region of the barrier structure and includes silicon oxide. The second barrier layer covers the side surface and the bottom surface of the core insulation layer, and The first barrier layer covers the outer surface of the second barrier layer and the bottom surface of the second barrier layer.

2. The semiconductor device according to claim 1, wherein, The first barrier layer comprises silicon oxide, and The second barrier layer comprises silicon nitride.

3. The semiconductor device according to claim 1, wherein The core insulation layer is in direct contact with the inner surface of the second barrier layer, and The horizontal thickness of the core insulation layer is greater than the horizontal thickness of the first barrier layer.

4. The semiconductor device of claim 1, wherein, The memory cell structure also includes a dummy channel structure, which penetrates the gate electrode in the second region, extends in the first direction, and includes a conductive dummy channel layer.

5. The semiconductor device according to claim 1, wherein The memory cell structure also includes a support structure located on the gate electrode, and The supporting structure has a first through area located on the isolation area and a second through area located on the blocking structure.

6. The semiconductor device of claim 5, wherein, The second through region overlaps with the blocking structure in the first direction.

7. The semiconductor device according to claim 5, wherein, The storage cell structure further includes a metal oxide layer that extends along the side surface of the second through region and covers the upper surface of the barrier structure.

8. The semiconductor device according to claim 7, wherein The memory cell structure further includes a barrier layer extending along the side surface of the isolation region and covering at least one surface of the conductive layer forming the gate electrode, and The metal oxide layer comprises the same material as the barrier layer.

9. The semiconductor device according to claim 7, wherein, The storage cell structure also includes a through insulating layer located in the second through region, and The through-insulating layer includes a first insulating layer located on the metal oxide layer and a second insulating layer having a lower surface and a side surface, the lower surface and the side surface of the second insulating layer being surrounded by the first insulating layer.

10. A semiconductor device, the semiconductor device comprising: First substrate; At least one of an active device or a passive device, wherein the active device or the at least one of the passive devices is located on the first substrate; A second substrate is located on at least one of the active device or the passive device; Gate electrodes, which are stacked on the second substrate in a first direction and spaced apart from each other; A channel structure that penetrates the gate electrode, extends in the first direction, and includes a channel layer; An isolation region that penetrates the gate electrode and extends in a second direction; A through-contact plug that penetrates the second substrate, extends in the first direction, and electrically connects the gate electrode to at least one of the active device or the passive device; A blocking structure, the blocking structure being spaced apart from and surrounding the through contact plug; as well as A support structure, located on the gate electrode, includes a support pattern. The supporting structure has a first through region spaced apart from each other in the second direction on the isolation area and a second through region that contacts the upper surface of the blocking structure.

11. The semiconductor device of claim 10, further comprising: A metal oxide layer covers the side surface of the support pattern exposed in the second through region and covers the upper surface of the barrier structure; A through-insulation layer, wherein the through-insulation layer is located in the second through-region; and An upper insulating layer, which is located on the through insulating layer.

12. The semiconductor device of claim 10, further comprising: A metal oxide layer, the metal oxide layer extending along the side surface of each of the first through regions along the support pattern and along the side surface of the isolation region in the first direction, the metal oxide layer covering at least one surface of the conductive layer of the gate electrode.

13. The semiconductor device according to claim 10, wherein The barrier structure includes a core insulating layer, a first barrier layer, and a second barrier layer. The core insulation layer is located in the central region of the barrier structure. The second barrier layer is located on the side surface of the core insulation layer, and The first barrier layer is located on the outer surface of the second barrier layer.

14. The semiconductor device according to claim 13, wherein, Both the core insulating layer and the first barrier layer comprise silicon oxide, and The second barrier layer comprises silicon nitride.

15. The semiconductor device of claim 13, wherein, The second barrier layer includes protrusions that project toward the core insulation layer.

16. The semiconductor device of claim 10, wherein, The blocking structure has a quadrilateral ring shape or a shape similar to a quadrilateral ring in the top view.

17. The semiconductor device of claim 10, further comprising: An insulating region surrounding the through contact plug. The insulating region includes a substrate insulating layer that penetrates the second substrate, a sacrificial insulating layer that is stacked on the inner surface of the barrier structure in the first direction and spaced apart from each other, and an interlayer insulating layer disposed between the sacrificial insulating layers.

18. The semiconductor device of claim 17, wherein, The gate electrode facing the outer surface of the barrier structure and the sacrificial insulating layer in contact with the inner surface of the barrier structure are located at different horizontal heights.

19. A data storage system, the data storage system comprising: A semiconductor memory device comprising: a first substrate; at least one of an active device or a passive device disposed on the first substrate; a second substrate disposed on the active device or the passive device; a gate electrode stacked on the second substrate in a first direction and spaced apart from each other; a channel structure penetrating the gate electrode, the channel structure extending in the first direction and each of the channel structures including a channel layer; an isolation region penetrating the gate electrode and extending in a second direction; and a through contact plug penetrating the second substrate. A substrate extending in the first direction, electrically connecting the gate electrode to at least one of the active or passive devices; a blocking structure spaced apart from and surrounding the through-contact plug; a support structure located on the gate electrode and including a support pattern; and input and output pads electrically connected to at least one of the active or passive devices, wherein the support structure includes a first through-region spaced apart from each other in the second direction on the isolation region and a second through-region contacting the upper surface of the blocking structure; and A controller circuit, which is electrically connected to the semiconductor memory device via the input and output pads and is configured to control the semiconductor memory device.

20. The data storage system according to claim 19, wherein In the semiconductor memory device, the barrier structure includes a core insulating layer, a first barrier layer, and a second barrier layer. The core insulating layer is located on the central region of the barrier structure and includes silicon oxide. The second barrier layer covers the side surface and bottom surface of the core insulating layer and includes silicon nitride. The first barrier layer covers the outer surface and bottom surface of the second barrier layer and includes silicon oxide. The semiconductor memory device further includes a metal oxide layer that extends in the first direction along the side surface of the support pattern exposed to the second through region and covers the upper surface of the barrier structure.

Images