Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

A semiconductor memory device and a method for manufacturing the semiconductor memory device are provided. A semiconductor memory device includes: a channel structure including a first pillar and a second pillar extending from the first pillar; a barrier insulating layer surrounding a sidewall of the first pillar; a data storage layer disposed between the first pillar and the barrier insulating layer; an upper select line overlapping an end of the barrier insulating layer and an end of the data storage layer facing the extension direction of the second pillar, the upper select line surrounding a sidewall of the second pillar; and a tunnel insulating layer disposed between the first pillar and the data storage layer, the tunnel insulating layer extending between the second pillar and the upper select line.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memory devices and methods for manufacturing semiconductor memory devices, and more specifically, to three-dimensional semiconductor memory devices and methods for manufacturing three-dimensional semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices comprise multiple memory cells capable of storing data. The memory cells of a three-dimensional semiconductor memory device can be arranged in three dimensions. During the manufacture of a three-dimensional semiconductor memory device, failures may occur for various reasons. Therefore, the operating characteristics of the semiconductor memory device may deteriorate. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor memory device may include a channel structure, a barrier insulating layer, a data storage layer, an upper select line, and a tunnel insulating layer. The channel structure may include a first pillar and a second pillar extending from the first pillar. The barrier insulating layer may surround a sidewall of the first pillar of the channel structure. The data storage layer may be disposed between the first pillar of the channel structure and the barrier insulating layer. The upper select line may overlap with an end of the barrier insulating layer and an end of the data storage layer, the ends of the barrier insulating layer and the end of the data storage layer facing the extension direction of the second pillar, and the upper select line surrounds a sidewall of the second pillar of the channel structure. The tunnel insulating layer may be disposed between the first pillar of the channel structure and the data storage layer, and the tunnel insulating layer extends between the second pillar of the channel structure and the upper select line.

[0004] According to another aspect of this disclosure, a semiconductor memory device may include a first channel structure, a second channel structure, a tunnel insulating layer, a data storage layer, a barrier insulating layer, a first down select line, a second down select line, an isolation layer, a first up select line, a second up select line, an interlayer insulating layer, and a word line. The first channel structure and the second channel structure may extend parallel to each other. The tunnel insulating layer may surround a sidewall of each of the first and second channel structures. The data storage layer may surround a sidewall of each of the first and second channel structures, and the tunnel insulating layer is interposed between the data storage layer and a sidewall of each of the first and second channel structures. The barrier insulating layer may surround a sidewall of each of the first and second channel structures, and the data storage layer and the tunnel insulating layer are interposed between the barrier insulating layer and a sidewall of each of the first and second channel structures. The first down select line may surround the first channel structure, and the barrier insulating layer, the data storage layer, and the tunnel insulating layer are interposed between the first down select line and the first channel structure. The second lower select line may surround the second channel structure, and a blocking insulation layer, a data storage layer, and a tunnel insulation layer are inserted between the second lower select line and the second channel structure. An isolation layer may be disposed between the first lower select line and the second lower select line. The first upper select line may surround the first channel structure, and a tunnel insulation layer is inserted between the first upper select line and the first channel structure; the first upper select line is disposed on the first lower select line. The second upper select line may surround the second channel structure, and a tunnel insulation layer is inserted between the second upper select line and the second channel structure; the second upper select line is disposed on the second lower select line. Interlayer insulation layers and word lines may be alternately stacked between the first lower select line and the first upper select line, wherein the interlayer insulation layer and word lines extend between the second lower select line and the second upper select line.

[0005] According to another aspect of this disclosure, a method of manufacturing a semiconductor memory device may include: forming a first conductive layer on a substrate; alternately stacking a first material layer and a second material layer on the first conductive layer; forming a hole penetrating the first material layer and the second material layer, the hole extending into the interior of the substrate; sequentially stacking a barrier insulating layer, a data storage layer, and a tunnel insulating layer on the surface of the hole; forming a channel structure on the tunnel insulating layer that fills a central region of the hole; removing the substrate to expose the first conductive layer and the barrier insulating layer; sequentially removing a portion of the barrier insulating layer and a portion of the data storage layer to define a recessed region between the first conductive layer and the tunnel insulating layer; and forming a second conductive layer that fills the recessed region, the second conductive layer surrounding the tunnel insulating layer. Attached Figure Description

[0006] Example implementations will now be described below with reference to the accompanying drawings. However, they may be implemented in different forms and should not be construed as being limited to the implementations set forth herein.

[0007] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between those two elements, or there may be one or more intermediate elements. Throughout the text, similar reference numerals refer to similar elements.

[0008] Figure 1 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 3A This is an example Figure 2 A plan view showing the layout of the bit lines of a semiconductor memory device.

[0011] Figure 3B It is along Figure 3A The cross-sectional view of the semiconductor memory device shown is taken by line II′.

[0012] Figure 4 yes Figure 3B An enlarged cross-sectional view of region A shown in the figure.

[0013] Figure 5A yes Figure 4 The diagram shows a cross-sectional view of the first part of the trench structure, the tunnel insulation layer, and the second conductive pattern. Figure 5B yes Figure 4 The diagram shows a cross-sectional view of the first column, tunnel insulation layer, data storage layer, and first barrier insulation layer of the trench structure.

[0014] Figure 6 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 7 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 8A This is an example Figure 7 A plan view showing the layout of the bit lines of a semiconductor memory device.

[0017] Figure 8B It is along Figure 8A The cross-sectional view of the semiconductor memory device shown is taken by line II-II′.

[0018] Figure 9 yes Figure 8B An enlarged cross-sectional view of region B shown in the figure.

[0019] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11 , Figure 12 , Figure 13 , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B and Figure 17C This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 18G , Figure 18H , Figure 18I , Figure 18J , Figure 18K , Figure 18L , Figure 18M and Figure 18N This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0021] Figure 19 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0022] Figure 20 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0024] The embodiments provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve the operating characteristics of the semiconductor memory device.

[0025] Figure 1 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1The semiconductor memory device may include multiple memory blocks BLK, wherein each memory block BLK may include multiple memory cell strings MS1, MS2 and MS3 connected to a common source layer CSL and a bit line BL.

[0027] Each of the memory cell strings MS1, MS2, and MS3 may include a plurality of memory cells MC connected in series, a source selection transistor SST, and at least one drain selection transistor DST. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include one drain selection transistor DST connected between the plurality of memory cells MC and the bit line BL. In another embodiment, each of the memory cell strings MS1, MS2, and MS3 may include two or more drain selection transistors DST connected between the plurality of memory cells MC and the bit line BL.

[0028] Multiple memory cells MC can be connected to a common source layer CSL via source select transistor SST, and can be connected to bit line BL via drain select transistor DST.

[0029] The gates of source select transistors (SST) at the same height can be connected to isolated source select lines SSL1, SSL2, and SSL3. Similarly, the gates of drain select transistors (DST) at the same height can be connected to isolated drain select lines DSL1, DSL2, and DSL3.

[0030] In one embodiment, the storage block BLK may include a first source select line SSL1, a second source select line SSL2, and a third source select line SSL3 isolated from each other at the same height. The storage block may also include a first drain select line DSL1, a second drain select line DSL2, and a third drain select line DSL3 isolated from each other at the same height. However, the embodiments of this disclosure are not limited thereto. In another embodiment, the storage block BLK may include two source select lines isolated from each other at the same height, or it may include four or more source select lines isolated from each other at the same height. Furthermore, the storage block BLK may include two drain select lines isolated from each other at the same height, or it may include four or more drain select lines isolated from each other at the same height, wherein the number of drain select lines isolated from each other at the same height may be equal to or different from the number of source select lines isolated from each other at the same height.

[0031] The gates of multiple memory cells MC can be connected to multiple word lines WL, wherein the word lines WL can be set at different heights, and the gates of memory cells MC set at the same height can be connected to a single word line WL.

[0032] Multiple memory cell strings MS1, MS2, and MS3 can be connected to each word line WL. In an implementation, the multiple memory cell strings MS1, MS2, and MS3 can be divided into a first group, a second group, and a third group, which can be individually selected by a first source select line SSL1, a second source select line SSL2, and a third source select line SSL3. The first group may include the first memory cell string MS1. The second group may include the second memory cell string MS2. The third group may include the third memory cell string MS3.

[0033] The first memory cell string MS1 can be connected to the bit line BL via the drain select transistor DST connected to the first drain select line DSL1. The second memory cell string MS2 can be connected to the bit line BL via the drain select transistor DST connected to the second drain select line DSL2. The third memory cell string MS3 can be connected to the bit line BL via the drain select transistor DST connected to the third drain select line DSL3. One of the first memory cell string MS1, one of the second memory cell string MS2, and one of the third memory cell string MS3 can be connected to a single bit line BL.

[0034] Based on the gate signal applied to the first source select line SSL1, the first memory cell string MS1 can be connected to the common source layer CSL. Based on the gate signal applied to the second source select line SSL2, the second memory cell string MS2 can be connected to the common source layer CSL. The third memory cell string MS3 can be connected to the common source layer CSL based on the gate signal applied to the third source select line SSL3. Therefore, the multiple memory cell strings MS1, MS2, and MS3 can be isolated into groups that can be individually selected simultaneously for each of the source select lines SSL1, SSL2, and SSL3 during read or verification operations. In an embodiment, during a read or verification operation, one of the first source select line SSL1, the second source select line SSL2, and the third source select line SSL3 can be selected, such that one of the first group of first memory cell strings MS1, the second group of second memory cell strings MS2, and the third group of third memory cell strings MS3 can be connected to the common source layer CSL. Therefore, in the embodiments of this disclosure, compared to the case where the first memory cell string MS1, the second memory cell string MS2, and the third memory cell string MS3 are simultaneously connected to the common source layer during read or verification operations, the channel resistance can be reduced. Therefore, in the embodiments of this disclosure, read interference can be reduced.

[0035] Figure 2 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0036] Reference Figure 2 A semiconductor memory device may include a peripheral circuit structure PS, a bit line BL, gate stack structures GST1 and GST2, and a common source layer CSL. Each of the gate stack structures GST1 and GST2 can constitute a memory block.

[0037] To control the operation of memory cells, the peripheral circuit structure PS may include peripheral circuits.

[0038] Each of the gate stack structures GST1 and GST2 can overlap with the peripheral circuit structure PS and can be positioned between the bit line BL and the common source layer CSL. The peripheral circuit structure PS can overlap with the gate stack structures GST1 and GST2, with the bit line BL interposed therebetween. The common source layer CSL can overlap with the bit line BL, and the gate stack structures GST1 and GST2 can be interposed therebetween.

[0039] The gate stack structures GST1 and GST2 may include a first gate stack structure GST1 and a second gate stack structure GST2, with the first gate stack structure GST1 and the second gate stack structure GST2 facing each other.

[0040] Each of the first gate stack structure GST1 and the second gate stack structure GST2 may include: an upper select group including an upper select line, a lower select group including a lower select line, and a word line WL disposed between the upper select group and the lower select group. In an embodiment, the upper select lines may be configured as source select lines SSL1, SSL2, and SSL3. The lower select lines may be configured as drain select lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B.

[0041] Each of the source selection lines SSL1, SSL2, and SSL3, the word line WL, and the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B can extend in a first direction D1 and a second direction D2, wherein the first direction D1 can be defined as the direction of the X-axis in the XYZ coordinate system, and the second direction D2 can be defined as the direction of the Y-axis in the XYZ coordinate system.

[0042] Source select lines SSL1, SSL2, and SSL3 can be isolated from each other at the same height. In one implementation, source select lines SSL1, SSL2, and SSL3 can be spaced apart from each other in a first direction D1. Source select lines SSL1, SSL2, and SSL3 can be positioned between a common source layer CSL and a stack-up structure including word lines WL.

[0043] The word lines WL can be spaced apart on the third direction D3, which can be defined as the direction of the Z-axis in the XYZ coordinate system.

[0044] Each word line WL can be extended to overlap with the source selection lines SSL1, SSL2, and SSL3, which are isolated from each other.

[0045] Drain select lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B can be disposed in at least one layer between the bit line BL and the stack-up structure including the word line WL. In an embodiment, the drain select lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B can include drain select lines DSL1A, DSL2A, and DSL3A of a first height and drain select lines DSL1B, DSL2B, and DSL3B of a second height. The drain select lines DSL1B, DSL2B, and DSL3B of the second height can be spaced apart from the drain select lines DSL1A, DSL2A, and DSL3A of the first height on a third direction D3. The drain select lines DSL1A, DSL2A, and DSL3A of the first height can be spaced apart from each other in the extension direction of the bit line BL, and the drain select lines DSL1B, DSL2B, and DSL3B of the second height can also be spaced apart from each other in the extension direction of the bit line BL. In this implementation, the drain selection lines DSL1A, DSL2A and DSL3A of the first height and the drain selection lines DSL1B, DSL2B and DSL3B of the second height can be spaced apart from each other in the first direction D1.

[0046] The peripheral circuit structure PS can overlap with the upper selection group, which includes source selection lines SSL1, SSL2, and SSL3. In addition to the lower selection group, which includes drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B, the bit line BL can be positioned between the peripheral circuit structure PS and the upper selection group, which includes source selection lines SSL1, SSL2, and SSL3.

[0047] Each of the bit line BL and the common source line can be extended to overlap with the first gate stack structure GST1 and the second gate stack structure GST2.

[0048] Figure 3A This is an example Figure 2 A plan view showing the layout of the bit lines of a semiconductor memory device.

[0049] Reference Figure 3A The bit lines BL can extend parallel to each other and can be spaced apart from each other. In an embodiment, the bit lines BL can extend in a first direction D1 and can be spaced apart from each other in a second direction D2.

[0050] Bit line BL can be connected to channel structure CH extending on third direction D3, and can be connected to channel structure CH via bit line contact structure CT.

[0051] The channel structure CH can extend through the first gate stack structure GST1 and the second gate stack structure GST2, and can be divided into groups controlled by mutually spaced source select lines SSL1, SSL2, and SSL3. In an embodiment, the channel structure CH may include a first group configured with the first channel structure CH1, a second group configured with the second channel structure CH2, and a third group configured with the third channel structure CH3. The sidewalls of the first channel structure CH1 may be surrounded by the first source select line SSL1 of the first gate stack structure GST1. The first channel structure CH1 may be controlled by the first source select line SSL1. The sidewalls of the second channel structure CH2 may be surrounded by the second source select line SSL2 of the first gate stack structure GST1, and the second channel structure CH2 may be controlled by the second source select line SSL2. The sidewalls of the third channel structure CH3 may be surrounded by the third source select line SSL3 of the second gate stack structure GST2. The third channel structure CH3 may be controlled by the third source select line SSL3.

[0052] One of the first channel structure CH1, one of the second channel structure CH2, and one of the third channel structure CH3 can be connected in parallel to a single bit line BL.

[0053] The word line WL of the first gate stack structure GST1 can extend to surround the sidewalls of the first channel structure CH1 and the second channel structure CH2.

[0054] The embodiments shown in the accompanying drawings illustrate an isolation structure between first-height drain select lines DSL1A, DSL2A, and DSL3A, and an isolation structure between second-height drain select lines DSL1B, DSL2B, and DSL3B that is similar to the isolation structure between second-source select line SSL2 and third-source select line SSL3. More specifically, the first-height drain select lines DSL1A, DSL2A, and DSL3A may include first-height to third-height drain select lines. The second-height drain select lines DSL1B, DSL2B, and DSL3B may include second-height first-height to third-height drain select lines.

[0055] The first channel structure CH1 can pass through the first drain selection line DSL1A of the first height and the first drain selection line DSL1B of the second height. The second channel structure CH2 can pass through the second drain selection line DSL2A of the first height and the second drain selection line DSL2B of the second height. The third channel structure CH3 can pass through the third drain selection line DSL3A of the first height and the third drain selection line DSL3B of the second height.

[0056] Reference Figure 3A In the middle, line II′ overlaps with a single bit line BL. The channel structure CH that overlaps with the single bit line BL may include: a channel structure connected to the single bit line BL via a bit line contact structure CT that overlaps with line II′; and a channel structure connected to another bit line BL via a bit line contact structure CT that does not overlap with line II′.

[0057] Figure 3B It is along Figure 3A The cross-sectional view of the semiconductor memory device shown is taken by line II′.

[0058] Reference Figure 3B The source select lines SSL1, SSL2, and SSL3 can be isolated from each other by a trench T, which can be filled with an upper insulating layer 197. The upper insulating layer 197 can extend between the common source layer CSL and the upper select group including the source select lines SSL1, SSL2, and SSL3.

[0059] The common source layer (CSL) may include a doped semiconductor layer 199A, a conductive metal barrier layer 199B, and a metal layer 199C sequentially stacked on the upper insulating layer 197. The doped semiconductor layer 199A may include at least one of an n-type impurity and a p-type impurity.

[0060] The word line WL of the first gate stack structure GST1 can be separated from the word line WL of the second gate stack structure GST2 by the gate isolation layer 151. The word line WL of the first gate stack structure GST1 can also be insulated from the word line WL of the second gate stack structure GST2 by the gate isolation layer 151. The gate isolation layer 151 can extend between a first lower select group including the drain select lines DSL1A, DSL2A, DSL1B and DSL2B of the first gate stack structure GST1 and a second lower select group including the drain select lines DSL3A and DSL3B.

[0061] Each of the first gate stack structure GST1 and the second gate stack structure GST2 may further include interlayer insulating layers 111 stacked spaced apart from each other on the third-direction D3. The conductive layers and interlayer insulating layers 111 provided for the word line WL and the drain select lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B may be alternately disposed on the third-direction D3.

[0062] A first drain select line DSL1A of a first height, included in the first gate stack structure GST1, is spaced apart from a second drain select line DSL2A of a first height, also included in the first gate stack structure GST1, via a drain isolation layer 153. The first drain select line DSL1A of a first height, included in the first gate stack structure GST1, is insulated from the second drain select line DSL2A of a first height, also included in the first gate stack structure GST1, via the drain isolation layer 153. The drain isolation layer 153 can extend between a first drain select line DSL1B of a second height and a second drain select line DSL2B of a second height. The first drain select line DSL1B of a second height is included in the first gate stack structure GST1. The second drain select line DSL2B of a second height is included in the first gate stack structure GST1.

[0063] Each of the channel structures CH may include a channel layer 131 and a core insulating layer 133, wherein the channel layer 131 may include a semiconductor material. The channel layer 131 may surround the sidewalls of the core insulating layer 133 and may extend along a first surface of the core insulating layer 133. The core insulating layer 133 faces the common source layer CSL and may also overlap with a doped semiconductor pattern 135. The doped semiconductor pattern 135 may contact a second surface of the core insulating layer 133 facing the bit line BL. The channel layer 131 may extend to surround the sidewalls of the doped semiconductor pattern 135.

[0064] Each channel structure CH may include a first pillar PA and a second pillar PB extending from the first pillar PA in a third direction D3, wherein the central region of the first pillar PA may be filled with a core insulating layer 133 and a doped semiconductor pattern 135, and the core insulating layer 133 may extend to the central region of the second pillar PB. The outer walls of the first pillar PA and the second pillar PB may be configured with a channel layer 131.

[0065] Referring to the first stacked structure GST1, the sidewalls of the first pillar PA can be surrounded not only by the interlayer insulating layer 111 and the word line WL, but also by drain selection lines DSL1A or DSL2A corresponding to the first height of the first pillar PA and drain selection lines DSL1B or DSL2B corresponding to the second height of the first pillar PA. The sidewalls of the second pillar PB can be surrounded by source selection lines SSL1 or SSL2 corresponding to the second pillar PB, wherein the second pillar PB of the channel structure CH can extend in the third direction D3 to penetrate the upper insulating layer 197 and can extend into the interior of the common source layer CSL.

[0066] The sidewall of the first pillar PA can be surrounded by a first barrier insulation layer 121, a data storage layer 123, and a tunnel insulation layer 125. The first barrier insulation layer 121, the data storage layer 123, and the tunnel insulation layer 125 can be disposed between the first pillar PA and each of the interlayer insulation layer 111 and the word line WL. The first barrier insulation layer 121, the data storage layer 123, and the tunnel insulation layer 125 can extend between the first pillar PA and the drain selection line DSL1A or DSL2A corresponding to a first height of the first pillar PA, and can extend between the first pillar PA and the drain selection line DSL1B or DSL2B corresponding to a second height of the first pillar PA.

[0067] The data storage layer 123 may be disposed between the first barrier insulation layer 121 and the first post PA. The tunnel insulation layer 125 may be disposed between the data storage layer 123 and the first post PA, and may extend between the second post PB and the source selection line SSL1 or SSL2 corresponding to the second post PB.

[0068] The second pillar PB of each channel structure CH can protrude more than the tunnel insulation layer 125 in the third direction D3. Each channel structure CH can have a tapered shape. As the channel structure CH gets closer to the bit line BL and the peripheral circuit structure PS, the width of the channel structure CH becomes wider.

[0069] Bit line BL can be separated from channel structure CH by insulating layer 161, which can extend between bit line BL and each of first gate stack structure GST1 and second gate stack structure GST2. Bit line contact structure CT can electrically connect some of channel structure CH to bit line BL while penetrating insulating layer 161.

[0070] Bit line BL can be separated from peripheral circuit structure PS by a first insulating structure 163, which may include two or more insulating layers stacked between bit line BL and peripheral circuit structure PS.

[0071] The first interconnect structure 165 and the first conductive bonding pad 167 may be embedded in the first insulating structure 163, wherein the first interconnect structure 165 may include a plurality of conductive patterns. The first conductive bonding pad 167 may be connected to the first interconnect structure 165 and may face the peripheral circuit structure PS. In an embodiment, the first conductive bonding pad 167 may be electrically connected to the bit line BL via the first interconnect structure 165.

[0072] The peripheral circuit structure PS may include a substrate 171 containing transistors 180A and 180B, a second insulating structure 191, a second interconnect structure 193, and a second conductive bonding pad 195.

[0073] Transistors 180A and 180B can be disposed in the active region of substrate 171 separated by isolation layer 173. Each of transistors 180A and 180B may include a gate insulating layer 181 disposed on the active region, a gate electrode 183 disposed on the gate insulating layer 181, and a junction 185 formed in the active region on both sides of the gate electrode 183. Some of transistors 180A and 180B (e.g., 180B) may constitute a page buffer circuit for controlling the precharge and discharge operations of bit line BL.

[0074] The second insulating structure 191 may be disposed between the first insulating structure 163 and the substrate 171, and may include two or more insulating layers and may be bonded to the first insulating structure 163.

[0075] The second interconnect structure 193 and the second conductive bonding pad 195 may be buried within the second insulating structure 191, wherein the second interconnect structure 193 may include a plurality of conductive patterns. The second conductive bonding pad 195 may be connected to the second interconnect structure 193 and may face the first conductive bonding pad 167. The second conductive bonding pad 195 may be bonded to the first conductive bonding pad 167 and may be electrically connected via the second interconnect structure 193 to the transistor 180B of the page buffer circuit.

[0076] According to the embodiments described above, bit line BL can be connected to transistor 180B of the page buffer circuit via first interconnect structure 165, first conductive bonding pad 167, second conductive bonding pad 195 and second interconnect structure 193.

[0077] Figure 4 yes Figure 3B An enlarged cross-sectional view of region A shown in the figure.

[0078] Reference Figure 4The first barrier insulating layer 121 may include an end EG1 facing a third direction D3, and the data storage layer 123 may also include an end EG2 facing a third direction D3. The positions of the ends EG1 and EG2 of the first barrier insulating layer 121 and the data storage layer 123 may vary depending on the etching amount of the first barrier insulating layer 121 and the data storage layer 123. The end EG1 of the first barrier insulating layer 121 may be at the same height as the end EG2 of the data storage layer 123, or it may be at a different height from the end EG2 of the data storage layer 123.

[0079] The source select line (e.g., SSL1) may overlap with the end EG1 of the first barrier insulating layer 121 and the end EG2 of the data storage layer 123. Depending on the etching amount of the first barrier insulating layer 121 and the data storage layer 123, the interface between the source select line SSL1 and the end EG1 of the first barrier insulating layer 121, and the interface between the source select line SSL1 and the end EG2 of the data storage layer 123, may be set at a height substantially equal to or different from the height of the interface between the source select line SSL1 and the interlayer insulating layer 111.

[0080] The source select line SSL1 may include a first conductive pattern 101 and a second conductive pattern 103, wherein the first conductive pattern 101 may extend in a planar direction to intersect with the second post PB. In one embodiment, the first conductive pattern 101 may extend in a first direction D1 and a second direction D2 to be parallel to the word line WL. The second conductive pattern 103 may be disposed between the first conductive pattern 101 and the tunnel insulating layer 125.

[0081] The second conductive pattern 103 may include at least one of silicon, metal silicide, and conductive metal barrier, wherein the metal silicide may include tungsten silicide or nickel silicide, and the conductive metal barrier may include titanium and titanium nitride.

[0082] The second pillar PB of the channel structure CH may include a first portion P1 surrounded by the source select line SSL1, a second portion P2 extending from the first portion P1 in the third direction D3, and a third portion P3 extending from the second portion P2 in the third direction D3. The second portion P2 and the third portion P3 may protrude further than the source select line SSL1 in the third direction D3. The sidewalls of the second portion P2 may be surrounded by an upper insulating layer 197. The third portion P3 may be in contact with the doped semiconductor layer 199A of the common source layer.

[0083] The core insulating layer 133 of the channel structure CH can extend from the central region of the first pillar PA to the central region of each of the first portion P1, the second portion P2, and the third portion P3. The channel layer 131 of the channel structure CH can extend to form the outer wall of each of the first portion P1, the second portion P2, and the third portion P3. The doped semiconductor layer 199A of the common source layer can contact the channel layer 131 of the third portion P3.

[0084] The word line WL may include a conductive metal barrier layer 143 and a metal layer 145. A second barrier insulating layer 141 may be disposed between the word line WL and the first barrier insulating layer 121, and may extend between the interlayer insulating layer 111 and the word line WL. Like the word line WL, Figure 3B Each of the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B shown may include a conductive metal barrier layer 143 and a metal layer 145. A second barrier insulating layer 141 may be disposed between the first barrier insulating layer 121 and... Figure 3B Between each of the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B shown, and between the interlayer insulation layer 111 and Figure 3B The drain selection lines shown extend between DSL1A, DSL2A, DSL3A, DSL1B, DSL2B and DSL3B.

[0085] The second barrier insulating layer 141 may include an insulating material with a dielectric constant higher than that of the first barrier insulating layer 121, and although not shown in the figures, the second barrier insulating layer 141 may be omitted.

[0086] Figure 5A yes Figure 4 The diagram shows a cross-sectional view of the first part of the trench structure, the tunnel insulation layer, and the second conductive pattern. Figure 5B yes Figure 4 The diagram shows a cross-sectional view of the first column, tunnel insulation layer, data storage layer, and first barrier insulation layer of the trench structure.

[0087] Reference Figure 5A and Figure 5B The sidewalls of the core insulation layer 133 of the channel structure CH can be surrounded by the channel layer 131 of the channel structure CH, wherein the sidewalls of the channel layer 131 can be surrounded by the tunnel insulation layer 125.

[0088] Reference Figure 5AThe tunnel insulation layer 125 may extend to surround a portion of the sidewall of the second pillar PB. The sidewall of the first portion P1 of the second pillar PB may be surrounded by the tunnel insulation layer 125, wherein the tunnel insulation layer 125 may contact the first portion P1 of the second pillar PB. The first portion P1 of the second pillar PB may be provided by a source selection line (e.g., Figure 4 The second conductive pattern 103 of the SSL1 shown is surrounded, and the tunnel insulating layer 125 is inserted therebetween, so that a source selection transistor with a gate all around (GAA) can be defined at the intersection of the first portion P1 and the source selection line.

[0089] Reference Figure 5B The tunnel insulation layer 125 may extend to surround the sidewall of the first pillar PA. The sidewall of the first pillar PA may be surrounded not only by the tunnel insulation layer 125, but also by the data storage layer 123 surrounding the sidewall of the tunnel insulation layer 125 and the first barrier insulation layer 121 surrounding the sidewall of the data storage layer 123.

[0090] In one embodiment, the data storage layer 123 may be formed as a material layer capable of storing data altered using Fowler-Nordheim tunneling. The material layer may include a nitride layer capable of trapping charge. The first barrier insulating layer 121 may include an oxide layer capable of blocking charge. The tunnel insulating layer 125 may be formed as a silicon oxide layer through which charge can tunnel.

[0091] Figure 6 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0092] Reference Figure 6 The semiconductor memory device may include multiple memory blocks BLK′, wherein each memory block BLK′ may include multiple memory cell strings MS1′, MS2′ and MS3′ connected to a common source layer CSL′ and a bit line BL′.

[0093] Each of the memory cell strings MS1′, MS2′, and MS3′ may include a plurality of memory cells MC′, a drain-select transistor DST′, and at least one source-select transistor SST′ connected in series. In one embodiment, each of the memory cell strings MS1′, MS2′, and MS3′ may include one source-select transistor SST′ connected between the plurality of memory cells MC′ and the common source layer CSL′. In another embodiment, each of the memory cell strings MS1′, MS2′, and MS3′ may include two or more source-select transistors SST′ connected in series between the plurality of memory cells MC′ and the common source layer CSL′.

[0094] Multiple memory cells MC' can be connected to a common source layer CSL' via source select transistor SST'. Multiple memory cells MC' can be connected to bit line BL' via drain select transistor DST'.

[0095] The gates of drain select transistors DST′, which are set at the same height, can be connected to drain select lines DSL1′, DSL2′ and DSL3′ that are isolated from each other.

[0096] In one embodiment, the memory block BLK' may include a first drain select line DSL1', a second drain select line DSL2', and a third drain select line DSL3' that are isolated from each other at the same height. However, the embodiments of this disclosure are not limited thereto. In another embodiment, the memory block BLK' may include two drain select lines that are isolated from each other at the same height, or it may include four or more drain select lines that are isolated from each other at the same height.

[0097] The gates of source select transistors SST′, which are set at the same height, can be connected to a single source select line SSL′.

[0098] The gates of multiple memory cells MC′ can be connected to multiple word lines WL′, wherein the word lines WL′ can be set at different heights, and the gates of memory cells MC′ set at the same height can be connected to a single word line WL′.

[0099] Multiple memory cell strings MS1′, MS2′, and MS3′ can be connected to each word line WL′. In an embodiment, the multiple memory cell strings MS1′, MS2′, and MS3′ can be divided into a first group, a second group, and a third group, which can be individually selected by a first drain select line DSL1′, a second drain select line DSL2′, and a third drain select line DSL3′. The first group may include the first memory cell string MS1′, the second group may include the second memory cell string MS2′, and the third group may include the third memory cell string MS3′.

[0100] The first memory cell string MS1' can be connected to the bit line BL' via the drain select transistor DST' connected to the first drain select line DSL1'. The second memory cell string MS2' can be connected to the bit line BL' via the drain select transistor DST' connected to the second drain select line DSL2'. The third memory cell string MS3' can be connected to the bit line BL' via the drain select transistor DST' connected to the third drain select line DSL3'. One of the first memory cell strings MS1', one of the second memory cell strings MS2', and one of the third memory cell strings MS3' can be connected to a single bit line BL'.

[0101] The first memory cell string MS1′, the second memory cell string MS2′, and the third memory cell string MS3′ can be connected to the common source layer CSL′ according to the gate signal applied to the source select line SSL′.

[0102] Figure 7 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0103] Reference Figure 7 A semiconductor memory device may include a peripheral circuit structure PS′, a common source layer CSL′, gate stack structures GST1′ and GST2′, and a bit line BL′, wherein each of the gate stack structures GST1′ and GST2′ can constitute a memory block.

[0104] The peripheral circuit structure PS′ may include peripheral circuitry for controlling the operation of memory cells and may overlap with gate stack structures GST1′ and GST2′, with a common source layer CSL′ inserted therebetween.

[0105] The common source layers CSL′ can be spaced apart from each other at the same height and can overlap with the bit line BL′, with the gate stack structures GST1′ and GST2′ interposed in between.

[0106] The gate stack structures GST1′ and GST2′ may include a first gate stack structure GST1′ and a second gate stack structure GST2′ facing each other.

[0107] Each of the first gate stack structure GST1′ and the second gate stack structure GST2′ may include: an upper select group including an upper select line, a lower select group including a lower select line, and a word line WL′ disposed between the upper select group and the lower select group. In an embodiment, the upper select line may be configured with drain select lines DSL1′, DSL2′ and DSL3′, while the lower select line may be configured with source select lines SSL′[A] and SSL′[B].

[0108] Each of the drain selection lines DSL1′, DSL2′ and DSL3′, the word line WL′ and the source selection lines SSL′[A] and SSL′[B] can extend in a first direction D1 and a second direction D2, wherein the first direction D1 can be defined as the direction of the X-axis in the XYZ coordinate system and the second direction D2 can be defined as the direction of the Y-axis in the XYZ coordinate system.

[0109] Drain select lines DSL1′, DSL2′, and DSL3′ can be isolated from each other at the same height and can be spaced apart from each other in the extension direction of bit line BL′. In an embodiment, drain select lines DSL1′, DSL2′, and DSL3′ can be spaced apart from each other in a first direction D1. Drain select lines DSL1′, DSL2′, and DSL3′ can be disposed between bit line BL′ and the stack-up structure including word line WL′.

[0110] The word lines WL′ can be spaced apart from each other on a third direction D3, where the third direction D3 can be defined as the direction of the Z-axis in the XYZ coordinate system. Each of the word lines WL′ can extend to overlap with the drain selection lines DSL1′, DSL2′, and DSL3′ that are isolated from each other.

[0111] Source select lines SSL′[A] and SSL′[B] can be disposed in at least one layer between the common source layer CSL′ and the stack-up structure including word lines WL′. In an embodiment, source select lines SSL′[A] and SSL′[B] can include a first-height source select line SSL′[A] and a second-height source select line SSL′[B]. The second-height source select line SSL′[B] can be spaced apart from the first-height source select line SSL′[A].

[0112] The peripheral circuit structure PS′ can overlap with the upper selection group, which includes drain selection lines DSL1′, DSL2′, and DSL3′. In addition to the lower selection group, which includes source selection lines SSL′[A] and SSL′[B], the common source layer CSL′ can be set between the peripheral circuit structure PS′ and the upper selection group, which includes drain selection lines DSL1′, DSL2′, and DSL3′.

[0113] Bit line BL′ can be extended to overlap with the first gate stack structure GST1′ and the second gate stack structure GST2′. Common source layer CSL′ can overlap with the first gate stack structure GST1′ and the second gate stack structure GST2′, respectively.

[0114] Figure 8A This is an example Figure 7 A plan view showing the layout of the bit lines of a semiconductor memory device.

[0115] Reference Figure 8A The bit lines BL′ can extend parallel to each other and can be spaced apart from each other. In an embodiment, the bit lines BL′ can extend in a first direction D1 and can be spaced apart from each other in a second direction D2.

[0116] Bit line BL′ can be connected to channel structure CH′ extending on third direction D3, and can be connected to channel structure CH′ via bit line contact structure CT′.

[0117] The channel structure CH′ can penetrate the first gate stack structure GST1′ and the second gate stack structure GST2′, and the channel structure CH′ can be divided into groups controlled by drain select lines DSL1′, DSL2′, and DSL3′ spaced apart from each other. In an embodiment, the channel structure CH′ may include a first group configured with the first channel structure CH1′, a second group configured with the second channel structure CH2′, and a third group configured with the third channel structure CH3′. The sidewalls of the first channel structure CH1′ can be surrounded by and controlled by the first drain select line DSL1′ of the first gate stack structure GST1′. The sidewalls of the second channel structure CH2′ can be surrounded by and controlled by the second drain select line DSL2′ of the first gate stack structure GST1′. The sidewalls of the third channel structure CH3′ can be surrounded by and controlled by the third drain select line DSL3′ of the second gate stack structure GST2′.

[0118] One of the first channel structure CH1′, one of the second channel structure CH2′, and one of the third channel structure CH3′ can be connected in parallel to a single bit line BL′.

[0119] Each of the word line WL′ of the first gate stack structure GST1′ and the source selection lines SSL′[A] and SSL′[B] of the first gate stack structure GST1′ can extend to surround the sidewalls of the first channel structure CH1′ and the second channel structure CH2′.

[0120] Reference Figure 8A Line II-II′ overlaps with a single bit line BL′. The channel structure CH that overlaps with the single bit line BL′ may include a channel structure connected to the single bit line BL′ via a bit line contact structure CT′ that overlaps with line II-II′, and a channel structure connected to another line BL′ via a bit line contact structure CT that does not overlap with line II-II′.

[0121] Figure 8B It is along Figure 8A The cross-sectional view of the semiconductor memory device shown is taken by line II-II′.

[0122] Reference Figure 8BThe word line WL′ of the first gate stack structure GST1′ can be spaced apart from the word line WL′ of the second gate stack structure GST2′ by a first trench T1′, wherein the first trench T1′ can extend between a first lower select group including the source select lines SSL′[A] and SSL′[B] of the first gate stack structure GST1′ and a second lower select group including the source select lines SSL′[A] and SSL′[B] of the second gate stack structure GST2′.

[0123] Each of the first gate stack structure GST1′ and the second gate stack structure GST2′ may further include interlayer insulating layers 211 stacked at intervals on the third-direction D3. The conductive layers provided for the word line WL′ and the source select lines SSL′[A] and SSL′[B], as well as the interlayer insulating layers 211, may be alternately disposed on the third-direction D3.

[0124] A common source layer CSL′ can be disposed between the first gate stack structure GST1′, the second gate stack structure GST2′, and the peripheral circuit structure PS′. A first trench T1′ can extend between the common source layers CSL′ and can be filled with a gate isolation layer 251. The gate isolation layer 251 and the common source layer CSL′ can face the peripheral circuit structure PS′, and a first insulating structure 261 is inserted therebetween.

[0125] An upper selection group including drain selection lines DSL1′, DSL2′, and DSL3′ may overlap with a common source layer CSL′, and a lower selection group including source selection lines SSL′[A] and SSL′[B] and a word line WL′ may be inserted therebetween. Drain selection lines DSL1′, DSL2′, and DSL3′ may be isolated from each other by a second trench T2′, wherein the second trench T2′ may be filled with a first upper insulating layer 295. The first upper insulating layer 295 may extend between the bit line BL′ and the upper selection group including drain selection lines DSL1′, DSL2′, and DSL3′. The bit line BL′ may be spaced apart from the drain selection lines DSL1′, DSL2′, and DSL3′, and a second upper insulating layer 297 and the first upper insulating layer 295 may be inserted therebetween.

[0126] Bit line BL′ may include a metal layer 299B and a conductive metal barrier layer 299A disposed between the metal layer 299B and the second upper insulating layer 297, and may be connected to the channel structure CH′ via bit line contact structure CT′.

[0127] The bit line contact structure CT′ can penetrate the first upper insulating layer 295 and the second upper insulating layer 297 to electrically connect some channel structures CH′ to bit lines BL′.

[0128] Referring to the first gate stack structure GST1′, each channel structure CH′ may include a channel layer 231 and a core insulating layer 233, wherein the sidewalls of the core insulating layer 233 may be surrounded by the first gate stack structure GST1′ and the first upper insulating layer 295. The channel layer 231 may include a semiconductor material, may be disposed between the core insulating layer 233 and the first gate stack structure GST1′, may extend between the core insulating layer 233 and the first upper insulating layer 295, and may extend between the common source layer CSL′ and the first gate stack structure GST1′.

[0129] Referring to the common source layer CSL′ corresponding to the first gate stack structure GST1′, the common source layer CSL′ may include a horizontal pattern HP extending parallel to the word line WL′ and a vertical pattern VP extending from the horizontal pattern HP in a third direction D3 toward the core insulating layer 233. The channel layer 231 may extend to surround the sidewalls of the vertical pattern VP and extend between the horizontal pattern HP and the first gate stack structure GST1′. The common source layer CSL′ may be formed as a doped semiconductor layer including at least one of n-type and p-type impurities.

[0130] Each channel structure CH′ may include a first pillar PA′ and a second pillar PB′ extending from the first pillar PA′ in a third direction D3. The central region of the first pillar PA′ may be filled with a vertical pattern VP of a core insulating layer 233 and a common source layer CSL′, and the core insulating layer 233 may extend to the central region of the second pillar PB′. The outer walls of the first pillar PA′ and the second pillar PB′ may be configured with channel layers 231.

[0131] Referring to the first gate stack structure GST1′, the sidewall of the first pillar PA′ may be surrounded not only by the interlayer insulating layer 211 and the word line WL′, but also by the source select line SSL′[A] corresponding to the first height of the first pillar PA′ and the source select line SSL′[B] corresponding to the second height of the first pillar PA′. The sidewall of the second pillar PB′ may be surrounded by the drain select line DSL1′ or DSL2′ corresponding to the second pillar PB′, and the second pillar PB′ of the channel structure CH′ may extend into the interior of the first upper insulating layer 295.

[0132] The sidewall of the first pillar PA' may be surrounded by a first barrier insulating layer 221, a data storage layer 223, and a tunnel insulating layer 225, wherein the first barrier insulating layer 221, the data storage layer 223, and the tunnel insulating layer 225 may be disposed between the first pillar PB' and each of the interlayer insulating layer 221 and the word line WL'. The first barrier insulating layer 221, the data storage layer 223, and the tunnel insulating layer 225 may extend between the source select line SSL'[A] of the first height and the first pillar PA', may extend between the source select line SSL'[B] of the second height and the first pillar PA', and may extend between the first gate stack structure GST1' and the channel layer 231.

[0133] The data storage layer 223 may be disposed between the first barrier insulation layer 221 and the first post PA′. The tunnel insulation layer 225 may be disposed between the data storage layer 223 and the first post PA′, and may extend between the second post PB′ and the drain selection line DSL1′ or DSL2′ corresponding to the second post PB′.

[0134] Each channel structure CH′ can have a tapered shape. The width of the channel structure CH′ increases as it gets closer to the common source layer CSL′ and the peripheral circuit structure PS′. Some channel structures CH′ can be connected to the bit line BL′ via bit line contact structures CT′. The bit line contact structure CT′ can penetrate the first upper insulating layer 295 and the second upper insulating layer 297, and can extend to contact the channel layer 231 of the channel structure CH′.

[0135] The common source layer CSL′ can be separated from the peripheral circuit structure PS′ by a first insulating structure 261, wherein the first insulating structure 261 can be bonded to the peripheral circuit structure PS′.

[0136] The peripheral circuit structure PS′ may include a substrate 271 containing transistors 280A and 280B, a second insulating structure 291, and an interconnect structure 293.

[0137] Transistors 280A and 280B can be disposed in an active region of substrate 271 separated by isolation layer 273, and each of transistors 280A and 280B may include a gate insulating layer 281, a gate electrode 283, and a junction 285, as shown in reference. Figure 3B The transistors 280A and 280B (e.g., 280B) can form a page buffer circuit for controlling the precharge and discharge operations of bit line BL′.

[0138] The second insulating structure 291 may be disposed between the first insulating structure 261 and the substrate 271, and may include two or more insulating layers and may be bonded to the first insulating structure 261.

[0139] The interconnect structure 293 may be buried in the second insulating structure 291, may include multiple conductive patterns, may be electrically connected to the transistor 280B of the page buffer circuit, and may be connected to the bit line BL′ via the first through-hole contact structure V1 and the second through-hole contact structure V2.

[0140] The first via contact structure V1 can penetrate the gate isolation layer 251, penetrate the first insulating structure 261 and the second insulating structure 291 to contact the interconnect structure 293, and can extend in the third direction D3 to penetrate the first upper insulating layer 295. The second via contact structure V2 can contact the first via contact structure V1 and can extend to penetrate the second upper insulating layer 297. The first via contact structure V1 may include a conductive metal barrier layer 296A and a metal layer 296B, while the second via contact structure V2 may also include a conductive metal barrier layer 298A and a metal layer 298B.

[0141] According to the embodiments described above, the bit line BL′ can be connected to the transistor 280B of the page buffer circuit via the first through-hole contact structure V1, the second through-hole contact structure V2 and the interconnect structure 293.

[0142] Figure 9 yes Figure 8B An enlarged cross-sectional view of region B shown in the figure.

[0143] Reference Figure 9 The first barrier insulation layer 221 may include an end EG1′ facing the third direction D3, and the data storage layer 223 may also include an end EG2′ facing the third direction D3.

[0144] The drain selection line (e.g., DSL1') may overlap with the end EG1' of the first barrier insulation layer 221 and the end EG2' of the data storage layer 223.

[0145] The drain select line DSL1′ may include a first conductive pattern 201 and a second conductive pattern 203. The first conductive pattern 201 may extend in a planar direction to intersect with the second pillar PB′. Specifically, the first conductive pattern 201 may extend in a first direction D1 and a second direction D2 to be parallel to the word line WL′. The second conductive pattern 203 may be disposed between the first conductive pattern 201 and the tunnel insulating layer 225, and may provide a drain select transistor with a gate-all-around (GAA) structure at the intersection between the drain select line DSL1′ and the second pillar PB′.

[0146] The second conductive pattern 203 may include at least one of silicon, metal silicide, and conductive metal barrier, wherein the metal silicide may include tungsten silicide or nickel silicide, and the conductive metal barrier may include titanium and titanium nitride.

[0147] The second post portion PB′ of the channel structure CH′ may include a first portion P1′ surrounded by the drain selection line DSL1′, a second portion P2′ extending from the first portion P1′ in the third direction D3, and a third portion P3′ extending from the second portion P2′ in the third direction D3. The second portion P2′ and the third portion P3′ may protrude further than the drain selection line DSL1′ in the third direction D3 and may be covered by the upper insulating layer 295.

[0148] The bit line contact structure CT′ can penetrate the first insulating layer 295 and can extend to contact the channel layer 231 of the third portion P3′. The conductive metal barrier layer 298A of the bit line contact structure CT′ can be disposed between the metal layer 298B of the bit line contact structure CT′ and the channel layer 231, and can extend between the metal layer 298B of the bit line contact structure CT′ and the first upper insulating layer 295.

[0149] The core insulation layer 233 of the channel structure CH′ can extend from the central region of the first post PA′ to the central regions of the first part P1′, the second part P2′ and the third part P3′.

[0150] For reference Figure 4 As described, the word line WL′ may include a conductive metal barrier layer 243 and a metal layer 245. (See reference...) Figure 4 As described, the second barrier insulating layer 241 can be disposed between the word line WL′ and the first barrier insulating layer 221. Similar to the word line WL′, Figure 8B Each of the source selection lines SSL′[A] and SSL′[B] shown may include a conductive metal barrier layer 243 and a metal layer 245. A second barrier insulating layer 241 may be disposed between the first barrier insulating layer 221 and... Figure 8B The source selection lines SSL′[A] and SSL′[B] shown are between each of them, and can be in the interlayer insulation layer 211 with Figure 8B The source selection lines SSL′[A] and SSL′[B] shown extend between each of them.

[0151] The tunnel insulation layer 225, the data storage layer 223, and the first barrier insulation layer 221 can be determined by reference. Figure 5B The material described is used. The second barrier insulating layer 241 may include an insulating material with a higher dielectric constant than the first barrier insulating layer 221.

[0152] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11 , Figure 12, Figure 13 , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B and Figure 17C This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0153] Figures 10A to 10E This is a cross-sectional view illustrating the process performed prior to the bonding process.

[0154] Reference Figure 10A A first conductive layer 305 may be formed on the first substrate 301. Before forming the first conductive layer 305, a first protective layer 303 having etch selectivity relative to the first substrate 301 may be formed on the first substrate 301. In an embodiment, the first substrate 301 may include silicon, and the first protective layer 303 may include a nitride.

[0155] The first conductive layer 305 may include a conductive material that is etch-resistant relative to the etch material when a subsequent etching process is performed to remove the first protective layer 303. In one embodiment, the first conductive layer 305 may include silicon.

[0156] Subsequently, a first material layer 311 and a second material layer 313 may be alternately stacked on the first conductive layer 303. In one embodiment, the first material layer 311 may be an insulating material for interlayer insulation, such as silicon oxide, and the second material layer 313 may be a sacrificial material with etch selectivity relative to the first material 311, such as silicon nitride. In another embodiment, the first material layer 311 may be an insulating material for interlayer insulation, and the second material layer 313 may be a conductive material for word lines and downselect lines. Hereinafter, for ease of description, the manufacturing process will be described primarily based on an embodiment where the first material layer 311 is made of an insulating material for interlayer insulation and the second material layer 313 is made of a sacrificial material. However, embodiments of this disclosure are not limited thereto.

[0157] Subsequently, a hole 320 can be formed to penetrate the first material layer 311 and the second material layer 313. The hole 320 can penetrate the first conductive layer 305 and the first protective layer 303, and extend into the interior of the first substrate 301. The hole 320 can be formed by performing an etching process from the first material layer 311, which is furthest from the first substrate 301, toward the first substrate 301. Therefore, the hole 320 can have a tapered shape. As the hole 320 becomes farther away from the first substrate 301, the width of the hole 320 becomes wider.

[0158] Subsequently, the first barrier insulating layer 321, the data storage layer 323, and the tunnel insulating layer 325 may be sequentially stacked on the surface of the via 320. The data storage layer 323 may be made of a material that enables data storage and has etch selectivity relative to the first barrier insulating layer 321 and the tunnel insulating layer 325. In an embodiment, the first barrier insulating layer 321 may include an oxide, the data storage layer 323 may include silicon nitride, and the tunnel insulating layer 325 may include silicon oxide.

[0159] Subsequently, the central region of the hole 320 can be filled with a channel structure 330 and a doped semiconductor pattern 335, wherein the channel structure 330 may include a channel layer 331 and a core insulating layer 333. The channel layer 331 may extend along the surface of the tunnel insulating layer 325 and may include a semiconductor material. In an embodiment, the channel layer may include silicon. The core insulating layer 333 and the doped semiconductor pattern 335 may fill the central region of the hole 320 opened through the channel layer 331. After a portion of the hole 320 is filled with the core insulating layer 333, the doped semiconductor pattern 335 may be disposed on the core insulating layer 333. The channel structure 330 filling the central region of the hole 320 may have a tapered shape. The width of the channel structure 330 increases as the hole 320 becomes farther away from the first substrate 301.

[0160] Reference Figure 10B This can form the first trench 340 to penetrate. Figure 3A The first material layer 311 and the second material layer 313 are shown, wherein the first trench 340 can be defined by etching the first material layer 311 and the second material layer 313. When etching the first material layer 311 and the second material layer 313, the first conductive layer 305 can be used as an etching stop layer.

[0161] when Figure 10A When the second material layer 313 shown is a sacrificial material, it can be replaced by a conductive pattern 347 through the first trench 340. Figure 10A The second material layer 313 is shown. It is replaced with a conductive pattern 347. Figure 10A The process of the second material layer 313 shown includes removing material via the first trench 340. Figure 10A The process shown is to use the second material layer 313 to open the gate region between the first material layers 311, and to fill the gate region with the conductive pattern 347.

[0162] Before filling the gate region with conductive pattern 347, a second barrier insulating layer 341 may be formed along the surface of each gate region, wherein each conductive pattern 347 may fill a portion of the gate region opened by the second barrier insulating layer 341.

[0163] The conductive pattern 347 can be formed from various conductive materials. In one embodiment, each conductive pattern 347 may include a conductive metal barrier layer 343 and a metal layer 345. Each conductive pattern 347 may surround the sidewalls of the channel structure 330 between the first material layers 311.

[0164] Reference Figure 10C The gate isolation layer 351, which can be an insulating material, can be used to fill the gap. Figure 10B The first trench 340 shown.

[0165] Subsequently, a second trench 353 can be formed to penetrate. Figure 10B At least one of the conductive patterns 347 shown. In an embodiment, the second trench 353 may extend through both conductive patterns. Figure 10B Some of the conductive patterns 347 shown can be isolated by the second trench 353 to form drain selection lines 347D. Other conductive patterns not penetrated by the second trench 353 can be defined as word lines 347W.

[0166] Reference Figure 10D It can be filled with a drain isolation layer 357 that can be formed of insulating material. Figure 10C The second groove 353 is shown in the figure.

[0167] Subsequently, the first insulating layer 361 may be formed to extend and overlap with the channel structure 330, the gate isolation layer 351, the drain isolation layer 357, and the interlayer insulating layer 311. Continuously, a bit line contact structure 363 may be formed to penetrate the first insulating layer 361. The bit line contact structure 363 may be electrically connected to the channel structure 330 and the doped semiconductor pattern 335.

[0168] Subsequently, bit line 365 can be formed to contact bit line contact structure 363. Bit line 365 can extend onto the first insulating layer 361. In an embodiment, bit line 365 can extend in a first direction D1.

[0169] Reference Figure 10E The bonding structure can be formed on bit line 365 and can include a first insulating structure 367 and a first conductive bonding pad 371 buried in the first insulating structure 367.

[0170] Before forming the first conductive bonding pad 371, a first interconnect structure 369 may be formed to include a plurality of conductive patterns embedded in a first insulating structure 367. Some of the conductive patterns of the first interconnect structure 369 may be electrically connected to bit lines 365. The first conductive bonding pad 371 may contact the first interconnect structure 369 and may be electrically connected to bit lines 365 via the first interconnect structure 369.

[0171] Figure 11 This is a cross-sectional view illustrating the process of forming the peripheral circuit structure.

[0172] Reference Figure 11 The process of forming the peripheral circuit structure 390 may include: forming an isolation layer 383 in the second substrate 381 that separates the active regions of the second substrate 381; forming transistors 385A and 385B in the active regions separated by the source isolation layer 383; forming a second interconnect structure 389 connected to transistors 385A and 385B; and forming a second conductive bonding pad 391 connected to the second interconnect structure 389.

[0173] Transistors 385A and 385B may include references Figure 3A The transistors described are the same components. Some of transistors 385A and 385B (e.g., 385B) can form a page buffer circuit.

[0174] The second substrate 381, including transistors 385A and 385B, can be covered by the second insulating structure 387. The second interconnect structure 389 and the second conductive bonding pad 391 can be buried in the second insulating structure 387.

[0175] The second interconnect structure 389 may include a plurality of conductive patterns, some of which may be connected to the transistor 385B of the page buffer circuit. The second conductive bonding pad 391 may be connected to the transistor 385B of the page buffer circuit via the second interconnect structure 389.

[0176] Figure 12 This is a cross-sectional view illustrating the joining process.

[0177] Reference Figure 12 The peripheral circuit structure 390 can be aligned with the first insulating structure 367 and the first conductive bonding pad 371, which are face-to-face bonding structures.

[0178] Subsequently, the second insulating structure 387 and the second conductive bonding pad 391 of the peripheral circuit structure 390 can be bonded to the first insulating structure 367 and the first conductive bonding pad 371 of the bonding structure.

[0179] After the bonding process is performed, the process temperature can be limited to 450°C or lower, which can reduce the occurrence of defects in the first conductive bonding pad 371 and the second conductive bonding pad 391 due to high temperature.

[0180] Figure 13 These are cross-sectional views illustrating some processes performed after the bonding process.

[0181] Reference Figure 13 It can remove Figure 12The first substrate 301 shown herein, and can be made of Figure 12 The first protective layer 303 shown protects the first conductive layer 305. It can then be selectively removed. Figure 12 The first protective layer 303 shown allows the first conductive layer 305 and the first barrier insulating layer 321 to be exposed.

[0182] Figure 14A and Figure 14B yes Figure 13 The enlarged process cross-section of region C shown in the figure.

[0183] Reference Figure 14A An initial recessed region 403 can be formed between the first conductive layer 305 and the data storage layer 323 by selectively removing a portion of the first barrier insulating layer 321. The retained first barrier insulating layer 321 can be configured to be closer to the first conductive layer 305 than the conductive metal barrier layer 343 and the metal layer 345.

[0184] Reference Figure 14B By selectively removing the data storage layer 323, a recessed region 405 can be defined between the first conductive layer 305 and the tunnel insulating layer 325. The retained first barrier insulating layer 321 and the retained data storage layer 323 can be configured to be closer to the first conductive layer 305 than the conductive metal barrier layer 343 and the metal layer 345.

[0185] Figure 15A and Figure 15B This is a cross-sectional view illustrating the subsequent processes that continue after the formation of the recessed area.

[0186] Reference Figure 15A A second conductive layer 411 can be formed along the surfaces of the first conductive layer 305 and the tunnel insulating layer 325, and the second conductive layer 411 can fill... Figure 14B The recessed area 405 is shown.

[0187] The second conductive layer 411 may include at least one of silicon, metal silicide, and conductive metal barrier, wherein the metal silicide may include tungsten silicide or nickel silicide, and the conductive metal barrier may include titanium and titanium nitride.

[0188] Reference Figure 15B A portion of the second conductive layer 411 can be removed, exposing the tunnel insulating layer 325 and the first conductive layer 305. The second conductive layer 411 can be retained as follows: Figure 14B The sidewalls surrounding the tunnel insulation layer 325 in the recessed region 405 shown.

[0189] Figure 16A and Figure 16B This is a process cross-sectional diagram illustrating the process of selecting the isolation line.

[0190] Reference Figure 16A The uneven structure can be defined by a channel structure 330 that protrudes further in the third direction D3 than the first conductive layer 305. A second protective layer 421 can be formed along the surface of the uneven structure, and the second protective layer 421 can be deposited under conditions that reduce step coverage. In an embodiment, the second protective layer 421 can be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) with less step coverage than atomic layer deposition (ALD). The second protective layer 421 may include a material that has etch selectivity relative to the first conductive layer 305. In an embodiment, the second protective layer 421 may include an amorphous carbon layer (ACL) that can be deposited by plasma-enhanced chemical vapor deposition (PE-CVD).

[0191] The second protective layer 421, deposited under conditions of reduced step coverage, can be relatively thicker on the convex portion of the uneven structure than on the concave portion, can have an overhang structure, and can have sidewalls facing each other, with each first opening 423 inserted between the facing sidewalls. As the overhang structure becomes farther away from the first conductive layer 305, the width of each first opening 423 can be narrowed by the second protective layer 421.

[0192] Subsequently, a mask pattern 431 can be formed on the second protective layer 421 using a photolithography process. The mask pattern 431 may be a photoresist pattern that may include a second opening 433.

[0193] The second opening 433 can overlap with the gate isolation layer 351 and the drain isolation layer 357, respectively. The first opening 423, which overlaps with the gate isolation layer 351 and the drain isolation layer 357, can be exposed through the second opening 433.

[0194] The first conductive layer 305 located on the periphery of the channel structure 330 can be blocked by the second protective layer 421 with a hanging structure.

[0195] Reference Figure 16B It can be done via Figure 16A The first opening 423 exposed by the second opening 433 shown is etched into the first conductive layer 305 to form a third trench 441 penetrating the first conductive layer 305. The third trench 441 can define an upper select line. In an embodiment, the upper select line can be a source select line 443. Each source select line 443 may include a first conductive layer 305 separated by the third trench 441 and a second conductive layer 411 between the first conductive layer 305 and the tunnel insulating layer 325.

[0196] According to embodiments of this disclosure, the second conductive layer 411 is retained around the trench structure 330 between the tunnel insulating layer 325 and the first conductive layer 305, such that the retention width of the source select line 443 between the tunnel insulating layer 325 and the third trench 441 can be widened. Therefore, in embodiments of this disclosure, a select transistor with a gate all around (GAA) can be stably formed.

[0197] Figures 17A to 17C An implementation of the subsequent process following the formation of source selection line 443 is illustrated.

[0198] Reference Figure 17A An upper insulating layer 451 may be formed to fill the third trench 441 and cover the source selection line 443, the trench structure 330 and the tunnel insulating layer 325, wherein the upper insulating layer 451 may include oxide.

[0199] Reference Figure 17B A portion of the upper insulating layer 451 and a portion of the tunnel insulating layer 325 can be etched using an etching process such as a back etching process, so that the channel layer 331 of the channel structure 330 can be exposed.

[0200] The upper insulating layer 451 can be retained in the third trench 441 and can be retained to cover the source selection line 433.

[0201] Reference Figure 17C A doped semiconductor layer 455 of the common source layer can be formed on the exposed area of ​​the channel layer 331.

[0202] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 18G , Figure 18H , Figure 18I , Figure 18J , Figure 18K , Figure 18L , Figure 18M and Figure 18N This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0203] Reference Figure 18A , as reference Figure 10A As described, a first protective layer 503 and a first conductive layer 505 can be formed on the substrate 501. Subsequently, as referred to... Figure 10A As described, the first material layer 511 and the second material layer 513 can be alternately stacked on the first conductive layer 505 to form a stacked structure 510.

[0204] Subsequently, a hole 520 can be formed, which penetrates the first material layer 511, the second material layer 513, the first conductive layer 505 and the first protective layer 503, and extends into the interior of the first substrate 501.

[0205] Reference Figure 18B The first barrier insulation layer 521, the data storage layer 523, and the tunnel insulation layer 525 can be sequentially stacked. Figure 18A On the surface of the hole 520 shown, each of the first barrier insulating layer 521, the data storage layer 523, and the tunnel insulating layer 525 can extend not only along the sidewalls and bottom surface of the hole 520, but also along the top surface of the stacked structure 510.

[0206] Data storage layer 523 may be made of a material that enables data storage and has etch selectivity relative to the first barrier insulating layer 521 and tunnel insulating layer 525, the first barrier insulating layer 521 and tunnel insulating layer 525 may be made of a reference material. Figure 10A Made from the described material.

[0207] Subsequently, the initial channel structure 530P can be used for filling. Figure 18A In the central region of the hole 520 shown, the preliminary channel structure 530P may include a channel layer 531 and a core insulating layer 533. The channel layer 531 may be formed as a semiconductor layer and may extend along the surface of the tunnel insulating layer 525. In an embodiment, the channel layer 531 may include silicon. The core insulating layer 533 may be disposed on the channel layer 531 and may be filled with, for example, silicon. Figure 18A The central region of the hole 520 shown. The core insulating layer 533 can be formed such that... Figure 18A The height at which the upper end of the hole 520 shown is opened.

[0208] After the core insulating layer 533 is formed, the upper end of the hole opened by the core insulating layer 533 can be filled with a doped semiconductor layer 539. The doped semiconductor layer 539 may include a vertical portion 539A that fills the upper end of the hole and a horizontal portion 539B that extends from the vertical portion 539A parallel to the top surface of the stacked structure 510.

[0209] Reference Figure 18C The first groove 540 can be formed, wherein the first groove 540 can penetrate through. Figure 18B The diagram shows a doped semiconductor layer 539, a channel layer 531, a tunnel insulating layer 525, a data storage layer 523, a first barrier insulating layer 521, a first material layer 511, and a second material layer 513. Therefore, a preliminary gate stack structure 510P and a channel structure 530 can be defined.

[0210] The channel structure 530 may include a pillar PP extending through the initial gate stack structure 510P, wherein the pillar PP of the channel structure 530 may include a core insulating layer 533 and a channel layer 531 extending through the initial gate stack structure 510P.

[0211] Figure 18B The doped semiconductor layer 539 shown can be isolated into a common source layer 539S through the first trench 540.

[0212] Reference Figure 18D , as reference Figure 10B As described, the second material layer 513 can be replaced with a conductive pattern 547, wherein at least one conductive pattern in the conductive pattern 547 adjacent to the common source layer 539S can be used as a source select line, while the other conductive patterns can be used as word lines. (See reference...) Figure 10B As described, a second barrier insulating layer 541 may be formed before the conductive pattern 547 is formed.

[0213] Reference Figure 18E It can be filled with gate isolation layer 551 Figure 18D The first trench 540 is shown. The gate isolation layer 551 may be formed of an insulating material.

[0214] Subsequently, a bonding structure can be formed, which can cover the gate isolation layer 551 and the common source layer 539S. The bonding structure can be configured with a first insulating structure 561.

[0215] Reference Figure 18F The system may provide a peripheral circuit structure 590, which may include transistors 585A and 585B, an interconnect structure 589 connected to transistors 585A and 585B, and a second insulating structure 587. Transistors 585A and 585B may be formed in an active region of the second substrate 581 separated by an isolation layer 583. Transistors 585A and 585B and the interconnect structure 589 may be buried in the second insulating structure 587, which may include two or more insulating layers.

[0216] Subsequently, the peripheral circuit structure 590 can be aligned such that the peripheral circuit structure 590 faces the first insulating structure 561. Subsequently, the second insulating structure 587 of the peripheral circuit structure 590 can be joined to the first insulating structure 561.

[0217] Reference Figure 18G It can be removed sequentially. Figure 18F The first substrate 501 and the first protective layer 503 shown in the figure allow the first conductive layer 505 and the first barrier insulating layer 521 to be exposed.

[0218] Reference Figure 18HIt can be done by using a reference Figure 14A and Figure 14B The described process removes a portion of the first barrier insulating layer 521 and a portion of the data storage layer 523. Therefore, a recessed region 605 can be defined between the first conductive layer 505 and the tunnel insulating layer 525.

[0219] Reference Figure 18I It can be done by using a reference Figure 15A and Figure 15B The described process will fill Figure 18H The second conductive layer 611 of the recessed region 605 shown is formed as a sidewall surrounding the tunnel insulating layer 625 between the first conductive layer 505 and the tunnel insulating layer 525.

[0220] Reference Figure 18J It can be done by using a reference Figure 16A and Figure 16B The described process for isolating the top select line involves forming a second trench 641 through the first conductive layer 505. The second trench 641 can define the top select line. In an embodiment, the top select line can be a drain select line 643. Each drain select line 643 can include the first conductive layer 505 separated by the second trench 641 and a second conductive layer 611 between the first conductive layer 505 and the tunnel insulating layer 525.

[0221] According to an embodiment of the present disclosure, the second conductive layer 611 is retained to surround the channel structure 530 between the tunnel insulating layer 525 and the first conductive layer 505, so that a select transistor having a gate all around (GAA) structure can be stably formed.

[0222] Reference Figure 18K The first upper insulating layer 651 can be formed to fill the second trench 641 and can be formed to cover the drain selection line 643, the channel structure 530, and the tunnel insulating layer 525. The first upper insulating layer 651 may include an oxide. The surface of the first upper insulating layer 651 can be planarized by a process such as chemical mechanical polishing (CMP).

[0223] Reference Figure 18L The first contact hole 660 may be formed to penetrate the portion of the first upper insulating layer 651 that overlaps with the gate isolation layer 551, the gate isolation layer 551, the first insulating structure 561, and the second insulating structure 587. The first contact hole 660 may be formed to expose the conductive pattern of the interconnect structure 589, and may expose the conductive pattern of the transistor (e.g., 585B) connected to the page buffer circuit of the interconnect structure 589.

[0224] Subsequently, a first through-hole contact structure 665 can be formed, which can fill the first contact hole 660 and may include a conductive metal barrier layer 661 extending along the surface of the first contact hole 660 and a metal layer 663 filling the central region of the first contact hole 660 opened by the conductive metal barrier layer 661.

[0225] Reference Figure 18M The second upper insulating layer 667 may be formed on the first upper insulating layer 651 and may extend to cover the first through-hole contact structure 665.

[0226] Subsequently, contact holes 670A and 670B can be formed, which can penetrate at least one of the first upper insulating layer 651 and the second upper insulating layer 667, and can include a second contact hole 670A and a third contact hole 670B.

[0227] The second contact hole 670A can penetrate the second upper insulating layer 667 to expose the first through-hole contact structure 665. In addition to the first upper insulating layer 651 and the second upper insulating layer 667, the third contact hole 670B can also penetrate the tunnel insulating layer 525 to expose the trench layer 531.

[0228] Reference Figure 18N It can be achieved by filling with conductive material. Figure 18M Each of the second contact hole 670A and the third contact hole 670B shown is used to form the second through-hole contact structure 675A and the bit line contact structure 675B. In an embodiment, the process of forming the second through-hole contact structure 675A and the bit line contact structure 675B may include: forming a conductive metal barrier layer 671 along the surface of each of the second contact hole 670A and the third contact hole 670B; and filling the central region of each of the second contact hole 670A and the third contact hole 670B opened by the conductive metal barrier layer 617 with a metal layer 673.

[0229] The second through-hole contact structure 675A can be filled. Figure 18M The second contact hole 670A shown is in contact with the first through-hole contact structure 665. The bit line contact structure 675B can be filled. Figure 18M The third contact hole 670B shown can contact the channel layer 531 of the channel structure 530.

[0230] Then, the following can be executed: Figure 8B The described subsequent processes for forming bit lines.

[0231] Figure 19 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0232] Reference Figure 19 The memory system 1100 may include a memory device 1120 and a memory controller 1110.

[0233] The memory device 1120 may include a channel structure, a barrier insulating layer, and a tunnel insulating layer. The channel structure may include a first post and a second post extending from the first post. The barrier insulating layer may surround a sidewall of the first post, a data storage layer is located between the barrier insulating layer and the first post, and a select line overlaps with an end of the data storage layer and an end of the barrier insulating layer facing the extension direction of the second post, the select line surrounding a sidewall of the second post. The tunnel insulating layer may be disposed between the first post and the data storage layer, extending between the select line and the second post.

[0234] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0235] The memory controller 1110 controls the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 can be used as the operating memory of the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110. The host interface 1113 may include a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 can detect and correct errors contained in data read from the memory device 1120. The memory interface 1115 can interface with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) for storing code data, etc., connected to the host interface.

[0236] Figure 20 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0237] Reference Figure 20 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0238] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211. The memory device 1212 may include a channel structure, a barrier insulating layer, and a tunnel insulating layer. The channel structure may include a first post and a second post extending from the first post. The barrier insulating layer may surround a sidewall of the first post, a data storage layer is located between the barrier insulating layer and the first post, and a select line overlaps with the end of the data storage layer and the end of the barrier insulating layer in the direction of extension of the second post, the select line surrounding a sidewall of the second post. The tunnel insulating layer may be disposed between the first post and the data storage layer, and the tunnel insulating layer extends between the select line and the second post.

[0239] In embodiments, this disclosure may provide a semiconductor device having a wafer bonding structure, comprising a select line, a barrier insulating layer, a data storage layer, and a tunnel insulating layer, wherein the select line includes a first conductive pattern and a second conductive pattern, wherein the first conductive pattern surrounds the tunnel insulating layer, and wherein the second conductive pattern overlaps with the ends of the barrier insulating layer and the ends of the data storage layer, and the second conductive pattern is interposed between the first conductive pattern and the tunnel insulating layer.

[0240] According to this disclosure, select lines with a gate-all-around (GAA) structure can be formed. Therefore, the operating characteristics of semiconductor memory devices can be improved.

[0241] Cross-reference to related applications

[0242] This application claims priority to Korean Patent Application No. 10-2020-0134645, filed on October 16, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A channel structure, the channel structure including a first column portion and a second column portion extending from the first column portion; A barrier insulating layer surrounds the sidewall of the first column portion of the trench structure; A data storage layer is disposed between the first pillar portion of the channel structure and the barrier insulating layer; The upper selection line overlaps with the end of the barrier insulating layer and the end of the data storage layer, the end of the barrier insulating layer and the end of the data storage layer face the extension direction of the second column, and the upper selection line surrounds the sidewall of the second column of the channel structure; as well as A tunnel insulation layer is disposed between the first pillar of the trench structure and the data storage layer, and extends between the second pillar of the trench structure and the upper selection line. The semiconductor memory device also includes multiple word lines, and The thickness of the upper selection line is greater than the thickness of each of the multiple character lines.

2. The semiconductor memory device according to claim 1, wherein, The upper selection line includes: A first conductive pattern, the first conductive pattern intersecting the second column portion of the channel structure; and A second conductive pattern is disposed between the first conductive pattern and the tunnel insulation layer, and the second conductive pattern surrounds the sidewall of the tunnel insulation layer.

3. The semiconductor memory device according to claim 2, wherein, The first conductive pattern comprises silicon.

4. The semiconductor memory device according to claim 2, wherein, The second conductive pattern includes at least one of silicon, metal silicide, and conductive metal barrier.

5. The semiconductor memory device according to claim 1, wherein, The second column portion of the channel structure includes: The first part is surrounded by the upper selection line; The second portion extends from the first portion in the extending direction of the second column, protruding further than the upper selection line in the extending direction of the second column; and The third part extends from the second part in the extending direction of the second column.

6. The semiconductor memory device according to claim 5, further comprising: An upper insulating layer is disposed on the upper selection line, and the upper insulating layer surrounds the sidewall of the second portion of the second column. as well as A common source layer is disposed on the upper insulating layer, and the common source layer is in contact with the third portion of the second pillar.

7. The semiconductor memory device according to claim 5, further comprising: An upper insulating layer is disposed on the upper selection line, and the upper insulating layer covers the second portion and the third portion of the second column; The bit line contact structure penetrates the upper insulating layer and contacts the third portion of the second post. as well as Bit lines are disposed on the upper insulating layer and are in contact with bit line contact structures.

8. The semiconductor memory device of claim 1, further comprising: At least one lower selection line, the at least one lower selection line surrounding the first column portion of the channel structure; as well as An interlayer insulating layer and word lines, the interlayer insulating layer and the word lines surrounding the first post portion of the channel structure between the upper select line and the at least one lower select line, wherein the interlayer insulating layer and the word lines are alternately stacked in the extending direction of the second post portion. The barrier insulation layer, the data storage layer, and the tunnel insulation layer extend between the first pillar and each of the interlayer insulation layer, the word line, and the at least one lower select line.

9. The semiconductor memory device of claim 8, further comprising: An external circuit structure, wherein the external circuit structure overlaps with the upper selection line, and at least one lower selection line is inserted between the external circuit structure and the upper selection line.

10. The semiconductor memory device according to claim 9, wherein, The channel structure has a width that increases as it gets closer to the peripheral circuit structure.

11. A semiconductor memory device, the semiconductor memory device comprising: A first channel structure and a second channel structure, the first channel structure and the second channel structure extending parallel to each other; A tunnel insulation layer surrounds the sidewalls of each of the first trench structure and the second trench structure; A data storage layer surrounds the sidewalls of each of the first trench structure and the second trench structure, and the tunnel insulation layer is inserted between the data storage layer and the sidewalls of each of the first trench structure and the second trench structure. A barrier insulating layer surrounds the sidewalls of each of the first trench structure and the second trench structure, and the data storage layer and the tunnel insulating layer are interposed between the barrier insulating layer and the sidewalls of each of the first trench structure and the second trench structure. A first lower selection line surrounds the first trench structure, and the barrier insulation layer, the data storage layer, and the tunnel insulation layer are interposed between the first lower selection line and the first trench structure. The second lower selection line surrounds the second trench structure, and the barrier insulation layer, the data storage layer, and the tunnel insulation layer are inserted between the second lower selection line and the second trench structure; An isolation layer is disposed between the first lower selection line and the second lower selection line; A first upper selection line surrounds the first trench structure, and the tunnel insulation layer is inserted between the first upper selection line and the first trench structure. The first upper selection line is disposed on the first lower selection line. The second upper selection line surrounds the second trench structure, and the tunnel insulation layer is inserted between the second upper selection line and the second trench structure. The second upper selection line is disposed on the second lower selection line. as well as An interlayer insulating layer and word lines are alternately stacked between the first lower select line and the first upper select line, wherein the interlayer insulating layer and the word lines extend between the second lower select line and the second upper select line. Wherein, the tunnel insulation layer surrounding the first trench structure is in contact with the first upper selection line, and The tunnel insulation layer surrounding the second trench structure is in contact with the second upper selection line.

12. The semiconductor memory device according to claim 11, wherein, Each of the first and second upper selection lines includes: A first conductive pattern, the first conductive pattern extending parallel to the letter lines; and A second conductive pattern is disposed between the first conductive pattern and the tunnel insulation layer, and the second conductive pattern surrounds the sidewall of the tunnel insulation layer.

13. The semiconductor memory device according to claim 12, wherein, The second conductive pattern overlaps with the ends of the barrier insulating layer and the ends of the data storage layer.

14. The semiconductor memory device according to claim 12, wherein, The first conductive pattern comprises silicon.

15. The semiconductor memory device according to claim 12, wherein, The second conductive pattern includes at least one of silicon, metal silicide, and conductive metal barrier.

16. The semiconductor memory device of claim 11, further comprising: An insulating layer is disposed between the first upper selection line and the second upper selection line, and the insulating layer overlaps with the isolation layer.

17. The semiconductor memory device of claim 11, further comprising: The peripheral circuit structure overlaps with the first upper selection line and the second upper selection line. The first lower selection line is inserted between the peripheral circuit structure and the first upper selection line, and The second lower selection line is inserted between the peripheral circuit structure and the second upper selection line.

18. The semiconductor memory device according to claim 17, wherein, Each of the first channel structure and the second channel structure has a width that increases as the first channel structure and the second channel structure are closer to the peripheral circuit structure.

19. A semiconductor device having a wafer bonding structure, the semiconductor device comprising: Selection line, the selection line including a first conductive pattern and a second conductive pattern; A barrier insulating layer and a data storage layer, wherein the second conductive pattern of the selection line overlaps with the ends of the barrier insulating layer and the ends of the data storage layer; and A tunnel insulation layer, the tunnel insulation layer being surrounded by a first conductive pattern of the selection line, wherein a second conductive pattern of the selection line is interposed between the first conductive pattern and the tunnel insulation layer.

20. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A first conductive layer is formed on the substrate; A first material layer and a second material layer are alternately stacked on the first conductive layer; A hole is formed that penetrates the first material layer and the second material layer, the hole extending into the interior of the substrate; A barrier insulation layer, a data storage layer, and a tunnel insulation layer are sequentially stacked on the surface of the hole; A trench structure is formed on the tunnel insulation layer to fill the central region of the hole; Remove the substrate to expose the first conductive layer and the barrier insulating layer; Sequentially remove a portion of the barrier insulating layer and a portion of the data storage layer to define a recessed region between the first conductive layer and the tunnel insulating layer; as well as A second conductive layer is formed to fill the recessed area, and the second conductive layer surrounds the tunnel insulation layer.

21. The method of claim 20, further comprising the step of: A portion of the second conductive layer is removed, such that the tunnel insulating layer and the first conductive layer are exposed, while the second conductive layer remains inside the recessed region; A trench is formed that penetrates the first conductive layer, thereby defining an upper selection line around the trench structure; as well as An upper insulating layer is formed to fill the trench, the upper insulating layer covering the upper selection line and the tunnel insulating layer.

22. The method of claim 21, further comprising the step of: A portion of the upper insulating layer and a portion of the tunnel insulating layer are removed, thereby exposing a portion of the trench structure; as well as A common source layer is formed on the upper insulating layer, which is in contact with the exposed portion of the channel structure.

23. The method of claim 21, further comprising the step of: A bit line contact structure is formed, which penetrates the upper insulating layer and the tunnel insulating layer to contact the trench structure; as well as A bit line is formed on the upper insulating layer to contact the bit line contact structure.

24. The method of claim 20, further comprising the step of: Before forming the first conductive layer, a protective layer is formed on the substrate, the protective layer having etch selectivity relative to the substrate; as well as After removing the substrate, the protective layer is removed.

25. The method of claim 20, further comprising the step of: After the channel structure is formed, the second material layer is replaced with a conductive pattern.

26. The method of claim 25, further comprising the step of: Before removing the substrate, at least one of the conductive patterns is isolated as a lower selection line.

27. The method of claim 20, further comprising the step of: Before removing the substrate, a bonding structure is formed on the channel structure; The peripheral circuit structure is configured to face the junction structure; and The peripheral circuit structure is bonded to the bonding structure.

28. The method according to claim 20, wherein, The first conductive layer comprises silicon.

29. The method according to claim 20, wherein, The second conductive layer includes at least one of silicon, metal silicide, and conductive metal barrier.

Images