Vertical field effect transistor and method for constructing a vertical field effect transistor
By introducing a shielding structure into the gallium nitride vertical field-effect transistor, the electrical breakdown problem was solved, the reliability and voltage withstand capability of the device were improved, and the potential utilization was enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ROBERT BOSCH GMBH
- Filing Date
- 2020-07-01
- Publication Date
- 2026-06-16
AI Technical Summary
Existing gallium nitride-based vertical field-effect transistors are prone to premature electrical breakdown under high electric fields, causing voltage to punch through to the gate and affecting device reliability.
A shielding structure is introduced into the drift region of the transistor. The shielding structure has a different conductivity type than the drift region and extends laterally and vertically to the trench structure or further away, forming a space charge region to prevent the electric field from concentrating at the bottom of the trench, increasing resistance and preventing electrical breakdown.
It effectively prevents electrical breakdown, improves the reliability and voltage withstand capability of transistors, enhances the potential utilization of devices, and reduces the risk of premature electrical breakdown.
Smart Images
Figure CN114375499B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a vertical field-effect transistor and a method for constructing the same. Background Technology
[0002] Compared to similar components based on silicon or silicon carbide, gallium nitride (GaN)-based transistors offer the possibility of achieving components with both higher breakdown voltages and lower on-resistance. Related technologies, in Figure 1 The transistor 10 shown is possibly structured as a so-called vertical HEMT (high-electron-mobility transistor), in which the channel is constructed via a two-dimensional electron gas (2DEG) at the interface of an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) heterostructure. This heterostructure is constructed, for example, by growth in a V-shaped trench. The transistor 10 has a conductive GaN substrate 11 on which a weakly n-type conductive GaN drift region 12 is applied. A p-type conductive GaN region 15 is located above the drift region 12 and has an insulating GaN or AlGaN region 16 thereon. The two regions 15 and 16 are penetrated by a V-shaped trench, over which an undoped or intrinsic GaN region 17 and an AlGaN region 21 extend. A 2DEG is generated in region 17 at the interface of the two regions 17 and 21. A p-type conductive GaN region 31 is introduced into a V-shaped trench to ensure normally-off operation of the component. The gate electrode 32 contacts the p-type GaN region 31. The source electrode 51 contacts not only the 2DEG but also the p-region 15. An insulator 41 separates the source electrode 51 and the gate electrode 32. The drain electrode 52 is located on the back side of the substrate 11. Without an applied gate voltage, the transistor 10 is normally-locked because the 2DEG below region 31 is depleted. By applying a positive voltage to the gate electrode 32, the entire 2DEG is filled with electrons, and these electrons flow from the source electrode 51 through the sidewalls of the trench to the bottom of the trench and from there to the drift region 12, through the substrate 11, and to the drain electrode 52.
[0003] During off-state operation, transistor 10 has a high electric field at the bottom of the trench. As a result, there is a risk that the voltage applied to the drain electrode 52 will prematurely break down transistor 10 and then pass through to the gates 31 and 32. Summary of the Invention
[0004] The objective of this invention is to provide a vertical field-effect transistor and a method for manufacturing it, wherein the vertical field-effect transistor / method addresses one or more of the aforementioned problems.
[0005] According to one aspect of the invention, this task is accomplished by a vertical field-effect transistor (VFET). The VFET comprises: a drift region having a first conductivity type; a trench structure above or above the drift region, wherein the trench structure has at least one sidewall on which a field-effect transistor (FET) channel region is formed, wherein the FET channel region has a III-V heterostructure for forming a two-dimensional electron gas at the interface of a III-V heterostructure; and a shielding structure laterally disposed beside at least one sidewall of the trench structure and extending vertically into the drift region, or extending vertically further than the trench structure in the direction of the drift region, wherein the shielding structure has a second conductivity type different from the first conductivity type; and source / drain electrodes electrically connected to the III-V heterostructure of the trench structure and the shielding structure.
[0006] The shielding structure provides shielding for the bottom of the trench structure relative to the electric field. This allows for full utilization of the transistor's potential. For example, it prevents premature electrical breakdown of the transistor, or the voltage applied to the drain electrode, from passing through to the gate.
[0007] According to another aspect of the invention, this task is accomplished by a method for constructing a vertical field-effect transistor. The method comprises: constructing a drift region having a first conductivity type; constructing a trench structure on or above the drift region, wherein the trench structure has at least one sidewall, on which a field-effect transistor (FET) channel region is constructed, wherein the FET channel region has a III-V heterostructure for constructing a two-dimensional electron gas at an interface of a III-V heterostructure; constructing a shielding structure laterally disposed next to at least one sidewall of the trench structure and extending vertically into the drift region, or extending further than the trench structure in a direction perpendicular to the drift region, wherein the shielding structure has a second conductivity type different from the first conductivity type; and constructing source / drain electrodes electrically connected to the III-V heterostructure of the trench structure and the shielding structure. Attached Figure Description
[0008] Extensions to the described aspects are explained in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and described in more detail below. The drawings show:
[0009] Figure 1 A cross-sectional view of a transistor structure related to this technology is shown.
[0010] Figure 2A , 2BViews 2C and 2D show vertical field-effect transistors according to different implementations;
[0011] Figure 3A and 3B Views of vertical field-effect transistors according to different embodiments are shown;
[0012] Figure 4A , 4B Views of vertical field-effect transistors according to different implementations are shown in Figures 4 and 4C.
[0013] Figure 5A , 5B Views of vertical field-effect transistors according to different embodiments are shown in figures 5C and 5C;
[0014] Figure 6A and 6B Views of vertical field-effect transistors according to different embodiments; and
[0015] Figure 7 A flowchart illustrating a method for constructing a vertical field-effect transistor according to different embodiments is shown. Detailed Implementation
[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification and illustrate specific embodiments in which the invention can be practiced. It will be understood that other embodiments can be used and structural or logical changes can be made without departing from the scope of the invention. It will be understood that features of the different embodiments described herein can be combined with each other unless specifically stated otherwise. Therefore, the following detailed description should not be construed as limiting, and the scope of the invention is defined by the appended claims. In the drawings, the same or similar elements are given the same reference numerals, provided that this is for the purpose.
[0017] Figures 2A to 6B Views of a vertical field-effect transistor 100 according to different embodiments are shown. In various embodiments, the vertical field-effect transistor 100 includes: a drift region 112; a trench structure 102 on or above the drift region 112; shielding structures 118, 119; a first source / drain electrode (e.g., source electrode) 151; a second source / drain electrode (e.g., drain electrode) 152; and a gate trench (which extends in the drawing plane and is also referred to as a trench structure, as shown in...). Figure 4C and Figure 5A(As shown in the top view). Hereinafter, it is exemplarily assumed that: the first source / drain electrode 151 is the source electrode, and the second source / drain electrode 152 is the drain electrode. The drift region 112 has a first conductivity type, and the shielding structures 118, 119 have a second conductivity type different from the first conductivity type. The trench structure 102 has at least one sidewall on which a field-effect transistor (FET) channel region is constructed, wherein the FET channel region has III-V heterostructures 117, 121 for constructing a two-dimensional electron gas (2DEG) at the interface of the III-V heterostructure. The shielding structures 118, 119 are arranged laterally next to at least one sidewall of the trench structure 102 and extend vertically into the drift region 112, or extend vertically in the direction of the drift region 112 further than the trench structure 102. The source electrode 151 is electrically connected to the III-V heterostructure of the trench structure 102 and the shielding structures 118, 119. For example, the source electrode 151 is formed of metal or metal alloy, and the shielding structures 118 and 119 are formed of doped semiconductor material.
[0018] Region 119 of the shielding structures 118 and 119 has a higher doping concentration than the drift region 112. The bottom 101 of the shielding trench structure 102 is achieved by introducing the shielding region 119, for example, in the form of a highly doped p-type GaN region, into the drift region 112. During operation, a space charge region can be constructed between region 119 of the shielding structures 118 and 119 and the drift region 112. This reduces the area in which current can flow, thereby increasing resistance. By introducing the shielding structures 118 and 119, a variation without a shielding structure (…) Figure 1 Compared to the previous case, this increases the total resistance of the field-effect transistor 100. The potential applied to the drain electrode 152 in the off state results in an electric field that has its maximum value directly below the shielding structures 118, 119, rather than as it would be without the shielding structures 118, 119 (see [reference]). Figure 1 This results in the maximum value being located at the bottom 101 of the trench structure 102. This, for example, prevents premature electrical breakdown of the field-effect transistor 100, or the voltage applied to the drain electrode 152, from passing through to the gate electrode 132.
[0019] The field-effect transistor 100 may further have a conductive GaN substrate 111 on which a weakly n-type conductive GaN drift region 112 is applied. A p-type conductive GaN region 115 and an insulating GaN or AlGaN region 116 can be constructed on the drift region 112. Both regions 115 and 116 are penetrated by a V-shaped trench, through which undoped or intrinsic GaN regions 117 and AlGaN regions 121 can extend. A 2DEG can be generated in region 117 at the interface of the two regions 117 and 121. A p-type conductive GaN region 131 can be introduced into the V-shaped trench to ensure normally-off operation of the field-effect transistor 100. The gate electrode 132 can contact the p-type GaN region 131. The source electrode 151 can contact not only the 2DEG but also the p-type region 115. Insulator 141 electrically insulates the source electrode 151 and gate electrode 132 from each other. Drain electrode 152 can be located on the back side of substrate 111. The field-effect transistor 100 can be latched without an applied gate voltage because the 2DEG below region 131 can be depleted. By applying a positive voltage to gate electrode 132, the entire 2DEG can be filled with electrons, and these electrons can flow from source electrode 151 through the sidewalls of trench structure 102 to the bottom 101 of trench structure 102 and from there into drift region 112, through substrate 111, and into drain electrode 152.
[0020] In another embodiment, the shielding structures 118 and 119 can also be constructed directly below the p-type conductive region 115, such as in... Figure 2B As shown in the diagram, shielding structures 118 and 119 can have additional highly doped p-type conductive regions 118 that connect regions 119 of shielding structures 118 and 119 to the source electrode 151. This achieves better electrical connection.
[0021] Furthermore, the shielding structures 118 and 119 can be configured such that they have the same lateral extension as the source electrode 151 (as shown in...). Figure 2C (as shown in the diagram), or alternatively, they can be configured such that they have a smaller lateral extension compared to the extension of the source electrode 151, as shown in the diagram. Figure 2D As shown in the figure. Variations in the lateral extension of shielding structures 118 and 119 provide the possibility of optimizing the components in terms of shielding (which can be improved as the lateral extension increases) or on-state resistance (which can be reduced as the lateral extension decreases).
[0022] In various embodiments, at least one highly doped n-type GaN region 122 can be constructed, which connects the source electrode 151 to the 2DEG, as in... Figure 2D As shown in the diagram. This enables an improved connection between the 2DEG and the source electrode 151.
[0023] In various embodiments, the p-type GaN shielding structure 113 can be constructed below, above, and / or within the drift region 112 of the trench structure 102, beneath, or in relation to the p-type conductive region 115. For example, in various embodiments, the GaN region 113 can be constructed between the drift region 112 and the bottom 101 of the trench structure 102, as in... Figure 3A As shown in the diagram, the GaN region 113 can be constructed, for example, alongside at least a portion of the shielding structures 118, 119, such as in a common layer plane. The GaN region 113 can be constructed, for example, to have higher n-type conductivity than the drift region 112. This results in a reduction in the extension of the space charge region, thereby reducing the increase in resistance.
[0024] In different embodiments, shielding structures 118, 119 are constructed on each side of the trench structure 102, such as in Figures 2A to 3A As shown in the diagram. In this case, the shielding structure 113 can be constructed between the two shielding regions 119 and / or between the two shielding regions 118. In different embodiments, additional shielding structures can be constructed to further improve the shielding effect. For example, a p-type conductive region 120 can be provided as a shielding structure below the bottom 101 of the trench structure 102, as shown in the diagram. Figure 3B As shown in the figure. This achieves maximum shielding of the bottom 101 of the trench structure 102 relative to the electric field.
[0025] In different embodiments, effective shielding of the bottom 101 of the trench structure 102 is achieved by the following method: shielding structures 118, 119 (e.g., shielding area 119 of the shielding structure) extend below the bottom of the trench structure, such as in Figure 4A As shown in the diagram (left shielding region 119). In another embodiment, this can also be achieved using shielding structures 118, 119, which are adjacent to, for example, the bottom 101 of the trench structure 102, contacting that bottom. In this case, in Figure 4B The FET channel constructed on the left side wall of the trench structure is no longer conductive because there is no continuous current path from the left source electrode 151 to the drain electrode 152. In different embodiments, the shielding region 119 can be alternately arranged on the right and left sides of the trench structure, as in... Figure 4C As shown in the top view. This is achieved, in Figure 4BElectrons located on the left side wall flow at this depth into the adjacent cell, and then flow out vertically from that cell to the drain electrode 152. Thus, the entire FET channel is able to contribute to the current flow.
[0026] In another embodiment, the lateral structure of the shielding region 119 can be decoupled from the structure of the unit located thereon, such as in Figure 5A , 5B As shown in 5C. For example, the shielding region 119 can be implemented as a continuous strip structure that extends in a direction perpendicular to the direction in which the gate trench extends, as in Figure 5A and Figure 5B As shown in the diagram, the following elements do not contribute to current flow or essentially no longer do: in said element, the shielding region 119 is constructed as a continuous strip structure below the bottom of the trench structure ( Figure 5B The strip-shaped shielding area 119 can also shield units in which no shielding area 119 is constructed below the bottom of the trench structure. Figure 5C This allows the photolithography of the trench structure 102 and the shielding region 119 to be, for example, not necessarily oriented relative to each other. This simplifies the fabrication of the field-effect transistor 100.
[0027] In other words, in different embodiments, additional trench structures can be provided, which are offset relative to trench structure 102 in the plane, so that source electrode 151 is arranged between trench structure 102 and additional trench structures. Here, shielding structures 118, 119 can have additional regions 119 arranged in drift region 112, which extend laterally at least below a portion of the bottom of the additional trench structure. The regions 119 of shielding structures 118, 119 arranged in drift region 112 and the additional regions 119 of shielding structures 118, 119 arranged in drift region 112 can be arranged offset from each other in the trench direction. The trench direction is, for example, the elongated (e.g., longest or linear) extension direction of trench structure 102.
[0028] The lateral extension direction of the shielding structure 119 can be selected to be at any angle relative to the extension direction of the gate trench. In addition to the linear implementation of the gate trench and the shielding structure, both can also be constructed in a grid pattern (e.g., hexagonal), as in... Figure 6A and Figure 6B As shown in the image. Figure 6A An embodiment with hexagonal gate trenches and strip-shaped shielding regions 119 is shown. Figure 6BOne embodiment is shown in which the gate trench has a hexagonal pattern. The shielding region 119 can be constructed, for example, at every second base point of the hexagonal grid. In other embodiments, other grid patterns, such as herringbone or three-dimensional grids, can be provided for the gate trench and / or shielding structure.
[0029] In various embodiments, the trench structure 102 can have at least one sidewall with a FET channel, the sidewall forming an angle with the substrate 111. For example, the sidewall of the trench structure 102 can form an angle with the upper side of the substrate 111, wherein the angle can be greater than 0° and less than 90°. The III-V heterostructures 117, 121 can have an AlGaN layer 121 and a GaN layer 117 adjacent to the AlGaN layer 121. Thus, the FET channel can have an aluminum gallium nitride (AlGaN) region and a gallium nitride (GaN) region.
[0030] The drift region 112 can also be referred to as the drift region 112 of the vertical field-effect transistor 100. The drift region 112 can have, for example, an n-type conductive GaN region 112, such as n-type doped GaN. The drift region 112 can be constructed on or above the semiconductor substrate 111, such as the GaN substrate 111. The shielding structures 118 and 119 can have, for example, at least one p-type conductive GaN region 118 or 119, where the doping concentration of the p-type conductive GaN region can be higher than the doping concentration of the drift region 112. For example, the drift region 112 can have n-type doped GaN, and the shielding structures 118 and 119 can have p++ doped GaN. The shielding structures 118 and 119 can have p++ GaN regions and are provided to laterally surround the bottom 101 of the trench structure 102. The vertical field-effect transistor 100 can have a p-type conductive GaN region 115 laterally surrounding the bottom 101 of the trench structure 102. The shielding structures 118 and 119 can extend at least partially below the p-type conductive GaN region 115. The shielding structures 118 and 119 can extend through the p-type conductive GaN region 115 into the n-type conductive GaN region 112.
[0031] In various embodiments, a region 113 having a first conductivity type can be constructed at least below the trench structure 102 in the drift region 112. Alternatively or additionally, region 113 can have a higher dopant concentration than the drift region 112. The region 113, at least below the trench structure 102, can be adjacent to, for example, conductively connected to, the shielding structures 118, 119. In various embodiments, an additional shielding structure 120 can be provided. The additional shielding structure 120 can be arranged in the region 113, at least below the trench structure 102. The additional shielding structure 120 can have a second conductivity type. The additional shielding structure 120 can be at least partially arranged below the trench structure 102. In various embodiments, the additional shielding structure 120 can be separated from the shielding structures 118, 119 by the region 113, at least below the trench structure 102.
[0032] Figure 7 A flowchart of a method 700 for constructing a vertical field-effect transistor 100 according to different embodiments is shown. Method 700 includes: constructing a drift region 710 having a first conductivity type; constructing a trench structure 720 above or on the drift region, wherein the trench structure has at least one sidewall, on which a field-effect transistor (FET) channel region is constructed, wherein the FET channel region has a III-V heterostructure for constructing a two-dimensional electron gas at an interface of a III-V heterostructure; constructing a shielding structure 730 laterally arranged next to at least one sidewall of the trench structure and extending vertically into the drift region, or extending vertically further than the trench structure in the direction of the drift region, wherein the shielding structure has a second conductivity type different from the first conductivity type; and constructing source / drain electrodes electrically connected to the III-V heterostructure of the trench structure and the shielding structure.
[0033] The trench structure can be constructed on or above the semiconductor substrate. The trench structure can have a bottom. A drift region is constructed between the bottom of the trench structure and the semiconductor substrate. A shielding structure can be constructed between the trench structure and the drift region. The shielding structure can be indirectly, for example, electrically connected to the trench structure via a source electrode. Obviously, the shielding structure can extend beyond the bottom of the trench structure in the direction of the semiconductor substrate. In different embodiments, the region between the bottom of the trench structure and the semiconductor substrate can remain unshielded.
[0034] The embodiments described and shown in the accompanying drawings are selected only by way of example. Different embodiments can be combined with each other completely or with respect to various features. One embodiment can also be supplemented by features of another embodiment. Furthermore, the described method steps can be performed repeatedly and in a different order than those described. In particular, the invention is not limited to the methods given.
Claims
1. A vertical field-effect transistor (100), said vertical field-effect transistor having: Drift region (112) having a first conductivity type; The groove structure (102) above or above the drift region (112), wherein, The trench structure (102) has at least one sidewall on which a field-effect transistor channel region is constructed, wherein the field-effect transistor channel region has a III-V heterostructure (117, 121), the III-V heterostructure being used to construct a two-dimensional electron gas at the interface of the III-V heterostructure (117, 121); and A shielding structure (118, 119) is arranged laterally next to at least one sidewall of the trench structure (102) and extends vertically into the drift region (112), or extends vertically beyond the trench structure (102) in the direction of the drift region (112), wherein the shielding structure (118, 119) has a second conductivity type different from the first conductivity type; and The source / drain electrode (151) is electrically connected to the III-V heterostructure (117, 121) and the shielding structure (118, 119) of the trench structure (102). (I) wherein the shielding structure (118, 119) has a region (119) arranged in the drift region (112), the region arranged in the drift region extending laterally in the direction of the trench structure (102), wherein the region (119) of the shielding structure (118, 119) arranged in the drift region (112) extends at least below a portion of the bottom (101) of the trench structure (102). (a) wherein the shielding structure (118, 119) further comprises: The region (118) extending vertically between the source / drain electrode (151) and the region (119) extending laterally in the shielding structure (118, 119), and / or (b) The vertical field-effect transistor further has: An additional trench structure, offset in a plane relative to the trench structure (102), such that the source / drain electrode (151) is arranged between the trench structure (102) and the additional trench structure, wherein the shielding structure (118, 119) has an additional region (119) arranged in the drift region (112), the additional region arranged in the drift region extending laterally at least below a portion of the bottom of the additional trench structure. Wherein, the region (119) of the shielding structure (118, 119) arranged in the drift region (112) and the additional region of the shielding structure (118, 119) arranged in the drift region (112) are arranged offset from each other in the trench direction, and / or (II) The vertical field-effect transistor further comprises: A region (113) is constructed at least below the trench structure (102) in the drift region (112), the region constructed at least below the trench structure in the drift region having the first conductivity type and having a higher dopant concentration than the drift region (112); The region (113) at least constructed below the trench structure (102) is adjacent to the shielding structure (118, 119). The vertical field-effect transistor also has: An additional shielding structure (120) is arranged in the region (113) at least below the trench structure (102) and has the second conductivity type, wherein the additional shielding structure (120) is at least partially arranged below the trench structure (102) and separated from the shielding structure (118, 119) by the region (113) at least below the trench structure (102).
2. The vertical field-effect transistor (100) according to claim 1. in, The III-V heterostructure (117, 121) has an AlGaN layer (121) and a GaN layer (117) adjacent to the AlGaN layer (121).
3. The vertical field-effect transistor (100) according to claim 2. in, The drift region (112) is n-type conductive, and the shielding structure (118, 119) has at least one p-type conductive GaN region (118) with a higher doping concentration than the drift region (112).
4. A method for constructing a vertical field-effect transistor (100), the method comprising: Construct a drift region (112) with a first conductivity type; A groove structure (102) is constructed on or above the drift region (112), wherein, The trench structure (102) has at least one sidewall on which a field-effect transistor channel region is constructed, wherein the field-effect transistor channel region has a III-V heterostructure (117, 121), the III-V heterostructure being used to construct a two-dimensional electron gas at the interface of the III-V heterostructure (117, 121). A shielding structure (118, 119) is constructed, the shielding structure being arranged laterally next to at least one sidewall of the trench structure (102) and extending vertically into the drift region (112), or extending vertically beyond the trench structure (102) in the direction of the drift region (112), wherein the shielding structure (118, 119) has a second conductivity type different from the first conductivity type; and A source / drain electrode (151) is constructed, which is electrically connected to the III-V heterostructure (117, 121) and the shielding structure (118, 119) of the trench structure (102). (I) wherein the shielding structure (118, 119) has a region (119) arranged in the drift region (112), the region arranged in the drift region extending laterally in the direction of the trench structure (102), wherein the region (119) of the shielding structure (118, 119) arranged in the drift region (112) extends at least below a portion of the bottom (101) of the trench structure (102). (a) wherein the shielding structure (118, 119) further comprises: The region (118) extending vertically between the source / drain electrode (151) and the region (119) extending laterally in the shielding structure (118, 119), and / or (b) The method further has the following characteristics: An additional trench structure is constructed, which is offset in a plane relative to the trench structure (102), such that the source / drain electrode (151) is arranged between the trench structure (102) and the additional trench structure, wherein the shielding structure (118, 119) has an additional region (119) arranged in the drift region (112), the additional region arranged in the drift region extending laterally at least below a portion of the bottom of the additional trench structure. Wherein, the region (119) of the shielding structure (118, 119) arranged in the drift region (112) and the additional region of the shielding structure (118, 119) arranged in the drift region (112) are arranged offset from each other in the trench direction, and / or (II) The method further comprises: A region (113) is constructed in the drift region (112) at least below the trench structure (102), and the region constructed in the drift region at least below the trench structure has the first conductivity type and has a higher dopant concentration than the drift region (112); The region (113) at least constructed below the trench structure (102) is adjacent to the shielding structure (118, 119). The method also has the following characteristics: An additional shielding structure (120) is constructed, which is arranged in the region (113) at least below the trench structure (102) and has the second conductivity type, wherein the additional shielding structure (120) is at least partially arranged below the trench structure (102) and separated from the shielding structure (118, 119) by the region (113) at least below the trench structure (102).
5. The method according to claim 4, in, The III-V heterostructure (117, 121) has an AlGaN layer (121) and a GaN layer (117) adjacent to the AlGaN layer (121).
6. The method according to claim 5, in, The drift region (112) is n-type conductive, and the shielding structure (118, 119) has at least one p-type conductive GaN region (118) with a higher doping concentration than the drift region (112).