Active y-capacitor control options for common mode electromagnetic interference (EMI) reduction

Abstract

A system includes an input voltage source (102) and a switching converter coupled to the input voltage source (102). The switching converter includes a transformer (T2) having a primary winding and a secondary winding. The switching converter also includes a Y-capacitor (C7) having a top plate and a bottom plate, wherein the top plate is coupled to a first end of the secondary winding. The switching converter also includes a push-pull current source (301) coupled to the bottom plate of the Y-capacitor (301). The switching converter also includes a controller (401) coupled to the push-pull current source (301).

Description

Background Technology

[0001] Power supplies and converters are used in a wide variety of electronic systems. Electricity is typically transmitted over long distances as an alternating current (AC) signal. AC signals are distributed and metered according to the needs of each business or home location and are usually converted to direct current (DC) for use by individual electronic devices or components. Battery-powered devices are also common. Modern electronic systems often employ devices or components designed to operate using different DC voltages. Therefore, such systems require different switching converters (AC-DC converters and / or DC-DC converters).

[0002] Many different switching converter topologies exist. Available topologies vary in the components used, the amount of power handled, one or more input voltages, one or more output voltages, efficiency, reliability, size, and / or other characteristics. One example switching converter is called a flyback converter. One of the existing challenges of flyback converters is the difficulty in meeting the common-mode electromagnetic interference (EMI) specifications for offline flyback converters, despite large common-mode chokes. The presence of parasitic capacitance across the transformer boundary makes this problem difficult to address. Efforts to improve switching converter designs, such as overcoming the aforementioned EMI issues, are ongoing. Summary of the Invention

[0003] In this example, the system includes an input voltage source and a switching converter coupled to the input voltage source. The switching converter includes a transformer having a primary winding and a secondary winding. The switching converter also includes a Y-stage capacitor having a top plate and a bottom plate, wherein the top plate is coupled to a first terminal of the secondary winding. The switching converter further includes a push-pull current source coupled to the bottom plate of the Y-stage capacitor. The switching converter also includes a controller coupled to the push-pull current source.

[0004] In the example, the switching converter circuit includes a first Y-stage capacitor node and a push-pull current source coupled to the first Y-stage capacitor node. The switching converter circuit further includes a controller coupled to the push-pull current source. The controller includes a sample-and-hold circuit coupled to a second Y-stage capacitor node. The controller also includes an integrator circuit coupled to the sample-and-hold circuit.

[0005] In the example, the integrated circuit includes a first Y-stage capacitor node and a second Y-stage capacitor node. The integrated circuit also includes a push-pull current source coupled to the first Y-stage capacitor node. The integrated circuit also includes a controller coupled to the push-pull current source, wherein the controller is configured to monitor voltage changes at the second Y-stage capacitor node and selectively push current into or pull current out of the first Y-stage capacitor node. Attached Figure Description

[0006] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 This is a schematic diagram showing a switch converter in some examples;

[0008] Figure 2 This is a schematic diagram illustrating another switching converter in some examples;

[0009] Figure 3A This is a schematic diagram illustrating another switch converter in a pull operation scenario in some examples;

[0010] Figure 3B This is shown in some examples of push operation scenarios. Figure 3A A schematic diagram of a switching converter;

[0011] Figure 4 This is a schematic diagram illustrating another switching converter in some examples;

[0012] Figures 5A-5D This is a timing diagram showing waveforms associated with a switching converter in some examples;

[0013] Figure 6A This is a schematic diagram illustrating another switching converter in some examples;

[0014] Figure 6B It is in some examples Figure 6A Timing diagrams related to the switching converter;

[0015] Figure 7 This is a schematic diagram illustrating another switching converter in some examples;

[0016] Figure 8A-1 and Figure 8A-2 This is a schematic diagram illustrating another switching converter in some examples;

[0017] Figure 8B These are timing diagrams related to the switch converter in Figure 8A of some examples; and

[0018] Figure 9A and Figure 9B This is a schematic diagram illustrating another switch converter in some examples. Detailed Implementation

[0019] This document describes control options for active Y-class capacitors for common-mode electromagnetic interference (EMI) reduction. As used herein, a Y-class capacitor refers to a capacitor that meets safety standards (e.g., a fault results in an open circuit rather than a short circuit) to prevent electric shock hazards. Example Y-class capacitor standards include UL 1414 and UL 1283. In some examples, the described active Y-class capacitor control options are used in switching converters. In one example, the switching converter includes a transformer with a primary winding and a secondary winding. The switching converter also includes a Y-class capacitor with a top plate and a bottom plate, wherein the top plate is coupled to a first end of the secondary winding. The switching converter also includes a push-pull current source coupled to the bottom plate of the Y-class capacitor. The switching converter also includes a controller coupled to the push-pull current source, wherein the controller provides at least some of the control options described herein. One control option includes selectively pushing current to the bottom plate of the Y-class capacitor. Another control option includes selectively pulling current from the bottom plate of the Y-class capacitor. In some examples, the active Y-stage capacitor control option is combined with other switching converter options, such as discontinuous conduction mode (DCM) circuitry (e.g., with DCM amplifiers and / or DCM clamps).

[0020] The switching converter described herein has various operating modes. When the required output power is higher than a predetermined level, the converter operates in continuous mode, where pulse width modulation (PWM) operation responds to the continuous application of the switching converter's output voltage. A second operating mode utilized at lower output power levels is "burst mode," where PWM operation responds to the switching converter's output voltage being turned on and off. As used herein, burst mode operation includes PWM ON mode and PWM OFF mode. To provide a better understanding, the various switching converter options are described below using accompanying figures.

[0021] Figure 1 This is a schematic diagram illustrating a switching converter 100 in some examples. The switching converter 100 is an example of an offline flyback converter. As shown, the switching converter 100 includes an AC source 102, a first terminal 103A of which is coupled via a circuit including L1, C1, and R1 to a first winding of a common-mode choke (T1) having subtractive polarity (indicated by the point on the same side of the winding of T1). More specifically, a first terminal of L1 is coupled to the first terminal 103A of the AC source 102, while a second terminal of L1 is coupled to the first winding of T1. The first winding of T1 is also coupled to the top plate of C1. As shown, the bottom plate of C1 is coupled to the first terminal of R1, while the second terminal of R1 is coupled to a ground node 110.

[0022] exist Figure 1In the example, the second terminal 103B of AC source 102 is coupled to the second winding of T1 via a circuit including L2, C2, and R2. More specifically, the first terminal of L2 is coupled to the second terminal 103B of AC source 102, while the second terminal of L2 is coupled to the second winding of T1. The second winding of T1 is also coupled to the top plate of C2. As shown, the bottom plate of C2 is coupled to the first terminal of R2, while the second terminal of R2 is coupled to ground node 110.

[0023] exist Figure 1 In the example, the output of T1 is rectified by a set of diodes D1-D4. More specifically, the anode of D1 and the cathode of D3 are coupled to the first winding of T1. Furthermore, the anode of D2 and the cathode of D4 are coupled to the second winding of T1. Additionally, the cathodes of D1 and D2 are coupled to the top plate of capacitor (C3) and the first terminal of inductor (L3). Furthermore, the anodes of D3 and D4 are coupled to the bottom plate of C3 and the primary (local) ground node 108. As shown, the second terminal of L3 is coupled to the top plate of another capacitor (C4) and the first winding of transformer (T2) having additive polarity (indicated by the points on opposite sides of the windings of T2). Furthermore, the bottom plate of C4 is coupled to the primary ground node 108. Meanwhile, the second winding of T2 has a first terminal coupled to the anode of diode (D5) and a second terminal coupled to the secondary ground node 115. As shown, the cathode of D5 is coupled to the top plate of the output capacitor (COUT) and the load 106 connected in parallel with COUT. Specifically, the top plate of COUT is coupled to the cathode of D5, and the bottom plate of COUT is coupled to the secondary grounding node 115.

[0024] exist Figure 1 In the example, the amount of power supplied to the load 106 is controlled by turning transistor M1 on and off. As shown, M1 has a first current terminal coupled to a first winding of T2, a second current terminal coupled to a primary ground node 108, and a control terminal coupled to a controller (not shown) for the switching converter 100. Figure 1 Also shown are two additional capacitors, C5 and C6, where C5 represents the inter-winding capacitance of T2, and C6 represents the stray capacitance between secondary ground node 115 and ground node 110. During the switching operation of M1, a voltage change 112 at the first winding of T2 causes a voltage change 114 at node 115. Due to C5 and C6, the switching operation of M1, and the associated voltage change 114, current 116 is injected from secondary ground node 115 to ground node 110. This current 116 flows back from node 110 through resistors R1 and R2 of the line impedance stabilization network (LISN). The resulting voltage drop across R1 and R2 is a significant contributor to EMI measurements. This type of EMI is undesirable.

[0025] Figure 2This is a schematic diagram showing another switch converter 200 in some examples. Figure 2 In the example, the switch converter 200 includes a switch for... Figure 1 Many of the same components described in the switching converter 100. Additionally, the switching converter 200 includes a Y-stage capacitor (C7) coupled between the secondary ground node 115 and the primary ground node 108. During the switching operation of M1, a voltage change 112 at the first winding of T2 results in a voltage change 214 at the secondary ground node 115. Due to C5 and C6, the switching operation of M1 and the associated voltage change 214 are contributors to the LISN EMI measured across R1 and R2. Using C7, with... Figure 1 Compared to voltage change 114, voltage change 214 at node 115 decreases, and... Figure 1 Compared to the switching converter 100, this reduces the LISN EMI of the switching converter 200. Figure 2 In the example, C7 provides a current flow path 216 to the primary ground node 108, and the current flow path 216 reduces the amount of current flowing along the current flow path 218 through C6 to the ground node 110.

[0026] Figure 3A This is a schematic diagram illustrating another switch converter 300 in a pull operation scenario in some examples. Figure 3A In the example, the switch converter 300 includes a design for Figure 1 and Figure 2 Many of the same components described in the switching converters 100 and 200. Additionally, switching converter 300 includes a push-pull current source 301 coupled to a base plate of C7. Figure 3A In the example, the push-pull current source 301 includes four transistors M2A, M2B, M3, and M4. As shown, the first current terminal of M2A is coupled to the input voltage source (VDD) node 305, the second current terminal of M2A is coupled to the first current terminal of M2B (referred to herein as the push-regulate transistor), and the control terminal of M2A is coupled to the driver circuit 302. Figure 3A In the example, driver circuit 302 is powered by an input voltage source (VDD) provided by node 305. In operation, driver circuit 302 responds to an input to node 307 to perform a push operation (see example...). Figure 3B The control signal (DVDT-) selectively provides a drive signal to M2 based on VDD. In some examples, DVDT- is a digital signal that goes high when the drain of M1 swings down. In such examples, "DVDT" represents dv / dt at the drain of M1. Note: Figure 3A This only indicates an operation involving the drain of M1 swinging upwards.

[0027] exist Figure 3A In the example, the second current terminal of M2B is coupled to the first current terminal of M3. Simultaneously, the control terminal of M2B is coupled to control node 310. Furthermore, the second current terminal of M3 is coupled to the first current terminal of M4, and the control terminal of M3 is coupled to control node 309. As shown, node 312 between the second current terminal of M2B and the first current terminal of M3 is coupled to the base plate of C7. Additionally, the second current terminal of M4 is coupled to primary ground node 108, while the control terminal of M4 is coupled to driver circuit 306. Figure 3A In the example, driver circuit 306 is powered by an input voltage source (VDD) provided by node 305. In such... Figure 3A During the pull operation, as shown in the diagram, driver circuit 306 responds to the control signal (DVDT+) input to node 311, providing a drive signal to M4 based on VDD, where DVDT+ is a digital signal that goes high when the drain of transistor M1 swings upward. The result of the pull operation is that current flows as indicated by current flow path 316.

[0028] use Figure 3A The pull operation indicated in the diagram causes a voltage change 112 at the first winding of T2, resulting in a reduced voltage change 314 at the secondary ground node 115. Due to C5 and C6, the switching operation of M1 and the associated voltage change 314 are contributors to EMI measured across LISN resistors R1 and R2. However, with C7 and the push-pull current source 301, the voltage change 314 at node 115 is... Figure 1 Voltage change 114 or Figure 2 The voltage change is reduced compared to 214. Figure 3A In the example, the voltage change 314 is reduced by using a push-pull current source 301 to pull current from the base of C7 through transistors M3 and M4 to the primary ground node 108. This reduces the voltage change 314 at the secondary ground node 115 due to the reverse polarity voltage change 318 at the base of C7. By reducing the voltage change 314 at the secondary ground node 115, the amount of current flowing from the secondary ground node 115 to the ground node 110 via C6 is also reduced. In this way, LISN EMI is reduced. Note: Figure 3A The example voltage changes 112, 314, and 318 in the diagram are not drawn to scale. In some scenarios, voltage change 318 can be as small as 1 / 100th of voltage change 112.

[0029] Figure 3B This is shown in some examples of push operation scenarios. Figure 3A A schematic diagram of the switch converter 300. Figure 3B In the example, the switch converter 300 includes a design for Figure 1 and Figure 2Many of the same components described in the switching converters 100 and 200. Additionally, switching converter 300 includes a push-pull current source 301 coupled to a base plate of C7. Figure 3B In the example, push-pull current source 301 performs a push operation that allows current to flow as shown in current flow path 326. More specifically, driver circuit 302 instructs M2A to close in response to DVDT-high (an indication that M1 is swinging down). Furthermore, M2B allows current to flow when M3 and M4 are open, and thus prevents current from flowing to primary ground node 108. With M2A and M2B closed and M3 and / or M4 open, current is pushed to the base of C7. Using M2B, the amount of current during the push operation can be adjusted between a minimum current and a maximum current. In other examples, M2B is replaced by a resistor corresponding to the maximum current used for the push operation (relative to using M2B).

[0030] With push-pull operation, the voltage change 322 at the first winding of T2 causes a decrease in the voltage change 324 at the secondary ground node 115. Due to C5 and C6, the switching operation of M1 and the associated voltage change 324 are contributors to EMI measured across LISN resistors R1 and R2. However, with C7 and push-pull current source 301, the voltage change 324 at node 115 is reduced. Figure 1 Voltage change 114 or Figure 2 The voltage change 214 is reduced compared to the previous example. In one example, the voltage change 324 is reduced by using a push-pull current source 301 to push current from VDD node 305 through transistors M2A and M2B to the base plate of C7. This reduces the voltage change 324 at the secondary ground node 115 due to the reverse polarity voltage change 328 at the base plate of C7. By reducing the voltage change 324 at the secondary ground node 115, the amount of current flowing from the secondary ground node 115 to the ground node 110 via C6 is also reduced. In this way, LISN EMI is reduced. Note: Figure 3B The example voltage changes 322, 324, and 328 in the diagram are not drawn to scale. In some scenarios, voltage change 328 can be as small as 1 / 100th of voltage change 322.

[0031] Figure 4 This is a schematic diagram showing another switch converter 400 in some examples. Figure 4 In the example, the switch converter 400 includes a switch for... Figure 1 - Many of the same components are described in the switching converters 100, 200 and 300 of Figure 3. In addition, the switching converter 400 includes a controller 401 for coupling a push-pull current source 301 to the base plate of C7.

[0032] As shown in the figure, controller 401 includes a sample-and-hold (S&H) circuit 404 coupled to integrator circuit 405. More specifically, S&H circuit 404 includes a switch (S1) and a capacitor (C10), wherein S1 is coupled between input node 403 of controller 401 and top plate of C10. Meanwhile, bottom plate of C10 is coupled to primary ground node 108. Figure 4 In this example, the input node 403 of the controller 401 is coupled to a sensing device including C8 and C9. In some examples, C7 is the first Y-stage capacitor of the switching converter 400 and C8 is the second Y-stage capacitor. As shown, the top plate of C8 is coupled to the secondary ground node 115 and the bottom plate of C8 is coupled to the top plate of C9. Furthermore, the bottom plate of C9 is coupled to the primary ground node 108. Using C8 and C9, a sensing signal 402 associated with the voltage change 414 is provided to the S&H circuit 404.

[0033] The output of the S&H circuit 404 is provided to the integrator circuit 405. As shown, the integrator circuit 405 includes a resistor (R5) and a capacitor (C11) at the positive input (+) node of the operational amplifier 406. More specifically, R5 is between the output of the S&H circuit 404 and the + node of the operational amplifier 406. Additionally, C11 is between the + node of the operational amplifier 406 and the primary ground node 108. The integrator circuit 405 also includes a resistor (R4) at the negative input (-) node of the operational amplifier 406. Figure 4 In the example, the integrator circuit 405 also includes a feedback loop 408, which has a capacitor (C12) between the output of the operational amplifier 406 and a node of the operational amplifier 406. The output of the integrator circuit 405 is coupled to the control node 309 at the control terminal of M3.

[0034] During the switching operation of M1, the voltage change 112 at the first winding of T2 causes a voltage change 414 at node 115. Due to C5 and C6, the switching operation of M1 and the associated voltage change 414 are contributors to the EMI measured across LISN resistors R1 and R2. Using C7-C9, push-pull current source 301, and controller 401, the voltage change 414 at node 115 is related to... Figure 1 Voltage change 114 or Figure 2 The voltage change 214 is reduced compared to the previous example. In one example, when the voltage change 414 occurs at node 115, the voltage change 414 is a result of the controller 401 directing the push-pull current source 301 to pull current from the base plate of C7, as indicated by the sensing signal 402. In some examples, the operation of the controller 401 and the push-pull current source 301 reduces the voltage change at node 115 by an amount 418, resulting in the voltage change 414. Figure 4In the example, C7 provides a current flow path 416 to the primary ground node 108 via M3 and M4, which reduces the amount of current flowing to the secondary ground node 110 via C6. In this way, EMI measured across LISN resistors R1 and R2 is reduced.

[0035] Figures 5A-5D This is a timing diagram showing waveforms associated with a switching converter in some examples. Figure 5A In timing diagram 510, waveform 512 represents the primary drain voltage (e.g., the voltage at the first current terminal of M1). As shown, the primary drain voltage transitions between low and high voltage values ​​(e.g., 0 to 300 volts) as represented by pulses 514A-514C, where the control signal of M1 determines the timing of pulses 514A-514C.

[0036] exist Figure 5B In timing diagram 520, waveform 522 represents the secondary ground voltage (e.g., the voltage at node 115) when a Y-stage capacitor (e.g., C7) is used. As shown, the secondary ground voltage transitions between low and high voltages (e.g., 0 to 4 volts) represented by pulses 524A-524C, where the control signal of M1 determines the timing of pulses 524A-524C.

[0037] exist Figure 5C In timing diagram 530, waveform 532 represents the effect when using a Y-stage capacitor (e.g., C7) and an active push-pull current source (e.g., having a...). Figure 4 The secondary ground voltage (e.g., the voltage at node 115) of the push-pull current source 301 of the controller 401 in the figure. As shown, the secondary ground voltage represented by waveform 532 decreases to the same level as the secondary ground voltage of the push-pull current source 301 of the controller 401 in the figure. Figure 5A The timing diagram 510 shows the short pulses 534A-534F corresponding to each low-to-high and high-to-low transition of the primary drain voltage.

[0038] exist Figure 5D In timing diagram 540, waveform 542 represents the control signal (e.g., from controller 401) provided to control node 309 at the control terminal of M3. As shown, waveform 542 includes a control signal relative to... Figure 5A The timing diagram 510 shows the primary drain voltage pulses 514A-514C and the inverted pulses 544A-544C.

[0039] Figure 6A This is a schematic diagram showing another switch converter 600 in some examples. Figure 6A In the example, the switch converter 600 includes features for... Figure 4 The same components described in the switch converter 400, wherein Figure 6A and Figure 4The difference lies in the fact that the sinusoidal signal 602 exists in Figure 6A At the first coil of T2, instead of the square wave pulse (or other non-sinusoidal pulse) corresponding to voltage change 112, a sinusoidal signal 602 may exist due to resonant oscillation during the converter's "off" phase when the switching converter 600 is controlled in burst mode (also known as PWM on / off control). The sinusoidal signal 602 and its associated voltage change are referred to as discontinuous conduction mode (DCM) ringing. DCM ringing causes a sinusoidal voltage change 604 at node 115. Figure 6A and Figure 4 As shown, the sinusoidal voltage change 604 is less effective at reducing voltage change 414 using C7, push-pull current source 301, and controller 401. In some examples, C7 is the first Y-stage capacitor of the switching converter 600 and C8 is the second Y-stage capacitor.

[0040] Figure 6B It is in some examples Figure 6A Timing diagram 610 is related to the switching converter 600. In timing diagram 610, the secondary ground waveform 611 is represented during burst mode operation. More specifically, during the converter "on" phase 612, the secondary ground voltage is a fixed voltage with brief and small pulses ( Figure 6B The secondary ground voltage (approximately 10V) is maintained by the action of the push-pull current source described above. During the converter's "off" phase 614, the secondary ground voltage rings between a high voltage (e.g., approximately 12V) and a low voltage (e.g., approximately 0V). In this phase, there is no switching edge, and the push-pull is ineffective. Therefore, the ringing does not subside. In the next "on" phase 615, the secondary ground voltage returns to an approximately constant voltage by introducing a burst frequency voltage change 616. In the next "off" phase 618, the secondary ground voltage again rings between a high voltage (e.g., approximately 12V) and a low voltage (e.g., approximately 0V). Figure 6B The ringing, as indicated in the figure, causes unwanted EMI measurements across LISN resistors R1 and R2. Figure 6B The sudden frequency voltage change 616 indicated in the figure causes additional unwanted EMI measurements across the LISN resistors R1 and R2.

[0041] Figure 7 This is a schematic diagram showing another switch converter 700 in some examples. Figure 7 In the example, the switch converter 700 includes a design for... Figures 1-4 Many of the same components described in the switch converters 100, 200, 300, and 400. Furthermore, in Figure 7 In the example, the switching converter 700 includes a DCM circuit 701 coupled to the C7 baseboard, instead of a push-pull current source 301.

[0042] As shown in the figure, the DCM circuit 701 includes an S&H circuit 714 coupled to the integrator circuit 715. More specifically, the S&H circuit 714 includes a switch (S2) and a capacitor (C13), wherein S2 is coupled between the input node 703 of the amplifier circuit 701 and the top plate of C13. Meanwhile, the bottom plate of C13 is coupled to the primary ground node 108. Figure 7 In the example, the input node 703 of the DCM circuit 701 is coupled to a sensing device including C8 and C9. Using C8 and C9, a burst frequency voltage change 616 (see...) Figure 6B The relevant sensing signal 708 is provided to the S&H circuit 714.

[0043] The output of the S&H circuit 714 is provided to the integrator circuit 715. As shown, the integrator circuit 715 includes a resistor (R7) and a capacitor (C14) at the positive input (+) node of the operational amplifier 716. More specifically, R7 is located between the output of the S&H circuit 714 and the + node of the operational amplifier 716. Furthermore, C14 is located between the + node of the operational amplifier 716 and the primary ground node 108. The integrator circuit 715 also includes a resistor (R6) at the negative input (-) node of the operational amplifier 716. Figure 7 In the example, the integrator circuit 715 also includes a feedback loop 717, which has a capacitor (C15) between the output of the operational amplifier 716 and a node of the operational amplifier 716. The output of the integrator circuit 715 is coupled to the amplifier circuit 720.

[0044] As shown in the figure, amplifier circuit 720 includes two resistors (R9 and R10) at the positive input (+) node of operational amplifier 722. More specifically, R9 is located between the output of integrator circuit 715 and the + node of operational amplifier 722. Additionally, R10 is located between the + node of operational amplifier 722 and primary ground node 108. Amplifier circuit 720 also includes a resistor (R8) at the negative input (-) node of operational amplifier 722. As shown, the - node of operational amplifier 722 is coupled to the input node 703 of DCM circuit 701 via R8. Figure 7 In the example, amplifier circuit 720 also includes a feedback loop 724, which has a resistor (R11) between the output of operational amplifier 722 and a node of operational amplifier 722. As shown, operational amplifiers 716 and 722 are powered by the input supply voltage (VDD) node. Figure 7In the example, the values ​​of R8-R11 determine the gain of amplifier circuit 720. During operation, S&H circuit 714 stores the secondary ground burst frequency voltage variation (ΔV) between "on" and "off" periods. Integrator circuit 715 minimizes this burst frequency voltage variation (ΔV) by creating an appropriate DC reference voltage for amplifier circuit 720, such that the DC component of the voltage at the amplifier's output node (which is also the base of Y capacitor C7) is balanced between the converter's "on" and "off" phases. Furthermore, amplifier circuit 720 attenuates sinusoidal DCM ringing by sensing sinusoidal ringing 704 at secondary ground node 115 and by generating an out-of-phase sinusoidal signal 706 at the base of Y-stage capacitor C7. In some examples, C7 is the first Y-stage capacitor of the switching converter 700 and C8 is the second Y-stage capacitor.

[0045] Figure 8A-1 and Figure 8A-2 This is a schematic diagram showing another switch converter 800 in some examples. Figure 8A-1 and Figure 8A-2 In the example, the switch converter 800 includes features for... Figure 1-4 Figure 6 and Figure 7 Many of the same components described in switching converters 100, 200, 300, 400, 600, and 700. In some examples, C7 is the first Y-stage capacitor of switching converter 800 and C8 is the second Y-stage capacitor. Figure 8A-1 and Figure 8A-2 As shown, the switching converter 800 includes a push-pull current source 301 and a DCM circuit 701 coupled to the base plate of C7 via corresponding switches S3 and S4. More specifically, S3 is closed during the "on" phase of the switching converter 800, allowing the push-pull current source 301 to selectively push current into or pull current out of the base plate of C7. Simultaneously, S4 is open during the "on" phase of the switching converter 800. Conversely, S4 is closed during the "off" phase of the switching converter 800, allowing the DCM circuit 701 to apply current to the base plate of C7 to reduce secondary ground signal ringing during the "off" phase. Furthermore, S3 is open during the "off" phase of the switching converter 800.

[0046] In some examples, during the PWM-based switching operation of M1, push-pull current source 301 and controller 401 operate to reduce voltage variations applied to the secondary ground node 110 as described herein (e.g., Figure 4 (Voltage variation 414 in M1). Furthermore, during burst-mode switching operation of M1 (when the switchover periodically turns on and off), the DCM circuit 701 operates to reduce secondary ground signal ringing as described herein.

[0047] Figure 8BThis is timing diagram 820 related to the switching converter in Figure 8A of some examples. In timing diagram 820, the secondary ground waveform 821 is represented during different converter operations. More specifically, during the converter "on" phase, the secondary ground voltage is at a fixed voltage due to the operation of the push-pull current source 301 and the controller 401. Figure 8B (Approximately 10V). During the converter's "off" phase, the secondary ground voltage remains at a fixed voltage due to the operation of the DCM circuit 701 minimizing burst frequency voltage variations and DCM ringing attenuation.

[0048] Figure 9A and Figure 9B This is a schematic diagram illustrating another switch converter 900 in some examples. In the example of Figure 9, the switch converter 900 includes a switch converter for... Figures 1-4 Many of the same components described in switching converters 100, 200, 300, and 400. Additionally, switching converter 900 includes an additional push-pull current source 901 coupled to the base plate of C7. Figure 9A and Figure 9B In the example, the push-pull current source 901 includes three transistors M5-M7. As shown, the first current terminal of M5 is coupled to the VDD node 305, the second current terminal of M5 is coupled to the first end of resistor (R12), and the control terminal of M5 is coupled to the driver circuit 902. R12 is used to set the current during push operation to a maximum level. In other examples, R12 is replaced by a transistor (see, for example...). Figure 3A The M2B transistor can be used to regulate the current from a minimum level to a maximum level during push operation.

[0049] exist Figure 9A and Figure 9B In the example, driver circuit 902 is powered by VDD provided by node 305. In operation, driver circuit 902 selectively provides a drive signal to M5 based on VDD in response to a control signal (DVDT-_BURST_1STCYC) input to node 707. Figure 9A and Figure 9B In the example, DVDT-_BURST_1STCYC is a digital signal that goes high during the first switching transition of the drain voltage of M1 (at the start of the PWM ON mode of the switch converter 900). This switching transition is caused by the first turn-on of M1 in PWM ON mode.

[0050] Furthermore, the first current terminal of M6 is coupled to the second terminal of R12, the second current terminal of M6 is coupled to the first current terminal of M7, and the control terminal of M6 is coupled to control node 909. As shown, node 912 between R12 and the first current terminal of M6 is coupled to the base plate of C7. Additionally, the second current terminal of M7 is coupled to primary ground node 108, while the control terminal of M7 is coupled to driver circuit 906. In the example of Figure 9, driver circuit 906 is powered by VDD provided by node 305. In operation, driver circuit 906 selectively provides a drive signal to M7 based on VDD in response to the control signal (DVDT-_BURST_LASTCYC) input to node 307. Figure 9A and Figure 9B In the example, DVDT-_BURST_LASTCYC is a digital signal that goes high during the last switching transition of the drain voltage of M1 (at the end of the PWM ON mode of the switch converter 900). This switching transition is caused by the last time M1 is turned off in PWM ON mode.

[0051] Furthermore, the switching converter 900 includes a controller 908 for a push-pull current source 901 coupled to the base plate of C7. As shown, the controller 908 includes an S&H circuit 914 coupled to the integrator circuit 915. More specifically, the S&H circuit 914 includes a switch (S5) and a capacitor (C16), wherein S5 is coupled between the input node 903 of the controller 908 and the top plate of C16. Meanwhile, the base plate of C16 is coupled to the primary ground node 108. Figure 9A and Figure 9B In this example, the input node 903 of the controller 908 is coupled to a sensing device including C8 and C9. Using C8 and C9, a sensing signal 402 related to a burst frequency voltage change at node 115 is provided to the S&H circuit 914. In some examples, C7 is the first Y-stage capacitor of the switching converter 900 and C8 is the second Y-stage capacitor.

[0052] The output of the S&H circuit 915 is provided to the integrator circuit 915. As shown, the integrator circuit 915 includes a resistor (R14) and a capacitor (C17) at the positive input (+) node of the operational amplifier 916. More specifically, R14 is between the output of the S&H circuit 914 and the + node of the operational amplifier 916. Furthermore, C17 is between the + node of the operational amplifier 916 and the primary ground node 108. The integrator circuit 915 also includes a resistor (R13) at the negative input (-) node of the operational amplifier 916. Figure 9A and Figure 9BIn the example, the integrator circuit 915 also includes a feedback loop 918, which has a capacitor (C18) between the output of the operational amplifier 916 and a node of the operational amplifier 916. The output of the integrator circuit 915 is coupled to a control node 909 at the control terminal of the M6.

[0053] During the switching operation of M1, voltage changes at the first winding of T2 result in voltage changes at node 115. Due to C5 and C6, the switching operation of M1 and the associated voltage changes are contributors to EMI measured across LISN resistors R1 and R2. Using C7-C9, push-pull current source 301, and controller 401, the voltage change at node 115 is reduced during PWM operation. Using C7-C9, push-pull current source 901, and controller 908, the burst frequency voltage change at node 115 is reduced during burst mode operation. In one example, when a burst frequency voltage change occurs at node 115, the voltage change at node 115 is a result of controller 908 directing push-pull current source 901 to pull current from the base plate of C7, as indicated by sensing signal 402. In some examples, the operation of controller 908 and push-pull current source 901 results in the secondary-to-ground burst frequency voltage change becoming zero.

[0054] Employing switch converters 400, 600, 800, and 900 (see...) Figure 4 , Figure 6A , Figure 8A-1 , Figure 8A-2 , Figure 9A , Figure 9B The switching converter circuit having a first Y-stage capacitor node (e.g., at the base plate of C7) along with a push-pull current source coupled to the first Y-stage capacitor node (e.g., Figure 4 , Figure 6A , Figure 8A-2 , Figure 9B The push-pull current source 301 in the circuit is shown together with the switch converter circuit. The switch converter circuit also includes a controller coupled to the push-pull current source (e.g., Figure 4 , Figure 6A , Figure 8A-2 , Figure 9B The controller is 410. In some examples, the controller includes a sample-and-hold circuit (e.g., sample-and-hold circuit 404) coupled to the second Y-stage capacitor node (at the base plate of C8). The controller also includes an integrator circuit (e.g., integrator circuit 405) coupled to the sample-and-hold circuit.

[0055] In some examples, the sample-and-hold circuit is a first sample-and-hold circuit, the integrator circuit is a first integrator circuit, and the switching converter circuit further includes a DCM circuit coupled to the second Y-stage capacitor node (e.g., Figure 8A-2The DCM circuit 701 in the DCM circuit includes a second sample-and-hold circuit coupled to the sample-and-hold circuit (e.g., Figure 8A-2 The sample-and-hold circuit 714) and the second integrator circuit (e.g., Figure 8A-2 The integrator circuit 715 in the middle. The DCM circuit also includes an amplifier coupled to the second integrator circuit (e.g., Figure 8A-2 Amplifier 720 in the middle), wherein the amplifier is connected via a switch (e.g. Figure 8A-2 S4 in the circuit is coupled to the first Y-stage capacitor node. In some examples, the switch is the first switch, and the switch-converter circuit includes a second switch (e.g., between the push-pull current source and the first Y-stage capacitor node) Figure 8A-2 (S3 in the example). During the PWM ON mode of the switching converter, the second switch is closed and the first switch is open. Furthermore, during the PWM OFF mode of the switching converter, the second switch is open and the first switch is closed.

[0056] In some examples, the push-pull current source is a first push-pull current source, and the switching converter circuit also includes a second push-pull current source coupled to the second Y-stage capacitor node (e.g., Figure 9B The first push-pull current source is configured to operate during the PWM ON mode of the switching converter circuit, and the second push-pull current source is configured to operate during the first and last switching cycles of the switching converter's burst mode.

[0057] In some examples, the integrated circuit includes a first Y-stage capacitor node (e.g., at the base of C7) and a second Y-stage capacitor node (at the bottom of C8). The integrated circuit also includes a push-pull current source coupled to the first Y-stage capacitor node (e.g., ...). Figure 4 , Figure 6A , Figure 8A-2 , Figure 9B The integrator circuit also includes a push-pull current source 301. Figure 4 , Figure 6A , Figure 8A-2 , Figure 9B The controller 410 is configured to monitor voltage changes at the second Y-stage capacitor node and selectively push current into or pull current out of the first Y-stage capacitor node. In some examples, the controller includes a sample-and-hold circuit coupled to the second Y-stage capacitor node (e.g., ...). Figure 4 The controller also includes an integrator circuit (e.g., integrator circuit 405) coupled to the sample-and-hold circuit.

[0058] Furthermore, push-pull current sources for integrated circuits include push transistors (e.g., Figure 4 , Figure 6A , Figure 8A-2 In the M2A), the push transistor has a first current terminal coupled to the input voltage source (VDD) via a resistor (e.g., Figure 9B R12 in the transistor or push-to-regulate transistor (e.g., R12 in the transistor) Figure 4 , Figure 6A , Figure 8A-2 The M2B in the first Y-stage capacitor node is coupled to the second current terminal and to the first driver circuit (e.g., Figure 3A , Figure 3B , Figure 4 , Figure 6A , Figure 8A-2 and Figure 9B The push-pull current source also includes a pull transistor (e.g., a driver circuit 302) with a first current terminal, a second current terminal, and a control terminal. Figure 3A , Figure 3B , Figure 4 , Figure 6A , Figure 8A-2 and Figure 9B In the M4 of the push-pull current source, the second current terminal of the pull transistor is coupled to the ground node. The push-pull current source also includes a control transistor (e.g., M4) having a first current terminal, a second current terminal, and a control terminal. Figure 3A , Figure 3B , Figure 4 , Figure 6A , Figure 8A-2 and Figure 9B M3 in the circuit). The first current terminal of the control transistor is coupled to one end of the resistor (e.g., M3 in the circuit). Figure 9B R12 in the middle) or the second current terminal of the push-regulating transistor (e.g., Figure 4 , Figure 6A , Figure 8A-2 (M2B in the diagram). The second current terminal of the control transistor is coupled to the first current terminal of the pull transistor. Furthermore, the control terminal of the control transistor is coupled to the sensing controller.

[0059] In some examples, sample-and-hold circuits (e.g., Figure 4 The sample-and-hold circuit 404 is a first sample-and-hold circuit, and the integrator circuit (e.g., integrator circuit 405) is a first integrator circuit. In such examples, the integrated circuit also includes a DCM circuit coupled to the second Y-stage capacitor node (e.g., Figure 8A-2 The DCM circuit 701 in the DCM circuit includes a second sample-and-hold circuit (e.g., Figure 8A-2 The sample-and-hold circuit 714 in the middle) and the second integrator circuit coupled to the second sample-and-hold circuit (e.g., Figure 8A-2The integrator circuit 715 in the middle. The DCM circuit also includes an amplifier coupled to the second integrator circuit (e.g., Figure 8A-2 Amplifier 720 in the middle), wherein the amplifier is connected via a switch (e.g. Figure 8A-2 S4 in the circuit is coupled to the first Y-stage capacitor node. In some examples, the switch is the first switch, and the integrator circuit also includes a second switch (e.g., between the push-pull current source and the first Y-stage capacitor node) Figure 8A-2 (S3 in the example). During the PWM ON mode of the switching converter, the second switch is closed and the first switch is open. During the PWM OFF mode of the switching converter, the second switch is open and the first switch is closed.

[0060] Furthermore, in some examples, push-pull current sources (e.g., Figure 4 , Figure 6A , Figure 8A-2 , Figure 9B The push-pull current source 301 in the integrated circuit is the first push-pull current source, and the integrated circuit also includes a second push-pull current source coupled to the second Y-stage capacitor node (e.g., Figure 9B The push-pull current source 908 is configured to operate during the PWM ON mode of the switching converter. Furthermore, the second push-pull current source is configured to operate during the PWM OFF mode of the switching converter.

[0061] The term "coupled" is used throughout this specification. This term can encompass a connection, communication, or signaling path that achieves a functional relationship consistent with the description herein. For example, if device A generates a signal to control device B to perform an action, in the first example, device A is coupled to device B; or in the second example, if intermediate component C does not significantly alter the functional relationship between device A and device B, device A is coupled to device B via intermediate component C, such that device B is controlled by device A via a control signal generated by device A.

[0062] Within the scope of the claims, modifications to the described embodiments are possible, and are also possible in other embodiments.

Claims

1. A power supply system, comprising: Voltage source input; A switching converter coupled to the voltage source input, the switching converter comprising: A transformer having a primary coil and a secondary coil, the primary coil being coupled to the voltage source input, and the secondary coil having a first terminal and a second terminal; Push-pull current source; A controller coupled to the push-pull current source, the controller including a sample-and-hold circuit; A first capacitor, coupled between the first terminal of the secondary coil and the push-pull current source; and A second capacitor is coupled between the first terminal of the secondary coil and the input terminal of the sample-and-hold circuit. The controller is configured to monitor voltage changes at the terminals of the second capacitor and selectively push current into or pull current out of the first capacitor.

2. The power supply system according to claim 1, wherein, The controller includes an integrator circuit coupled to the output of the sample-and-hold circuit.

3. The power supply system according to claim 1, wherein the power supply system comprises: Discontinuous conduction mode circuit, also known as DCM circuit, includes: An integrator circuit coupled to the output of the sample-and-hold circuit, and an input of the integrator circuit coupled to the second capacitor; and An amplifier, coupled to the output of the integrator circuit, and A switch is coupled between the first capacitor and the output of the amplifier.

4. The power supply system according to claim 3, wherein, The switch includes a first switch, wherein the power system includes a second switch between the push-pull current source and the first capacitor, wherein the second switch is closed and the first switch is open during the pulse width modulation on mode (PWM ON) of the switch converter, and the second switch is open and the first switch is closed during the PWM off mode (PWM OFF) of the switch converter.

5. The power supply system according to claim 1, wherein, The push-pull current source is a first push-pull current source, and the power supply system includes a second push-pull current source coupled to the base plate of the second capacitor. The first push-pull current source is configured to operate during the pulse width modulation on mode (PWM ON mode) of the switching converter, and the second push-pull current source is configured to operate during the first and last switching cycles of the burst mode of the switching converter.

6. The power supply system according to claim 1, wherein the power supply system includes a discontinuous conduction mode clamping circuit, i.e., a DCM clamping circuit, coupled to the transformer.

7. A switching converter circuit, comprising: First capacitor; Second capacitor; A push-pull current source coupled to the first capacitor; as well as A controller coupled to the push-pull current source, the controller comprising: A sample-and-hold circuit, coupled to the second capacitor; and An integrator circuit, which is coupled to the sample-and-hold circuit, The controller is configured to monitor voltage changes at the terminals of the second capacitor and selectively push current into or pull current out of the first capacitor.

8. The switch converter circuit according to claim 7, wherein, The sample-and-hold circuit is a first sample-and-hold circuit, the integrator circuit is a first integrator circuit, and the switching converter circuit includes: Discontinuous conduction mode circuit, also known as DCM circuit, includes: A second sample-and-hold circuit has an input terminal coupled to the second capacitor; A second integrator circuit, coupled to the output of the second sample-and-hold circuit; and An amplifier coupled to the output of the second integrator circuit; and A switch is coupled between the output of the amplifier and the first capacitor.

9. The switch converter circuit according to claim 8, wherein, The switch includes a first switch, and the switch converter circuit includes a second switch between the push-pull current source and the first capacitor, wherein the second switch is closed and the first switch is open during the pulse width modulation on mode (PWM ON) of the switch converter, and the second switch is open and the first switch is closed during the PWM off mode (PWM OFF) of the switch converter.

10. The switch converter circuit according to claim 7, wherein, The push-pull current source is a first push-pull current source, the switch converter circuit includes a second push-pull current source coupled to the second capacitor, the first push-pull current source is configured to operate during the pulse width modulation on mode (PWM ON mode) of the switch converter, and the second push-pull current source is configured to operate during the first and last switching cycles of the burst mode of the switch converter.

11. The switch converter circuit according to claim 7, wherein the switch converter circuit comprises: A transformer having a primary coil and a secondary coil, wherein a first end of the secondary coil is coupled to the first capacitor; as well as The discontinuous conduction mode clamping circuit, or DCM clamping circuit, is coupled to the transformer.

12. The switch converter circuit according to claim 7, wherein, The first capacitor, the second capacitor, the push-pull current source, and the controller are components of an integrated circuit.

13. The switching converter circuit according to claim 12, comprising: A transformer having a primary coil and a secondary coil, the secondary coil having a first terminal and a second terminal; The first capacitor is coupled between the first terminal of the secondary coil and the push-pull current source; and The second capacitor is coupled between the first end of the secondary coil and the controller.

14. An integrated circuit, comprising: First Y-stage capacitor; Second Y-stage capacitor; A push-pull current source is coupled to the first Y-stage capacitor; A controller coupled to the push-pull current source, wherein the controller is configured to monitor voltage changes at the terminals of the second Y-stage capacitor and selectively push current into or pull current out of the nodes of the first Y-stage capacitor, the controller comprising: A sample-and-hold circuit, coupled to the second Y-stage capacitor; and An integrator circuit coupled to the sample-and-hold circuit.

15. The integrated circuit according to claim 14, wherein, The push-pull current source includes: A push transistor has a first current terminal coupled to an input voltage source, a second current terminal coupled to the first Y-stage capacitor via a resistor, and a control terminal coupled to a first driver circuit. A pull transistor having a first current terminal, a second current terminal, and a control terminal, wherein the second current terminal of the pull transistor is coupled to a ground terminal; and A control transistor having a first current terminal, a second current terminal, and a control terminal, wherein the first current terminal of the control transistor is coupled to one end of the resistor, the second current terminal of the control transistor is coupled to the first current terminal of the pull transistor, and the control terminal of the control transistor is coupled to the controller.

16. The integrated circuit according to claim 14, wherein, The sample-and-hold circuit is a first sample-and-hold circuit, the integrator circuit is a first integrator circuit, and the integrated circuit includes a discontinuous conduction mode (DCM) circuit coupled to the node of the second Y-stage capacitor, the DCM circuit including: Second sample and hold circuit; A second integrator circuit, coupled to the second sample-and-hold circuit; and An amplifier coupled to the second integrator circuit, which is coupled to the first Y-stage capacitor node via a switch.

17. The integrated circuit according to claim 16, wherein, The switch includes a first switch, and the integrated circuit includes a second switch between the push-pull current source and the first Y-stage capacitor node. During the pulse width modulation on mode (PWM ON) of the switch converter, the second switch is closed and the first switch is open, and during the PWM off mode (PWM OFF) of the switch converter, the second switch is open and the first switch is closed.

18. The integrated circuit according to claim 14, wherein, The push-pull current source is a first push-pull current source, and the integrated circuit includes a second push-pull current source coupled to a second Y-stage capacitor node. The first push-pull current source is configured to operate during the pulse width modulation on mode (PWM ON) of the switching converter, and the second push-pull current source is configured to operate during the PWM off mode of the switching converter.

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