Printed circuit board configuration for surface mounting dual density QSFP connector footprint to promote belly-to-belly alignment

Abstract

An electronic device includes a printed circuit board (PCB). The PCB includes first and second grids (50) arranged on top and bottom surfaces of the PCB, respectively. Each grid includes a plurality of footprint pins (60), and a plurality of vias (52) extending through the PCB to the top and bottom surfaces. Each footprint pin (60) includes a connection end (62) and a free end (64) opposite the connection end (62). Each via (52) includes a contact end (54) at one of the grids and in electrical contact with the connection end (62) of one of the footprint pins, and each via (52) also includes a non-contact end (56) at the other of the grids and not in electrical contact with any of the footprint pins (60). First and second connectors are mounted to the top and bottom surfaces of the PCB and connected with the footprint pins (60) of the first and second grids (50).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 896,619, filed September 6, 2019, entitled “Print CircuitBoard Configuration To Facilitate a Surface Mount Double Density QSFP Connector Footprint in a Belly-To-Belly Alignment,” filed under 35 USC §119(e), the disclosure of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This disclosure relates to network interface module connections on printed circuit boards for data communication applications. Background Technology

[0004] With the increasing prevalence of high-speed data communication, 400 Gigabit Ethernet (400GbE) faces signaling challenges. Current switching systems employ Double-Density Quad Small Form Factor Pluggable (QSFP-DD) designs to improve capacity and efficiency, with eight channels for the electrical interface operating at up to 53.125 Gbps Pulse-Amplitude Modulation 4-Level (PAM4). However, connector footprint design is limited to single-height and stacked configurations currently available from connector manufacturers in cage / connector systems supporting QSFP-DD modules. The aim is to address critical signal integrity issues and design a high-density, low-crosstalk, ultra-compact footprint to enable 400GbE data communication and future roadmaps for data communication beyond 400GbE. Attached Figure Description

[0005] Figure 1A This is a schematic diagram of a printed circuit board (PCB) for electronic devices, including QSFP-DD surface mount connectors arranged in a belly-to-belly surface mount configuration on the top and bottom surfaces of the PCB. In one example embodiment, the PCB includes transmitter (Tx) and receiver (Rx) surface contact / footprint pins for connection to corresponding Tx and Rx connector pins of the surface mount connectors.

[0006] Figure 1B yes Figure 1A A partial view of the PCB depicts the surface mount connectors separated from the PCB, showing the underlying mesh of the (Tx) and receiver (Rx) surface contacts / footprint pins for connection to the corresponding Tx and Rx connector pins of the surface mount connectors.

[0007] Figure 2A and Figure 2B They are Figure 1A and Figure 1B A view of the vias and contact arrangement or grid on the top and bottom surfaces of the PCB, showing Tx and Rx surface contacts / footprint pins and vias configured to align and connect with the corresponding QSFP-DD surface mount connectors.

[0008] Figure 2C yes Figure 2A A magnified view of the surface contacts / footprint pins in the grid depicted in the image.

[0009] Figure 3A and Figure 3B yes Figure 1A and Figure 1B A partial cross-sectional view of the device's PCB shows an example embodiment of the Tx and Rx surface mount technology (SMT) pins of the QSFP-DD surface mount connector, and how such SMT pins connect to the corresponding Tx and Rx footprint pins along the top and bottom surfaces of the PCB.

[0010] Figure 4 It is a schematic diagram showing Figure 1A and Figure 1B A partial cross-section of the PCB (along such as...) Figure 2A and Figure 2B The diagram shows a through-hole and footprint pin arrangement (AA line obtained) and a partial view of two connectors, which are arranged as shown. Figure 1B The connection is shown along the top and bottom surfaces of the PCB.

[0011] Figure 5A and Figure 5B These are schematic diagrams associated with the top and bottom surfaces of the PCB, respectively. According to an example embodiment, the routing of the Tx and Rx footprint pins along the electrical / escape traces connected to the PCB surface (e.g., arranged within one or more layers of the PCB) is shown.

[0012] Figure 6A , Figure 6B and Figure 6C An example embodiment of a design configuration of reverse pads associated with vias of Tx and Rx footprint pins on different layers of a PCB is shown. Detailed Implementation

[0013] Overview

[0014] In one embodiment, a printed circuit board (PCB) includes a grid comprising a plurality of footprint pins and a plurality of vias arranged along one or more linear rows. Each footprint pin is disposed on a top or bottom surface of the PCB, and each via extends through the PCB to both the top and bottom surfaces. Each footprint pin is elongated and includes a connecting end and a free end opposite to the connecting end. Each via includes a contact end located on one of the top and bottom surfaces and electrically contacting the connecting end of one of the footprint pins. Each via also includes a non-contact end located on the other of the top and bottom surfaces and not electrically contacting any of the footprint pins. Each linear row includes a first pair and a second pair of footprint pins, each of the first and second pairs comprising two footprint pins arranged adjacent to each other in the linear row. Furthermore, the free end of each footprint pin in the first pair extends along the PCB in a first direction, and the free end of each footprint pin in the second pair extends along the PCB in a second direction, with the first and second directions being 180° opposite each other.

[0015] In another embodiment, an electronic device includes a printed circuit board (PCB) comprising a first grid disposed on a top surface of the PCB and a second grid disposed on a bottom surface of the PCB. Each of the first and second grids includes a plurality of footprint pins and a plurality of through-holes, the plurality of footprint pins and the plurality of through-holes being arranged along one or more linear rows at each of the first and second grids, wherein each through-hole extends through the PCB to both the top and bottom surfaces of the PCB such that each through-hole is part of the first and second grids. Each footprint pin is elongated and includes a connecting end and a free end opposite to the connecting end. Each through-hole includes a contact end located at one of the first and second grids and electrically contacting the connecting end of one of the plurality of footprint pins, and each through-hole also includes a non-contact end located at the other of the first and second grids and not electrically contacting any of the plurality of footprint pins. Each linear row of the first and second grids includes a first pair and a second pair of the plurality of footprint pins, each of the first pair and the second pair including two footprint pins arranged adjacent to each other in the linear row. The free end of each footprint pin in the first pair extends along the PCB in a first direction, and the free end of each footprint pin in the second pair extends along the PCB in a second direction, with the first and second directions being 180° opposite each other. The device also includes a first surface mount connector mounted to the top surface of the PCB and including surface mount pins for connection to the footprint pins of the first grid, and a second surface mount connector mounted to the bottom surface of the PCB and including surface mount pins for connection to the footprint pins of the second grid.

[0016] In another embodiment, a method includes providing an electronic device including a printed circuit board (PCB), wherein the PCB includes a first grid disposed on a top surface of the PCB and a second grid disposed on a bottom surface of the PCB, each of the first and second grids including a plurality of footprint pins and a plurality of through-holes, the plurality of footprint pins and the plurality of through-holes being arranged along one or more linear rows at each of the first and second grids, wherein each through-hole extends through the PCB to both the top and bottom surfaces of the PCB such that each through-hole is part of the first and second grids. Each footprint pin is elongated and includes a connecting end and a free end opposite to the connecting end, each through-hole including a contact end located at one of the first and second grids and electrically contacting the connecting end of one of the plurality of footprint pins, and each through-hole also including a non-contact end located at the other of the first and second grids and not electrically contacting any of the plurality of footprint pins. Each linear row of the first and second grids includes a first pair of a plurality of footprint pins and a second pair of a plurality of footprint pins. Each of the first and second pairs includes two footprint pins arranged adjacent to each other in the linear row. The free end of each footprint pin in the first pair extends along the PCB in a first direction, and the free end of each footprint pin in the second pair extends along the PCB in a second direction, wherein the first and second directions are 180° opposite. A first surface mount connector is mounted to the top surface of the PCB such that its surface mount pins connect to the footprint pins of the first grid, and a second surface mount connector is mounted to the bottom surface of the PCB such that its surface mount pins connect to the footprint pins of the second grid.

[0017] Example Implementation

[0018] This disclosure relates to an electronic device including a printed circuit board (PCB) comprising a surface contact configuration that facilitates surface mount connections to Ethernet and / or other data communication connectors along the top and bottom surfaces of the PCB in a belly-to-belly configuration. In one embodiment, the PCB includes a configuration of mutually aligned surface contacts and vias on its top and bottom surfaces to facilitate connections to surface mount connectors arranged relative to each other in a belly-to-belly configuration (i.e., the bottom ends of connectors on the top surface of the PCB face the bottom ends of connectors on the bottom surface of the PCB). Such a configuration provides a footprint layout design on the PCB that arranges a series of connectors in a tight, densely packed manner to meet the signaling challenges of PAM4 Ethernet and other data communication.

[0019] refer to Figures 1A-1B , Figures 2A-2C and Figures 3A-3BThis describes an example embodiment of an electronic device 2 including a PCB 4, which facilitates connections along the top and bottom surfaces 10, 20 of the PCB using surface mount connectors. The electronic device 2 may include one or more integrated circuits (in...) Figure 1A The PCB 10 is generally shown as IC 6 on its top surface 10, along with any other suitable electrical components arranged on the top or bottom surface of the PCB and / or integrated within one or more layers of the PCB. This electronic device may include, for example, any suitable type of networking device (e.g., gateway, bridge, hub, switch, router, etc.) and / or any other suitable type of computing device (or part of a computing device) that facilitates communication of data signals from the device to other devices in the network and data signals to the device. PCB 4 may include one or more signal layers with traces embedded at different depths and in different numbers within the PCB to route signals between electronic components integrated with the PCB. Some examples of electronic components associated with PCB 4 are surface mount connectors 100. As described herein, surface mount connector 100 may be a small form factor connector, such as a QSFP-Dual Density (QSFP-DD) connector, which facilitates high-speed signal communication between device 2 and other electronic devices over a network.

[0020] Surface mount connectors 100 are directly mounted to the top surface 10 and bottom surface 20 of PCB 4. Each surface mount connector 100 includes an array of surface mount technology (SMT) pins 110. Figure 3A , Figure 3B and Figure 4These pins, when mounted to the surface of a PCB as described herein, make electrical contact with a signal transmission array or contact grid 50 of corresponding electrical contact pads or footprint pins, which are electrically connected to vias and arranged along the top and bottom surfaces of the PCB. The SMT pins 110 of each surface mount connector 100 may be formed of metal or other suitable conductive material (e.g., copper) and extend from the lower surface of the connector, having a generally "L" shape that bends to form a generally flat contact surface area for the corresponding footprint pins of the corresponding grid 50 of the footprint pins on the top surface 10 or bottom surface 20 of the PCB. Similarly, the surface contacts or footprint pins of the PCB 4 are also formed of metal or other suitable conductive material (e.g., copper) and are appropriately sized to engage with the flat contact surface area of ​​the SMT pins 110. As described herein, the footprint pins provided along grid 50 may be provided in pairs (e.g., two footprint pins are provided adjacent to each other along a row of footprint pins and vias in the grid), with two or more pairs of different types (e.g., first pair, second pair, etc.) for facilitating the transmission of different types of signals (e.g., transmit or Tx signal, receive or Rx signal, etc.).

[0021] PCB 4 may include a contact grid 50 of any appropriate number of footprint pins 60, the size and orientation of which are appropriately set to facilitate connection with surface mount connector 100 to facilitate signal transmission and reception between the PCB and the connector, wherein through-holes of the grid 50 extend through PCB 4 to define the mounting positions of the two connectors 100 in a belly-to-belly configuration at approximately the same or similar surface locations and along the top surface 10 and bottom surface 20 of the PCB (e.g., Figure 1A (As shown). Connector 100 may further be connected and make electrical contact with the corresponding footprint pins of contact grid 50 via SMT pins 110 in any suitable manner, such as via soldering connection (e.g., each SMT pin of the connector is soldered to the corresponding footprint pin of the PCB contact grid), friction engagement using press-fit and / or spring-loaded connection to secure the connector to the top or bottom surface of the PCB, etc.

[0022] refer to Figures 2A-2C , Figure 3A , Figure 3B and Figure 4The grid 50 includes multiple linear rows of surface contacts or footprint pins 60 and vias 52, which correspond in orientation, arrangement, and number to the SMT pins 110 of the corresponding linear rows of connector 100. To facilitate high-speed signal transmission, each surface of the PCB includes an array or grid 50 of vias 52, including ground vias, transmitter (Tx) vias, and receiver (Rx) vias. The grid 50 also includes contact pads or footprint pins 60, including ground footprint pins, Tx footprint pins, and Rx footprint pins, which are aligned with and make electrical contact with the corresponding ground, Tx, and Rx vias. As described herein, each via 52 extends through the PCB 4 (i.e., to each of the top surface 10 and the bottom surface 20 of the PCB), but only includes a single footprint pin 60 connected to the via on the top or bottom surface of the PCB. Tx footprint pins and Tx vias facilitate the transmission of signals from electronic devices (e.g., via traces electrically connected to the vias) to the module via their connectors, while Rx footprint pins and Rx vias facilitate the reception or acceptance of signals from the module to electronic components via their connectors.

[0023] In one example embodiment, the grid 50 of the footprint pins 60 and via 52 includes four rows of footprint pins, with eight pairs of transmitter (Tx) footprint pins and eight pairs of receiver (Rx) footprint pins. A pair of Tx or Rx footprint pins comprises two Tx or Rx footprint pins arranged adjacent to each other or continuously adjacent to each other along a row of grid 50. Each row of footprint pins includes two pairs of Tx footprint pins and two pairs of Rx footprint pins, which make electrical contact with the Tx and Rx SMT pins 110 of connector 100 when the connector is secured to the PCB surface. Each row of footprint pins 60 also includes ground footprint pins and low-speed footprint pins, wherein the ground footprint pins are positioned adjacent to or continuously adjacent to each pair of Tx and Rx footprint pins within a row of grid 50. Additionally, pairs of Tx and Rx footprint pins in each row of grid 50 are located near the ends of the row, while low-speed footprint pins are located in the middle of each row.

[0024] As described herein, the surface mount connector that connects to the grid 50 of the footprint pins 60 can be a small-form-factor pluggable surface mount connector, such as a QSPF-DD surface mount connector, capable of performing high-speed signal transmission to and from the electronic device 2. A suitable QSFP-DD surface mount connector is configured with rows of SMT pins to connect to the grid 50 of the footprint pins 60 along the top or bottom surface of the PCB 4. A non-limiting example embodiment of this surface mount connector is an optical module connector (part number: 202718-0100) designed by Molex, LLC. This surface mount connector may have multiple rows of signal contact / SMT pins and ground contact / SMT pins that extend from the mating interface of the optical module to engage with the footprint pins of the printed circuit board.

[0025] Each footprint pin 60 has an elongated configuration with a generally uniform or constant width, wherein the footprint pin 60 contacts or is electrically connected to a corresponding through-hole 52 at one end 62 (connection end), and includes an opposite terminal or free end 64, which is tapered (i.e., the width dimension at the free end is smaller relative to the generally constant width of the footprint pin along the rest of its length).

[0026] The tapered free end 64 of each footprint pin 60 allows adjacent footprint pins within a row of grid 50 to have a close spacing while avoiding contact with adjacent vias on either side of the footprint pin (i.e., as shown, the tapered free ends of at least some footprint pins are arranged between two vias within each linear row of the grid). All footprint pins 60 in each row of grid 50 are arranged generally parallel to each other, with vias 52 arranged between the tapered free ends 64 of every two consecutive footprint pins 60. Figure 2A The view of grid 50 depicted corresponds to a top-plan view of how the grid is arranged at the top surface 10 of PCB 4 (e.g., Figure 1B The grid depicted in the middle (50), while Figure 2B The view of grid 50 depicted corresponds to the grid arrangement at the bottom surface 20 of the PCB when viewed from the top surface 10 (i.e., looking down from the top surface 10 towards the bottom surface 20). Thus, the grid 50 at the top surface 10, which covers and is substantially aligned with the grid 50 at the bottom surface 20, is configured such that vias extending through the PCB 4 are located within two aligned grids, wherein each line row of the footprint pins and vias of the top surface grid corresponds to or aligns with the corresponding line row of the footprint pins and vias of the bottom surface grid that shares the same vias with the top surface grid (i.e., the same vias are located in both the top surface grid and the bottom surface grid).

[0027] refer to Figure 4Each via 52 extends through the PCB 4 to the top surface 10 and the bottom surface 20. Each via 52 connects at its contact end 54 to only a single footprint pin 60 on the top or bottom surface of the PCB (via the connection end or end 62 of the footprint pin 60), while the other end or non-contact end 56 of the via 52 does not connect to any footprint pin. The contact end 54 of each via 52 includes a metal or other conductive contact member 55 provided along the surface of the via, extending within the PCB 4 to an appropriate depth in a selected layer for connection with a conductive trace 70. The traces 70 of the different vias 52 may be located at different depths and / or different layers within the PCB 4, wherein, during operation of the device 2, these traces facilitate the transmission of signals (e.g., Tx and Rx signals) between the components of the PCB 4 and the surface mount connector 100. The non-contact end 56 of the via 52 may be drilled back to an appropriate / selected depth (e.g., so that no electrical contacts extend within the via to the non-contact end 56).

[0028] like Figure 2A and Figure 2B As depicted, the grid 50 comprises four linear rows of footprint pins 60, each row including two pairs (or a total of four) of Tx footprint pins and two pairs (or a total of four) of Rx footprint pins. The Tx footprint pins 60(Tx) in each row are oriented in the same direction from their adjacent and electrically contacting ends 62 of their corresponding Tx vias 52(Tx) towards their free ends 64. Similarly, the Rx footprint pins 60(Rx) in each row are oriented in the same direction from their adjacent and electrically contacting ends 62 of their corresponding Rx vias 52(Rx) towards their free ends 64. Each Tx footprint pin 60(Tx) within each row is also positioned 180° opposite to each Rx footprint pin 60(Rx) within the same row. Thus, the tapered free end 64 of the Tx footprint pin 60 (Tx) lies on the top or bottom surface of the PCB along a linear path corresponding to the end 62 of the Rx footprint pin 60 (Rx), and the tapered free end 64 of the Rx footprint pin 60 (Rx) lies on the top or bottom surface of the PCB along a linear path corresponding to the end 62 of the Tx footprint pin 60 (Tx). In other words, the linear rows of grid 50 include Tx pairs of Tx footprint pins 60 (Tx) and Rx pairs of Rx footprint pins 60 (Rx) (where each pair of footprint pins includes two footprint pins arranged adjacent to each other in the row), and the free end 64 of each Tx footprint pin 60 (Tx) in the Tx pair extends along the PCB in a first direction, and the free end 64 of each Rx footprint pin 60 (Rx) in the Rx pair extends along the PCB in a second direction, and the first direction and the second direction are 180° opposite.

[0029] The Tx and Rx footprint pins, aligned along the rows of grid 50 on the top surface 10 and bottom surface 20 of the PCB, facilitate belly-to-belly configuration of the surface mount connector 100 on either side of the PCB 4, while maintaining alignment of the connector's SMT pins 110 with the Tx footprint pins 60 (Tx) and Rx footprint pins 60 (Rx), as shown. Figure 3A , Figure 3B and Figure 4 As depicted in [the description]. Specifically, each SMT pin 110 of the surface mount connector 100 has a generally L-shape, which includes a free, generally flat terminal portion or tail member 112 of the pin that contacts the footprint pin 60 of the via 52, and the shape also includes an upwardly extending portion or head member 114 that connects to the SMT pin 110 within the connector. The orientation of each SMT pin 110 of the surface mount connector 100 is arranged in the same manner, with its tail member 112 extending outward from its head member 114 in the same direction. The connector orientation is also configured such that the tail member 112 of each SMT pin 110 that engages / electrically connects to the Tx footprint pin 60 (Tx) extends toward the Tx via 52 (Tx), while the tail member 112 of each SMT pin 110 that engages / electrically connects to the Rx footprint pin 60 (Rx) extends outward from the Rx via 52 (Rx). Figure 1A and Figure 4 As further depicted, each connector 100 connected to the PCB 4 in a belly-to-belly configuration along the top surface 10 and bottom surface 20 is aligned in the same direction (i.e., the tail members 112 of both connectors 100 extend in the same direction). In other words, the connectors 100 in the belly-to-belly configuration are oriented in a 180° rotational position relative to each other, but their SMT pins 110 extend in the same direction.

[0030] Refer again Figure 2A and Figure 2B Due to the configuration of the footprint pins and vias of each grid 50, the rows of footprint pins 60 of the grid 50 on the top surface 10 of PCB 4 are displaced or offset by the pin width in the linear direction of the rows relative to the rows of footprint pins 60 of the grid 50 on the bottom surface 10 of the PCB that share vias with the top surface grid. In other words, each linear row of footprint pins and vias of the top surface grid is offset by the footprint pin width in the linear direction of the linear row relative to the corresponding linear row of footprint pins and vias of the bottom surface grid that shares vias with the top surface grid. This causes the connectors 100 to be displaced or offset relative to each other by the same pin width distance in a belly-to-belly configuration (so that the SMT pins 110 of the connector 100 are aligned to engage / connect with the corresponding footprint pins 60).

[0031] Minimizing return loss in the footprint pins 60 of the grid 50 enables high-speed data transmission (e.g., 400GbE data transmission). The footprint pins 60 can have any size configured to properly mate with the tail member 112 of the SMT pin 110. The contact area between the footprint pins 60 and the tail member 112 of the SMT pin 110 can have a generally rectangular shape. In one example embodiment, each footprint pin 60 can have a width of approximately 0.35 mm (tapering until it tapers at the free end 64) and a length of approximately 1.6 mm.

[0032] The current flow from SMT pin 110 to the corresponding via 52 and the contact area between tail member 112 and footprint pin 60 acts as a stub, wherein the stub length configured in the Tx and Rx configurations between the surface mount connector and the PCB is within Figure 3A and Figure 3B As shown in the diagram. This configuration of the connection between the tail member 112 of the SMT pin 110 and the Tx footprint pin 60 (Tx) is desirable because, for this configuration, the current flow path through the head member 114 of the SMT pin 110 and through the contact area between the tail member 112 and the footprint pin 60 is minimized (e.g., Figure 3A and Figure 3B As shown in the comparison of the directions, the stub length SL1 associated with the Tx current flow path is less than the stub length SL2 of the Rx current flow path. This orientation is particularly beneficial for reducing the stub length and signal loss of the Tx channel, as the Tx channel is typically more sensitive to return loss during signal transmission. In an example embodiment using a QSFP-DD connector and a grid 50 sized to connect to the SMT pins of such a connector, the stub length of the Tx channel (the connection between the SMT pins and the Tx footprint pins and Tx vias) can be minimized to approximately 20 mil, while the stub length of the Rx channel (the connection between the SMT pins and the Rx footprint pins and Rx vias) is approximately 40 mil or approximately twice that length.

[0033] The orientation of the Tx and Rx channels along the PCB surface within the grid allows for optimal Tx performance during high-speed data signal communication between Device 2 and other devices. In high-speed signal transmission operations, each Tx and Rx channel can operate at speeds up to 53 Gbps. At such signal speeds, even small impedance fluctuations can cause unwanted signal loss and other problems. The via and footprint pin configuration of grid 50, as described herein, effectively controls impedance and minimizes reflections. Furthermore, since Tx performance is often a bottleneck in high-speed data communication (e.g., for 400G optical compliance testing), minimizing the stub length of the Tx signal transmission channels provides reduced signal reflections, resulting in better Tx signal quality during high-speed data communication.

[0034] In addition to providing a minimized stub length to reduce Tx signal reflections, PCB grids with specified via footprints and Tx / Rx footprint pin orientations offer other advantages for enhanced high-speed data signal communication between devices.

[0035] For example, PCB mesh configurations allow surface mount connectors to be connected belly-to-belt to the PCB (e.g., Figure 1A (As shown) this improves the routeability of data signals. The pitch size of a standard or conventional QSFP-DD connector (center-to-center distance between two adjacent footprint pins 60 on PCB 4) is 31.5 mil. The PCB vias and footprint pin grid 50, as described herein, enable free routeability, with no limitations on the design of Tx and Rx pairs, and each differential pair can utilize the upper and lower routing channels. Reference Figure 5A and Figure 5B An example of the escape / routing route of the traces 70 of the Tx via 52 (Tx) and Rx via 52 (Rx) pairs along the top and bottom PCB surfaces is depicted. Figure 5A The top surface traces are shown in the diagram. Figure 5B The diagram shows the bottom surface trace routing. Due to the optimized arrangement of Tx and Rx pins and vias along both surfaces of the PCB, the trace routing can be configured within a single layer of the PCB, thus requiring a minimal number of routing PCB layers for this footprint design. Alternatively, depending on the specific application, traces can be routed across two or more layers.

[0036] Antipad configurations can further enhance the PCB footprint, pin and via mesh arrangement, by providing impedance control optimized during signal transmission operations. Antipads include gaps, spaces, voids, or cut-out holes in layers surrounding or located around vias. (Reference) Figures 6A-6CThe image depicts different PCB layers adjacent to the top or bottom surface, showing the pad configurations around vias. The size or dimensions of these pad configurations vary depending on whether the corresponding via is electrically connected to a footprint pin. Figure 6A The outer top layer 4A and Figure 6B A cut-off design is shown in each of the bottom 4B layers (e.g., the G02 layer). To control impedance, the shape of the voids in the ground (GND) layer is designed to minimize pin capacitance. Figure 6A Layer 4A provides a cut-off region 30, in Figure 6B The corresponding excision region 32 is provided in the bottom layer 4B. (Reference) Figure 6C Another PCB layer 4C is shown, indicating that two pad sizes are used for all PCB layers from the top surface to the bottom surface of the PCB. Figure 6C The PCB layer 4C depicted can be a signal layer, where Tx and / or Rx traces are routed within PCB 4. For PCB layers with vias passing through to connect to the traces (e.g., as shown in the image), this also applies. Figures 6A-6C The via 52 (Tx) shown herein has a first cross-sectional dimension (e.g., a diameter of 32 mil) suitable for achieving optimized impedance control for signal transmission using the via. For layers where the via is drilled back (i.e., layers adjacent to the non-contact end 56 of the via), the reverse pad 42 has a second cross-sectional dimension (e.g., a diameter of 26 mil), smaller than the first dimension. This smaller second dimension of the reverse pad 42 at these layers facilitates sufficient routing channel width within the signal layers associated with such reverse pads. Thus, unlike conventional designs utilizing reverse pads of a single size, the various reverse pad configurations for the different layers of PCB 4 described herein can have different sizes (e.g., smaller reverse pad sizes in layers with drilled-back via portions and larger reverse pad sizes for via portions in layers without drilled-back portions) to provide easy routing of contact areas for the SMT pins of mating connectors and for routing traces within the PCB.

[0037] Another advantage of the via footprint configuration of the grid 50 on the top and bottom surfaces of the PCB, as described herein, is that it minimizes signal crosstalk between the footprint pins on the PCB surface and the traces arranged within the PCB. The footprint pins 60 can be evenly spaced (e.g., ...). Figure 2A and Figure 2B As shown), a routing path is formed, in which signal contacts and ground contacts are arranged in a pattern to reduce crosstalk. See, for example... Figure 5A and Figure 5BA routing channel is defined between two adjacent rows of vias, along which the Tx and Rx traces are routed. The routing channel width can be appropriately sized to minimize crosstalk between vias (e.g., the routing channel width could be approximately 32 mil). To mitigate crosstalk between vias, the routing of the traces can be configured as follows (e.g., ...). Figure 5A and Figure 5B As shown, this means that only one attacker's Tx or Rx pair (adjacent pairs in the same row) could introduce crosstalk interference. Figure 5A and Figure 5B As depicted in the trace path diagram, the first pair of Tx or Rx traces is routed along the routing channel along a first side of a row of vias, opposite to the second side of the row. A second pair of Tx or Rx traces from the same row is routed from this second side. The routing channel size, and the routing configuration that routes only a single Tx or Rx trace pair in each routing channel, effectively minimizes trace-to-layer crosstalk and via-to-trace crosstalk.

[0038] Thus, PCB via designs in which Tx and Rx contacts / pads are arranged in an array or grid on each of the top and bottom PCB surfaces facilitate belly-to-belly connection configurations using, for example, SMT QSFP-DD connectors. The combination of PCB footprint pin design, configuration, and via design, configuration, and arrangement to form a grid, along with the via and Tx and Rx routing reverse pad design within one or more layers of the PCB, also enhances efficient high-speed signal transmission, for example, for enhanced high-speed data communication (e.g., 400GbE and above), and provides a high-density, low-crosstalk, ultra-compact footprint design for connection to surface-mount connectors on the device's PCB.

[0039] Thus, an example embodiment of a printed circuit board (PCB) includes a grid comprising a plurality of footprint pins and a plurality of vias arranged along one or more linear rows. Each footprint pin is disposed on a top or bottom surface of the PCB, and each via extends through the PCB to both the top and bottom surfaces. Each footprint pin is elongated and includes a connected end and a free end opposite to the connected end. Each via includes a contact end located on one of the top and bottom surfaces and electrically contacting the connected end of one of the plurality of footprint pins. Each via also includes a non-contact end located on the other of the top and bottom surfaces and not electrically contacting any of the plurality of footprint pins. Furthermore, each linear row includes a first pair and a second pair of the plurality of footprint pins, each of the first and second pairs comprising two footprint pins arranged adjacent to each other in the linear row; the free ends of each footprint pin in the first pair extend along the PCB in a first direction, and the free ends of each footprint pin in the second pair extend along the PCB in a second direction, the first and second directions being 180° opposite each other.

[0040] The non-contact end of each via on the PCB can be drilled back to a selected depth within the PCB. Furthermore, the free end of each footprint pin can be tapered, such that the first width dimension of the free end is smaller than the second width dimension of the other longitudinal portions along the footprint pin. At least some of the free ends of the footprint pins can be arranged between two vias arranged along a linear row.

[0041] The PCB grid may include four linear rows of footprint pins and vias. For example, each linear row may include two pairs of transmitter (Tx) footprint pins that facilitate signal transmission from the PCB to a connector connected to the transmitter (Tx) footprint pins, and each linear row may also include two pairs of receiver (Rx) footprint pins that facilitate signal reception from a connector connected to the receiver (Rx) footprint pins, wherein the free ends of the transmitter (Tx) footprint pins in each row extend in a first direction and the free ends of the receiver (Rx) footprint pins in each row extend in a second direction.

[0042] The PCB may include a first grid disposed on the top surface of the PCB and a second grid disposed on the bottom surface of the PCB, wherein vias (extending through the PCB) are located within the first and second grids. Each of the first and second grids includes multiple line rows of footprint pins and vias, and each line row of the first grid is aligned with a corresponding line row of the second grid. Additionally, each line row of footprint pins in the first grid may be offset by the footprint pin width in the linear direction of the line row relative to a corresponding line row of footprint pins in the second grid.

[0043] The PCB may include multiple layers, wherein anti-particle pads are located around vias within each layer, and the cross-sectional dimensions of the anti-particle pads vary across different layers for at least one via. Anti-particle pads located at the contact end of at least one via may have a larger cross-sectional dimension than anti-particle pads located at the non-contact end of that at least one via.

[0044] In another example embodiment, an electronic device includes a printed circuit board (PCB) and first and second surface mount connectors. The PCB may include a first grid disposed on a top surface of the PCB and a second grid disposed on a bottom surface of the PCB. Each of the first and second grids includes a plurality of conductive footprint pins and a plurality of vias, the footprint pins and vias being arranged along one or more linear rows at each of the first and second grids. Each via may extend through the PCB to both the top and bottom surfaces of the PCB, such that each via is part of the first and second grids. Each footprint pin may be elongated and include a connecting end and a free end opposite the connecting end. Each via may include a contact end located at one of the first and second grids and electrically contacting the connecting end of one of the plurality of footprint pins. Each via may also include a non-contact end located at the other of the first and second grids and not electrically contacting any of the plurality of footprint pins. Each linear row of the first and second grids may include a first pair and a second pair of the plurality of footprint pins, wherein each of the first and second pairs includes two footprint pins arranged adjacent to each other in the linear row. The free end of each footprint pin in the first pair can extend along the PCB in a first direction, and the free end of each footprint pin in the second pair can extend along the PCB in a second direction, such that the first direction and the second direction are 180° opposite. A first surface mount connector can be mounted to the top surface of the PCB and includes surface mount pins that connect to the footprint pins of the first grid, and a second surface mount connector can be mounted to the bottom surface of the PCB and includes surface mount pins that connect to the footprint pins of the second grid.

[0045] The non-contact end of each via in the first and second grids of the electronic device can be drilled back to a selected depth within the PCB. Furthermore, the free end of each footprint pin in the first and second grids can be tapered, such that the first width dimension of the free end is smaller than the second width dimension along the other longitudinal portions of the footprint pin. Additionally, at least some of the free ends of the footprint pins in the first and second grids can be arranged between two vias arranged in a linear row along which each footprint pin is disposed.

[0046] Each of the first and second grids of the electronic device may include four linear rows. For example, each linear row may include two pairs of transmitter (Tx) footprint pins that facilitate signal transmission from the PCB to corresponding surface mount pins of a first or second surface mount connector connected to the transmitter (Tx) footprint pins, and each linear row may also include two pairs of receiver (Rx) footprint pins that facilitate signal reception from surface mount pins of a first or second surface mount connector connected to the receiver (Rx) footprint pins, wherein the free ends of the transmitter (Tx) footprint pins in each row extend in a first direction and the free ends of the receiver (Rx) footprint pins in each row extend in a second direction.

[0047] Each line row of the first grid can be aligned with a corresponding line row of the second grid, and each line row of the footprint pins of the first grid can be offset in the line direction of the line row relative to the corresponding line row of the footprint pins of the second grid, such that the first surface mount connector mounted to the top surface is offset in the line direction relative to the second surface mount connector mounted to the bottom surface.

[0048] In another example embodiment, a method includes providing an electronic device including a printed circuit board (PCB), wherein the PCB includes a first grid disposed on a top surface of the PCB and a second grid disposed on a bottom surface of the PCB, each of the first and second grids including a plurality of conductive footprint pins and a plurality of vias, the plurality of footprint pins and the plurality of vias being arranged along one or more linear rows at each of the first and second grids. Each via is permissible through the PCB extending to both the top and bottom surfaces of the PCB, such that each via is part of the first and second grids. Each footprint pin may be elongated and includes a connecting end and a free end opposite to the connecting end. Each via may include a contact end located at one of the first and second grids and electrically contacting the connecting end of one of the plurality of footprint pins, and each via may also include a non-contact end located at the other of the first and second grids and not electrically contacting any of the plurality of footprint pins. Each linear row of the first and second grids may include a first pair and a second pair of the plurality of footprint pins, each of the first pair and the second pair including two footprint pins arranged adjacent to each other in the linear row. The free end of each footprint pin in the first pair can extend along the PCB in a first direction, and the free end of each footprint pin in the second pair can extend along the PCB in a second direction, such that the first direction and the second direction are 180° opposite. A first surface mount connector can be mounted to the top surface of the PCB such that the surface mount pins of the first surface mount connector are connected to the footprint pins of the first grid, and a second surface mount connector can be mounted to the bottom surface of the PCB such that the surface mount pins are connected to the footprint pins of the second grid.

[0049] In this method, each linear row may include two pairs of transmitter (Tx) footprint pins that facilitate signal transmission from the PCB to corresponding surface mount pins of a first or second surface mount connector connected to the transmitter (Tx) footprint pins, and each linear row may also include two pairs of receiver (Rx) footprint pins that facilitate signal reception from surface mount pins of the first or second surface mount connector connected to the receiver (Rx) footprint pins, wherein the free ends of the transmitter (Tx) footprint pins in each row extend in a first direction and the free ends of the receiver (Rx) footprint pins in each row extend in a second direction.

[0050] In this method, each line row of footprint pins of the first grid can be aligned with a corresponding line row of footprint pins of the second grid, and each line row of footprint pins of the first grid can be offset in the line direction of the line row relative to a corresponding line row of footprint pins of the second grid, such that the first surface mount connector mounted to the top surface is offset in the line direction relative to the second surface mount connector mounted to the bottom surface.

[0051] The above description is intended to be illustrative only. The description of various embodiments is for illustrative purposes only and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best describe the principles of the embodiments, their practical application, or technical improvements relative to technologies available in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A printed circuit board (PCB), comprising: A grid comprising multiple footprint pins and multiple vias arranged along one or more linear rows, each footprint pin being disposed on the top or bottom surface of the PCB, and each via extending through the PCB to both the top and bottom surfaces of the PCB, wherein: Each footprint pin is elongated and includes a connecting end and a free end opposite to that connecting end; Each through-hole includes a contact end located at one of the top surface and the bottom surface and electrically in contact with a connection end of one of the plurality of footprint pins, and each through-hole also includes a non-contact end located at the other of the top surface and the bottom surface and not electrically in contact with any of the plurality of footprint pins; Each linear row includes a first pair and a second pair of the plurality of footprint pins, each of the first pair and the second pair including two footprint pins arranged adjacent to each other in the linear row; and The free end of each footprint pin of the first pair extends along the PCB in a first direction, and the free end of each footprint pin of the second pair extends along the PCB in a second direction, wherein the first direction and the second direction are 180° opposite.

2. The PCB as described in claim 1, wherein, The non-contact end of each through-hole is drilled back to a selected depth within the PCB.

3. The PCB as described in claim 1 or 2, wherein, The free end of each footprint pin is tapered, such that the first width dimension of the free end is smaller than the second width dimension along the other longitudinal portions of the footprint pin.

4. The PCB as described in claim 1, wherein, At least some of the free ends of the footprint pins are arranged between two through holes arranged along a linear row.

5. The PCB as described in claim 1, wherein, The grid comprises four linear rows of footprint pins and through holes.

6. The PCB as described in claim 5, wherein, Each linear row includes two pairs of transmitter Tx footprint pins that facilitate signal transmission from the PCB to a surface mount connector connected to the transmitter Tx footprint pins, and each linear row also includes two pairs of receiver Rx footprint pins that facilitate signal reception from a surface mount connector connected to the receiver Rx footprint pins, wherein the free ends of the transmitter Tx footprint pins in each row extend in the first direction and the free ends of the receiver Rx footprint pins in each row extend in the second direction.

7. The PCB as described in claim 1, wherein, The PCB includes a first grid disposed on the top surface of the PCB and a second grid disposed on the bottom surface of the PCB. The vias are located within the first grid and the second grid. Each of the first grid and the second grid includes a plurality of linear rows of footprint pins and vias, and each linear row of the first grid is aligned with a corresponding linear row of the second grid.

8. The PCB as described in claim 7, wherein, Each line row of footprint pins and vias in the first grid is offset by the footprint pin width relative to the corresponding line row of the second grid in the linear direction of that line row.

9. The PCB as described in claim 1, wherein, The PCB comprises multiple layers, wherein anti-padded pads are located around vias in each layer, and the cross-sectional dimensions of the anti-padded pads vary in different layers for at least one via.

10. The PCB as claimed in claim 9, wherein, The reverse pad located at the contact end of the at least one through hole has a larger cross-sectional dimension than the reverse pad located at the non-contact end of the at least one through hole.

11. An electronic device, comprising: Printed circuit boards (PCBs) include: A first grid is disposed on the top surface of the PCB and a second grid is disposed on the bottom surface of the PCB. Each of the first grid and the second grid includes: a plurality of footprint pins and a plurality of through-holes, the plurality of footprint pins and the plurality of through-holes being arranged along one or more linear rows at each of the first grid and the second grid. Each through-hole extends through the PCB to both the top and bottom surfaces of the PCB, such that each through-hole is part of both the first grid and the second grid, wherein: Each footprint pin is elongated and includes a connecting end and a free end opposite to that connecting end; Each via includes a contact end located at one of the first grid and the second grid and electrically in contact with a connection end of one of the plurality of footprint pins, and each via also includes a non-contact end located at the other of the first grid and the second grid and not electrically in contact with any of the plurality of footprint pins; Each line row of the first grid and the second grid includes a first pair and a second pair of the plurality of footprint pins, each of the first pair and the second pair including two footprint pins arranged adjacent to each other in the line row; and The free end of each footprint pin of the first pair extends along the PCB in a first direction, and the free end of each footprint pin of the second pair extends along the PCB in a second direction, wherein the first direction and the second direction are 180° opposite. A first surface mount connector is mounted to the top surface of the PCB and includes surface mount pins that connect to the footprint pins of the first grid; and A second surface mount connector is mounted to the bottom surface of the PCB and includes surface mount pins that connect to the footprint pins of the second grid.

12. The electronic device of claim 11, wherein, The non-contact ends of each through-hole in the first and second grids are drilled back to a selected depth within the PCB.

13. The electronic device of claim 12, wherein, The free end of each footprint pin in the first and second grids is tapered, such that the first width dimension of the free end is smaller than the second width dimension along the other longitudinal portion of the footprint pin.

14. The electronic device of claim 13, wherein, At least some of the free ends of the footprint pins of the first grid and the second grid are arranged between two through holes arranged along a linear row of each footprint pin.

15. The electronic device according to any one of claims 11 to 14, wherein, Each of the first grid and the second grid comprises four linear rows.

16. The electronic device of claim 15, wherein, Each linear row includes two pairs of transmitter Tx footprint pins that facilitate signal transmission from the PCB to corresponding surface mount pins of the first or second surface mount connector connected to the transmitter Tx footprint pins, and each linear row also includes two pairs of receiver Rx footprint pins that facilitate signal reception from surface mount pins of the first or second surface mount connector connected to the receiver Rx footprint pins, wherein the free ends of the transmitter Tx footprint pins in each row extend in the first direction and the free ends of the receiver Rx footprint pins in each row extend in the second direction.

17. The electronic device of claim 15, wherein, Each line row of footprint pins of the first grid is aligned with a corresponding line row of footprint pins of the second grid, and each line row of footprint pins of the first grid is offset in the line direction of the line row relative to a corresponding line row of footprint pins of the second grid, such that the first surface mount connector mounted to the top surface is offset in the line direction relative to the second surface mount connector mounted to the bottom surface.

18. A communication method, comprising: Provide an electronic device including a printed circuit board (PCB), said PCB comprising: A first grid is disposed on the top surface of the PCB and a second grid is disposed on the bottom surface of the PCB. Each of the first grid and the second grid includes a plurality of footprint pins and a plurality of through-holes. The plurality of footprint pins and the plurality of through-holes are arranged in one or more linear rows at each of the first grid and the second grid. Each through-hole extends through the PCB to both the top and bottom surfaces of the PCB, such that each through-hole is part of both the first grid and the second grid, wherein: Each footprint pin is elongated and includes a connecting end and a free end opposite to that connecting end; Each via includes a contact end located at one of the first grid and the second grid and electrically in contact with a connection end of one of the plurality of footprint pins, and each via also includes a non-contact end located at the other of the first grid and the second grid and not electrically in contact with any of the plurality of footprint pins; Each line row of the first grid and the second grid includes a first pair and a second pair of the plurality of footprint pins, each of the first pair and the second pair including two footprint pins arranged adjacent to each other in the line row; and The free end of each footprint pin of the first pair extends along the PCB in a first direction, and the free end of each footprint pin of the second pair extends along the PCB in a second direction, wherein the first direction and the second direction are 180° opposite. A first surface mount connector is mounted to the top surface of the PCB such that the surface mount pins of the first surface mount connector are connected to the footprint pins of the first grid; and The second surface mount connector is mounted to the bottom surface of the PCB such that the surface mount pins are connected to the footprint pins of the second grid.

19. The method of claim 18, wherein, Each linear row includes two pairs of transmitter Tx footprint pins that facilitate signal transmission from the PCB to corresponding surface mount pins of the first or second surface mount connector connected to the transmitter Tx footprint pins, and each linear row also includes two pairs of receiver Rx footprint pins that facilitate signal reception from surface mount pins of the first or second surface mount connector connected to the receiver Rx footprint pins, wherein the free ends of the transmitter Tx footprint pins in each row extend in the first direction and the free ends of the receiver Rx footprint pins in each row extend in the second direction.

20. The method of claim 18 or 19, wherein, Each line row of footprint pins of the first grid is aligned with a corresponding line row of footprint pins of the second grid, and each line row of footprint pins of the first grid is offset in the line direction of the line row relative to a corresponding line row of footprint pins of the second grid, such that the first surface mount connector mounted to the top surface is offset in the line direction relative to the second surface mount connector mounted to the bottom surface.

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