A memory cell detection method and detection circuit

Abstract

The application relates to a detection method and a detection circuit of a storage unit. The detection method of the storage unit comprises the following steps: before packaging a storage block, one end of a word line and one end of a bit line of an edge unit of the storage block are connected with input ends of built-in self-test logic circuits through first amplifiers and second amplifiers respectively; a measurement voltage or a measurement current is applied to the word line and the bit line connected with the built-in self-test logic circuits; and a measurement result of the edge unit is output through output ends of the built-in self-test logic circuits. The one end of the word line and the one end of the bit line located at the edge unit of the storage block are connected with the input ends of the built-in self-test logic circuits through the first amplifiers and the second amplifiers respectively, then the measurement voltage or the measurement current is applied, and the measurement result is output through the output ends of the built-in self-test logic circuits, so that the performance of the storage block can be detected without affecting the storage unit, the method is convenient, and the product yield and product cost are not affected.

Description

Technical Field

[0001] This application relates to the field of memory technology, and specifically to a method and circuit for detecting memory cells. Background Technology

[0002] As DRAM memory cell sizes shrink and operating voltages decrease, the distribution of memory cells significantly impacts product performance, and measurements taken from surrounding areas fail to reflect the product's characteristics. Adjusting the substrate's body bias is necessary to minimize the influence of cell distribution. Cell characteristics are measured via scribe lanes, and the DRAM block's characteristics are adjusted based on these measurements. However, measurements taken in scribe lanes cannot fully capture the product's features. Furthermore, with the miniaturization of semiconductor processes, various unforeseen factors can cause inconsistencies between characteristics measured in scribe lanes and those of surrounding products. Because measuring actual product characteristics requires very high precision, existing testing methods increase the testing time required for adjusting product characteristics, thereby increasing costs.

[0003] Measuring the characteristics of memory cells within a product is difficult. To directly measure the performance of DRAM memory cells within the product, it is necessary to modify or add peripheral circuitry, but such modifications or additions are very difficult to implement and cannot be achieved.

[0004] Existing technologies can measure the characteristics of storage cells inside a product, but this testing method has a high probability of damaging the storage cell being measured, affecting the product yield. Therefore, it is necessary to repair the storage cell being measured to make it a redundant memory cell, which increases costs.

[0005] Therefore, there is a need for a method and circuit for detecting memory cells that can detect memory cells without affecting product yield and cost. Summary of the Invention

[0006] To address the aforementioned problems, this application provides a method for detecting memory cells, comprising the following steps: before packaging the memory block, connecting one end of the word line and one end of the bit line of the edge cell of the memory block to the input terminal of a built-in self-test logic circuit via a first amplifier and a second amplifier, respectively; applying a measurement voltage or measurement current to the word line and bit line connected to the built-in self-test logic circuit; and outputting the measurement result of the edge cell through the output terminal of the built-in self-test logic circuit.

[0007] To address the aforementioned problems, this application provides a method for detecting memory cells, comprising the following steps: before packaging the memory block, connecting one end of the word line and one end of the bit line of the edge cell of the memory block to a signal amplifier, wherein the output of the signal amplifier is connected to the input of a built-in self-test logic circuit; and the output of the built-in self-test logic circuit outputs the measurement result of the edge cell.

[0008] To address the aforementioned problems, this application also provides a memory cell detection circuit for detecting memory cells with built-in self-test logic circuits. The memory cell detection circuit uses the aforementioned memory cell detection method to detect memory cells in a memory block. The memory cell detection circuit includes: a first amplifier and a second amplifier; the input terminal of the first amplifier is connected to one end of the word line of the edge cell in the memory block to be detected; the input terminal of the second amplifier is connected to one end of the bit line of the edge cell in the memory block to be detected; the output terminals of both the first amplifier and the second amplifier are connected to the built-in self-test logic circuit of the memory cell.

[0009] To address the aforementioned problems, this application also provides a memory cell detection circuit for detecting memory cells with built-in self-test logic circuits. The memory cell detection circuit uses the aforementioned memory cell detection method to detect memory cells within a memory block. The memory cell detection circuit includes: a signal amplifier; the input terminal of the signal amplifier is connected to one end of the word line of the edge cell in the memory block to be detected and one end of the bit line of the edge cell in the memory block to be detected; the output terminal of the signal amplifier is connected to the built-in self-test logic circuit of the memory cell.

[0010] The advantages of this application are as follows: one end of the word line and one end of the bit line located at the edge cell of the memory block are connected to the input terminal of the built-in self-test logic circuit through the first amplifier and the second amplifier, respectively. Then, a measurement voltage or measurement current is applied to the word line and bit line connected to the built-in self-test logic circuit, and the measurement result is output through the output terminal of the built-in self-test logic circuit. The performance of the memory block can be tested without affecting the memory cell. The method is convenient and does not affect the product yield or the product cost. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0012] Figure 1A schematic diagram of an existing DRAM memory block is shown;

[0013] Figure 2 A schematic diagram of the detection circuit of the storage cell according to an embodiment of this application is shown;

[0014] Figure 3 A schematic diagram of a detection circuit for another storage cell according to an embodiment of this application is shown;

[0015] Figure 4 A schematic diagram illustrating the steps of a method for detecting a storage cell according to an embodiment of this application is shown;

[0016] Figure 5 A schematic diagram illustrating the steps of a method for detecting another storage cell according to an embodiment of this application is shown. Detailed Implementation

[0017] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0018] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0019] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0020] Figure 1 This illustrates the circuitry of a memory cell in an existing DRAM memory block. (Example:) Figure 1As shown, in the DRAM memory block 100, the bit line DBL and word line DWL connected to the dummy cell 101 in the edge cell are both grounded. The bit line BL, which connects to memory cells other than the dummy cell, is connected to the S / A pad 104 for connecting the sense amplifier S / A. The edge cell 102 includes at least one column or row of memory cells at the edge of the memory block 100. The word line WL is connected to the gate of the memory cell, and the bit line BL is connected to the P-well of the memory cell. The edge cell 102 includes a dummy cell 101. The dummy cell 101 includes one column or row of memory cells at the outermost edge of the memory block.

[0021] If DRAM or merged DRAM logic (MDL) products have built-in self-test (BIST) logic, this BIST logic can be used to fine-tune product characteristics, thereby minimizing test time. Although the manufacturing cost per wafer increases gradually, the actual manufacturing cost of the product decreases due to the reduction in product size. However, regardless of product size, the test time for testing based on the product's operational instructions changes. Therefore, measuring the characteristics of memory cells and then fine-tuning based on the measurement results increases test time, thus increasing factors contributing to price increases. Fine-tuning using built-in self-test logic reduces factors contributing to product price increases.

[0022] Figure 2 A schematic diagram of a detection circuit for a memory cell according to an embodiment of this application is shown, such as... Figure 2As shown, the detection circuit for a memory cell is used to detect memory cells with built-in self-test logic circuit 203, and includes: a first amplifier 201 and a second amplifier 202. The input terminal of the first amplifier 201 is connected to one end of the word line WL of the edge cell 102 in the memory block 100 to be detected; the input terminal of the second amplifier 202 is connected to one end of the bit line BL of the edge cell 102 in the memory block 100 to be detected; the output terminals of the first amplifier 201 and the second amplifier 202 are both connected to the built-in self-test logic circuit 203 of the memory cell. An embodiment of this application provides a memory cell detection circuit for detecting memory cells with built-in self-test logic circuit 203. The edge cell 102 is at least one row or column of memory cells located at the edge of the memory block 100, and the edge cell 102 includes pseudo cells 101. Specifically, the first amplifier 201 is connected to one end of the word line DWL of the pseudo-cell 101 in the edge cell 102, and the second amplifier 202 is connected to one end of the bit line DBL of the pseudo-cell 101 in the edge cell 102. The detection circuit also includes a fuse 204 or an anti-fuse 205. The output of the built-in self-test logic circuit 203 is connected to the fuse 204 or the anti-fuse 205, and the measurement result is sent to the fuse 204 or the anti-fuse 205 for storage. The memory cell detection circuit uses the memory cell detection method to detect the memory cells in the memory block 100.

[0023] Figure 3 A schematic diagram showing a detection circuit for another memory cell according to an embodiment of this application is shown, as follows. Figure 3 As shown, the detection circuit for the memory cell includes a signal amplifier (sense amplifier S / A) 206. The input of the signal amplifier 206 is connected to one end of the word line WL of the edge cell 102 in the memory block 100 to be tested and one end of the bit line BL of the edge cell 102 in the memory block 100 to be tested. The output of the signal amplifier 206 is connected to the built-in self-test logic circuit 203 of the memory cell. The edge cell 102 is at least one row or column of memory cells located at the edge of the memory block 100, and the edge cell 102 includes pseudo-cells 101. Specifically, the input of the signal amplifier 206 is connected to one end of the word line DWL of the pseudo-cell 101 in the edge cell 102, and the input of the signal amplifier 206 is also connected to one end of the bit line DBL of the pseudo-cell 101 in the edge cell 102. The detection circuit also includes a fuse 204 or an anti-fuse 205. The output of the built-in self-test logic circuit 203 is connected to fuse 204 or antifuse 205 to send the measurement result to fuse 204 or antifuse 205 for storage. The memory cell detection circuit uses the memory cell detection method to detect the memory cells in memory block 100.

[0024] Figure 4A method for detecting memory cells is illustrated. An example method begins at operation 401, where, before encapsulating memory block 100, one end of the word line WL and one end of the bit line BL of the edge cells 102 of memory block 100 are connected to the input of a built-in self-test logic circuit 203 via a first amplifier 201 and a second amplifier 202, respectively. The edge cell 102 is at least one row or column of memory cells located at the edge of memory block 100, and includes pseudo-cells 101. Pseudo-cells 101 include one row and / or one column of memory cells at the outermost edge of memory block 100. Specifically, the first amplifier 201 is connected to one end of the word line DWL of pseudo-cell 101, and the second amplifier 202 is connected to one end of the bit line DBL of pseudo-cell 101.

[0025] Continue with operation 402, applying a measurement voltage or current to the word line DWL and bit line DBL connected to the built-in self-test logic circuit 203. Continue with operation 403, outputting the measurement results of edge cell 102 through the output terminal of the built-in self-test logic circuit 203. The measurement results include: the characteristics of the gate dielectric film of edge cell 102, the characteristics of the channel transistor of edge cell 102, the characteristics of the pass transistor of the memory cell in memory block 100, the resistance value of bit line WL and / or the resistance value of word line BL.

[0026] The measurement results can also be stored in fuse 204 or antifuse 205. Based on the stored measurement results, the manufacturing process, performance parameters and testing methods of memory block 100 can be adjusted, and the manufacturing process of memory block 100 can be managed.

[0027] Figure 5 Another method for detecting memory cells is illustrated. The example method begins at operation 501, where, before encapsulating memory block 100, one end of the word line DWL and one end of the bit line BL of the edge cells 102 of memory block 100 are respectively connected to signal amplifier 206. The edge cells 102 are at least one row or column of memory cells located at the edge of memory block 100, and include pseudo cells 101. Pseudo cells 101 include the outermost row and / or column of memory cells of memory block 100. Specifically, signal amplifier 206 is connected to one end of the word line DWL of pseudo cells 101, and signal amplifier 206 is also connected to one end of the bit line DBL of pseudo cells 101.

[0028] Continue with operation 502, connecting the output of signal amplifier 206 to the input of built-in self-test logic circuit 203. Continue with operation 503, the output of built-in self-test logic circuit 203 outputs the measurement results of edge cell 102. The measurement results include: the characteristics of the gate dielectric film of edge cell 102, the characteristics of the channel transistor of edge cell 102, the characteristics of the transmission transistor of the memory cell in memory block 100, the resistance value of bit line WL and / or the resistance value of word line BL.

[0029] By directly amplifying the signals transmitted on the word line WL and bit line BL using signal amplifiers, the performance of the memory block can be tested without affecting the memory cells. This method is convenient, does not affect product yield or cost, and does not require additional components or amplifiers, resulting in low cost.

[0030] To minimize the impact of testing on the memory cells of the memory block (product) and thus affect actual use, the gate and / or P-well of the dummy cell, which are connected to ground, are electrically connected. This ensures that measurements of the dummy cell do not electrically affect the memory cells. By connecting the ground-connected gate and / or P-well of the dummy cell to the built-in self-test logic circuit, the characteristics of the memory cell are measured. Based on the measurement results, fine-tuning of the product performance is performed, and the results are stored in fuse 204 or anti-fuse 205. In this way, in the ROM (Read Only Memory), the built-in self-test logic circuit 203 is ultimately applied with a ground terminal or P-well voltage, thus not affecting product operation. Because the dummy cell 101 is located on the periphery of the memory cells, the distribution of the actually used memory cells is improved, and the electrical characteristics of the memory cells are not affected. By connecting the gate and / or P-well of the pseudo cell 101 connected to ground to the built-in self-test logic circuit 203 to measure the characteristics, the characteristics of the memory cell are accurately measured within the memory block 100, and measurement results that can accurately reflect the characteristics of the memory block 100 are obtained. Based on the measurement results, the fuse 204 or anti-fuse 205 stored in the product can be fine-tuned.

[0031] The method in this application connects one end of the word line and one end of the bit line located at the edge of the memory block to the input of a built-in self-test logic circuit via a first amplifier and a second amplifier, respectively. A measurement voltage or current is then applied to the word line and bit line connected to the built-in self-test logic circuit, and the measurement result is output through the output of the built-in self-test logic circuit. This method enables performance testing of the memory block without affecting the memory cell itself, is convenient, and does not affect product yield or cost. While the production cost of memory cells decreases with the miniaturization of semiconductor manufacturing processes, testing costs increase. The memory cell characteristic evaluation in this application is performed internally based on the built-in self-test logic circuit, reducing testing time and thus lowering costs. Fine adjustments are made to the built-in self-test logic circuit based on the measurement results.

[0032] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0033] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for detecting a storage cell, characterized in that, The steps include the following: Before encapsulating the memory block, one end of the word line and one end of the bit line of the edge cell of the memory block are connected to the input terminal of the built-in self-test logic circuit through the first amplifier and the second amplifier, respectively. A measurement voltage or measurement current is applied to the word lines and bit lines connected to the built-in self-test logic circuit. The measurement results of the edge unit are output through the output terminal of the built-in self-test logic circuit; After outputting the measurement result of the edge unit through the output terminal of the built-in self-test logic circuit, the following steps are also included: Based on the measured results of the storage, the manufacturing process, performance parameters, and testing methods of the storage block are adjusted; After outputting the measurement result of the edge unit through the output terminal of the built-in self-test logic circuit, the following steps are also included: The manufacturing process of the storage block is managed based on the measurement results of the storage. The measurement results of the edge cell include: the characteristics of the gate dielectric film of the edge cell, the characteristics of the channel transistor of the edge cell, the characteristics of the transmission transistor of the memory cell in the memory block, the resistance value of the bit line and / or the resistance value of the word line. The edge unit is at least one row or one column of storage units located at the edge of the storage block; After outputting the measurement result of the edge unit through the output terminal of the built-in self-test logic circuit, the following steps are also included: The measurement results are stored in a fuse or antifuse.

2. The method for detecting a storage cell according to claim 1, characterized in that, The edge unit includes: a pseudo unit.

3. The method for detecting a storage cell according to claim 2, characterized in that, One end of the word line of the edge unit includes: one end of the pseudo-unit word line; One end of the bit line of the edge unit includes: one end of the pseudo-unit bit line.

4. A method for detecting a storage cell, characterized in that, The steps include the following: Before encapsulating the memory block, one end of the word line and one end of the bit line of the edge cell of the memory block are respectively connected to the signal amplifier; Connect the output of the signal amplifier to the input of the built-in self-test logic circuit; The built-in self-test logic circuit outputs the measurement result of the edge unit. After outputting the measurement result of the edge unit through the output terminal of the built-in self-test logic circuit, the following steps are also included: Based on the measured results of the storage, the manufacturing process, performance parameters, and testing methods of the storage block are adjusted; After outputting the measurement result of the edge unit through the output terminal of the built-in self-test logic circuit, the following steps are also included: The manufacturing process of the storage block is managed based on the measurement results of the storage. The measurement results of the edge cell include: the characteristics of the gate dielectric film of the edge cell, the characteristics of the channel transistor of the edge cell, the characteristics of the transmission transistor of the memory cell in the memory block, the resistance value of the bit line and / or the resistance value of the word line. The edge unit is at least one row or one column of storage units located at the edge of the storage block; After outputting the measurement result of the edge unit through the output terminal of the built-in self-test logic circuit, the following steps are also included: The measurement results are stored in a fuse or antifuse.

5. A detection circuit for a memory cell, characterized in that, For detecting memory cells with built-in self-test logic circuitry, the detection circuitry of the memory cells uses a memory cell detection method according to any one of claims 1 to 3 to detect memory cells in a memory block, the memory cell detection circuitry comprising: a first amplifier and a second amplifier; The input terminal of the first amplifier is connected to one end of the word line of the edge cell in the memory block to be detected; The input terminal of the second amplifier is connected to one end of the bit line of the edge cell in the memory block to be tested; The output terminals of the first amplifier and the second amplifier are both connected to the built-in self-test logic circuit of the memory cell.

6. The detection circuit for a storage cell according to claim 5, characterized in that, Also includes: Fuse or anti-fuse; The fuse or antifuse is connected to the output terminal of the built-in self-test circuit.

7. A detection circuit for a memory cell, characterized in that, For detecting memory cells with built-in self-test logic circuitry, the detection circuitry of the memory cells uses a memory cell detection method according to claim 4 to detect memory cells in a memory block, the memory cell detection circuitry comprising: a signal amplifier; The input terminal of the signal amplifier is connected to one end of the word line of the edge cell in the memory block to be tested and one end of the bit line of the edge cell in the memory block to be tested. The output of the signal amplifier is connected to the built-in self-test logic circuit of the storage unit.

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