Multilayer capacitor, board for mounting multilayer capacitor, and method for manufacturing the same

Abstract

A multilayer capacitor, a board for mounting the multilayer capacitor, and a manufacturing method thereof are provided. The multilayer capacitor includes a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes, and a pair of external electrodes each including a conductive layer disposed on an opposite end of the capacitor body, a conductive resin layer covering the conductive layer, and a reduced graphene oxide (RGO) layer disposed between the conductive layer and the conductive resin layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0136814, filed on October 21, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to a multilayer capacitor and a plate for mounting the multilayer capacitor, as well as a method for manufacturing the same. Background Technology

[0003] Multilayer capacitors (or multilayer ceramic capacitors (MLCCs)) are compact, ensure high capacitance, and are easy to install.

[0004] In recent years, with the increasing demand for automotive electrical components and information technology (IT) fields, there has been a need to develop multilayer capacitors with stable mechanical properties and high reliability.

[0005] Here, in order to ensure the stable mechanical properties and reliability of the multilayer capacitor, a secondary external electrode including conductive resin is used. However, a lifting phenomenon may occur between the surface of the metal, which is the main component of the primary external electrode, and the interface of the secondary external electrode formed by conductive resin. Summary of the Invention

[0006] An exemplary embodiment provides a multilayer capacitor and a plate for mounting the multilayer capacitor, which can prevent lifting at the interface between the conductive layer and the conductive resin layer of the outer electrode.

[0007] According to an exemplary embodiment, a multilayer capacitor includes: a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes; and a pair of external electrodes, each including a conductive layer disposed on opposite ends of the capacitor body, a conductive resin layer covering the conductive layer, and a reduced graphene oxide (RGO) layer disposed between the conductive layer and the conductive resin layer.

[0008] The RGO layer can be continuously disposed on the conductive layer.

[0009] The RGO layer may have an island shape on the conductive layer.

[0010] The capacitor body may include a first surface and a second surface opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other. The internal electrode may include a first internal electrode and a second internal electrode. One end of the first internal electrode and one end of the second internal electrode are alternately exposed through the third surface and the fourth surface of the capacitor body, and are respectively connected to an external electrode disposed on the third surface and the fourth surface of the capacitor body. A dielectric layer may be disposed between the first internal electrode and the second internal electrode.

[0011] The pair of outer electrodes may also include a plating layer covering the conductive resin layer.

[0012] The plating may include a nickel plating covering the conductive resin layer and a tin plating covering the nickel plating.

[0013] The thickness of the reduced graphene oxide (RGO) layer can be greater than or equal to 1 nm and less than or equal to 50 nm.

[0014] According to an exemplary embodiment, a board for mounting a multilayer capacitor includes: a substrate having a pair of electrode pads spaced apart from each other on one surface of the substrate; and a multilayer capacitor mounted on the substrate, wherein the multilayer capacitor includes: a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes; and a pair of external electrodes, each including a conductive layer disposed on opposite ends of the capacitor body, a conductive resin layer covering the conductive layer, and a reduced graphene oxide (RGO) layer disposed between the conductive layer and the conductive resin layer and respectively connected to the pair of electrode pads.

[0015] According to an exemplary embodiment, a method of manufacturing a multilayer capacitor includes: forming a capacitor body comprising a plurality of dielectric layers and a first internal electrode and a second internal electrode; forming a conductive layer comprising a metal on the capacitor body to be connected to one of the first internal electrode and the second internal electrode; forming a coating layer comprising graphene oxide on the first conductive layer; forming a conductive resin layer covering the coating layer comprising graphene oxide; and performing a heat treatment on the coating layer comprising graphene oxide and the conductive resin layer.

[0016] A reduced graphene oxide (RGO) layer can be formed using the coating containing graphene oxide through the heat treatment.

[0017] The coating containing graphene oxide can be formed by spraying a graphene oxide solution. Attached Figure Description

[0018] The above and other aspects, features and advantages of the present invention will become more clearly understood by taking into account the accompanying drawings and the following detailed description, in which:

[0019] Figure 1 This is a schematic perspective view of a multilayer capacitor according to exemplary embodiments of the present disclosure;

[0020] Figures 2A to 2B These are respectively shown as applied to Figure 1 A three-dimensional view of the first and second internal electrodes of a multilayer capacitor.

[0021] Figure 3 It is along Figure 1 A cross-sectional view taken from line I-I';

[0022] Figure 4 This is a cross-sectional view showing a reduced graphene oxide (RGO) layer according to another exemplary embodiment of the present disclosure;

[0023] Figure 5 yes Figure 4 An enlarged cross-sectional view of part A;

[0024] Figure 6 It is shown Figure 3 A cross-sectional view of the coating further configured in the middle;

[0025] Figure 7 This is a schematic diagram showing the bonding structure of the conductive layer, the conductive resin layer, and the RGO layer; and

[0026] Figure 8 It is shown Figure 4 A schematic cross-sectional view of a multilayer capacitor mounted on a substrate. Detailed Implementation

[0027] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0028] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various modifications, variations, and equivalents of the methods, apparatus, and / or systems described herein will be readily apparent to those skilled in the art. The order of operations described herein is merely illustrative and is not limited to the order presented; changes that will be apparent to those skilled in the art may be made, except for operations that must occur in a specific order. Furthermore, for clarity and brevity, descriptions of functions and structures known to those skilled in the art may be omitted.

[0029] The features described herein may be implemented in various forms and are not to be construed as being limited to the examples described herein. Rather, the examples provided herein make this disclosure thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0030] Note, here, the use of the term “may” in relation to examples or embodiments. For example, regarding what an example or embodiment may include or implement, it means that there exists at least one example or embodiment that includes or implements such a feature, but all examples and embodiments are not limited thereto.

[0031] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on" another element, "connected to" another element, or "bonded to" another element, that element may be directly "on" another element, directly "connected to" another element, or directly "bonded to" another element, or there may be one or more other elements in between. In contrast, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bonded to" another element, there are no other elements in between.

[0032] As used in this way, the term "and / or" includes any one or any combination of any two or more of the relevant listed items.

[0033] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Therefore, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as the first component, first assembly, first region, first layer, or first part may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0034] For ease of description, spatial relative terms such as “above,” “above,” “below,” and “under” are used herein to describe the relationship between one element and another as shown in the accompanying drawings. Such spatial relative terms are intended to include not only the orientation depicted in the drawings but also different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as “above” or “above” relative to another element will then be “below” or “under” relative to said other element. Therefore, the term “above” includes both “above” and “below” orientations depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing various examples only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms “comprising,” “including,” and “having” enumerate the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0036] Due to manufacturing techniques and / or tolerances, variations in the shape shown in the accompanying drawings may occur. Therefore, the examples described herein are not limited to the specific shapes shown in the accompanying drawings, but include shape variations that occur during manufacturing.

[0037] The features of the examples described herein can be combined in a variety of ways that will become apparent upon understanding the disclosure of this application. Furthermore, while the examples described herein have multiple constructions, other constructions that will become apparent upon understanding the disclosure of this application are possible.

[0038] The accompanying drawings may be drawn off-scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of the elements in the drawings may be exaggerated.

[0039] In the following description, to illustrate exemplary embodiments of the present disclosure, the orientations of the capacitor body 110 shown in the drawings are defined as follows: the X direction, Y direction, and Z direction represent the length direction, width direction, and thickness direction of the capacitor body 110, respectively. Furthermore, in this exemplary embodiment, the Z direction can be used to have the same concept as the stacking orientation of the stacked dielectric layers.

[0040] Figure 1 This is a schematic perspective view of a multilayer capacitor according to exemplary embodiments of the present disclosure. Figures 2A to 2B These are respectively shown as applied to Figure 1 A three-dimensional view of the first and second internal electrodes of a multilayer capacitor, and Figure 3 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0041] Reference Figures 1 to 3 The multilayer capacitor 100 according to this exemplary embodiment includes a capacitor body 110, a first external electrode 130, and a second external electrode 140.

[0042] The capacitor body 110 is obtained by stacking multiple dielectric layers 111 in the Z direction and then sintering the stacked dielectric layers 111, and adjacent dielectric layers 111 of the capacitor body 110 can be integrated, making it difficult to distinguish the boundaries between them without using a scanning electron microscope (SEM).

[0043] Here, the capacitor body 110 may have a substantially hexahedral shape, but this disclosure is not limited thereto. Furthermore, the shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 are not limited to those shown in the figures of this exemplary embodiment.

[0044] In this exemplary embodiment, for ease of description, the two surfaces of the capacitor body 110 that are opposite to each other in the Z direction are defined as the first surface 1 and the second surface 2, the two surfaces connected to the first surface 1 and the second surface 2 and opposite to each other in the X direction are defined as the third surface 3 and the fourth surface 4, and the two surfaces connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and opposite to each other in the Y direction are defined as the fifth surface 5 and the sixth surface 6.

[0045] In addition, in this exemplary embodiment, the mounting surface of the multilayer capacitor 100 may be the first surface 1 of the capacitor body 110.

[0046] The dielectric layer 111 may include a ceramic material with a high dielectric constant, and may include, for example, barium titanate (BaTiO3) based ceramic powder or strontium titanate (SrTiO3) based ceramic powder, but this disclosure is not limited thereto, as long as sufficient capacitance can be obtained.

[0047] In addition, ceramic additives, organic solvents, plasticizers, binders and dispersants may be further added to the dielectric layer 111 together with the ceramic powder.

[0048] As ceramic additives, transition metal oxides or transition metal carbides, rare earth elements, magnesium (Mg) or aluminum (Al) can be used, for example.

[0049] The capacitor body 110 may include an effective region as well as an upper cover 112 and a lower cover 113. The effective region is the part that helps to form the capacitance of the capacitor. The upper cover 112 and the lower cover 113 are respectively formed in the Z direction as the upper edge of the upper surface of the effective region and the lower edge of the lower surface.

[0050] The upper cover 112 and the lower cover 113 may have the same material and construction as the dielectric layer 111, except that they do not include the inner electrode.

[0051] These upper covers 112 and lower covers 113 can be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the effective area in the Z direction, respectively, and are essentially used to prevent damage to the first inner electrode 121 and the second inner electrode 122 due to physical or chemical stress.

[0052] The first inner electrode 121 and the second inner electrode 122 are electrodes with different polarities. The first inner electrode 121 and the second inner electrode 122 are alternately arranged along the Z direction, the dielectric layer 111 is located between the first inner electrode 121 and the second inner electrode 122, and one end of the first inner electrode 121 and one end of the second inner electrode 122 can be exposed through the third surface 3 and the fourth surface 4 of the capacitor body 110, respectively.

[0053] In this case, the first inner electrode 121 and the second inner electrode 122 can be electrically insulated from each other by a dielectric layer 111 disposed therebetween.

[0054] In this way, the ends of the first inner electrode 121 and the second inner electrode 122, which are alternately exposed by the third surface 3 and the fourth surface 4 of the capacitor body 110, can be electrically connected to the first conductive layer 131 and the second conductive layer 141 (which will be described later) of the first outer electrode 130 and the second outer electrode 140 disposed on the third surface 3 and the fourth surface 4 of the capacitor body 110, respectively.

[0055] According to the above configuration, when a predetermined voltage is applied to the first external electrode 130 and the second external electrode 140, charge accumulates between the first internal electrode 121 and the second internal electrode 122.

[0056] Here, the capacitance of the multilayer capacitor 100 is proportional to the overlap area of ​​the first inner electrode 121 and the second inner electrode 122 that overlap each other along the Z direction in the effective region.

[0057] Furthermore, there are no particular limitations on the materials used to form the first internal electrode 121 and the second internal electrode 122, and conductive pastes including at least one of noble metal materials (such as platinum (Pt), palladium (Pd), palladium-silver (Pd-Ag) alloy, nickel (Ni), and copper (Cu) can be used to form them.

[0058] Here, screen printing or gravure printing can be used as the printing method for conductive paste, but this disclosure is not limited to these methods.

[0059] The first external electrode 130 and the second external electrode 140 can be provided with voltages of different polarities, can be disposed at both ends of the capacitor body 110 in the X direction, and can be electrically connected to the exposed portions of the first internal electrode 121 and the second internal electrode 122.

[0060] Here, the first external electrode 130 includes a first conductive layer 131 formed on the surface of the capacitor body 110 and connected to the first internal electrode 121, and a first conductive resin layer 132 formed to cover the first conductive layer 131; the second external electrode 140 includes a second conductive layer 141 formed on the surface of the capacitor body 110 and connected to the second internal electrode 122, and a second conductive resin layer 142 formed to cover the second conductive layer 141.

[0061] The first conductive layer 131 may include a first inner connection portion 131a and a first inner band portion 131b.

[0062] The first inner connection portion 131a is a portion formed on the third surface 3 of the capacitor body 110 and connected to the first inner electrode 121, and the first inner band portion 131b is a portion extending from the first inner connection portion 131a to a portion of the first surface 1 of the capacitor body 110.

[0063] Here, the first inner band 131b may further extend to a portion of the fifth surface 5 and the sixth surface 6 of the capacitor body 110 and a portion of the second surface 2 to improve adhesion strength, etc.

[0064] The second conductive layer 141 may include a second inner connection portion 141a and a second inner band portion 141b.

[0065] The second inner connection portion 141a is a portion formed on the fourth surface 4 of the capacitor body 110 and connected to the second inner electrode 122, and the second inner band portion 141b is a portion extending from the second inner connection portion 141a to a portion of the first surface 1 of the capacitor body 110.

[0066] Here, the second inner band 141b may further extend to a portion of the fifth surface 5, a portion of the sixth surface 6, and a portion of the second surface 2 of the capacitor body 110 to improve adhesion strength, etc.

[0067] In this case, the first conductive layer 131 and the second conductive layer 141 may include at least one of nickel (Ni), copper (Cu) and silver (Ag), and may also include glass.

[0068] The first conductive resin layer 132 may include a first external connection portion 132a and a first external strip portion 132b.

[0069] The first external connection portion 132a is the portion that covers the first internal connection portion 131a, and the first external band portion 132b is the portion that covers the first internal band portion 131b and extends to a portion of the first surface 1 of the capacitor body 110.

[0070] Here, according to the structure of the first inner band portion 131b, the first outer band portion 132b may further extend to a portion of the fifth surface 5 and a portion of the sixth surface 6 and a portion of the second surface 2 of the capacitor body 110.

[0071] In other words, the length of the first inner band portion 131b in the first conductive layer 131 can be shorter than the length of the first outer band portion 132b in the first conductive resin layer 132.

[0072] The second conductive resin layer 142 may include a second external connection portion 142a and a second external strip portion 142b.

[0073] The second outer connection portion 142a is the portion that covers the second inner connection portion 141a, and the second outer band portion 142b is the portion that covers the second inner band portion 141b and extends to a portion of the first surface 1 of the capacitor body 110.

[0074] Here, according to the structure of the second inner band 141b, the second outer band 142b can further extend to a portion of the fifth surface 5, a portion of the sixth surface 6, and a portion of the second surface 2 of the capacitor body 110.

[0075] In other words, the length of the second inner band portion 141b in the second conductive layer 141 can be shorter than the length of the second outer band portion 142b in the second conductive resin layer 142.

[0076] These first conductive resin layers 132 and second conductive resin layers 142 provide stress absorption effects and may include conductive metal particles and a thermosetting resin as the matrix resin.

[0077] In this case, the conductive metal can be at least one of copper (Cu), nickel (Ni), zinc (Zn) and iron (Fe), but this disclosure is not limited thereto.

[0078] In addition, the thermosetting resin may be, for example, epoxy resin, but this disclosure is not limited thereto.

[0079] In addition, when a plating layer is formed on the surface of the first conductive resin layer 132 and the second conductive resin layer 142, the plating layer can be used to prevent the electroplating solution from penetrating into the first conductive layer 131, the second conductive layer 141 and the capacitor body 110, and to prevent the first external electrode 130, the second external electrode 140 or the capacitor body 110 from cracking due to external impact.

[0080] Additionally, the first external electrode 130 may include a first reduced graphene oxide (RGO) layer 133' disposed between the first conductive layer 131 and the first conductive resin layer 132.

[0081] In this case, the first RGO layer 133' can be continuously formed as a single unit on the first conductive layer 131.

[0082] As another example, such as Figure 4 and Figure 5 As shown, multiple first RGO layers 133 can be formed in an island shape on the first conductive layer 131 and spaced apart from each other.

[0083] The first RGO layer 133' can be formed by coating graphene oxide onto the surface of the first conductive layer 131.

[0084] Here, a spraying method can also be used to uniformly coat graphene oxide.

[0085] The graphene oxide thinly coated onto the first conductive layer 131 by spraying is heat-treated at 240°C (the curing temperature of the first conductive resin layer 132) for 24 hours to form the first RGO layer 133'.

[0086] The preferred thickness of the first RGO layer 133' can be 50 nm or less.

[0087] If the thickness of the first RGO layer 133' exceeds 50 nm, the first RGO layer 133' may not be properly formed and may accidentally separate from the first conductive layer 131.

[0088] Here, the thickness of the first RGO layer 133' can be 1 nm or greater.

[0089] Here, the optimal thickness of the first RGO layer 133' can be obtained by adjusting the spray injection volume, the concentration of the sprayed graphene oxide solution, and the number of sprayed coating layers. The thicknesses of the first RGO layer 133', the second RGO layer 143' (described later), etc., can be measured, for example, by transmission electron microscopy (TEM) in a cross-section of the capacitor body 110 cut in the XZ plane at the central portion in the Y direction (or in the XY plane at the central portion in the Z direction). Other methods and / or tools understood by those skilled in the art may be used, even if not described in this disclosure. In one example, the thickness of the RGO layer can be one of an average thickness, a maximum thickness, and a thickness measured in the measurement area. In one example, the thickness of the RGO layer can be determined by measuring the thickness at each point at equal (or alternatively, unequal) intervals, defined to the left and to the right, from a reference center point of the element, at equal (or alternatively, unequal) intervals, and obtaining an average value therefrom. Optionally, the thickness can be the maximum thickness across multiple measurements. Optionally, the thickness can be the thickness at a reference center point within the measurement area.

[0090] The second external electrode 140 may include a second RGO layer 143' disposed between the second conductive layer 141 and the second conductive resin layer 142.

[0091] Here, the second RGO layer 143' can be continuously formed as a single unit on the second conductive layer 141.

[0092] As another example, such as Figure 4 and Figure 5 As shown, multiple second RGO layers 143 can be formed in an island shape on the second conductive layer 141 and spaced apart from each other.

[0093] The second RGO layer 143' can be formed by coating RGO onto the surface of the second conductive layer 141.

[0094] Here, spraying is preferred to coat the RGO evenly.

[0095] The graphene oxide thinly coated onto the second conductive layer 141 by spraying is heat-treated at 240°C (the curing temperature of the second conductive resin layer 142) for 24 hours to form the second RGO layer 143'.

[0096] The preferred thickness of the second RGO layer 143' can be 50 nm or less.

[0097] If the thickness of the second RGO layer 143' exceeds 50 nm, the second RGO layer 143' may not be properly formed and may accidentally separate from the second conductive layer 141.

[0098] Here, the thickness of the second RGO layer 143' can be 1 nm or greater.

[0099] Here, the optimal thickness of the second RGO layer 143' can be obtained by adjusting the spray injection volume, the concentration of the sprayed graphene oxide solution, and the number of sprayed coating layers.

[0100] On the other hand, such as Figure 6 As shown, the first external electrode 130' and the second external electrode 140' may further include a plating layer formed to cover the first conductive resin layer 132 and the second conductive resin layer 142.

[0101] The plating may include a first nickel (Ni) plating layer 134 and a second nickel (Ni) plating layer 144 covering the first conductive resin layer 132 and the second conductive resin layer 142 respectively, and a first tin (Sn) plating layer 135 and a second tin (Sn) plating layer 145 covering the first nickel plating layer 134 and the second nickel plating layer 144 respectively.

[0102] In existing multilayer capacitors where the external electrode comprises a conductive layer and a conductive resin layer, the conductive layer and the conductive resin layer are bonded to each other only by hydrogen bonds with relatively weak bond strengths having bond energies of 10 kJ / mol to 40 kJ / mol.

[0103] Therefore, during the preform reflow process, carbon dioxide gas generated from the curing agent inside the conductive resin layer cannot be released to the outside and remains there, causing lifting defects between the conductive layer and the conductive resin layer.

[0104] In this exemplary embodiment, when the epoxy resin adheres to the transition metals Zn, Cu, and Fe on the surface of the conductive layer, charge is transferred from the d orbitals of the transition metals to the p orbitals of oxygen and the π orbitals of benzene in the epoxy groups to form a bonding layer.

[0105] Here, as Figure 7 As shown, an RGO layer 133 having various functional groups including oxygen and having excellent conductivity can be disposed between the first conductive layer 131 and the first conductive resin layer 132 to provide additional hydrogen bonds (represented by circles) and π-π bonds (represented by rhombuses) at the interface between the first conductive layer 131 and the first conductive resin layer 132.

[0106] In addition, the RGO layer allows the stress applied to the external electrode to be stably transferred to the interface between the conductive layer and the conductive resin layer, thereby reducing noise and improving the mechanical properties of the conductive resin layer.

[0107] Through these effects, the RGO layer minimizes the phenomenon of the conductive resin layer lifting off the conductive layer.

[0108] Therefore, the multilayer capacitor according to this exemplary embodiment can be advantageously used in applications requiring reduced acoustic noise, high flexural strength, high moisture resistance and high capacitance.

[0109] Figure 8 It is shown schematically. Figure 4 A cross-sectional view of a multilayer capacitor mounted on a substrate.

[0110] Reference Figure 8 According to this exemplary embodiment, the mounting plate includes a substrate 210 and a first electrode pad 221 and a second electrode pad 222 spaced apart from each other on the upper surface of the substrate 210.

[0111] Here, the multilayer capacitor 100 is mounted on the substrate 210, such that the first external electrode 130 and the second external electrode 140 are positioned to contact the first electrode pad 221 and the second electrode pad 222, respectively.

[0112] Here, the first external electrode 130 can be bonded to solder 231 for electrical connection and physical connection to the first electrode pad 221, and the second external electrode 140 can be bonded to solder 232 for electrical connection and physical connection to the second electrode pad 222.

[0113] As described above, according to an exemplary embodiment, the phenomenon of the conductive resin layer in the external electrode of a multilayer capacitor lifting off the conductive layer can be improved.

[0114] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A multilayer capacitor, comprising: The capacitor body includes multiple dielectric layers and multiple internal electrodes; as well as A pair of external electrodes includes a conductive layer disposed on opposite ends of the capacitor body, a conductive resin layer covering the conductive layer, and a reduced graphene oxide layer disposed between the conductive layer and the conductive resin layer. The interface is formed between the reduced graphene oxide layer and the conductive layer and the conductive resin layer.

2. The multilayer capacitor according to claim 1, wherein, The reduced graphene oxide layer is continuously disposed on the conductive layer.

3. The multilayer capacitor according to claim 1, wherein, The reduced graphene oxide layer has an island shape on the conductive layer.

4. The multilayer capacitor according to claim 1, wherein, The capacitor body includes a first surface and a second surface opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other. The internal electrode includes a first internal electrode and a second internal electrode. One end of the first internal electrode and one end of the second internal electrode are alternately exposed through the third surface and the fourth surface of the capacitor body and are respectively connected to an external electrode disposed on the third surface and the fourth surface of the capacitor body. The dielectric layer is located between the first inner electrode and the second inner electrode.

5. The multilayer capacitor according to claim 1, wherein, The outer electrodes also include a plating layer covering the conductive resin layer.

6. The multilayer capacitor according to claim 5, wherein, The plating layer includes a nickel plating layer covering the conductive resin layer and a tin plating layer covering the nickel plating layer.

7. The multilayer capacitor according to claim 1, wherein, The thickness of the reduced graphene oxide layer is greater than or equal to 1 nm and less than or equal to 50 nm.

8. A plate for mounting multilayer capacitors, the plate comprising: A substrate having a pair of electrode pads spaced apart from each other on one surface; as well as Multilayer capacitors are mounted on the substrate. The multilayer capacitor includes: The capacitor body includes multiple dielectric layers and multiple internal electrodes; and A pair of external electrodes each includes a conductive layer disposed on opposite ends of the capacitor body, a conductive resin layer covering the conductive layer, and a reduced graphene oxide layer disposed between the conductive layer and the conductive resin layer, and the pair of external electrodes are respectively connected to the pair of electrode pads. The interface is formed between the reduced graphene oxide layer and the conductive layer and the conductive resin layer.

9. The plate according to claim 8, wherein, The reduced graphene oxide layer is continuously disposed on the conductive layer.

10. The plate according to claim 8, wherein, The reduced graphene oxide layer has an island shape on the conductive layer.

11. The plate according to claim 8, wherein, The capacitor body includes a first surface and a second surface opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other. The internal electrode includes a first internal electrode and a second internal electrode. One end of the first internal electrode and one end of the second internal electrode are alternately exposed through the third surface and the fourth surface of the capacitor body and are respectively connected to an external electrode disposed on the third surface and the fourth surface of the capacitor body. The dielectric layer is located between the first inner electrode and the second inner electrode.

12. The plate according to claim 8, wherein, The outer electrodes also include a plating layer covering the conductive resin layer.

13. The plate according to claim 12, wherein, The plating layer includes a nickel plating layer covering the conductive resin layer and a tin plating layer covering the nickel plating layer.

14. The plate according to claim 8, wherein, The thickness of the reduced graphene oxide layer is greater than or equal to 1 nm and less than or equal to 50 nm.

15. A method for manufacturing a multilayer capacitor, the method comprising: A capacitor body comprising multiple dielectric layers and a first internal electrode and a second internal electrode is formed; A conductive layer comprising metal is formed on the capacitor body to connect to one of the first internal electrode and the second internal electrode; A coating layer containing graphene oxide is formed on the conductive layer; A conductive resin layer is formed covering the coating layer containing graphene oxide; The coating layer containing graphene oxide and the conductive resin layer are subjected to heat treatment; and The heat treatment utilizes the coating containing graphene oxide to form a reduced graphene oxide layer. The interface is formed between the reduced graphene oxide layer and the conductive layer and the conductive resin layer.

16. The method according to claim 15, wherein, The reduced graphene oxide layer is continuously disposed on the conductive layer.

17. The method according to claim 15, wherein, The reduced graphene oxide layer has an island shape on the conductive layer.

18. The method according to claim 15, wherein, The thickness of the reduced graphene oxide layer is greater than or equal to 1 nm and less than or equal to 50 nm.

19. The method according to claim 15, wherein, The coating containing graphene oxide is formed by spraying a graphene oxide solution.

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